JPH07297387A - Horizontal semiconductor device - Google Patents

Abstract

PURPOSE:To enable execution of such a control as to make a main current of a horizontal semiconductor device reach a prescribed value by connecting a sense electrode and a sense terminal by a sense line and by connecting a control electrode of a semiconductor unit cell and a control terminal by a control line. CONSTITUTION:A sense electrode 10 is disposed in a part of one or a plurality of semiconductor unit cells out of a large number of semiconductor unit cells. This sense electrode 10 and a sense terminal are connected by a sense line 11, while a control electrode of one or a plurality of the semiconductor unit cells out of those in large numbers and a control terminal are connected by a control line. The place of disposition of the semiconductor unit cell having the sense electrode 10 or the place of disposition of the semiconductor unit cell having the control electrode connected to the control line 12 is selected properly respectively. According to this constitution, an increase in a main current of a horizontal type semiconductor device is not suppressed before it reaches a prescribed value, and a control of the current can be executed with high accuracy.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor) or (EST Emitter Switched Thyristor). The present invention relates to a lateral semiconductor device in which one or a plurality of semiconductor unit cells have a current sensing function and current control of the entire lateral semiconductor device is performed based on this sensing function.

[0002]

2. Description of the Related Art Generally, a vertical type or a lateral type IGBT has been known as a semiconductor device capable of switching and controlling a relatively large current at a high speed, but EST is also known relatively recently. Became. Then, this EST is, for example, “Proceedings of
1992 International Symposs
ium on Power Semiconductor
r Devices & ICs, Tokyo "pp. Two
56-260.

Here, FIGS. 6A and 6B are configuration diagrams showing an example of the configuration of a known lateral IGBT, in which FIG.
Is a plan view and (b) is a lateral cross-sectional view of one semiconductor unit cell.

In FIGS. 6A and 6B, 51 is an n-type low impurity concentration (n-) semiconductor substrate, 52 is a p-type well region, 53 is an n-type high impurity concentration (n +) emitter region, 54 is a p-type high impurity concentration (p +) collector region,
55 is an emitter electrode, 56 is a collector electrode, 57 is a gate electrode, 58 is an insulating film, 59 is an insulating layer, 60 is a sense electrode, 61 is a sense line, and 62 is a gate line.

A p-type well region 52 and a p-type collector region 54 are selectively formed on one main surface of the n-type semiconductor substrate 51 at a distance from each other.
An n-type emitter region 53 is selectively formed on the surface of the. An emitter electrode 55 is arranged in contact with each surface of the p-type well region 52 and the n-type emitter region 53, and a p-type collector region 54 is provided.
The collector electrode 56 is arranged in contact with the surface of the. A gate electrode 57 is arranged over one main surface of the n-type semiconductor substrate 51 and each surface of the p-type well region 52 and the n-type emitter region 53 with an insulating film 58 interposed between the emitter electrode 55 and the gate electrode 57 and the collector electrode. 56 and n-type semiconductor substrate 5
An insulating layer 59 is provided between each one of the main surfaces. Further, the emitter electrode 55 and the collector electrode 56 are both configured so as to form a comb shape as a whole, and are arranged so that the tooth portions of the emitter electrode 55 and the collector electrode 56 mesh with each other. The gate electrode 57 is also configured to have a comb shape as a whole. In this case, the portion surrounded by the frame A shown in FIG. 6 is a lateral IGBT unit (unit) cell, and I
The GBT unit cells A are arranged so that their directions are opposite to each other, that is, they are continuously formed in a meandering state in a lateral direction, and a lateral IGBT is configured by a combination of all the IGBT unit cells. In the IGBT unit cell at the right end in FIG. 6A, a part of the emitter electrode 55 in the longitudinal direction is arranged apart, and the separated part constitutes a sense electrode 60 for current detection. The sense electrode 60 is the sense line 6
1 is connected to a sense terminal (not shown), and a portion of the gate electrode 57 near the sense electrode 60 is connected to a control terminal (not shown) via a control line 62.

The operation of the lateral IGBT having such a configuration is well known in the art, and therefore the description of the operation of the lateral IGBT will be omitted.

FIG. 7 is a sectional view showing an example of the structure of the EST according to the above disclosure.

In FIG. 7, 63 is an n-type low impurity concentration (n-) drift region, and 64 is a p-type low impurity concentration (p).
-) Base region, 65 is a p-type high impurity concentration (p +) region, 66 is an n-type high impurity concentration (n +) region, 67 is an n-type high impurity concentration (n +) floating region, and 68 is n.
A type buffer region, 69 is a p-type high impurity concentration (p +) anode region, 70 is an anode electrode, 71 is a cathode electrode, 72 is a gate electrode, 73 is an insulating film, and 74 is an n-type channel.

Then, p type base region 64 and p type region 65 are selectively arranged on one main surface of n type drift region 63 so as to be in contact with each other, and these p type base region 64 and p type region 65 are provided.
The n-type region 66 is selectively arranged on the surface of a portion adjacent to the n-type region 66, and the n-type floating region 67 is selectively arranged on the surface of the p-type base region 64 so as to be separated from the n-type region 66. N-type buffer region 68 is arranged on the other main surface of n-type drift region 63, and p-type anode region 69 is arranged on the surface of n-type buffer region 68. An anode electrode 70 is disposed in contact with the surface of the p-type anode region 69, and the p-type region 65 and the n-type region 6 are
Cathode electrode 71 is placed in contact with each surface of 6. One main surface of the n-type drift region 63, the surface of the p-type base region 64, and the surface of the n-type floating region 67, and between the surface of the n-type floating region 67, the surface of the p-type base region 64, and the n-type region 66. A gate electrode 72 is arranged over the surface with an insulating film 73 interposed therebetween.

In this case, the portion surrounded by the one-dot chain line shown in FIG. 7, that is, the p-type anode region 69, the n-type buffer region 68, the n-type drift region 63, the p-type base region 64, n.
The portion composed of the mold floating region 67 constitutes the thyristor portion T, and is the portion surrounded by the dotted line shown in FIG.
p-type base region 64, n-type floating region 67, n
The portion formed of the type region 66 and the n-type drift region 63 is M
It constitutes the OSFET section M.

The EST having the above-mentioned configuration operates as follows.

First, the gate electrode 72 of the MOSFET section M.
When a control voltage exceeding a predetermined threshold is not applied to the MOSFET section M, the MOSFET section M is in the OFF state, and the thyristor section T is also in the OFF state in which no forward current flows.

Then, when a control voltage exceeding the predetermined threshold value is applied to the gate electrode 72, an n-type channel 74 is formed in the p-type base region 64 below the gate electrode 72 in the MOSFET section M. Are formed, whereby the electron flow flows from the n-type region 66 to the n-type drift region 63 through the n-type channel 74, the n-type floating region 67, and the n-type channel 74, and the holes form the p-type anode region 69. To n
The p-type base region 64 is implanted into the mold drift region 63.
Collected in. In this case, since the p-type base region 64 has a low impurity concentration, it has a high sheet resistance (lateral resistance), so that the pn junction formed by the p-type base region 64 and the n-type drift region 63 is formed. It is forward biased and the thyristor section T turns on. Then, due to the turn-on of the thyristor portion T, at this time, the electron flow transmitted to the n-type drift region 63 and the holes injected into the n-type drift region 63 increase, and the turn-on state is maintained. In this case, since the n-type floating region 67 is connected to the cathode electrode through the two n-type channels 74, the MO
The SFET part M can control the value of the on-current of the thyristor part T by the control voltage applied to the gate electrode 72.

As described above, the EST having the above-described structure operates as a thyristor at the time of turn-on, so that a known IGB is used.
The forward voltage drop can be made lower than that of T, and the trade-off relationship between the forward voltage drop and the turn-off time is known.
It is improved as compared with BT, and a turn-off time of about 500 nsec can be obtained in an EST having a breakdown voltage of 600V.

[0015]

By the way, MOSFE
The turn-on speed of lateral semiconductor devices such as T and IGBT is
It is determined by the timing of application of a control voltage exceeding a predetermined threshold value to the gate.
When the gate drive circuit of the IGBT or the IGBT is physically long, it depends on the charging speed of the gate drive circuit, that is, the product of the stray capacitance component of the gate drive circuit and the resistance component added in series to the gate drive circuit. . Therefore, as in the known lateral semiconductor device (lateral IGBT) shown in FIG. 6, a large number of IGBT unit cells A are arranged in the lateral direction,
In the lateral IGBT having a structure in which the length of each gate drive circuit from the control (gate) terminal to each IGBT unit cell A is different, there is a difference in the turn-on time of each IGBT unit cell A. Like The difference in the turn-on time depends on the length of the gate drive circuit from the control (gate) terminal to the gate electrode of the IGBT unit cell A. The longer the length, the longer the length of the gate drive circuit. , The turn-on time of the IGBT unit cell A is delayed.

On the other hand, this type of lateral semiconductor device, for example,
In a lateral IGBT or the like, when an integrated circuit (IC) structure is formed by including this IGBT and other circuits, the IC chip area can be minimized and the layout wiring can be the shortest and simplest. , A sense terminal and a control (gate) terminal are usually provided side by side on one short side of a rectangular lateral IGBT, and a gate from the control (gate) terminal to the gate electrode of each IGBT unit cell A is provided. The driving circuits have different lengths.

Here, FIGS. 8A and 8B are characteristic diagrams showing a temporal change state of the main current and the sense current when the known lateral IGBT shown in FIG. 6 is turned on. , (A) is a temporal change state of the main current expressed in ampere (A), and (b) is a temporal change state of the sense current expressed in milliampere (mA).
In (a) and (b), a dotted line shows an ideal temporal change state, and a solid line shows an actual temporal change state. In this case, the main current represents a current flowing in the lateral IGBT, that is, a current flowing in a main unit cell described later, and the sense current represents a current flowing in a sense unit cell described later.

Now, in the lateral IGBT in which the ratio of the length in the electrode longitudinal direction of the portion in contact with the p-type well region 52 and the n-type emitter region 53 in the sense electrode 60 to that of the whole emitter electrode 55 is 1: 1000. , Fig. 8
As shown in (a) and (b), 1A of this lateral IGBT
The main current of is controlled by a sense current of 1 mA. In this control, in the ideal control, as shown by the dotted line, the sense current and the main current increase at the same rate from the time t0 as a starting point, and when the main current reaches 1A at time t4, Sense current is also 1
Since the current reaches mA, it should be possible to perform highly accurate control of the main current after time t4. That
Experiments conducted by the inventors of the present invention have revealed that the actual control does not simply increase the main current and the sense current as shown by the solid line.

The reason why such control characteristics are obtained is considered to be as follows. This lateral IGBT
The gate line 62 for supplying the control signal is the sense electrode 60.
Is connected to the gate electrode 57 on the arrangement side, the control signal is supplied at time t0, and the I electrode having the sense electrode 60 is supplied.
At the moment when the GBT unit cell A (hereinafter referred to as the sense unit cell) turns on, the remaining IGB
Of the T unit cells A (hereinafter, referred to as main unit cells), for example, only about half of the main unit cells arranged in proximity to the sense unit cells are turned on. Therefore, in the initial stage from time t0 to time t1, only half the current value of the original main current flowing through the lateral IGBT flows. next,
Between time t1 and time t2, the current value of the sense current is doubled so that an external or internal operation detection unit (not shown) increases the main current of the lateral IGBT, and about half the turn-on is performed. In the same manner, the current value of the main unit cell and the current value of the main unit cell turned on after the time t1 are also increased, and as a result, the value of the main current comes close to an ideal value. Subsequently, between time t2 and time t3, the current value of the main unit cell that has been turned on increases with the increase of the current value of the sense current, and the current value of the main unit cell that has turned on after time t2 increases. Due to addition or the like, the main current rapidly increases, and its value exceeds the ideal value. Then, at time t3, when the value of the sense current reaches the specified 1 mA due to the increase in the current value of the sense current, a current detection circuit (not shown) detects that the specified current value has been reached, and the sense current is reached. Of 1 mA or more is suppressed. As a result, the increase of the main current is suppressed before reaching 1 A, for example, at 0.7 A, and thereafter, the main current value is constantly maintained at 0.7 A which is equal to or less than the specified 1 A.

As described above, in the known lateral IGBT, there is a problem that the main current value cannot be reliably increased to the specified current value due to the difference in the turn-on time of each IGBT unit cell.

On the other hand, the known EST has a MOSFE inside.
Since the T section and the thyristor section are connected in series, the T section and the thyristor section have a function of naturally limiting the flowing current. The current limiting function allows excess current to flow through the EST due to a short circuit of an external load or the like. It is possible to prevent them from being destroyed. However, this EST does not have a sense part, and since no attempt has been made to add this sense part to the EST, the output current is appropriately limited according to the current withstand capacity of the external load. There is a problem that you can not.

The present invention solves each of the problems described above, and an object thereof is to control such that the main current of a lateral semiconductor device reaches a specified value when a large number of semiconductor unit cells are arranged in the lateral direction. It is to provide a lateral semiconductor device capable of

Another object of the present invention is to provide a lateral type semiconductor device in which the whole is lateral type and a main current sensing function is added so that the output current can be limited according to the current withstanding capacity of an external load, and more particularly, a lateral type semiconductor device. To provide EST.

[0024]

To achieve the above object, the present invention provides a semiconductor substrate of a first conductivity type and a first semiconductor of a second conductivity type selectively arranged on one main surface of the semiconductor substrate. A region, a second semiconductor region of the first conductivity type selectively arranged on the surface of the first semiconductor region, and a second conductivity selectively arranged on the one main surface of the semiconductor substrate so as to be separated from the first semiconductor region. A third semiconductor region having a high impurity concentration, a control electrode disposed over one main surface of the semiconductor substrate, a surface of the first semiconductor region, and a surface of the second semiconductor region via an insulating layer, and the second semiconductor A semiconductor device comprising a first main electrode arranged in contact with the surface of the region and a second main electrode arranged in contact with the surface of the third semiconductor region is integrated and arranged so as to meander in a lateral direction. Control and sense terminals on one end of A lateral semiconductor device including: a first main electrode of one or a plurality of semiconductor unit cells, which are partially spaced apart in a longitudinal direction to form a sense electrode, and the sense electrode and the sense terminal are sensed. It is provided with a first means which is connected by a line and which connects the control electrode of one or more semiconductor unit cells and the control terminal by a control line.

In order to achieve the above-mentioned other object, the present invention provides a first conductivity type semiconductor substrate and a second conductivity type first semiconductor region selectively arranged on one main surface of the semiconductor substrate.
A second semiconductor region of the first conductivity type selectively arranged on the surface of the first semiconductor region, and a second impurity of high conductivity type selectively arranged on the one main surface of the semiconductor substrate so as to be separated from the first semiconductor region. A third semiconductor region having a high concentration, a fourth semiconductor region having a second conductivity type and a high impurity concentration, which is selectively arranged adjacent to the first semiconductor region on one main surface of the semiconductor substrate, the first semiconductor region and the second semiconductor region. A fifth semiconductor region having a high impurity concentration of the first conductivity type selectively arranged on each surface of the fourth semiconductor region, one main surface of the semiconductor substrate, the surface of the first semiconductor region, and the surface of the second semiconductor region. And a surface of the second semiconductor region, a surface of the first semiconductor region, and the fifth
A control electrode disposed over the surface of the semiconductor region via an insulating layer, the fourth semiconductor region and the fifth semiconductor region, respectively.
A plurality of semiconductor unit cells, each of which has a first main electrode arranged in contact with each surface of the semiconductor region and a second main electrode arranged in contact with the surface of the third semiconductor region, are integrated in a laterally meandering manner. A second means having a control terminal and a sense terminal is provided on one end surface of the device.

[0026]

According to the first means, the sense electrode is arranged in a part of one or a plurality of semiconductor unit cells among a large number of semiconductor unit cells, and the sense electrode is connected to the sense line. The control line is connected to the control electrode of one or a plurality of semiconductor unit cells among a large number of semiconductor unit cells.

In this case, the control line can be selected by appropriately selecting the location of the semiconductor unit cell having the sense electrode (sense unit cell) or the location of the semiconductor unit cell having the control electrode connected to the control line. When a control signal is supplied to the sense unit unit cell, the delay of the turn-on time of some of the remaining semiconductor unit cells (main unit cell) is known with respect to the turn-on time of the sense unit unit cell. This can be made considerably smaller than that of the lateral semiconductor device, so that the increase of the main current of the lateral semiconductor device before it reaches a specified value is not suppressed. Then, the current control of the lateral semiconductor device can be performed with high accuracy, and the margin at the time of defining the current rating can be reduced,
The area occupied by the lateral semiconductor device in the integrated circuit device is also small, which is economical.

Further, according to the second means, since the EST is laterally configured and the sense electrode is arranged in one or a plurality of EST unit cells, the EST having the sensing function is obtained. Therefore, it becomes possible to limit the output current value of the EST according to the withstand current of the external load.

In this case, the EST is arranged on both sides of the second semiconductor region in which the control (gate) electrode is in a floating state, and the area of the control (gate) electrode is IGBT or M.
Since it is wider than the control (gate) electrode of the OSFET, the EST unit cell having the control (gate) electrode connected to the location of the EST unit cell (sense unit cell) having the sense electrode or the control (gate) line. By appropriately selecting each of the arrangement positions, the turn-on time of some of the remaining semiconductor unit cells (main unit cells) can be sufficiently reduced with respect to the turn-on time of the sense unit cell. Therefore, the increase in the main current of the lateral EST is not suppressed before reaching the specified value.

[0030]

Embodiments of the present invention will now be described in detail with reference to the drawings.

1A and 1B are configuration diagrams showing the configuration of a first embodiment of a lateral semiconductor device according to the present invention, wherein FIG. 1A is a top view and FIG. 1B is one semiconductor. FIG. 6 is a cross-sectional view of a unit cell in the lateral direction, showing an example in which a lateral semiconductor device constitutes an IGBT.

In FIGS. 1A and 1B, 1 is a semiconductor substrate having an n-type low impurity concentration (n-), 2 is a p-type well region (first semiconductor region), and 3 is an n-type high impurity concentration ( n +) emitter region (second semiconductor region), 4 p-type high impurity concentration (p +) collector region (third semiconductor region), 5 emitter electrode (first main electrode), 6 collector electrode (second semiconductor region) Main electrode), 7 is a gate electrode (control electrode), 7a is a gate electrode lead portion, 8 is an insulating film, 9 is an insulating layer, 10 is a sense electrode, 11 is a sense line, and 12 is a gate line (control line). .

On one main surface of the n-type semiconductor substrate 1, a p-type well region 2 and a p-type collector region 4 are selectively formed so as to be separated from each other, and on the surface of the p-type well region 2, an n-type emitter region is formed. 3 are selectively formed. An emitter electrode 5 is formed on each surface of the p-type well region 2 and the n-type emitter region 3.
Are arranged in contact with each other, and a collector electrode 6 is arranged in contact with the surface of the p-type collector region 4. A gate electrode 7 is arranged over the main surface of the n-type semiconductor substrate 1, the surface of the p-type well region 2 and the surface of the n-type emitter region 3 with an insulating film 8 interposed between the emitter electrode 5 and the gate electrode 7. An insulating layer 9 is arranged between collector electrode 6 and one main surface of n-type semiconductor substrate 1. In this case, the emitter electrode 5
The collector electrode 6 and the collector electrode 6 are configured so as to have a comb shape as a whole when viewed from the upper surface of the IGBT, and the respective tooth portions of the emitter electrode 5 and the collector electrode 6 are arranged so as to mesh with each other. The gate electrode 7 is also configured so as to have a comb shape as a whole when viewed from the upper surface of the IGBT. Here, a portion surrounded by a frame A shown in FIG. 1A is an IGBT unit (unit) cell, and the plurality of IGBT unit cells A have their directions reversed to each other, that is, in a meandering lateral direction. And a plurality of IGBT unit cells A are combined to form a substantially rectangular lateral IGBT. Although not shown in FIG. 1 (a),
A sense terminal and a gate terminal (control terminal) are provided on one end surface portion of the short side of the lateral IGBT, and at the same time, a collector terminal and an emitter terminal are also provided.

Further, as shown in FIG. 1A, the IGBT unit cells at the right end and the left end of the lateral IGBT are the first
And the second sense unit cells, and the remaining many IGBT unit cells are main unit cells. In the first and second sense unit cells, a part of the emitter electrode 5 in the longitudinal direction is arranged so as to be separated from each other, and this separated portion serves as the current detection sense electrode 10. In this case, each sense electrode 10 is connected to the sense terminal via a common sense line 11. On the other hand, as shown in FIG.
Is provided with a gate electrode lead-out portion 7a near the rightmost IGBT unit cell (first sense unit cell), and the gate electrode lead-out portion 7a is connected to the gate terminal through a gate line 12.

In the lateral IGBT having the above-mentioned structure, the required switching operation is achieved by the following process. That is, when a gate voltage higher than a predetermined threshold value than the voltage of the emitter electrode 5 is supplied to the gate electrode 7 with a predetermined voltage applied between the collector electrode 6 and the emitter electrode 5, the lower side of the gate electrode 7 , An n-type channel is formed in the p-type well region 2, and electrons flow from the n-type emitter region 3 into the n-type semiconductor substrate 1 through the n-type channel, and at the same time, holes are formed in the p-type collector region. 4 to the n-type semiconductor substrate 1. At this time, the lateral IGBT is turned on, and a current flows from the collector electrode 6 to the emitter electrode 5.
On the other hand, when the lateral IGBT is in the ON state, the supply of the gate voltage to the gate electrode 7 is stopped or the emitter electrode 5
Supply of a control voltage lower than or substantially equal to the voltage of n.sub.2, the n-type channel in the p-type well region 2 disappears, so that the inflow of electrons into the n-type semiconductor substrate 1 is stopped, and at the same time, the n-type The injection of holes into the semiconductor substrate 1 is also stopped, and the lateral IGBT is immediately turned off.

Here, FIGS. 2A and 2B are characteristic diagrams showing a temporal change state of the main current and the sense current when the lateral IGBT of the first embodiment is turned on. , (A) is a temporal change state of the main current expressed in ampere (A), and (b) is a temporal change state of the sense current expressed in milliampere (mA).
In (a) and (b), a dotted line shows an ideal temporal change state, and a solid line shows an actual temporal change state. Here again, the main current represents the current flowing through the lateral IGBT, that is, the total current flowing through each main unit cell, and the sense current represents the current flowing through the sense unit cell.

The current control operation in the lateral IGBT according to the first embodiment will be described with reference to FIGS. 2 (a) and 2 (b). However, in this lateral IGBT, in each sense electrode 10, the ratio of the length in the comb electrode longitudinal direction of the portion in contact with the p-type well region 2 and the n-type emitter region 3 to that of the entire emitter electrode 5 is 1: 2000. The ratio of the total of the two sense electrodes 10 is 1: 1000, and as shown in FIGS. 2A and 2B, the lateral IGBT
The main current of 1 A is controlled by the sense current of 1 mA. Also in the current control of this lateral IGBT, the ideal current control is that, as shown by the dotted line, the sense current and the main current increase at the same rate starting from time t0, and at time t4, the main current increases. When the current reaches 1 A, the sense current also reaches 1 mA.

First, when the gate signal is supplied through the gate line 12 at time t0, the time t0 to the time t
During the first period up to 1, since the first sense unit cell is located near the gate terminal, it immediately turns on, and at the same time, the first sense unit cell in the main unit cell is turned on. Some things nearby,
For example, about half of them turn on. Meanwhile, the second
Since the sense section unit cells are arranged at a great distance from the gate terminal, they do not turn on during this first period, and the remaining half of the main section unit cells in the vicinity thereof do not turn on either. Therefore, in the first period, the sense current becomes half the ideal sense current due to the non-operation of one sense unit cell, and the main current output from the IGBT is also half the ideal main current. Is only output.

Next, in the second period from time t1 to time t2, the gates supplied to the gate line 12 so that about half of the main unit cells that are already turned on output the current of the specified value. The signal is boosted appropriately. Therefore, the sense current flowing through the first sense unit cell, that is, the entire sense current increases, and as the sense current increases, the main current of each main unit cell that is turned on also changes to the sense current. It grows at the same rate as it grows.

Then, the third time from time t2 to time t3
In the period (2), the second sense unit cell in the off state is turned on, so that the sense current rapidly increases. Also, in the third period,
Similarly, the remaining main unit cells, which were also in the OFF state, are turned on one after another, so that the main current increases at the same rate as the rapid increase of the sense current. Then, at time t3, the current value of the sense current reaches the specified value of 1 mA, and at the same time, the current value of the main current also reaches the specified value of 1 A. Thereafter, the current value of the main current is It is controlled to keep the value of 1A. The change state of the sense current and the main current is shown in FIG.
The curve (b) in (b) is obtained.

In the current control of the IGBT, it is described that both the second sense unit cell and the remaining main unit cell are turned on at time t2. However, for example, before the time t2 is reached. , When the second sense unit cell and the remaining main unit cell are both turned on, the change states of the sense current and the main current are as shown in the curves (a) of FIGS. 2 (a) and 2 (b). On the other hand, when the second sense unit cell and the remaining main unit cell are both turned on slightly after time t2, the change states of the sense current and the main current are as shown in FIG.
As shown in the curves (c) of (a) and (b).

As described above, in the lateral IGBT according to the present embodiment, when the current control is performed, the main current and the sense current can be changed with time regardless of which curve (b) to (c) the curve follows. As the rising curve of a similar shape is drawn according to the progress, when the main current reaches the specified value of 1A,
The sense current also reaches the same specified value of 1 mA,
As a result, highly accurate current control is performed.

Next, FIGS. 3A and 3B are configuration diagrams showing the configuration of a second embodiment of the lateral semiconductor device according to the present invention, wherein FIG. 3A is a top view and FIG. FIG. 6 is a cross-sectional view of one semiconductor unit cell in the lateral direction, showing an example in which a lateral semiconductor device constitutes an IGBT.

In FIGS. 3A and 3B, 7a is the first
, A second gate electrode lead-out portion,
12-1 is a first gate line (control line), 12-2
Is a second gate line (control line), and the same components as those shown in FIGS. 1A and 1B are denoted by the same reference numerals.

The difference between the configuration of the second embodiment and the configuration of the first embodiment is that the first embodiment has first and second sense unit cells at the right end and the left end of the lateral IGBT, respectively. Whereas the second embodiment is provided with a horizontal IG
The first sense unit cell IGBT is provided only at the right end of the BT.
And that the gate line 12 is connected to the gate electrode lead-out portion 7a in the vicinity of the first sense portion unit cell at the right end of the lateral IGBT in the first embodiment. In the embodiment, the first gate line 12-1 is connected to the first gate electrode lead-out portion 7a near the first sense portion unit cell at the right end of the lateral IGBT, and the lateral IGBT is connected.
It is only that the second gate line 12-2 is connected to the second gate electrode lead-out portion 7b in the vicinity of the IGBT unit cell (main portion unit cell) at the left end of T. In addition, the second embodiment There is no structural difference between the example and the first embodiment.

The outline of the switching operation of the lateral IGBT having the above-mentioned structure is essentially the lateral IGBT of the first embodiment.
The switching operation in the lateral IGBT according to the second embodiment is omitted because it is the same as the switching operation in the above.

In the current control operation of the lateral IGBT according to the second embodiment, when the gate signal is supplied via the first and second gate lines 12-1 and 12-2, the first sense signal is supplied. The sub unit cell is directly connected to the first gate line 12-1, and the left main unit cell of the lateral IGBT is also directly connected to the second gate line 12-2. However, at the same time, some main unit cells near the first sense unit cell, for example, about half of all sense unit cells and the lateral IG.
Some main unit cells near the left main unit cell of the BT, for example, about half of the remaining main unit cells, turn on in the same short time. As described above, in the second embodiment, the first sense unit cells and most of the main unit cells of the entire main unit cells are supplied within a short time after the gate signal is supplied. Since both of them are turned on, the time change of the main current almost follows the time change of the sense current, and the main current and the sense current correspond to the passage of time, and are roughly shown in FIG. As a result, a similar rising curve is drawn along the ideal change state indicated by the dotted line in b), and when the main current reaches the specified value of 1 A, the sense current is also specified. The value reaches 1 mA, and high-precision current control is performed as in the first embodiment.

Next, FIGS. 4A and 4B are structural views showing the structure of a third embodiment of the lateral semiconductor device according to the present invention, in which FIG. 4A is a top view and FIG. FIG. 6 is a cross-sectional view of one semiconductor unit cell in the lateral direction, showing an example in which a lateral semiconductor device constitutes an IGBT.

In FIGS. 4A and 4B, FIG.
The same components as those shown in (a) and (b) are designated by the same reference numerals.

The difference between the configurations of the third embodiment and the second embodiment is that the second embodiment has the first gate in the vicinity of the first sense section unit cell at the right end of the lateral IGBT. The electrode lead-out portion 7a and the left end IGBT of the lateral IGBT
Second near the T unit cell (main unit cell)
The first and second gate electrode lead-out portions 7b of both
While the gate lines 12-1 and 12-2 are connected, the third embodiment does not have the first gate line 12-1 (the first gate electrode lead-out portion 7a has nothing. (Not connected), the second gate line 12-2 is connected to the second gate electrode lead-out portion 7b in the vicinity of the leftmost IGBT unit cell (main unit cell) of the lateral IGBT, Other than that, there is no structural difference between the third embodiment and the second embodiment.

The outline of the switching operation of the lateral IGBT having the above-described structure is essentially the same as the switching operation of the lateral IGBT of the first and second embodiments.
The description of the switching operation in the lateral IGBT according to the third embodiment is also omitted.

Further, the current control operation in the lateral IGBT of the third embodiment is performed by the left end main unit unit of the lateral IGBT in the first period when the gate signal is supplied through the second gate line 12-2. Since the cell is directly connected to the second gate line 12-2, it immediately turns on, and at the same time, some main unit cells near the left main unit cell of this lateral IGBT, such as the main unit cell, are connected. About half of the unit cells turn on as well. However, during the first period, the sense unit cell at the right end of the lateral IGBT is not turned on because it is far from the connection point of the second gate line 12-2, and is close to the sense unit cell. Some main unit cells in, for example, about half of the main unit cells are not turned on. Then, when time passes and the second period following the first period is entered, the main unit cells that have not been turned on are sequentially turned on,
Finally, the sense unit cell is turned on. In this case, since the sense unit cell is in the OFF state during the first period and no sense current is generated,
The current flowing through about half the main unit cells in the ON state is not suppressed by the sense current, and the sense unit cells are in the ON state during the second period to generate the sense current. However, at this point, all the main unit cells are in the ON state.
After the sense current is generated, the temporal change of the main current almost follows the temporal change of the sense current. The main current and the sense current correspond to the passage of time, and the schematic diagram shown in FIG. When the main current reaches the specified value of 1 A as a result, it follows a similar rising curve along the ideal change state shown by the dotted lines in (a) and (b). The sense current also reaches the same specified value of 1 mA, and high-precision current control is performed as in the first embodiment.

In the third embodiment, the main current has already flowed before the sense current is generated. Therefore, in some cases, the current value of all the main currents is generated when the sense current is generated. It is necessary to provide some means to prevent the growth of. As such means, for example, the detection current value of the main current in the current detection circuit (not shown) is set to a value lower than the normal value, and when the total main current reaches the detection current value, the total main current is A means or the like may be used for suppressing the increase.

Next, FIGS. 5A and 5B are structural views showing the structure of a fourth embodiment of the lateral semiconductor device according to the present invention, in which FIG. 5A is a top view and FIG. FIG. 6 is a cross-sectional view of one semiconductor unit cell in the lateral direction, showing an example in which a lateral semiconductor device constitutes an EST.

In FIGS. 5A and 5B, 3'is a floating region (second semiconductor region) having an n-type high impurity concentration (n +), and 4'is an anode region having a p-type high impurity concentration (p +) ( Third semiconductor region) 5'is a cathode electrode, 6'is an anode electrode, 13 is a p-type high impurity concentration (p +) semiconductor region (fourth semiconductor region), and 14 is an n-type high impurity concentration (n +) semiconductor. The region (fifth semiconductor region) and the other components shown in FIG. 1 are denoted by the same reference numerals.

On one main surface of the n-type semiconductor substrate 1, the p-type well region 2 and the p-type anode region 4'are selectively formed so as to be separated from each other, and the p-type well region 2 is adjacent to the p-type well region 2. The semiconductor region 13 is selectively formed. An n-type floating region 3'is selectively formed on the surface of the p-type well region 2, and an n-type semiconductor region 14 is selectively formed on each surface of the p-type well region 2 and the p-type semiconductor region 13. A cathode electrode 5 ′ is arranged in contact with each surface of the p-type semiconductor region 13 and the n-type semiconductor region 14, and a p-type anode region 4 ′ is provided.
An anode electrode 6'is arranged in contact with the surface of the. Over the main surface of the n-type semiconductor substrate 1, the surface of the p-type well region 2 and the surface of the n-type floating region 3 ′, and the surface of the n-type floating region 3 ′, the surface of the p-type well region 2 and the n-type semiconductor. The insulating film 8 is formed over the surface of the region 14 respectively.
The gate electrode 7 is disposed via the insulating layer 9 and the insulating layer 9 is disposed between the cathode electrode 5 ′ and the gate electrode 7 and between the anode electrode 6 ′ and one main surface of the n-type semiconductor substrate 1. It In this case, the cathode electrode 5 ′ and the anode electrode 6 ′ are configured so as to have a comb shape as a whole when viewed from the upper surface of the EST, and the tooth portions of the cathode electrode 5 ′ and the anode electrode 6 ′ mesh with each other. It is arranged in a state. The gate electrode 7 is also configured so as to have a comb shape as a whole when viewed from the upper surface of the EST. Here, a portion surrounded by a frame B shown in FIG. 5A is an EST unit (unit) cell, and the plurality of EST unit cells B have their directions reversed to each other, that is, in a meandering lateral direction. Are continuously formed and arranged, and a large number of these EST unit cells B are combined to form a substantially rectangular lateral EST. In addition,
Although not shown in FIG. 5A, a sense terminal and a gate terminal (control terminal) are provided on one end surface portion of the short side of the horizontal EST.
Is provided, and at the same time, an anode terminal and a cathode terminal are also provided.

As shown in FIG. 5A, the rightmost EST unit cell of the lateral EST constitutes a sense unit cell, and the remaining many EST unit cells are main unit cells. In the sense unit cell, a part of the cathode electrode 5 ′ in the longitudinal direction is arranged so as to be separated from each other, and this separated part serves as the current detection sense electrode 10. In this case, each sense electrode 10 is connected to the sense terminal via a sense line 11.
On the other hand, as shown in FIG. 5A, the gate electrode 7 is the rightmost EST unit cell (sense unit cell).
A gate electrode lead-out portion 7a is provided in the vicinity, and this gate electrode lead-out portion 7a is connected to the gate terminal via a gate line 12.

Here, the p-type anode regions 4 ', n
The portion composed of the type semiconductor substrate 1, the p-type well region 2, and the n-type floating region 3 ′ constitutes a thyristor portion T,
The portion formed of the p-type well region 2, the n-type floating region 3 ′, the n-type semiconductor region 14, and the n-type semiconductor substrate 1 is M
It constitutes the OSFET section M. That is, this EST is
It is a composite body composed of a thyristor part T and a MOSFET part M.

Further, when the sense electrode 10 is provided in a specific EST unit cell B to form the sense unit cell, the place where the sense electrode 10 is provided is in the thyristor T or in the MOSFET M. There are two ways. In this case, when it is provided in the thyristor portion T, the sense electrode 10 may be placed in contact with each surface of the p-type semiconductor region 13 and the n-type semiconductor region 14, and
When it is provided in the FET part M, it may be disposed in contact only with the surface of the n-type semiconductor region 14. And the thyristor part T
In the case of the above, the ratio of the length in the electrode longitudinal direction of the portion of the cathode electrode 5 ′ in all the main unit cells contacting the n-type semiconductor region 14 and the p-type semiconductor region to that of the sense electrode 10 in the sense unit cell is set. There is an advantage that the proportional current can be extracted accurately,
On the other hand, when it is provided in the MOSFET part M, although the proportional current cannot be taken out, it is a parasitic composed of the p-type anode region 4 ′, the n-type semiconductor substrate 1, the p-type semiconductor region 13, and the n-type semiconductor region 14. It has the advantage that it is less susceptible to current fluctuations due to thyristors.

An outline of the horizontal EST having the above-mentioned structure is as follows.
The required switching operation is achieved by the following process. That is, when a predetermined voltage is applied between the anode electrode 6'and the cathode electrode 5 ', the gate (control) is applied to the gate electrode 7 at a predetermined threshold value or more than the applied voltage of the cathode electrode 5'. When no voltage is applied, MOSFE
The T section M is in an off state, and the thyristor section T is also in an off state in which no forward current flows. When a gate voltage above the predetermined threshold value is applied to the gate electrode 7, M
An n-type channel is formed in each of the p-type well regions 2 below the two gate electrodes 7 in the OSFET portion M, so that an electron flow from the n-type semiconductor region 14 to one n-type channel, n-type flow. Flowing through the n-type semiconductor substrate 1 through the n-type channel and the other n-type channel.
It is injected into the n-type semiconductor substrate 1 from the type anode region 4 ′ and collected in the p-type well region 2. At this time, the p-type well region 2 is formed with a low impurity concentration,
Since it has a high sheet resistance (lateral resistance), the pn junction formed by the p-type well region 2 and the n-type semiconductor substrate 1 is forward biased, and the MOSFET section M is turned on. When the MOSFET section M turns on, the electron flow flowing into the n-type semiconductor substrate 1 and the holes injected into the n-type semiconductor substrate 1 increase, and the thyristor section T also turns on. On the other hand, if the supply of the gate voltage to the gate electrode 7 is stopped while the EST is on, the MOSFE
2 formed in the p-type well region 2 in the T portion M
Since the two n-type channels disappear, which blocks the flow of electron flow into the n-type semiconductor substrate 1, the MOSF
Since the ET portion M is turned off and the supply of holes injected into the n-type semiconductor substrate 1 is stopped, the thyristor portion T is also turned off. Thus, this EST is
ON / OFF is controlled by the gate voltage applied to the gate electrode 7.

Regarding the current control operation in this EST, this EST connects the sense line 11 to the EST unit cell (sense section unit cell) at the right end of the EST, and further, the gate in the vicinity of the sense section unit cell. Since the structure is such that the gate line 12 is connected to the electrode lead-out portion 7a, the operating characteristic is basically similar to the operating characteristic at the time of turn-on of the known lateral IGBT described above. Due to such operation characteristics, the relationship between the main current of the EST and the sense current is such that the main current sequentially increases as the sense current increases as shown in FIGS. Before reaching a specified value, for example, 1 A, the sense current reaches the specified value, and the main current is suppressed to about 0.7 A, which is less than the specified value.

However, also in this EST, as shown in the first embodiment, the IG at the right end and the left end of the EST
A configuration in which the BT unit cells are changed to be the first and second sense unit cells and the first sense line and the second sense line are separately connected to these first and second sense unit cells Or in the vicinity of the sense unit cell as shown in the second embodiment (first
(In) gate electrode lead-out portion 7a (first) gate line 1
2-1 is also connected to the second gate electrode lead-out portion 7b near the EST unit cell at the left end of the EST.
Or the gate line 12 or the first gate line 12-1 is omitted as shown in the third embodiment.
If the second gate line 12-2 is connected only to the second gate electrode lead-out portion 7b near the EST unit cell at the left end of T, the current control operation in each of the embodiments will be described. As described above, the main current and the sense current of the EST are shown in FIG.
When the main current reaches the specified value of 1 A, the sense current also rises when the main current reaches the specified value of 1 A along the ideal change state indicated by the dotted lines in (a) and (b). As the current reaches the same specified value of 1 mA, the first to third
High-precision current control is performed in the same manner as in the above embodiment.

As described above, according to the fourth embodiment, it is possible to realize the addition of the sense function which has not been considered at all in the EST up to now, and the addition of the sense function allows the load current withstand capability. It becomes possible to limit the output current of the EST accordingly.

Also in the fourth embodiment, the relationship between the main current and the sense current is required by selecting the arrangement and connection configuration of the sense line 11 and the gate lines 12, 12-1, 12-2. It becomes possible to perform high-precision current control by setting the state.

The EST gate electrodes 7 are doubly arranged on both sides of the n-type floating region 3 ', and
Since the area is larger and the stray capacitance component is larger than that of the single-layered gate electrodes, the EST unit cells are strongly affected by the turn-on time difference. Therefore, in the EST, as described above, by selecting the arrangement and connection configuration of the sense line 11 and the gate lines 12, 12-1, 12-2, the relationship between the main current and the sense current is brought into a desired state. By performing the high-accuracy current control as described above, it is significantly effective as compared with the case where the high-accuracy current control is performed in the IGBT or the like.

By the way, in the above embodiments,
Although the case where the lateral semiconductor device is a lateral IGBT or a lateral EST has been described as an example, the lateral semiconductor device of the present invention is not limited to the lateral IGBT and the lateral EST, and other devices such as a lateral MOSFET. May be

[0067]

As described above, according to the present invention,
The sense electrode 10 is arranged in a part of one or a plurality of semiconductor unit cells among a large number of semiconductor unit cells,
The sense electrode 10 is connected to the sense line 11, and the control line 12 is connected to the control electrode 7 of one or a plurality of semiconductor unit cells among a large number of semiconductor unit cells. Part unit cell) placement location or control line 12
The arrangement location of the semiconductor unit cell having the control electrode 7 connected to is properly selected.

Therefore, when the control signal is supplied to the control line 12, the turn-on time of some of the remaining semiconductor unit cells (main unit cells) is delayed from the turn-on time of the sense unit cells. Can be significantly reduced compared to known lateral semiconductor devices of this type, whereby the increase of the main current of the lateral semiconductor device is not suppressed before reaching a specified value, and the current of the lateral semiconductor device is also suppressed. There is an effect that the control can be performed with high accuracy. In addition to this, since the margin for defining the current rating can be reduced, the area occupied in the integrated circuit device of the lateral semiconductor device is also reduced, which has the secondary effect of being economical. is there.

Further, according to the present invention, the EST is formed laterally and the sense electrode 10 is arranged in one or a plurality of EST unit cells.

Therefore, it is possible to obtain the EST having the sensing function, and it is possible to limit the output current value of the EST in accordance with the withstand current of the external load.

In this case, the EST is arranged so as to be insulated on both sides of the second semiconductor region 3'where the gate electrode 7 is in a floating state, and the area of the gate electrode 7 is wider than the area of the gate electrode such as the IGBT. By appropriately selecting the arrangement location of the EST unit cell (sense unit cell) having the sense electrode 10 or the connection location of the gate line 12, the remaining semiconductor unit cells (main unit cell) for the turn-on time of the sense unit cell ), The turn-on time delay of some of the
The increase in the main current is not suppressed before reaching the specified value, and the current control of the horizontal EST can be performed with high accuracy.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of a first embodiment of a lateral semiconductor device according to the present invention.

FIG. 2 is a characteristic diagram showing a temporal change state of a main current and a sense current when the lateral IGBT of the embodiment shown in FIG. 1 is turned on.

FIG. 3 is a configuration diagram showing a configuration of a second embodiment of a lateral semiconductor device according to the present invention.

FIG. 4 is a configuration diagram showing a configuration of a third embodiment of a lateral semiconductor device according to the present invention.

FIG. 5 is a configuration diagram showing a configuration of a fourth embodiment of a lateral semiconductor device according to the present invention.

FIG. 6 is a configuration diagram showing an example of a configuration of a known lateral IGBT.

FIG. 7 is a cross-sectional view showing an example of the configuration of a known EST.

8 is a characteristic diagram showing a temporal change state of a main current and a sense current when the known lateral IGBT shown in FIG. 6 is turned on.

[Description of Reference Signs] 1 n-type low impurity concentration (n−) semiconductor substrate 2 p-type well region (first semiconductor region) 3 n-type high impurity concentration (n +) emitter region (second semiconductor region) 3 ′ n Type high impurity concentration (n +) floating region (second semiconductor region) 4 p-type high impurity concentration (p +) collector region (third semiconductor region) 4 ′ p-type high impurity concentration (p +) anode region (third)
Semiconductor region) 5 emitter electrode (first main electrode) 5'cathode electrode (first main electrode) 6 collector electrode (second main electrode) 6'anode electrode (second main electrode) 7 gate electrode (control electrode) 7a gate Electrode leading part (first gate electrode leading part) 7a Second gate electrode leading part 8 Insulating film 9 Insulating layer 10 Sense electrode 11 Sense line 12 Gate line (control line) 12-1 First gate line 12-2 No. 2 gate line 13 p-type high impurity concentration (p +) semiconductor region (fourth semiconductor region) 14 n-type high impurity concentration (n +) semiconductor region (fifth semiconductor region)

Claims (8)

[Claims] 1. A semiconductor substrate of a first conductivity type, a first semiconductor region of a second conductivity type selectively arranged on one main surface of the semiconductor substrate, and a first semiconductor region selectively arranged on the surface of the first semiconductor region. A second semiconductor region of one conductivity type; a third semiconductor region of high impurity concentration of the second conductivity type, which is selectively arranged on one main surface of the semiconductor substrate and spaced apart from the first semiconductor region; A control electrode disposed over the main surface, the surface of the first semiconductor region, and a surface of the second semiconductor region with an insulating layer interposed therebetween; a first main electrode disposed in contact with the surface of the second semiconductor region; 3. A horizontal semiconductor device in which a plurality of semiconductor unit cells each including a second main electrode arranged in contact with the surface of the semiconductor region are arranged in a zigzag manner in the lateral direction, and a control terminal and a sense terminal are provided on one end face of the device. And one or more Controlling one or a plurality of semiconductor unit cells by partially arranging a first main electrode of the semiconductor unit cell in a longitudinal direction to form a sense electrode and connecting the sense electrode and the sense terminal with a sense line. A lateral semiconductor device, wherein an electrode and the control terminal are connected by a control line. 2. The lateral semiconductor device according to claim 1, wherein the plurality of semiconductor unit cells having the sense electrodes are arranged apart from each other. 3. The lateral semiconductor device according to claim 1, wherein the plurality of semiconductor unit cells in which the control lines are connected to the control electrodes are arranged apart from each other. 4. The lateral semiconductor device according to claim 2, wherein the plurality of semiconductor unit cells are provided at both ends of the semiconductor unit cells arranged in a lateral direction. 5. The lateral semiconductor device according to claim 1, wherein the lateral semiconductor device is an insulated gate bipolar transistor (IGBT). 6. A semiconductor substrate of a first conductivity type, a first semiconductor region of a second conductivity type selectively arranged on one main surface of the semiconductor substrate, and a first semiconductor region selectively arranged on the surface of the first semiconductor region. A second semiconductor region of one conductivity type; a third semiconductor region of high impurity concentration of the second conductivity type, which is selectively arranged on one main surface of the semiconductor substrate and spaced apart from the first semiconductor region; A fourth semiconductor region having a second conductivity type and a high impurity concentration, which is selectively arranged on the main surface adjacent to the first semiconductor region;
A fifth semiconductor region of a first conductivity type and a high impurity concentration, which is selectively arranged on each surface of the first semiconductor region and the fourth semiconductor region, one main surface of the semiconductor substrate, a surface of the first semiconductor region, and Over the surface of the second semiconductor region, and
Control electrodes arranged over the surface of the second semiconductor region, the surface of the first semiconductor region, and the surface of the fifth semiconductor region via insulating layers, and the fourth semiconductor region and the fifth semiconductor region, respectively. A plurality of semiconductor unit cells, each of which has a first main electrode arranged in contact with the surface and a second main electrode arranged in contact with the surface of the third semiconductor region, are arranged in a zigzag manner in the lateral direction, and one end of the device is provided. A lateral semiconductor device having a control terminal and a sense terminal on a surface thereof. 7. The lateral semiconductor device forms a sense electrode by partially arranging first main electrodes of one or a plurality of semiconductor unit cells in a longitudinal direction so that the sense electrode and the sense terminal are separated from each other. Connect with a sense line, 1
7. The lateral semiconductor device according to claim 6, wherein the control electrode of one or a plurality of semiconductor unit cells and the control terminal are connected by a control line. 8. The lateral semiconductor device according to claim 6, wherein the lateral semiconductor device is an emitter-switched thyristor (EST).