JP2012123142A - Method for manufacturing electro-optic device and electro-optic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing an electro-optic device capable of preventing generation of electrostatic breakdown even when a high dielectric constant insulating film is used for a dielectric layer and dry etching is employed for etching the high dielectric constant insulating film or the like, and to provide an electro-optic device manufactured by the method.SOLUTION: In manufacturing a liquid crystal device 100, a dielectric material layer 42a is formed in a predetermined region in a step of forming a high dielectric constant insulating film and a step of patterning the high dielectric constant insulating film, then a capacitor line 5b (second electrode) is formed in a step of forming a conductive film for forming a second electrode and a step of patterning the conductive film for forming a second electrode. Thus, a high dielectric constant insulating film 42 as formed in a wide area is subjected to plasma in dry etching only in the step of patterning the high dielectric constant insulating film, and the film has already been patterned in the step of patterning the conductive film for forming the second electrode.

Description

  The present invention relates to a method for manufacturing an electro-optical device having a capacitive element on one side of a substrate for an electro-optical device, and an electro-optical device manufactured by the method.

  In an electro-optical device such as a liquid crystal device or an organic electroluminescence device, a capacitive element in which a first electrode, a dielectric layer, and a second electrode are stacked is formed on one surface side of an element substrate (electro-optical device substrate). (Patent Documents 1 and 2).

  When forming such a capacitive element, in the technique described in Patent Document 1, first, after forming the first electrode, a dielectric film is formed, and the dielectric film is patterned by etching to form a dielectric layer. ing. Next, after forming a second electrode forming conductor film for forming the second electrode, the second electrode forming conductor film is patterned by etching to form a second electrode. Here, the dielectric film and the second electrode are patterned with different planar shapes.

  In the technique described in Patent Document 2, dry etching is employed for etching the dielectric film and the second electrode forming conductor film, and the first electrode forming conductor film for forming the first electrode is used. After the dielectric film and the second electrode forming conductor film are formed in this order, the plurality of layers are collectively patterned by dry etching to form a capacitive element.

JP 2005-128299 A JP 2005-128309 A

  However, when the method of collectively patterning the first electrode forming conductor film, the dielectric film, and the second electrode forming conductor film by dry etching as in the invention described in Patent Document 2, the dielectric The body film and the second electrode forming conductor film are dry-etched while being formed over a wide range. Therefore, for the purpose of increasing the capacitance per unit area of the capacitive element, if a high dielectric constant insulating film having a dielectric constant higher than that of the silicon oxide film is used as the dielectric film, plasma generated during dry etching is used. For this reason, there is a problem in that large charges are accumulated in the high dielectric constant insulating film and electrostatic breakdown occurs.

  In view of the above problems, the object of the present invention is to prevent the occurrence of electrostatic breakdown even when a high dielectric constant insulating film is used for the dielectric layer and dry etching is employed for etching the high dielectric constant insulating film or the like. It is an object of the present invention to provide a method for manufacturing an electro-optical device, and an electro-optical device manufactured by the method.

  In order to solve the above-described problems, the present invention provides a method for manufacturing an electro-optical device including a capacitive element in which a first electrode, a dielectric layer, and a second electrode are stacked on one side of a substrate for an electro-optical device. Forming a high dielectric constant insulating film having a dielectric constant higher than that of a silicon oxide film on the upper layer side of the first electrode; and patterning the high dielectric constant insulating film by dry etching to form the dielectric A high dielectric constant insulating film patterning step for forming a layer, a second electrode forming conductive film forming step for forming a second electrode forming conductor film for forming the second electrode, and the second electrode forming step And a conductive film patterning step for forming a second electrode by patterning the conductive film by dry etching.

  In the present invention, after the dielectric layer is formed in a predetermined region by the high dielectric constant insulating film forming step and the high dielectric constant insulating film patterning step, the second electrode forming conductive film forming step and the second electrode forming conductive film patterning step are performed. To form a second electrode. Therefore, the high dielectric constant insulating film is subjected to plasma in a state where it is formed over a wide area only during the high dielectric constant insulating film patterning process, and at the time of performing the second electrode forming conductive film patterning process. Already patterned. For this reason, even when a high dielectric constant insulating film is used for the dielectric layer, it is possible to suppress the charge accumulated in the high dielectric constant insulating film (dielectric layer) by the plasma during dry etching. Occurrence can be prevented.

  In the present invention, an etching mask formed on the surface of the high dielectric constant insulating film when the high dielectric constant insulating film patterning step is performed, and the second electrode formation when the second electrode forming conductive film patterning step is performed. It is preferable to form the etching mask formed on the surface of the conductive film in the same region with the same planar shape. According to this configuration, the exposure mask used for forming the etching mask used in the high dielectric constant insulating film patterning process by the photolithography technique and the etching mask used in the second electrode forming conductive film patterning process are formed by the photolithography technique. The same exposure mask can be used. Therefore, even when the high dielectric constant insulating film patterning step and the second electrode forming conductive film patterning step are performed as separate steps, an increase in manufacturing cost can be minimized.

  In the present invention, the high dielectric constant insulating film includes at least one oxide film of an aluminum oxide film, a titanium oxide film, a tantalum oxide film, a niobium oxide film, a hafnium oxide film, a lanthanum oxide film, and a zirconium oxide film. A configuration can be employed. If such a high dielectric constant insulating film is used, the capacitance per unit area of the capacitive element can be increased.

  In the present invention, before performing the high dielectric constant insulating film forming step, an etching stopper insulating film forming step of forming an etching stopper insulating film on the upper layer side of the first electrode, and etching the etching stopper insulating film And performing an etching stopper insulating film patterning step of partially exposing the first electrode and leaving the etching stopper insulating film as an etching stopper layer in a region overlapping with an edge of the second electrode. preferable. According to this configuration, since the etching stopper layer is formed in the region overlapping with the edge of the second electrode, the lower layer side of the second electrode is etched by overetching when performing the conductive film patterning process for forming the second electrode. However, a short circuit between the second electrode and the first electrode does not occur.

  Alternatively, after performing the high dielectric constant insulating film patterning step and before performing the second electrode forming conductive film forming step, an etching stopper insulating film is formed on the upper side of the dielectric layer. A film forming step, etching the etching stopper insulating film to partially expose the dielectric layer, and leaving the etching stopper insulating film as an etching stopper layer in a region overlapping with an edge of the second electrode; It is preferable to perform an insulating film patterning process for an etching stopper. According to this configuration, since the etching stopper layer is formed in the region overlapping with the edge of the second electrode, the lower layer side of the second electrode is etched by overetching when performing the conductive film patterning process for forming the second electrode. However, a short circuit between the second electrode and the first electrode does not occur.

  The electro-optical device manufacturing method according to the present invention can be applied to various electro-optical device manufacturing methods such as a liquid crystal device manufacturing method and an organic electroluminescence device manufacturing method. Among these electro-optical devices, when the present invention is applied to a method of manufacturing a liquid crystal device, the electro-optical device substrate is used as at least one of a pair of liquid crystal device substrates facing each other through a liquid crystal layer in the liquid crystal device. .

It is a block diagram which shows the electric constitution of the liquid crystal device to which this invention is applied. It is explanatory drawing of the liquid crystal panel used for the liquid crystal device which concerns on Embodiment 1 of this invention. It is explanatory drawing of the pixel of the liquid crystal device which concerns on Embodiment 1 of this invention. It is process sectional drawing which shows the principal part of the manufacturing process of the 1st board | substrate used for the liquid crystal device which concerns on Embodiment 1 of this invention. It is process sectional drawing which shows the principal part of the manufacturing process of the 1st board | substrate used for the liquid crystal device which concerns on Embodiment 1 of this invention. It is sectional drawing of the pixel of the liquid crystal device which concerns on Embodiment 2 of this invention. It is sectional drawing of the pixel of the liquid crystal device which concerns on Embodiment 3 of this invention. It is process sectional drawing which shows the principal part of the manufacturing process of the 1st board | substrate used for the liquid crystal device which concerns on Embodiment 3 of this invention. It is a schematic block diagram of the projection type display apparatus using the liquid crystal device to which this invention is applied.

  Embodiments of the present invention will be described with reference to the drawings. In the following description, the case where the present invention is applied to a liquid crystal device and a manufacturing method thereof among various electro-optical devices will be mainly described. In the drawings referred to in the following description, the scales are different for each layer and each member so that each layer and each member have a size that can be recognized on the drawing.

[Embodiment 1]
(overall structure)
FIG. 1 is a block diagram showing an electrical configuration of a liquid crystal device (electro-optical device) to which the present invention is applied. In FIG. 1, a liquid crystal device 100 has a liquid crystal panel 100p in a TN (Twisted Nematic) mode or a VA (Vertical Alignment) mode, and the liquid crystal panel 100p has a plurality of pixels 100a arranged in a matrix in the central region. The pixel area 10a (image display area) is provided. In the liquid crystal panel 100p, on the first substrate 10 (see FIG. 2 and the like) described later, a plurality of data lines 6a and a plurality of scanning lines 3a extend vertically and horizontally inside the pixel region 10a, and at the intersections thereof. A pixel 100a is configured at a corresponding position. In each of the plurality of pixels 100a, a pixel transistor 30 made of a field effect transistor and a pixel electrode 9a described later are formed. The data line 6 a is electrically connected to the source of the pixel transistor 30, the scanning line 3 a is electrically connected to the gate of the pixel transistor 30, and the pixel electrode 9 a is electrically connected to the drain of the pixel transistor 30. Has been.

  In the first substrate 10, a scanning line driving circuit 104 and a data line driving circuit 101 are provided on the outer peripheral side of the pixel region 10a. The data line driving circuit 101 is electrically connected to each data line 6a, and sequentially supplies the image signal supplied from the image processing circuit to each data line 6a. The scanning line driving circuit 104 is electrically connected to each scanning line 3a, and sequentially supplies a scanning signal to each scanning line 3a.

  In each pixel 100a, the pixel electrode 9a is opposed to a common electrode formed on a second substrate 20 (see FIG. 2 and the like), which will be described later, via a liquid crystal layer, and constitutes a liquid crystal capacitor 50a. Each pixel 100a is provided with a holding capacitor 55 (capacitance element) in parallel with the liquid crystal capacitor 50a in order to prevent fluctuations in the image signal held in the liquid crystal capacitor 50a. In this embodiment, in order to form the storage capacitor 55, the capacitor line 5b extending in parallel with the scanning line 3a is formed across the plurality of pixels 100a, and the common potential Vcom is applied to the capacitor line 5b. The common potential line 5c is electrically connected.

(Configuration of the liquid crystal panel 100p)
FIG. 2 is an explanatory diagram of the liquid crystal panel 100p used in the liquid crystal device 100 according to Embodiment 1 of the present invention. FIGS. 2A and 2B are respectively liquid crystals of the liquid crystal device 100 to which the present invention is applied. It is the top view which looked at the panel 100p from the 2nd board | substrate side with each component, and its HH 'sectional drawing.

  As shown in FIGS. 2A and 2B, in the liquid crystal panel 100p, a first substrate 10 (electro-optical device substrate / liquid crystal device substrate) as an element substrate and a second substrate 20 (an opposite substrate) ( A liquid crystal device substrate) is bonded to a sealing material 107 through a predetermined gap, and the sealing material 107 is provided in a frame shape along the outer edge of the second substrate 20. The sealing material 107 is an adhesive made of a photo-curing resin, a thermosetting resin, or the like, and is mixed with a gap material such as glass fiber or glass beads for setting the distance between both substrates to a predetermined value.

  In the liquid crystal panel 100p having such a configuration, the first substrate 10 and the second substrate 20 are both square, and the pixel area 10a described with reference to FIG. 1 is provided as a square area in the approximate center of the liquid crystal panel 100p. It has been. Corresponding to this shape, the sealing material 107 is also provided in a substantially rectangular shape, and a substantially rectangular peripheral region 10b is provided in a frame shape between the inner peripheral edge of the sealing material 107 and the outer peripheral edge of the pixel region 10a. . In the first substrate 10, the data line driving circuit 101 and the plurality of terminals 102 are formed along one side of the first substrate 10 outside the pixel region 10 a, and scanning is performed along another side adjacent to the one side. A line driving circuit 104 is formed. Note that a flexible wiring substrate (not shown) is connected to the terminal 102, and various potentials and various signals are input to the first substrate 10 through the flexible wiring substrate.

  As will be described in detail later, in the substrate surface on one side of the first substrate 10, the pixel transistor 10 described with reference to FIG. 1 and the pixel electrode 9a electrically connected to the pixel transistor 30 are provided in the pixel region 10a. An alignment film 16 is formed on the upper layer side of the pixel electrode 9a.

  In addition, on one side of the first substrate 10, a dummy pixel electrode 9b (see FIG. 2B) that is formed simultaneously with the pixel electrode 9a is formed in the peripheral region 10b. For the dummy pixel electrode 9b, a configuration in which the dummy pixel transistor is electrically connected, a configuration in which the dummy pixel transistor is not provided, and a configuration in which the dummy pixel electrode is directly electrically connected to the wiring, or a floating state in which no potential is applied The structure which exists in is adopted. The dummy pixel electrode 9b compresses the height positions of the pixel region 10a and the peripheral region 10b when the surface on which the alignment film 16 is formed on the first substrate 10 is flattened by polishing, so that the alignment film 16 is formed. This contributes to a flat surface. Further, if the dummy pixel electrode 9b is set to a predetermined potential, it is possible to prevent the disorder of the alignment of the liquid crystal molecules at the outer peripheral side end of the pixel region 10a.

  A common electrode 21 is formed on one surface of the second substrate 20 facing the first substrate 10, and an alignment film 26 is formed on the common electrode 21. The common electrode 21 is formed across the plurality of pixels 100a as substantially the entire surface of the second substrate 20 or as a plurality of strip electrodes. Further, a light shielding layer 108 is formed on the lower layer side of the common electrode 21 on one surface side of the second substrate 20 facing the first substrate 10. In this embodiment, the light shielding layer 108 is formed in a frame shape extending along the outer peripheral edge of the pixel region 10a, and functions as a parting. Here, the outer peripheral edge of the light shielding layer 108 is located with a gap between the inner peripheral edge of the sealing material 107 and the light shielding layer 108 and the sealing material 107 do not overlap. In the second substrate 20, the light shielding layer 108 may be formed in a region that overlaps with a region sandwiched between adjacent pixel electrodes 9a.

  In the liquid crystal panel 100p configured as described above, the first substrate 10 is electrically connected between the first substrate 10 and the second substrate 20 in a region overlapping the corner portion of the second substrate 20 outside the sealant 107. An inter-substrate conducting electrode 109 for conducting is formed. The inter-substrate conducting electrode 109 is provided with an inter-substrate conducting material 109 a containing conductive particles, and the common electrode 21 of the second substrate 20 is interposed between the inter-substrate conducting material 109 a and the inter-substrate conducting electrode 109. Thus, it is electrically connected to the first substrate 10 side. For this reason, the common potential Vcom is applied to the common electrode 21 from the first substrate 10 side.

  The sealing material 107 is provided along the outer peripheral edge of the second substrate 20 with substantially the same width dimension. For this reason, the sealing material 107 is substantially rectangular. However, the sealing material 107 is provided so as to pass inside avoiding the inter-substrate conduction electrode 109 in a region overlapping with the corner portion of the second substrate 20, and the corner portion of the sealing material 107 has a substantially arc shape.

  In the liquid crystal device 100 having such a configuration, when the pixel electrode 9a and the common electrode 21 are formed of a light-transmitting conductive film, a transmissive liquid crystal device can be configured. On the other hand, when the common electrode 21 is formed of a light-transmitting conductive film and the pixel electrode 9a is formed of a reflective conductive film, a reflective liquid crystal device can be configured. When the liquid crystal device 100 is of a reflective type, light incident from the second substrate 20 side is modulated while being reflected by the substrate on the first substrate 10 side and emitted, thereby displaying an image. When the liquid crystal device 100 is a transmissive type, the light incident from one of the first substrate 10 and the second substrate 20 is modulated while being transmitted through the other substrate, and an image is displayed. To do.

  The liquid crystal device 100 can be used as a color display device of an electronic device such as a mobile computer or a mobile phone. In this case, a color filter (not shown) and a protective film are formed on the second substrate 20. Further, in the liquid crystal device 100, the polarizing film, the retardation film, the polarizing plate, etc. have a predetermined orientation with respect to the liquid crystal panel 100p according to the type of the liquid crystal layer 50 to be used and the normally white mode / normally black mode. Placed in. Furthermore, the liquid crystal device 100 can be used as a light valve for RGB in a projection display device (liquid crystal projector) described later. In this case, each color liquid crystal device 100 for RGB receives light of each color separated through RGB color separation dichroic mirrors as projection light, so that no color filter is formed.

  In this embodiment, the liquid crystal device 100 is a transmissive liquid crystal device used as an RGB light valve in a projection display device described later, and light incident from the second substrate 20 is transmitted through the first substrate 10. The explanation will be focused on the case of emission. Further, in this embodiment, the liquid crystal device 100 will be described focusing on the case where the liquid crystal layer 50 includes a VA mode liquid crystal panel 100p using a nematic liquid crystal compound having a negative dielectric anisotropy.

(Specific pixel configuration)
FIG. 3 is an explanatory diagram of pixels of the liquid crystal device 100 according to Embodiment 1 of the present invention, and FIGS. 3A and 3B are respectively a first substrate used in the liquid crystal device 100 to which the present invention is applied. 10 is a plan view of adjacent pixels in FIG. 10 and a cross-sectional view when the liquid crystal device 100 is cut at a position corresponding to the line FF ′ in FIG. In FIG. 3A, the semiconductor layer 1a is indicated by a thin and short dotted line, the scanning line 3a is indicated by a thick solid line, the data line 6a and a thin film formed simultaneously with the data line 6a are indicated by an alternate long and short dash line, and the capacitor line 5b (holding) The second electrode of the capacitor 55 is indicated by a two-dot chain line, and the pixel electrode 9a is indicated by a thick and long broken line. In FIG. 3A, the lower electrode layer 4a (first electrode of the storage capacitor 55) and the opening 40b of the etching stopper layer 40a are indicated by a double thin solid line. Of these, the outer solid line corresponds to the formation region of the lower electrode layer 4a, and the inner solid line corresponds to the opening 40b of the etching stopper layer 40a. In addition, a dielectric layer 42a is formed in a region overlapping the capacitance line 5b indicated by a two-dot chain line.

  As shown in FIG. 3A, a rectangular pixel electrode 9a is formed on each of the plurality of pixels 100a on the first substrate 10, and data along the vertical and horizontal boundaries of each pixel electrode 9a. Lines 6a and scanning lines 3a are formed. Each of the data line 6a and the scanning line 3a extends linearly, and a pixel transistor 30 is formed in a region where the data line 6a and the scanning line 3a intersect. On the first substrate 10, a capacitor line 5b is formed so as to overlap the scanning line 3a. In this embodiment, the capacitor line 5b includes a main line portion extending linearly so as to overlap the scanning line 3a, and a sub-line portion extending so as to overlap the data line 6a at the intersection of the data line 6a and the scanning line 3a. It has.

  As shown in FIGS. 3A and 3B, the first substrate 10 is formed on the surface (one surface side) of the translucent substrate body 10w such as a quartz substrate or a glass substrate on the liquid crystal layer 50 side. The second substrate 20 is mainly composed of a pixel electrode 9a, a pixel transistor 30 for pixel switching, and an alignment film 16. The second substrate 20 is a translucent substrate body 20w such as a quartz substrate or a glass substrate, and the liquid crystal layer 50 side. The main electrode 21 and the alignment film 26 are mainly formed on the surface (one surface side facing the first substrate 10).

  In the first substrate 10, a pixel transistor 30 including the semiconductor layer 1a is formed in each of the plurality of pixels 100a. The semiconductor layer 1a includes a channel region 1g, a source region 1b, and a drain region 1c that are opposed to the gate electrode 3c, which is a part of the scanning line 3a, via the translucent gate insulating layer 2. The source region 1b and the drain region 1c each have a low concentration region and a high concentration region. The semiconductor layer 1a is composed of, for example, a polycrystalline silicon film or the like formed on a transparent base insulating film 12 made of a silicon oxide film or the like on the substrate body 10w, and the gate insulating layer 2 is formed by a CVD method or the like. The silicon oxide film and the silicon nitride film formed by the above. The gate insulating layer 2 may have a two-layer structure of a silicon oxide film obtained by thermally oxidizing the semiconductor layer 1a and a silicon oxide film or silicon nitride film formed by a CVD method or the like. For the scanning line 3a, a conductive polysilicon film, a metal silicide film, or a metal film is used.

  A translucent first interlayer insulating film 41 made of a silicon oxide film or the like is formed on the upper layer side of the scanning line 3a, and a lower electrode layer 4a (first electrode) is formed on the first interlayer insulating film 41. Is formed. The lower electrode layer 4a is formed in a substantially L-shape extending along the scanning line 3a and the data line 6a with a position where the scanning line 3a and the data line 6a intersect as a base point. The lower electrode layer 4a is made of a conductive polysilicon film, a metal silicide film, a metal film, or the like, and is electrically connected to the drain region 1c through the contact hole 7c.

  A dielectric layer 42a is formed on the upper layer side of the lower electrode layer 4a. Further, on the upper layer side of the dielectric layer 42a, a capacitor line 5b (second electrode) is formed so as to face the lower electrode layer 4a with the dielectric layer 42a interposed therebetween. The capacitor line 5b, the dielectric layer 42a, and A storage capacitor 55 is formed by the lower electrode layer 4a. The capacitor line 5b is made of a conductive polysilicon film, a metal silicide film, a metal film, or the like. In this embodiment, the capacitor line 5b is composed of a two-layer structure of an aluminum layer and a titanium nitride film, or a copper-containing aluminum layer. Here, the lower electrode layer 4a, the dielectric layer 42a, and the capacitor line 5b are formed on the upper layer side of the pixel transistor 30 and overlap the pixel transistor 30 in plan view. Therefore, the storage capacitor 55 is formed on the upper layer side of the pixel transistor 30 and overlaps at least the pixel transistor 30 in plan view.

In this embodiment, the dielectric layer 42a includes at least one high dielectric constant insulating film such as an aluminum oxide film, a titanium oxide film, a tantalum oxide film, a niobium oxide film, a hafnium oxide film, a lanthanum oxide film, or a zirconium oxide film. In this embodiment, the dielectric layer 42a is made of a single layer film of the above-described high dielectric constant insulating film. Such a high dielectric constant insulating film has a dielectric constant higher than that of a silicon oxide film (dielectric constant = 3 to 4), as will be described below.
Dielectric constant of dielectric layer 42a (high dielectric constant insulating film) Aluminum oxide film = about 8
Titanium oxide film = about 66
Tantalum oxide film = about 25
Niobium oxide film = about 42
Hafnium oxide film = about 41
Lanthanum oxide film = about 24
Zirconium oxide film = about 31

  Therefore, if the above-described high dielectric constant insulating film is used as the dielectric layer 42a, the capacitance per unit area of the storage capacitor 55 can be increased. The dielectric layer 42a may be a laminated film in which a plurality of the above-described high dielectric constant insulating films are laminated, or a multi-component high dielectric constant insulating film in which the above metal oxide is mixed.

  In this embodiment, the dielectric layer 42a has substantially the same shape as the capacitor line 5b and is formed in the same region. Further, the end edge 42e of the dielectric layer 42a and the end edge 5e of the capacitance line 5b are at positions overlapping the lower electrode layer 4a.

  In this embodiment, an etching stopper layer 40a made of a silicon oxide film or the like is formed between the lower electrode layer 4a and the dielectric layer 42a. The etching stopper layer 40a includes one of the lower electrode layers 4a. An opening 40b is formed in a region overlapping the portion. For this reason, the lower electrode layer 4a and the capacitor line 5b are opposed to each other through the dielectric layer 42a in the opening 40b to form a storage capacitor 55. The etching stopper layer 40a is formed in a region that overlaps the end edge 42e of the dielectric layer 42a and the end edge 5e of the capacitor line 5b.

  A translucent second interlayer insulating film 43 made of a silicon oxide film or the like is formed on the upper side of the capacitor line 5b, and a data line 6a and a drain electrode 6b are formed on the upper layer of the second interlayer insulating film 43. Yes. Data line 6a is electrically connected to source region 1b through contact hole 7a. The drain electrode 6b is electrically connected to the lower electrode layer 4a through the contact hole 7b, and is electrically connected to the drain region 1c through the lower electrode layer 4a. The data line 6a and the drain electrode 6b are made of a conductive polysilicon film, a metal silicide film, a metal film, or the like.

  A light-transmitting third interlayer insulating film 44 made of a silicon oxide film or the like is formed on the upper side of the data line 6a and the drain electrode 6b. In the third interlayer insulating film 44, a contact hole 7d leading to the drain electrode 6b is formed. Over the third interlayer insulating film 44, a pixel electrode 9a made of a light-transmitting conductive film such as an ITO (Indium Tin Oxide) film as a metal oxide layer is formed. The pixel electrode 9a is connected to the contact hole 7d. Is electrically connected to the drain electrode 6b. In this embodiment, the surface of the third interlayer insulating film 44 is a flat surface.

  Here, the dummy pixel electrode 9b (not shown in FIG. 3) described with reference to FIG. 2B is formed on the surface of the third interlayer insulating film 44, and the dummy pixel electrode 9b is The light-transmitting conductive film is formed simultaneously with the pixel electrode 9a.

An alignment film 16 is formed on the surface of the pixel electrode 9a. The alignment film 16 is made of a resin film such as polyimide or an oblique deposition film such as a silicon oxide film. In this embodiment, the alignment film 16 is an obliquely deposited film of SiO _x (x <2), SiO ₂ , TiO ₂ , MgO, Al ₂ O ₃ , In ₂ O ₃ , Sb ₂ O ₃ , Ta ₂ O ₅ or the like. A transparent protective film 17 such as a silicon oxide film or a silicon nitride film is formed between the alignment film 16 and the pixel electrode 9a. The protective film 17 has a flat surface, and fills a recess formed between adjacent pixel electrodes 9a. Therefore, the alignment film 16 is formed on the flat surface of the protective film 17.

In the second substrate 20, a translucent conductive film such as an ITO film is formed on the surface of the translucent substrate body 20 w such as a quartz substrate or a glass substrate on the liquid crystal layer 50 side (a surface facing the first substrate 10). A common electrode 21 is formed, and an alignment film 26 is formed so as to cover the common electrode 21. Similar to the alignment film 16, the alignment film 26 is made of a resin film such as polyimide or an oblique deposition film such as a silicon oxide film. In this embodiment, the alignment film 26 is an obliquely deposited film such as SiO _x (x <2), SiO ₂ , TiO ₂ , MgO, Al ₂ O ₃ , In ₂ O ₃ , Sb ₂ O ₃ , Ta ₂ O _5. A protective film 27 such as a silicon oxide film or a silicon nitride film is formed between the alignment film 26 and the common electrode 21. The protective film 27 has a flat surface, and the alignment film 26 is formed on the flat surface. The alignment films 16 and 26 vertically align the nematic liquid crystal compound having negative dielectric anisotropy used for the liquid crystal layer 50, and the liquid crystal panel 100p operates as a normally black VA mode.

  Note that the data line driving circuit 101 and the scanning line driving circuit 104 described with reference to FIGS. 1 and 2 are complementary transistor circuits each including an N-channel driving transistor and a P-channel driving transistor. Etc. are configured. Here, the driving transistor is formed by utilizing a part of the manufacturing process of the pixel transistor 30. Therefore, the region where the data line driving circuit 101 and the scanning line driving circuit 104 are formed on the first substrate 10 also has a cross-sectional configuration substantially similar to the cross-sectional configuration shown in FIG.

(Manufacturing method of the liquid crystal device 100)
4 and 5 are process cross-sectional views illustrating the main part of the manufacturing process of the first substrate 10 used in the liquid crystal device 100 according to Embodiment 1 of the present invention. In addition, although the manufacturing process described below is performed in a state of a large substrate capable of obtaining a large number of single-sized first substrates 10, in the following description, the “first substrate 10” is not distinguished from the single-sized and large substrates. ".

  In manufacturing the liquid crystal device 100 of the present embodiment, in the manufacturing method of the first substrate 10, as shown in FIG. 4A, the pixel transistor 30, the first interlayer insulating film 41, and the like are formed, and then the first interlayer insulation is formed. A contact hole 7 c is formed in the film 41.

  Next, in the first electrode formation step shown in FIGS. 4B and 4C, the lower electrode layer 4a (first electrode) is formed. More specifically, as shown in FIG. 4B, first, in the first electrode forming conductor film forming step, the lower electrode layer 4a is formed on the upper layer side of the first interlayer insulating film 41. The first electrode forming conductive film 4 is formed on the entire substrate by sputtering or vapor deposition. Next, in the first electrode forming conductive film patterning step, a resist mask 91 (etching mask) is formed on the first electrode forming conductive film 4 by using a photolithography technique. More specifically, a photosensitive resin layer is applied to the upper layer of the first electrode forming conductive film 4 and then exposed through an exposure mask, and then the photosensitive resin layer is developed to form a resist mask 91. . In the first electrode forming conductive film patterning step, wet etching or dry etching is performed on the first electrode forming conductive film 4 to pattern the first electrode forming conductive film 4, and then the resist mask 91 is removed. As a result, as shown in FIG. 4C, the lower electrode layer 4a (first electrode) is formed. In this embodiment, dry etching is performed as etching on the first electrode forming conductive film 4.

  Next, in the etching stopper layer forming step shown in FIGS. 4D and 4E, an etching stopper layer 40a is formed. More specifically, as shown in FIG. 4D, first, in the etching stopper insulating film forming step, an etching stopper insulating film 40 such as a silicon oxide film is formed on the upper side of the lower electrode layer 4a by the CVD method. Etc. to form the entire substrate. Next, in the etching stopper insulating film patterning step, a resist mask 92 (etching mask) is formed on the etching stopper insulating film 40 using a photolithography technique. In the etching stopper insulating film patterning step, wet etching or dry etching is performed on the etching stopper insulating film 40 to pattern the etching stopper insulating film 40, and then the resist mask 92 is removed. As a result, as shown in FIG. 4E, an etching stopper layer 40a is formed. In the etching stopper layer 40a, an opening 40b is formed in a region overlapping the lower electrode layer 4a, and the lower electrode layer 4a. Is partially exposed at the opening 40b. In the patterning of the etching stopper insulating film 40, the etching stopper layer 40a is left in a region overlapping with the edge 42e of the dielectric layer 42a and the edge 5e of the capacitor line 5b formed in a later step. In this embodiment, dry etching is performed as etching on the etching stopper insulating film 40.

  Next, in the dielectric layer forming step shown in FIGS. 5A and 5B, the dielectric layer 42a is formed. More specifically, as shown in FIG. 5A, in the high dielectric constant insulating film forming step, an aluminum oxide film, a titanium oxide film, a tantalum oxide film, a niobium oxide film is formed on the upper side of the etching stopper layer 40a. A high dielectric constant insulating film 42 such as a film, a hafnium oxide film, a lanthanum oxide film, or a zirconium oxide film is formed on the entire substrate by sputtering, vapor deposition, or the like. Next, in a high dielectric constant insulating film patterning step, a resist mask 93 (etching mask) is formed on the high dielectric constant insulating film 42 using a photolithography technique. In the high dielectric constant insulating film patterning step, the high dielectric constant insulating film 42 is dry-etched to pattern the high dielectric constant insulating film 42, and then the resist mask 93 is removed. As a result, as shown in FIG. 5B, a dielectric layer 42a is formed, and the edge 42e of the dielectric layer 42a overlaps the etching stopper layer 40a. In such a high dielectric constant insulating film patterning step, dry etching generates plasma in the apparatus chamber and etches the high dielectric constant insulating film 42 using ions and radicals generated therein. For this reason, charges are accumulated in the high dielectric constant insulating film 42 (dielectric layer 42a) due to the influence of plasma, but a conductive film is still formed on the upper layer side of the high dielectric constant insulating film 42 (dielectric layer 42a). Since it is not, electrostatic breakdown does not occur.

  In the second electrode formation step shown in FIGS. 5C and 5D, the capacitor line 5b is formed. More specifically, as shown in FIG. 5C, first, formation of the second electrode for forming the capacitor line 5b on the upper side of the dielectric layer 42a in the second electrode forming conductive film forming step. The conductive film 5 is formed on the entire substrate by sputtering or vapor deposition. Next, in the second electrode forming conductive film patterning step, a resist mask 94 (etching mask) is formed on the second electrode forming conductive film 5 by using a photolithography technique. In the second electrode forming conductive film patterning step, the second electrode forming conductive film 5 is dry-etched to pattern the second electrode forming conductive film 5, and then the resist mask 94 is removed. As a result, the capacitor line 5b is formed as shown in FIG. The capacitor line 5b is opposed to the lower electrode layer 4a through the dielectric layer 42a in the opening 40b, and the storage capacitor 55 is formed by the capacitor line 5b, the dielectric layer 42a, and the lower electrode layer 4a.

  Here, the exposure mask for forming the resist mask 94 and the exposure mask for forming the resist mask 93 used in the high dielectric constant insulating film patterning step are common. Therefore, the capacitor line 5b and the dielectric layer 42a are formed in the same region with the same shape. Therefore, the end edge 5e of the capacitor line 5b and the end edge 42e of the dielectric layer 42a substantially overlap each other, and the etching stopper layer 40a is located on the lower layer side of the end edges 42e and 5e. In the second electrode forming conductive film patterning step, dry etching generates plasma in the apparatus chamber and etches the second electrode forming conductive film 5 using ions and radicals generated therein. A second electrode forming conductive film 5 is laminated on the upper layer side of the high dielectric constant insulating film 42 (dielectric layer 42a). For this reason, charges are accumulated in the dielectric layer 42a due to the influence of plasma, but the dielectric layer 42a has already been patterned. Therefore, since the charge accumulated in each of the dielectric layers 42a is small, electrostatic breakdown does not occur.

  Thereafter, when the second interlayer insulating film 43, the data line 6a, the third interlayer insulating film 44, the pixel electrode 9a, the protective film 17, the alignment film 16 and the like shown in FIG. The first substrate 10 described with reference to FIG. 3 and the like can be obtained.

(Main effects of this form)
As described above, in the liquid crystal device 100 of the present embodiment, the second electrode forming conductive film is formed after the dielectric layer 42a is formed in a predetermined region by the high dielectric constant insulating film forming step and the high dielectric constant insulating film patterning step. The capacitor line 5b (second electrode) is formed by the forming step and the second electrode forming conductive film patterning step. Therefore, the high dielectric constant insulating film 42 is subjected to plasma in a state where it is formed over a wide area only during the high dielectric constant insulating film patterning step, and when the second electrode forming conductive film patterning step is performed. Then, it has already been patterned. For this reason, even when the high dielectric constant insulating film 42 is used for the dielectric layer 42a, the charge accumulated in the high dielectric constant insulating film 42 (dielectric layer 42a) due to plasma during dry etching can be suppressed to a low level. The occurrence of electrostatic breakdown can be prevented.

  Also, the exposure mask for forming the resist mask 93 used in the high dielectric constant insulating film patterning step and the exposure mask for forming the resist mask 94 used in the second electrode forming conductive film patterning step are common. It is. Therefore, even when the high dielectric constant insulating film patterning step and the second electrode forming conductive film patterning step are performed as separate steps, an increase in manufacturing cost can be minimized.

  Also, in this embodiment, before performing the high dielectric constant insulating film forming step shown in FIG. 5A, an etching stopper insulating film forming step for forming the etching stopper insulating film 40 on the upper layer side of the lower electrode layer 4a, Then, the etching stopper insulating film patterning step is performed by etching the etching stopper insulating film 40 to leave the etching stopper layer 40a. For this reason, even if the lower layer side of the capacitor line 5b is etched by overetching when performing the second electrode forming conductive film patterning step, a short circuit between the capacitor line 5b and the lower electrode layer 4a does not occur.

[Embodiment 2]
FIG. 6 is a cross-sectional view of a pixel of the liquid crystal device 100 according to Embodiment 2 of the present invention. Since the basic configuration of this embodiment is substantially the same as that of Embodiment 1, common portions are denoted by the same reference numerals and description thereof is omitted.

  In the first embodiment, the etching stopper layer 40a is formed over a wide range in addition to the region overlapping the end edge 42e of the dielectric layer 42a and the end edge 5e of the capacitor line 5b. As shown in FIG. 5, the etching stopper layer 40a may be formed in a limited manner along a region overlapping the edge 42e of the dielectric layer 42a and the edge 5e of the capacitor line 5b. Further, when the dielectric layer 42a and the capacitor line 5b partially protrude outward from the edge of the lower electrode layer 4a, the region overlaps with the edge 42e of the dielectric layer 42a and the edge 5e of the capacitor line 5b. However, the formation of the etching stopper layer 40a may be omitted for the region where the lower electrode layer 4a is not provided on the lower layer side.

[Embodiment 3]
FIG. 7 is a cross-sectional view of a pixel of the liquid crystal device 100 according to Embodiment 3 of the present invention. FIG. 8 is a process cross-sectional view showing the main part of the manufacturing process of the first substrate 10 used in the liquid crystal device 100 according to Embodiment 3 of the present invention. Since the basic configuration of this embodiment is substantially the same as that of Embodiment 1, common portions are denoted by the same reference numerals and description thereof is omitted.

  In the first embodiment, the etching stopper layer 40a is provided between the lower electrode layer 4a and the dielectric layer 42a. However, as shown in FIG. 7, the etching stopper is provided between the dielectric layer 42a and the capacitor line 5b. A layer 40a may be provided.

  In such a configuration, the etching stopper layer forming step described with reference to FIGS. 4D and 4E is performed after the dielectric layer forming step described with reference to FIGS. 5A and 5B. . More specifically, as shown in FIG. 8A, after performing a high dielectric constant insulating film patterning step to form the dielectric layer 42a, as shown in FIG. 8B, the insulating film for etching stopper is formed. In the formation step, an etching stopper insulating film 40 is formed on the upper side of the dielectric layer 42a by a CVD method or the like. Next, in the etching stopper insulating film patterning step, a resist mask 92 (etching mask) is formed on the etching stopper insulating film 40 using a photolithography technique. In the etching stopper insulating film patterning step, wet etching or dry etching is performed on the etching stopper insulating film 40 to pattern the etching stopper insulating film 40, and then the resist mask 92 is removed. As a result, as shown in FIG. 7, an etching stopper layer 40a is formed. In the etching stopper layer 40a, an opening 40b is formed in a region overlapping the lower electrode layer 4a, and the dielectric layer 42a is partially exposed in the opening 40b.

  After the etching stopper layer 40a is formed in this way, the second electrode forming step described with reference to FIGS. 5C and 5D is performed, and as shown in FIG. The line 5b faces the opening 40b via the dielectric layer 42a, and the storage capacitor 55 is formed. Further, an etching stopper layer 40a is located on the lower layer side of the edge 5e of the capacitor line 5b. Therefore, even when the dielectric layer 42a is etched on the lower layer side of the capacitor line 5b by overetching when performing the second electrode forming conductive film patterning step, a short circuit between the capacitor line 5b and the lower electrode layer 4a does not occur. .

[Other embodiments]
In the above embodiment, the pixel electrode 9a is formed of a light-transmitting conductive film and the liquid crystal device 100 is configured as a transmission type. However, the pixel electrode 9a is formed of a reflective conductive film such as an aluminum film and the liquid crystal device is formed. You may comprise 100 as a reflection type.

[Example of mounting on electronic devices]
An electronic apparatus to which the liquid crystal device 100 according to the above-described embodiment is applied will be described. FIG. 9 is a schematic configuration diagram of a projection type display device using the liquid crystal device 100 to which the present invention is applied. FIGS. 9A and 9B are respectively a projection type display using the transmission type liquid crystal device 100. FIG. 2 is an explanatory diagram of the device and an explanatory diagram of a projection display device using the reflective liquid crystal device 100.

(First example of projection display device)
The projection display device 110 shown in FIG. 9A is a so-called projection type projection display device that irradiates light onto a screen 111 provided on the viewer side and observes the light reflected by the screen 111. . The projection display device 110 includes a light source unit 130 including a light source 112, dichroic mirrors 113 and 114, liquid crystal light valves 115 to 117 (liquid crystal device 100), a projection optical system 118, a cross dichroic prism 119, and a relay. System 120.

  The light source 112 is composed of an ultrahigh pressure mercury lamp that supplies light including red light, green light, and blue light. The dichroic mirror 113 is configured to transmit red light from the light source 112 and reflect green light and blue light. The dichroic mirror 114 is configured to transmit blue light and reflect green light among the green light and the blue light reflected by the dichroic mirror 113. Thus, the dichroic mirrors 113 and 114 constitute a color separation optical system that separates the light emitted from the light source 112 into red light, green light, and blue light.

  Here, between the dichroic mirror 113 and the light source 112, an integrator 121 and a polarization conversion element 122 are sequentially arranged from the light source 112. The integrator 121 is configured to uniformize the illuminance distribution of the light emitted from the light source 112. Further, the polarization conversion element 122 is configured to change the light from the light source 112 into polarized light having a specific vibration direction such as s-polarized light.

  The liquid crystal light valve 115 is a transmissive liquid crystal device 100 that modulates red light transmitted through the dichroic mirror 113 and reflected by the reflection mirror 123 in accordance with an image signal. The liquid crystal light valve 115 includes a λ / 2 phase difference plate 115a, a first polarizing plate 115b, a liquid crystal panel 115c, and a second polarizing plate 115d. Here, the red light incident on the liquid crystal light valve 115 remains s-polarized light because the polarization of the light does not change even if it passes through the dichroic mirror 113.

  The λ / 2 phase difference plate 115a is an optical element that converts s-polarized light incident on the liquid crystal light valve 115 into p-polarized light. The first polarizing plate 115b is a polarizing plate that blocks s-polarized light and transmits p-polarized light. The liquid crystal panel 115c is configured to convert p-polarized light into s-polarized light (circularly polarized light or elliptically polarized light in the case of halftone) by modulation according to the image signal. Furthermore, the second polarizing plate 115d is a polarizing plate that blocks p-polarized light and transmits s-polarized light. Therefore, the liquid crystal light valve 115 is configured to modulate the red light in accordance with the image signal and to emit the modulated red light toward the cross dichroic prism 119.

  Note that the λ / 2 phase difference plate 115a and the first polarizing plate 115b are disposed in contact with a light-transmitting glass plate 115e that does not convert polarized light, and the λ / 2 phase difference plate 115a and the first polarizing plate 115b. It is possible to avoid distortion of 115b due to heat generation.

  The liquid crystal light valve 116 is a transmissive liquid crystal device 100 that modulates green light reflected by the dichroic mirror 114 after being reflected by the dichroic mirror 113 in accordance with an image signal. Similarly to the liquid crystal light valve 115, the liquid crystal light valve 116 includes a first polarizing plate 116b, a liquid crystal panel 116c, and a second polarizing plate 116d. Green light incident on the liquid crystal light valve 116 is s-polarized light that is reflected by the dichroic mirrors 113 and 114 and then incident. The first polarizing plate 116b is a polarizing plate that blocks p-polarized light and transmits s-polarized light. The liquid crystal panel 116c is configured to convert s-polarized light into p-polarized light (circularly polarized light or elliptically polarized light in the case of halftone) by modulation according to the image signal. The second polarizing plate 116d is a polarizing plate that blocks s-polarized light and transmits p-polarized light. Accordingly, the liquid crystal light valve 116 is configured to modulate green light in accordance with the image signal and to emit the modulated green light toward the cross dichroic prism 119.

  The liquid crystal light valve 117 is a transmissive liquid crystal device 100 that modulates blue light reflected by the dichroic mirror 113 and transmitted through the dichroic mirror 114 and then through the relay system 120 in accordance with an image signal. Similarly to the liquid crystal light valves 115 and 116, the liquid crystal light valve 117 includes a λ / 2 retardation film 117a, a first polarizing plate 117b, a liquid crystal panel 117c, and a second polarizing plate 117d. Here, since the blue light incident on the liquid crystal light valve 117 is reflected by the two reflecting mirrors 125a and 125b described later of the relay system 120 after being reflected by the dichroic mirror 113 and transmitted through the dichroic mirror 114, the s-polarized light is reflected. It has become.

  The λ / 2 phase difference plate 117a is an optical element that converts s-polarized light incident on the liquid crystal light valve 117 into p-polarized light. The first polarizing plate 117b is a polarizing plate that blocks s-polarized light and transmits p-polarized light. The liquid crystal panel 117c is configured to convert p-polarized light into s-polarized light (circularly polarized light or elliptically polarized light in the case of halftone) by modulation according to the image signal. Furthermore, the second polarizing plate 117d is a polarizing plate that blocks p-polarized light and transmits s-polarized light. Accordingly, the liquid crystal light valve 117 is configured to modulate blue light in accordance with an image signal and to emit the modulated blue light toward the cross dichroic prism 119. The λ / 2 phase difference plate 117a and the first polarizing plate 117b are disposed in contact with the glass plate 117e.

  The relay system 120 includes relay lenses 124a and 124b and reflection mirrors 125a and 125b. The relay lenses 124a and 124b are provided to prevent light loss due to a long blue light path. Here, the relay lens 124a is disposed between the dichroic mirror 114 and the reflection mirror 125a. The relay lens 124b is disposed between the reflection mirrors 125a and 125b. The reflection mirror 125a is disposed so as to reflect the blue light transmitted through the dichroic mirror 114 and emitted from the relay lens 124a toward the relay lens 124b. The reflection mirror 125b is arranged to reflect the blue light emitted from the relay lens 124b toward the liquid crystal light valve 117.

  The cross dichroic prism 119 is a color combining optical system in which two dichroic films 119a and 119b are arranged orthogonally in an X shape. The dichroic film 119a is a film that reflects blue light and transmits green light, and the dichroic film 119b is a film that reflects red light and transmits green light. Therefore, the cross dichroic prism 119 is configured to combine the red light, the green light, and the blue light modulated by the liquid crystal light valves 115 to 117 and emit the resultant light toward the projection optical system 118.

  Note that light incident on the cross dichroic prism 119 from the liquid crystal light valves 115 and 117 is s-polarized light, and light incident on the cross dichroic prism 119 from the liquid crystal light valve 116 is p-polarized light. Thus, by making the light incident on the cross dichroic prism 119 into different types of polarized light, the light incident from the liquid crystal light valves 115 to 117 in the cross dichroic prism 119 can be synthesized. Here, in general, the dichroic films 119a and 119b are excellent in the reflection characteristics of s-polarized light. Therefore, red light and blue light reflected by the dichroic films 119a and 119b are s-polarized light, and green light transmitted through the dichroic films 119a and 119b is p-polarized light. The projection optical system 118 has a projection lens (not shown) and is configured to project the light combined by the cross dichroic prism 119 onto the screen 111.

(Second example of projection display device)
In the projection display device 1000 shown in FIG. 9B, the light source unit 890 includes a polarization illumination device 800 in which a light source 810, an integrator lens 820, and a polarization conversion element 830 are arranged along the system optical axis L. . The light source unit 890 also reflects the S-polarized light beam emitted from the polarization illumination device 800 along the system optical axis L by the S-polarized light beam reflecting surface 841 and the S-polarized light beam of the polarized beam splitter 840. Of the light reflected from the reflecting surface 841, the dichroic mirror 842 that separates the blue light (B) component and the red light (R) component of the luminous flux after the blue light is separated are separated. And a dichroic mirror 843.

  The projection display device 1000 includes three reflective liquid crystal devices 100 (liquid crystal devices 100R, 100G, and 100B) on which each color light is incident, and the light source unit 890 includes three liquid crystal devices 100 (liquid crystal devices 100R). , 100G, 100B).

  In the projection display apparatus 1000, the light modulated by the three liquid crystal devices 100R, 100G, and 100B is synthesized by the dichroic mirrors 842 and 843 and the polarization beam splitter 840, and then the synthesized light is projected by the projection optical system 850. Is projected onto a projection target member such as a screen 860.

(Other projection display devices)
In addition, about a projection type display apparatus, you may comprise the LED light source etc. which radiate | emit the light of each color as a light source part, and supply each color light radiate | emitted from this LED light source to another liquid crystal device. .

(Other electronic devices)
As for the liquid crystal device 100 to which the present invention is applied, in addition to the electronic devices described above, mobile phones, personal digital assistants (PDAs), digital cameras, liquid crystal televisions, car navigation devices, video phones, POS terminals, You may use as a direct view type | mold display apparatus in electronic devices, such as an apparatus provided with the touch panel.

[Other electrical devices]
In the above embodiment, the liquid crystal device is exemplified as the electro-optical device. However, as long as a translucent substrate (electro-optical device substrate) is provided, not only the liquid crystal device but also an organic electroluminescence device and a plasma display device. The present invention may be applied to a method of manufacturing an electro-optical device such as an electrophoretic display device, a device using electron emission (Field Emission Display), or a DLP (Digital Light Processing).

4a ... Lower electrode layer (first electrode), 5b ... Capacitance line (second electrode), 9a ... Pixel electrode, 10 ... First substrate (electro-optical device substrate), 20 ... Second substrate, 50 ... Liquid crystal layer, 40a ... Etching stopper layer, 42a ... Dielectric layer, 55 ... Holding capacity (capacitance element), 100 ... Liquid crystal device (electro-optical device), 110, 1000 ... Projection type display device

Claims (7)

A method of manufacturing an electro-optical device including a capacitive element in which a first electrode, a dielectric layer, and a second electrode are laminated on one side of a substrate for an electro-optical device,
Forming a high dielectric constant insulating film having a dielectric constant higher than that of the silicon oxide film on the upper layer side of the first electrode; and
A high dielectric constant insulating film patterning step of patterning the high dielectric constant insulating film by dry etching to form the dielectric layer; and
A second electrode forming conductive film forming step of forming a second electrode forming conductor film for forming the second electrode;
A second electrode forming conductive film patterning step of patterning the second electrode forming conductor film by dry etching to form the second electrode;
A method for manufacturing an electro-optical device.   An etching mask formed on the surface of the high dielectric constant insulating film when performing the high dielectric constant insulating film patterning step, and the second electrode forming conductor film when performing the second electrode forming conductive film patterning step The method of manufacturing an electro-optical device according to claim 1, wherein the etching mask formed on the surface of the electro-optical device is formed in the same region with the same planar shape.   The high dielectric constant insulating film includes an oxide film of at least one of an aluminum oxide film, a titanium oxide film, a tantalum oxide film, a niobium oxide film, a hafnium oxide film, a lanthanum oxide film, and a zirconium oxide film. The method of manufacturing the electro-optical device according to claim 1. Before performing the high dielectric constant insulating film forming step,
An etching stopper insulating film forming step of forming an etching stopper insulating film on the upper layer side of the first electrode;
Etching the etching stopper insulating film to partially expose the first electrode, and leaving the etching stopper insulating film as an etching stopper layer in a region overlapping the edge of the second electrode A patterning process;
The method of manufacturing an electro-optical device according to claim 1, wherein: After performing the high dielectric constant insulating film patterning step and before performing the second electrode forming conductive film forming step,
An etching stopper insulating film forming step of forming an etching stopper insulating film on the upper side of the dielectric layer;
Etching the etching stopper insulating film to partially expose the dielectric layer, and leaving the etching stopper insulating film as an etching stopper layer in a region overlapping the edge of the second electrode A patterning process;
The method of manufacturing an electro-optical device according to claim 1, wherein:   6. The electro-optical device according to claim 1, wherein the electro-optical device substrate is used as one of a pair of liquid crystal device substrates facing each other through a liquid crystal layer in the liquid crystal device. Production method.   An electro-optical device manufactured by the method according to claim 1.

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