JP3199692U - Electro-optical device and electronic apparatus - Google Patents

Abstract

An electro-optical device capable of appropriately providing a large storage capacitor even when a conductive layer formed on a tip surface of a convex portion is exposed from a flat surface and the conductive layer and a pixel electrode are electrically connected. Providing equipment and electronics. In an electro-optical device, a surface of an interlayer insulating film between a relay electrode and a pixel electrode is a flat surface. On the flat surface 460, the conductive portion 8c formed on the tip surface 45f of the convex portion 45e is exposed, and the pixel electrode 9a is electrically connected to the exposed portion of the conductive portion 8c. In the storage capacitor 55, the first capacitor electrode 6a to which the constant potential is applied, the first dielectric layer 55e, the second capacitor electrode 7a through which the pixel electrode 9a is conducted, the second dielectric layer 55f, and the constant potential are applied. Since the third capacitor electrode 8a is sequentially laminated, the capacitance is high. In the storage capacitor 55, a constant potential is applied to the third capacitor electrode 8a located closest to the pixel electrode 9a. [Selection] Figure 5

Description

  The present invention relates to an electro-optical device and an electronic apparatus in which a storage capacitor and a pixel electrode are formed on one side of a substrate.

  In an element substrate used in an electro-optical device such as a liquid crystal device, a pixel electrode is electrically connected to a lower conductive layer through a contact hole formed in an interlayer insulating film. In such an electro-optical device, when the planar size of the contact hole is large and large irregularities are formed on the surface of the pixel electrode, the display quality is deteriorated due to the reason that the alignment film cannot be suitably formed. In view of this, a configuration has been proposed in which a plug is embedded in a contact hole of an interlayer insulating film, and the pixel electrode and a lower layer side electrode are conducted through the plug. However, in order to form the plug, since it is necessary to newly prepare a metal material such as tungsten which is not normally used in the electro-optical device, the cost increases. Further, when a conductive structure using plugs is employed, productivity is reduced because a metal film for plugs needs to be thickly formed until the contact holes are filled.

  Therefore, a convex portion is provided at a position overlapping the pixel electrode in plan view, and a conductive layer having a conductive portion overlapping in plan view on the tip surface of the convex portion, and a flat surface that exposes the conductive portion on the pixel electrode side surface are provided. There has been proposed a configuration in which a provided insulating film is provided and a pixel electrode is stacked on a flat surface of the insulating film to be electrically connected to a conductive portion (see Patent Document 1).

JP 2013-25069 A

  In the case where the configuration described in Patent Document 1 is employed, when a storage capacitor is formed using a conductive layer having a conductive portion, a constant potential is applied to the side opposite to the pixel electrode with respect to the conductive layer. Capacitance electrodes must be placed. For this reason, when a storage capacitor having a large plane area and a large capacitance is formed by utilizing a region overlapping with an inter-pixel region sandwiched between adjacent pixel electrodes in the plan view or the vicinity thereof, a pixel adjacent to the conductive layer is formed. Potential interference occurs between the electrodes and the image quality deteriorates.

  In view of the above problems, the problem of the present invention is that even when the conductive layer formed on the tip surface of the convex portion is exposed from the flat surface of the insulating film and the conductive layer and the pixel electrode are made conductive, An object of the present invention is to provide an electro-optical device and an electronic apparatus that can appropriately provide a large storage capacity.

  In order to solve the above-described problem, an aspect of the electro-optical device according to the present invention is provided between a first pixel electrode provided on one surface side of a substrate and the first pixel electrode and the substrate. A pixel transistor; a first capacitor electrode provided between the pixel transistor and the first pixel electrode to which a constant potential is applied; and the first capacitor electrode between the first capacitor electrode and the first pixel electrode. A second capacitor electrode provided so as to overlap with the capacitor electrode in plan view; and provided between the second capacitor electrode and the first pixel electrode so as to overlap with the second capacitor electrode in plan view. A third capacitor electrode to which a potential is applied; a first dielectric layer provided between the first capacitor electrode and the second capacitor electrode; and between the second capacitor electrode and the third capacitor electrode. A second dielectric layer provided on the first capacitor electrode, the second capacitor electrode, and the first pixel electrode. A first insulating film provided with a convex portion projecting toward the first pixel electrode at a position overlapping with the first pixel electrode in plan view, and a part of the first insulating film overlapping the tip surface of the convex portion A relay electrode that is electrically connected to a portion of the second capacitor electrode exposed from the first insulating film, and is provided between the relay electrode and the first pixel electrode, and has a flat surface on the first pixel electrode side. A second insulating film, wherein the relay electrode is exposed at least partially from the second insulating film in a portion overlapping the tip end surface of the convex portion, and the first pixel electrode is connected to the relay electrode. The electrode is electrically connected to a portion exposed from the second insulating film.

  In the present invention, the relay electrode overlaps the tip surface of the convex portion that overlaps the pixel electrode in plan view, and the relay electrode is exposed from the flat surface of the second insulating film. The first pixel electrode is connected to the exposed portion of the relay electrode from the flat surface. Therefore, it is possible to suppress the formation of large irregularities on the first pixel electrode, and the storage capacitor (first storage capacitor) formed by the first capacitor electrode, the first dielectric layer, and the second capacitor electrode. Since the storage capacitor (second storage capacitor) formed by the second capacitor electrode, the second dielectric layer, and the third capacitor electrode is stacked in the thickness direction, the plane area for forming the storage capacitor is narrow. That's it. In addition, a constant potential is applied to the third capacitor electrode located closest to the first pixel electrode in the storage capacitor, and a constant potential is applied to the second capacitor electrode to which the same potential as the first pixel electrode is applied. The third capacitor electrode is located on the opposite side of the first pixel electrode. For this reason, the potential of the second capacitor electrode (the potential of the first pixel electrode) is unlikely to affect the potential of the adjacent pixel electrode (second pixel electrode).

  In the present invention, a second pixel electrode adjacent to the first pixel electrode is provided, and the third capacitor electrode is seen in a plan view in an inter-pixel region sandwiched between the first pixel electrode and the second pixel electrode. An overlapping mode can be adopted. According to this configuration, it is possible to provide a storage capacitor in a region that does not directly contribute to display, and thus it is possible to suppress a decrease in display light amount. Even in such a configuration, the second capacitor electrode to which the same potential as the first pixel electrode is applied is located on the opposite side of the first pixel electrode with respect to the third capacitor electrode to which the constant potential is applied. . For this reason, the potential of the second capacitor electrode (the potential of the first pixel electrode) is unlikely to affect the potential of the adjacent second pixel electrode.

  In the present invention, a data line provided between the substrate and the first capacitor electrode and electrically connected to the pixel transistor, and provided between the substrate and the first capacitor electrode, the pixel transistor And a scanning line extending in a direction intersecting the data line, and the third capacitor electrode extends in a direction along the data line and extends to the scanning line. It is preferable to protrude in the direction along. According to such a configuration, it is possible to provide a storage capacitor having a large capacitance by efficiently using a region that does not directly contribute to display.

  In the present invention, it is preferable that the third capacitor electrode and the relay electrode are provided in the same layer. According to such a configuration, the third capacitor electrode and the relay electrode can be formed simultaneously, so that the number of manufacturing steps can be reduced.

  In the present invention, a third insulating film is provided between the first capacitor electrode and the second capacitor electrode, and the third insulating film includes the first capacitor electrode and the second capacitor electrode. A through hole provided to overlap with the first dielectric layer, wherein the second capacitor electrode and the third capacitor electrode have a recess shape by the through hole, and the bottom and side surfaces of the recess shape It is preferable that the layers overlap with each other via the second dielectric layer. According to such a configuration, since the facing area between the second capacitor electrode and the third capacitor electrode is wide, a storage capacitor having a large capacitance can be configured.

  In the present invention, the second capacitor electrode may be configured to be electrically connected to the pixel transistor through a contact hole formed in the third insulating film.

  In the present invention, it is possible to adopt a mode in which the contact hole is formed at a position adjacent to the convex portion in a plan view or a position overlapping the convex portion in a plan view.

  In the present invention, a fourth insulating film is provided between the second insulating film and the first pixel electrode, and the fourth insulating film includes at least a portion overlapping a tip surface of the convex portion. An opening may be provided so that a part of the relay electrode is exposed, and the first pixel electrode may be electrically connected to the relay electrode through the opening.

  In the present invention, the first pixel electrode is preferably formed of a laminated film in which at least a first light-transmissive conductive film, a refractive index adjusting dielectric film, and a second light-transmissive conductive film are sequentially laminated. According to this configuration, the first translucent conductive film, the refractive index adjusting dielectric film, and the second translucent conductive film are adjusted to adjust the refractive index and film thickness of each of the first translucent conductive film, the refractive index adjusting dielectric film, and the second translucent conductive film. Wavelength dispersion of light can be suppressed.

  In the present invention, it is preferable that the first translucent conductive film and the second translucent conductive film protrude from an end portion of the refractive index adjusting dielectric film and contact each other. According to such a configuration, the first translucent conductive film and the second translucent conductive film can be conducted without using a contact hole. Therefore, even when the electrical resistance of the first pixel electrode is reduced, it is possible to prevent the first pixel electrode from being uneven due to the contact hole.

  The electro-optical device to which the present invention is applied can be used for various display devices such as a direct-view display device in various electronic devices. The electro-optical device to which the present invention is applied can be used for a projection display device. Such a projection display device includes a light source unit that emits illumination light applied to an electro-optical device to which the present invention is applied, and a projection optical system that projects light modulated by the electro-optical device. .

1 is a block diagram showing an aspect of an electrical configuration of an electro-optical device to which the present invention is applied. It is a top view which shows the one aspect | mode of the liquid crystal panel used for the electro-optical apparatus to which this invention is applied. It is sectional drawing of the liquid crystal panel shown in FIG. It is a top view which shows the one aspect | mode of the adjacent pixel in the element substrate of the electro-optical apparatus to which this invention is applied. It is sectional drawing which shows typically the one aspect | mode of the pixel of the electro-optical apparatus to which this invention is applied. FIG. 5 is a plan view of the pixel transistor shown in FIGS. 3 and 4. FIG. 5 is a plan view of the source electrode and the first drain electrode shown in FIGS. 3 and 4. FIG. 5 is a plan view of a data line and a second drain electrode shown in FIGS. 3 and 4. FIG. 5 is a plan view of a first capacitor electrode (capacitor line) shown in FIGS. 3 and 4. FIG. 5 is a plan view of a second capacitor electrode and a first dielectric layer shown in FIGS. 3 and 4. FIG. 5 is a plan view of a third capacitor electricity, a second dielectric layer, and a relay electrode shown in FIGS. 3 and 4. FIG. 5 is a plan view of the pixel electrode shown in FIGS. 3 and 4. It is process sectional drawing which shows the manufacturing method of the electro-optical apparatus to which this invention is applied. It is process sectional drawing which shows the manufacturing method of the electro-optical apparatus to which this invention is applied. It is process sectional drawing which shows the manufacturing method of the electro-optical apparatus to which this invention is applied. It is process sectional drawing which shows the manufacturing method of the electro-optical apparatus to which this invention is applied. It is process sectional drawing which shows the manufacturing method of the electro-optical apparatus to which this invention is applied. It is a schematic block diagram of an aspect of a projection display device (electronic apparatus) using an electro-optical device to which the present invention is applied.

  Embodiments of the present invention will be described with reference to the drawings. In the drawings to be referred to in the following description, the scales are different for each layer and each member so that each layer and each member have a size that can be recognized on the drawing. In addition, when a driving method that reverses the direction of the current flowing through the pixel transistor is used, the source and the drain are interchanged. In the following description, the side to which the pixel electrode is connected (pixel side source / drain region) is defined as the drain. The side to which the data line is connected (data line side source / drain region) is the source. Further, when describing the layers formed on the element substrate, the upper layer side or the surface side means the side opposite to the side where the substrate body of the element substrate is located (the side on which the counter substrate is located), and the lower layer side means It means the side where the substrate body of the element substrate is located (the side opposite to the side where the counter substrate is located).

[Description of electro-optical device (liquid crystal device)]
(overall structure)
FIG. 1 is a block diagram showing an aspect of an electrical configuration of an electro-optical device to which the present invention is applied. Note that FIG. 1 is a block diagram showing the electrical configuration to the last, and therefore the layout, such as the direction in which the capacitor electrodes extend, is schematically shown.

  In FIG. 1, an electro-optical device 100 (liquid crystal device) of this embodiment includes a liquid crystal panel 100p in a TN (Twisted Nematic) mode or a VA (Vertical Alignment) mode, and the liquid crystal panel 100p includes a plurality of liquid crystal panels 100p in the central region. Pixels 100a are provided with an image display area 10a (pixel area) arranged in a matrix. In the liquid crystal panel 100p, in an element substrate 10 (see FIG. 2 and the like) to be described later, a plurality of data lines 5a and a plurality of scanning lines 3a extend vertically and horizontally inside the image display region 10a. A pixel 100a is configured at a position corresponding to. In each of the plurality of pixels 100a, a pixel transistor 30 made of a field effect transistor or the like and a pixel electrode 9a described later are formed. The data line 5 a is electrically connected to the source of the pixel transistor 30, the scanning line 3 a is electrically connected to the gate of the pixel transistor 30, and the pixel electrode 9 a is electrically connected to the drain of the pixel transistor 30. Has been.

  In the element substrate 10, a scanning line driving circuit 104 and a data line driving circuit 101 are provided on the outer peripheral side of the image display region 10 a. The data line driving circuit 101 is electrically connected to each data line 5a, and sequentially supplies the image signal supplied from the image processing circuit to each data line 5a. The scanning line driving circuit 104 is electrically connected to each scanning line 3a, and sequentially supplies a scanning signal to each scanning line 3a.

  In each pixel 100a, the pixel electrode 9a is opposed to a common electrode formed on a counter substrate 20 (see FIG. 2 and the like), which will be described later, via a liquid crystal layer, thereby forming a liquid crystal capacitor 50a. Each pixel 100a is provided with a holding capacitor 55 in parallel with the liquid crystal capacitor 50a in order to prevent fluctuation of the image signal held in the liquid crystal capacitor 50a. In this embodiment, in order to configure the storage capacitor 55, a first capacitor electrode 6a (capacitor line) to which a fixed potential (common potential Vcom) is applied is provided, and the first capacitor electrode 6a is connected to the constant potential line 5c. Is conducting.

(Configuration of the liquid crystal panel 100p)
FIG. 2 is a plan view showing an aspect of the liquid crystal panel 100p used in the electro-optical device 100 to which the present invention is applied. 3 is a cross-sectional view (HH ′ cross-sectional view) of the liquid crystal panel 100p shown in FIG.

  As shown in FIGS. 2 and 3, in the liquid crystal panel 100p, the element substrate 10 (element substrate for the electro-optical device) and the counter substrate 20 are bonded to each other with a sealant 107 through a predetermined gap. Reference numeral 107 denotes a frame shape along the outer edge of the counter substrate 20. The sealing material 107 is an adhesive made of a photo-curing resin, a thermosetting resin, or the like, and is mixed with a gap material such as glass fiber or glass beads for setting the distance between both substrates to a predetermined value.

  In the liquid crystal panel 100p of this embodiment, the element substrate 10 and the counter substrate 20 are both square, and the image display area 10a described with reference to FIG. 1 is provided as a square area in the approximate center of the liquid crystal panel 100p. ing. Corresponding to this shape, the sealing material 107 is also provided in a substantially rectangular shape, and a substantially rectangular peripheral region 10b is provided in a frame shape between the inner peripheral edge of the sealing material 107 and the outer peripheral edge of the image display region 10a. Yes. In the element substrate 10, a data line driving circuit 101 and a plurality of terminals 102 are formed along one side of the element substrate 10 outside the image display region 10 a, and scanning lines are formed along other sides adjacent to the one side. A drive circuit 104 is formed. Note that a flexible wiring board (not shown) is connected to the terminal 102, and various potentials and various signals are input to the element substrate 10 through the flexible wiring board.

  As will be described in detail later, on the one surface 10s side of the one surface 10s and the other surface 10t of the element substrate 10, the pixel transistor 30 and the pixel transistor 30 described with reference to FIG. The pixel electrodes 9a to be connected are formed in a matrix, and an alignment film 16 is formed on the upper layer side of the pixel electrodes 9a. On the one surface 10s side of the element substrate 10, a dummy pixel electrode 9b formed simultaneously with the pixel electrode 9a is formed in the peripheral region 10b.

  A common electrode 21 is formed on one surface of the counter substrate 20 facing the element substrate 10, and an alignment film 26 is formed on the surface of the common electrode 21 on the element substrate 10 side. The common electrode 21 is formed on substantially the entire surface of the counter substrate 20. A light shielding layer 108 is formed on a lower layer side of the common electrode 21 on one surface side of the counter substrate 20 facing the element substrate 10. In this embodiment, the light shielding layer 108 is formed in a frame shape extending along the outer peripheral edge of the image display region 10a, and functions as a parting. The outer peripheral edge of the light shielding layer 108 is located with a gap between the inner peripheral edge of the sealing material 107 and the light shielding layer 108 and the sealing material 107 do not overlap. In the counter substrate 20, the light shielding layer 108 may be formed as a black matrix portion in an area that overlaps an inter-pixel area sandwiched between adjacent pixel electrodes 9 a. The counter substrate 20 may be configured as a lens array substrate on which lenses (microlenses) that face each of the plurality of pixel electrodes 9a are formed.

  In the liquid crystal panel 100p, the element substrate 10 is for inter-substrate conduction for providing electrical continuity between the element substrate 10 and the counter substrate 20 in a region overlapping the corner portion of the counter substrate 20 outside the sealant 107. An electrode 109 is formed. The inter-substrate conducting electrode 109 is provided with an inter-substrate conducting material 109 a containing conductive particles, and the common electrode 21 of the counter substrate 20 is connected via the inter-substrate conducting material 109 a and the inter-substrate conducting electrode 109. It is electrically connected to the element substrate 10 side. Therefore, the common potential Vcom is applied to the common electrode 21 from the element substrate 10 side. The sealing material 107 is provided along the outer peripheral edge of the counter substrate 20 with substantially the same width dimension. For this reason, the sealing material 107 is substantially rectangular. However, the sealing material 107 is provided so as to pass inside avoiding the inter-substrate conduction electrode 109 in a region overlapping the corner portion of the counter substrate 20, and the corner portion of the sealing material 107 has a substantially arc shape.

  In the electro-optical device 100, when the pixel electrode 9a and the common electrode 21 are formed of a light-transmitting conductive film such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), a transmissive liquid crystal device can be configured. . On the other hand, when the common electrode 21 is formed of a translucent conductive film and the pixel electrode 9a is formed of a reflective conductive film such as aluminum, a reflective liquid crystal device can be configured. When the electro-optical device 100 is a reflection type, light incident from the counter substrate 20 side is modulated while being reflected and emitted by the substrate on the element substrate 10 side, and an image is displayed. In the case where the electro-optical device 100 is a transmissive type, the light incident from one of the element substrate 10 and the counter substrate 20 is modulated while being transmitted through the other substrate and emitted to display an image. . In this embodiment, the electro-optical device 100 is configured as a transmissive liquid crystal device.

  The electro-optical device 100 can be used as a color display device of an electronic device such as a mobile computer or a mobile phone. In this case, a color filter (not shown) and a protective film are formed on the counter substrate 20. In the electro-optical device 100, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction with respect to the liquid crystal panel 100p according to the type of the liquid crystal layer 50 to be used and the normally white mode / normally black mode. Is done. Furthermore, the electro-optical device 100 can be used as a light valve for RGB in a projection display device (liquid crystal projector) described later. In this case, each of the RGB electro-optical devices 100 receives light of each color separated through RGB color separation dichroic mirrors as projection light, so that no color filter is formed. .

  In this embodiment, the electro-optical device 100 is a transmissive liquid crystal device used as an RGB light valve in a projection display device described later, and light incident from the counter substrate 20 is transmitted through the element substrate 10. The explanation will be focused on the case of emission. In the present embodiment, the electro-optical device 100 will be described focusing on the case where the liquid crystal layer 50 includes a VA mode liquid crystal panel 100p using a nematic liquid crystal compound having a negative dielectric anisotropy.

(Specific pixel configuration)
FIG. 4 is a plan view showing an aspect of adjacent pixels in the element substrate 10 of the electro-optical device 100 to which the present invention is applied. FIG. 5 is a cross-sectional view schematically showing one aspect of a pixel of the electro-optical device 100 to which the present invention is applied. 5 shows a state in which the electro-optical device 100 is cut along a conduction portion between the data line 5a, the pixel transistor 30, the scanning line 3a, the pixel electrode 9a, and the relay electrode 8b. The drain region 1c of the pixel transistor 30 and the like are also shown so that the general connection relationship can be easily understood.

  FIG. 6 is a plan view of the pixel transistor 30 shown in FIGS. 3 and 4. FIG. 7 is a plan view of the source electrode 4a and the first drain electrode 4b shown in FIGS. FIG. 8 is a plan view of the data line 5a and the second drain electrode 5b. FIG. 9 is a plan view of the first capacitor electrode 6a (capacitor line) shown in FIG. 3 and FIG. FIG. 10 is a plan view of the second capacitor electrode 7a and the first dielectric layer 55e shown in FIG. 3 and FIG. FIG. 11 is a plan view of the third capacitor electrode 8a, the second dielectric layer 55f, and the relay electrode 8b shown in FIGS. FIG. 12 is a plan view of the pixel electrode 9a shown in FIGS.

  In addition, in FIG.4, FIG.6, FIG.7, FIG.8, FIG.9, FIG.10, FIG.11, and FIG. FIG. 4 shows only the outer edge of the pixel electrode 9a, and the refractive index adjusting dielectric film 96a is not formed.

4 and 6
Scanning line 3a = thin solid line Semiconductor layer 1a = thin and short dotted line Gate electrode 3b = thick solid line FIGS. 4 and 7
Source electrode 4a and first drain electrode 4b = thick dashed line
Data line 5a and second drain electrode 5b = thin alternate long and short dash line FIG. 4 and FIG.
First capacitor electrode 6a (capacitor line) = thin two-dot chain line
Second capacitor electrode 7a = thin and long broken line First dielectric layer 55e = thick and short broken line Recess 7e = thin and short broken line FIGS. 4 and 11
Third capacitor electrode 8a and relay electrode 8b = thick two-dot chain line Through hole 44c = thin and short broken line second dielectric layer 55f = thick and short broken line FIGS. 4 and 12
Pixel electrode 9a (first translucent conductive film 91a, second translucent conductive film 92a) = thick and long broken line Pixel electrode 9a refractive index adjusting dielectric film 96a = thin dashed line

  As shown in FIG. 4, on the element substrate 10, a rectangular pixel electrode 9a is formed on each of the plurality of pixels 100a. Although the plurality of pixel electrodes 9a have the same configuration, in FIGS. 4 and 12, one of the plurality of pixel electrodes 9a is a first pixel electrode 9a1 and is adjacent to the first pixel electrode 9a1. The matching pixel electrode 9a is represented as a second pixel electrode 9a2. Of the plurality of pixel electrodes 9a, the data lines 5a and the scanning lines 3a are formed along regions overlapping the vertical and horizontal inter-pixel regions 10f sandwiched between adjacent pixel electrodes 9a. That is, in the inter-pixel region 10f, the scanning line 3a extends along the first inter-pixel region 10g extending in the first direction (X direction), and the second extends in the second direction (Y direction). A data line 5a extends along the inter-pixel region 10h. Each of the data line 5a and the scanning line 3a extends linearly, and a pixel transistor 30 is formed corresponding to a portion where the data line 5a and the scanning line 3a intersect.

  As shown in FIG. 5, in the element substrate 10, the pixel transistor 30, the pixel electrode 9 a, and the alignment are arranged on the surface (one surface 10 s side) of the translucent substrate main body 10 w such as a quartz substrate or a glass substrate. A film 16 and the like are configured. In the counter substrate 20, the common electrode 21, the alignment film 26, and the like are configured on the surface of the light transmitting substrate main body 20 w such as a quartz substrate or a glass substrate on the liquid crystal layer 50 side (one surface side facing the element substrate 10). ing.

More specifically, first, in the element substrate 10, the scanning line 3a made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal film compound is formed on the one surface 10s side of the substrate body 10w. Is formed. In this embodiment, the scanning line 3 a is made of a light-shielding conductive film such as tungsten silicide (WSi _x ), and also functions as a light-shielding film for the pixel transistor 30.

  A light-transmitting base insulating film 40 such as a silicon oxide film is formed on the upper layer side of the scanning line 3a (the side opposite to the substrate body 10w with respect to the scanning line 3a). On the upper layer side of the base insulating film 40 (on the side opposite to the substrate body 10 w with respect to the base insulating film 40), the semiconductor layer 1 a of the pixel transistor 30 is formed. The pixel transistor 30 includes a semiconductor layer 1a extending along the data line 5a, and a gate electrode 3c overlapping the central portion in the extending direction of the semiconductor layer 1a (see FIG. 6). The pixel transistor 30 has a translucent gate insulating layer 2 between the semiconductor layer 1a and the gate electrode 3c. The semiconductor layer 1a includes a channel region 1g facing the gate electrode 3c via the gate insulating layer 2, and includes a source region 1b and a drain region 1c on both sides of the channel region 1g. In this embodiment, the pixel transistor 30 has an LDD structure. Therefore, each of the source region 1b and the drain region 1c includes the low concentration regions 1b1 and 1c1 on both sides of the channel region 1g, and the high concentration in the region adjacent to the low concentration regions 1b1 and 1c1 on the opposite side to the channel region 1g. Regions 1b2 and 1c2 are provided.

  The semiconductor layer 1a is composed of a polycrystalline silicon film or the like. The gate insulating layer 2 is, for example, a two-layer structure of a first gate insulating layer made of a silicon oxide film obtained by thermally oxidizing the semiconductor layer 1a and a second gate insulating layer made of a silicon oxide film formed by a CVD method or the like. Consists of. The gate electrode 3c is made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal film compound, and is a contact hole penetrating the gate insulating layer 2 and the base insulating film 40 on both sides of the semiconductor layer 1a. It is electrically connected to the scanning line 3a through 2a (see FIG. 6). The gate electrode 3c has, for example, a two-layer structure of a conductive polysilicon film and a tungsten silicide film. In this embodiment, when the light after passing through the electro-optical device 100 is reflected by another member, the reflected light is prevented from entering the semiconductor layer 1a and causing malfunction due to the photocurrent in the pixel transistor 30. For this purpose, the scanning line 3a is formed of a light-shielding conductive film. However, the scanning line 3a may be formed in the upper layer of the gate insulating layer 2, and a part thereof may be used as the gate electrode 3c. In this case, the scanning line 3a is formed only for light shielding.

  A translucent interlayer insulating film 41 is formed on the upper layer side of the gate electrode 3c (between the gate electrode 3c and the pixel electrode 9a). The interlayer insulating film 41 is made of a silicon oxide film or the like formed by a plasma CVD method or the like.

  On the upper layer side of the interlayer insulating film 41 (between the interlayer insulating film 41 and the pixel electrode 9a), the source electrode 4a and the first drain electrode 4b are formed of the same type of conductive film. The source electrode 4a and the first drain electrode 4b are made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal film compound. In this embodiment, the source electrode 4a and the first drain electrode 4b are, for example, a multilayer film of a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum (Al) film, or a multilayer film of a titanium nitride film and an aluminum film. It consists of a film. The source electrode 4a is electrically connected to the source region 1b through a contact hole 41a penetrating the interlayer insulating film 41 and the gate insulating layer 2. The first drain electrode 4 b is electrically connected to the drain region 1 c through a contact hole 41 b that penetrates the interlayer insulating film 41 and the gate insulating layer 2. The source electrode 4a extends in the second direction Y from a position overlapping the source region 1b of the pixel transistor 30, and the first drain electrode 4b extends in the first direction X from a position overlapping the drain region 1c of the pixel transistor 30. (See FIG. 7).

  A translucent interlayer insulating film 42 is formed on the upper layer side (between the source electrode 4a and the pixel electrode 9a) of the source electrode 4a and the first drain electrode 4b. The interlayer insulating film 42 is made of, for example, a silicon oxide film formed by a plasma CVD method or the like. In this embodiment, the surface of the interlayer insulating film 42 is a flat surface 420 by chemical mechanical polishing or the like.

  On the upper layer side of the interlayer insulating film 42 (between the interlayer insulating film 42 and the pixel electrode 9a), the data line 5a and the second drain electrode 5b are formed of the same type of conductive film. The data line 5a and the second drain electrode 5b are made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal film compound. In this embodiment, the data line 5a and the second drain electrode 5b are made of, for example, a multilayer film of a titanium film, a titanium nitride film, and an aluminum film, or a multilayer film of a titanium nitride film and an aluminum film. The data line 5a is electrically connected to the source electrode 4a through a contact hole 42a penetrating the interlayer insulating film 42. The second drain electrode 5 b is electrically connected to the first drain electrode 4 b through a contact hole 42 b that penetrates the interlayer insulating film 42. The data line 5a extends in the second direction Y from a position overlapping the source electrode 4a in a region overlapping the second inter-pixel region 10h. The second drain electrode 5b extends in a first direction X from a position overlapping the first drain electrode 4b in a region overlapping with the first inter-pixel region 10g, and via a contact hole 42b at a substantially central position in the first direction X. Is electrically connected to the first drain electrode 4b (see FIG. 8).

  A translucent interlayer insulating film 43 is formed on the upper side of the data line 5a and the second drain electrode 5b (between the data line 5a and the pixel electrode 9a). The interlayer insulating film 43 is made of, for example, a silicon oxide film formed by a plasma CVD method or the like. In this embodiment, the surface of the interlayer insulating film 43 is a flat surface 430 by chemical mechanical polishing or the like.

  A first capacitor electrode 6a (capacitor line) is formed on the interlayer insulating film 43 (between the interlayer insulating film 43 and the pixel electrode 9a). The first capacitor electrode 6a is made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal film compound. In this embodiment, the first capacitor electrode 6a is made of, for example, a multilayer film of a titanium film, a titanium nitride film, and an aluminum film, or a multilayer film of a titanium nitride film and an aluminum film. The first capacitor electrode 6a includes a main line portion 6a1 extending in the second direction Y so as to overlap with the data line 5a in plan view, and one side in the first direction X so as to overlap with the scanning line 3a from the main line portion 6a1 in plan view. And a branch line portion 6a2 protruding to the side X1 (see FIG. 9).

  A translucent interlayer insulating film 44 (third insulating film) is formed on the first capacitor electrode 6a (between the first capacitor electrode 6a and the pixel electrode 9a). The interlayer insulating film 44 is made of, for example, a silicon oxide film formed by a plasma CVD method or the like.

  A through hole 44c reaching the first capacitor electrode 6a is formed in the interlayer insulating film 44. Inside the through hole 44c, the upper layer side of the first capacitor electrode 6a (the first capacitor electrode 6a and the pixel electrode 9a) is formed. The second capacitor electrode 7a is provided so as to overlap the first capacitor electrode 6a in plan view. The through hole 44c has a first portion 44c1 extending from the intersection of the data line 5a and the scanning line 3a to the one side X1 in the first direction X along the scanning line 3a in the first inter-pixel region 10g. (See FIG. 10). The through hole 44c has a second portion 44c2 extending from the intersection of the data line 5a and the scanning line 3a to the one side Y1 in the second direction Y along the data line 5a in the second inter-pixel region 10h. (See FIG. 10).

  A first dielectric layer 55e is provided between the first capacitor electrode 6a and the second capacitor electrode 7a. The first dielectric layer 55e is formed on the entire bottom and side surfaces of the through hole 44c. Therefore, in the entire bottom of the through hole 44c, the first capacitor electrode 6a, the first dielectric layer 55e, and the second capacitor electrode 7a are sequentially overlapped with each other at the bottom of the through hole 44c, and the first bottom of the through hole 44c One holding capacitor 55a is configured. As the first dielectric layer 55e, a silicon compound such as a silicon oxide film or a silicon nitride film can be used, and an aluminum oxide film, a titanium oxide film, a tantalum oxide film, a niobium oxide film, a hafnium oxide film, or a lanthanum oxide film. A dielectric layer having a high dielectric constant such as a zirconium oxide film can be used.

  In this embodiment, the interlayer insulating film 44 is formed between the first capacitor electrode 6a and the first dielectric layer 55e among the first capacitor electrode 6a and the second capacitor electrode 7a. Therefore, the first dielectric layer 55e is also formed on a part of the surface of the interlayer insulating film 44 in addition to the inside of the through hole 44c. The second capacitor electrode 7a is formed over a wider area than the formation region of the through hole 44c, and is electrically connected to the second drain electrode 5b via the interlayer insulating film 43 and the contact hole 44b penetrating the interlayer insulating film 44. Yes. Accordingly, the second capacitor electrode 7 a is electrically connected to the drain region 1 c of the pixel transistor 30 via the contact hole 44 b of the interlayer insulating film 44. In this embodiment, the contact hole 44b is formed in the end portion 7a3 on the one side X1 in the portion extending in the first direction X of the second capacitor electrode 7a (see FIG. 10). Note that the end portion on the one side X1 in the first direction X of the second capacitor electrode 7a protrudes toward the one side Y1 in the second direction Y.

  A third capacitor electrode 8a is provided on the upper layer side of the second capacitor electrode 7a (between the second capacitor electrode 7a and the pixel electrode 9a) so as to overlap the second capacitor electrode 7a in plan view. The third capacitor electrode 8a extends in the second direction Y so as to overlap the data line 5a and the first capacitor electrode 6a in plan view, and overlaps the scan line 3a from the main line portion 8a1 in plan view. And a branch line portion 8a2 protruding to one side X1 in the first direction X (see FIG. 11).

  A second dielectric layer 55f is provided between the second capacitor electrode 7a and the third capacitor electrode 8a. The second capacitor electrode 7a has a shape including a recess 7e reflected by the through hole 44c. Accordingly, the second capacitor electrode 7a, the second dielectric layer 55f, and the third capacitor electrode 8a are sequentially overlapped on the bottom and side surfaces of the recess 7e, and the second storage capacitor 55b is configured on the entire bottom and side surfaces of the recess 7e. Has been. In the present embodiment, the second dielectric layer 55f and the third capacitor electrode 8a are also provided with recesses by the through holes 44c, like the second capacitor electrode 7a. As the second dielectric layer 55f, a silicon compound such as a silicon oxide film or a silicon nitride film can be used, an aluminum oxide film, a titanium oxide film, a tantalum oxide film, a niobium oxide film, a hafnium oxide film, or a lanthanum oxide film. A dielectric layer having a high dielectric constant such as a zirconium oxide film can be used.

  The third capacitor electrode 8a is formed over a wider area than the formation region of the recess 7e, and is electrically connected to the first capacitor electrode 6a through a contact hole 44a penetrating the interlayer insulating film 44. For this reason, the first storage capacitor 55a and the second storage capacitor 55b are connected in parallel between the first capacitor electrode 6a and the second capacitor electrode 7a to form the storage capacitor 55. The storage capacitor 55 is formed in a region overlapping the through hole 44c in plan view. Therefore, the storage capacitor 55 extends from the intersection of the data line 5a and the scanning line 3a to the one side X1 in the first direction X along the scanning line 3a in the first inter-pixel region 10g. In the inter-region 10h, the data line 5a and the scanning line 3a extend from the intersecting portion to the one side Y1 in the second direction Y along the data line 5a. Further, the contact hole 44a is provided at a position spaced apart from the storage capacitor 55 on one side Y1 in the second direction Y in the region where the third capacitor electrode 8a is formed (see FIG. 11).

  In this embodiment, a light-transmitting interlayer insulating film 45 (first insulating film) is formed between the second capacitor electrode 7a and the third capacitor electrode 8a. The interlayer insulating film 45 is made of, for example, a silicon oxide film formed by a plasma CVD method or the like. The second dielectric layer 55f is also formed on a part of the surface of the interlayer insulating film 45 in addition to the inside of the recess 7e. In this embodiment, the interlayer insulating film 45 is formed between the second capacitor electrode 7a and the second dielectric layer 55f among the layers between the second capacitor electrode 7a and the third capacitor electrode 8a. Alternatively, it may be formed between the second dielectric layer 55f and the third capacitor electrode 8a.

  On the interlayer insulating film 45, a protrusion 45e protruding toward the pixel electrode 9a is formed. In this embodiment, the convex portion 45e is formed at a position adjacent to the contact hole 44b of the interlayer insulating film 44 in plan view. The protrusion 45e may be formed at a position overlapping the contact hole 44b of the interlayer insulating film 44 in plan view. A relay electrode 8b is formed on the interlayer insulating film 45 (between the interlayer insulating film 45 and the pixel electrode 9a). In this embodiment, the relay electrode 8b is formed in the same layer as the third capacitor electrode 8a, and is electrically connected to the exposed portion of the second capacitor electrode 7a from the interlayer insulating film 45. More specifically, the relay electrode 8 b is electrically connected to the second capacitor electrode 7 a through a contact hole 45 a that penetrates the interlayer insulating film 45. The relay electrode 8b is formed at a position separated from the branch line portion 8a2 of the third capacitor electrode 8a on one side X1 in the first direction X, and overlaps the end portion 7a3 of the second capacitor electrode 7a in plan view. A contact hole 45a is formed in the contact hole 45a (see FIG. 11). In addition, the relay electrode 8b includes a conduction portion 8c that overlaps the tip surface 45f of the convex portion 45e in plan view.

  A light-transmitting interlayer insulating film 46 (second insulating film) is formed between the relay electrode 8b and the pixel electrode 9a. The interlayer insulating film 46 is made of, for example, a silicon oxide film formed by a plasma CVD method or the like. The interlayer insulating film 46 is formed with a flat surface 460 that exposes the conductive portion 8c on the pixel electrode 9a side, and the pixel electrode 9a is in contact with the exposed portion of the conductive portion 8c from the flat surface 460.

  In this embodiment, a light-transmitting insulating film 47 (fourth insulating film) is formed between the interlayer insulating film 46 and the pixel electrode 9a. An opening 47a is formed in the interlayer insulating film 47 so as to overlap at least a part of the exposed portion from the flat surface 460 of the conductive portion 8c. The pixel electrode 9a is in contact with the conductive portion 8c inside the opening 47a. Yes. Here, the insulating film 47 is thinner than the interlayer insulating film 46. For this reason, the depth of the opening 47a is shallow. In this embodiment, the insulating film 47 is made of boron, silicate, glass, or the like. For this reason, since the water | moisture content which entered in the middle of the manufacturing process and the water | moisture content which exists in the liquid crystal layer 50 can be hold | maintained, deterioration of the liquid crystal layer 50 resulting from a water | moisture content can be suppressed.

  As shown in FIGS. 5 and 12, the pixel electrode 9a includes at least a first translucent conductive film 91a made of an ITO film, a refractive index adjusting dielectric film 96a, and a second translucent conductive film made of an ITO film. It consists of a laminated film (IMITO film: Index Matched ITO) in which 92a are laminated in order. In this embodiment, the pixel electrode 9a has a three-layer structure in which a first translucent conductive film 91a, a refractive index adjusting dielectric film 96a, and a second translucent conductive film 92a are sequentially stacked. Therefore, by adjusting the refractive index and film thickness of each of the first light-transmissive conductive film 91a, the refractive index adjusting dielectric film 96a, and the second light-transmissive conductive film 92a, the light of the pixel electrode 9a can be transmitted. Wavelength dispersion can be suppressed.

  The first translucent conductive film 91a and the second translucent conductive film 92a have the same formation region, and have the same shape and overlap in plan view. The first translucent conductive film 91a and the second translucent conductive film 92a are formed in a wider area than the refractive index adjusting dielectric film 96a, and project from the end of the refractive index adjusting dielectric film 96a. Yes. Therefore, the first translucent conductive film 91a and the second translucent conductive film 92a are in contact with each other at the projecting portions 91e and 92e from the end of the refractive index adjusting dielectric film 96a and are electrically connected. Therefore, the first translucent conductive film 91a and the second translucent conductive film 92a can be made conductive without forming a contact hole in the refractive index adjusting dielectric film 96a. Therefore, even when the electrical resistance of the pixel electrode 9a is reduced, the unevenness due to the contact hole can be prevented from occurring in the pixel electrode 9a. The refractive index adjusting dielectric film 96a is not formed in a region overlapping the connecting portion (opening 47a) between the pixel electrode 9a and the conducting portion 8c in plan view.

(Method of manufacturing electro-optical device 100)
With reference to FIGS. 13 to 17, the manufacturing process of the element substrate 10 among the manufacturing processes of the electro-optical device 100 will be described. 13 to 17 are process cross-sectional views illustrating a method for manufacturing the electro-optical device 100 to which the present invention is applied. 15 to 17, only the upper layer side from the first capacitance electrode 6a is shown.

  In the pixel transistor formation step ST1 shown in FIG. 13, after the pixel transistor 30 is formed, the interlayer insulating film 41, the source electrode 4a, and the first drain electrode 4b are formed. Next, in the data line forming step ST2, after forming the interlayer insulating film 42, contact holes 42a and 42b are formed, and then the data line 5a and the second drain electrode 5b are formed. Next, in the first capacitor electrode forming step ST3, after forming the interlayer insulating film 43, the first capacitor electrode 6a is formed. Note that after the interlayer insulating film 42 is formed and after the interlayer insulating film 43 is formed, a planarization process such as chemical mechanical polishing is performed to make the surfaces of the interlayer insulating films 42 and 43 flat surfaces 420 and 430, respectively. .

  Next, in the through hole forming step ST4 shown in FIG. 14, after forming the interlayer insulating film 44, the through hole 44 c is formed in the interlayer insulating film 44. At this time, a contact hole 44 b penetrating the interlayer insulating film 44 and the interlayer insulating film 43 is also formed. Next, in the second capacitor electrode formation step ST5, after forming the dielectric film, the dielectric film is patterned to form the first dielectric layer 55e. Next, after forming the conductive film, the conductive film is patterned to form the second capacitor electrode 7a. In addition, after forming the first dielectric layer 55e, a contact hole 44b penetrating the interlayer insulating film 44 and the interlayer insulating film 43 may be formed.

  Next, in the interlayer insulating film forming step ST6 shown in FIG. 15, after the interlayer insulating film 45 is formed, the interlayer insulating film 45 is etched in the interlayer insulating film etching step ST7, from the region where the through hole 44c is formed. The interlayer insulating film 45 is removed. At this time, the mask formation step and etching are performed a plurality of times to form contact holes 45a and protruding portions 45e protruding upward in the interlayer insulating film 45. Note that after forming an etching mask by a photolithography process using a halftone mask, etching may be performed to form the interlayer insulating film 45 including the contact holes 45a and the protrusions 45e. Next, in a contact hole forming step ST8, a contact hole 44a is formed in the interlayer insulating film 44. Such a contact hole 44a may be formed in the interlayer insulating film etching step ST7. Next, in the third capacitor electrode forming step ST9, after forming the dielectric film, the dielectric film is patterned to form the second dielectric layer 55f. Next, after forming a conductive film, the conductive film is patterned to form a third capacitor electrode 8a. At that time, the relay electrode 8b having the conductive portion 8c is simultaneously formed on the tip surface 45f of the convex portion 45e of the interlayer insulating film 45.

  Next, in an interlayer insulating film forming step ST10 shown in FIG. 16, an interlayer insulating film 46 made of a silicon oxide film or the like is formed. Next, in the planarization step ST11, the interlayer insulation film 46 is subjected to a planarization process such as chemical mechanical polishing, so that the surface of the interlayer insulation film 46 becomes a flat surface 460. As a result, the conductive portion 8 c is exposed from the flat surface 460, and the conductive portion 8 c constitutes a plane that is continuous with the flat surface 460. Next, in an insulating film forming step ST12, an insulating film 47 made of boron, silicate, glass or the like is formed. Since the insulating film 47 is formed on the flat surface 460 of the interlayer insulating film 46 and the surface of the conductive portion 8 c, the surface is a flat surface 470. Next, in the opening forming step, the opening 47a is formed in a region overlapping the conductive portion 8c of the insulating film 47 in plan view.

  Next, in the first translucent conductive film step ST14 shown in FIG. 17, a translucent conductive film 91 made of an ITO film is formed. Next, in the refractive index adjusting dielectric film step ST15, after forming the translucent insulating film, the translucent insulating film is patterned, and the refractive index adjusting dielectric is formed in a region inside the formation region of the pixel electrode 9a. Leave film 96a. At this time, the refractive index adjusting dielectric film 96a is removed from the region overlapping the opening 47a in plan view. Next, in the second light transmissive conductive film step ST16, a light transmissive conductive film 92 made of an ITO film is formed. Next, in the translucent conductive film patterning step ST17, the translucent conductive film 91 and the translucent conductive film 92 are collectively etched outside the outer edge of the refractive index adjusting dielectric film 96a to obtain the first translucent film. The pixel electrode 9a is formed by laminating the conductive film 91a, the refractive index adjusting dielectric film 96a, and the second translucent conductive film 92a. After that, as shown in FIG. 5, if the alignment film 16 is formed on the surface of the pixel electrode 9a, the element substrate 10 is completed. In the pixel electrode 9a, in addition to the first translucent conductive film 91a, the refractive index adjusting dielectric film 96a, and the second translucent conductive film 92a, the translucent conductive film and the translucent insulating film are further provided. May be added and laminated.

(Main effects of this form)
As described above, in the electro-optical device 100 according to this embodiment, the interlayer insulating film 45 (first insulating film) provided between the second capacitor electrode 7a and the pixel electrode 9a has a planar view with the pixel electrode 9a. A projecting portion 45e that protrudes toward the pixel electrode 9a is formed at a position overlapping with the conductive electrode 8b, and the conducting portion 8c of the relay electrode 8b overlaps the tip surface 45f of the projecting portion 45e in plan view. The surface of the interlayer insulating film 46 (second insulating film) provided between the relay electrode 8b and the pixel electrode 9a is a flat surface 460 that exposes the conductive portion 8c, and the pixel electrode 9a is conductive. The portion 8c is in contact with the exposed portion from the flat surface 460. For this reason, it is possible to suppress the formation of large irregularities on the pixel electrode 9a.

  In the storage capacitor 55, the first capacitor electrode 6a, the first dielectric layer 55e to which the constant potential is applied, the second capacitor electrode 7a in which the pixel electrode 9a is conducted, the second dielectric layer 55f, and the constant potential are applied. The third capacitor electrodes 8a thus formed are sequentially stacked. Therefore, the first storage capacitor 55a formed by the first capacitor electrode 6a, the first dielectric layer 55e, and the second capacitor electrode 7a, the second capacitor electrode 7a, the second dielectric layer 55f, and the third capacitor electrode 8a. Is connected in parallel with the second holding capacitor 55b. For this reason, the storage capacitor 55 having a high electrostatic capacity can be provided in a narrow area.

  The third capacitor electrode 8a located closest to the pixel electrode 9a in the storage capacitor 55 is applied with a constant potential, and the second capacitor electrode 7a to which the same potential as the pixel electrode 9a is applied has a constant potential. It is located on the opposite side to the pixel electrode 9a with respect to the applied third capacitance electrode 8a. Therefore, when one of the plurality of pixel electrodes 9a is the first pixel electrode 9a1 and the pixel electrode 9a adjacent to the first pixel electrode 9a1 is the second pixel electrode 9a2, the potential of the second capacitor electrode 7a ( It is possible to appropriately provide the storage capacitor 55 having a high capacitance such that the potential of the first pixel electrode 9a1 is less likely to affect the potential of the adjacent pixel electrode 9a (second pixel electrode 9a2). In addition, the third capacitor electrode 8a is provided in a region overlapping the region sandwiched between adjacent pixel electrodes 9a (inter-pixel region 10f) in plan view to prevent display light from being blocked by the third capacitor electrode 8a. Even in this case, the potential of the second capacitor electrode 7a (pixel electrode 9a (potential of the first pixel electrode 9a1)) hardly affects the potential of the adjacent pixel electrode 9a (second pixel electrode 9a2). In addition, since the third capacitor electrode 8a extends from the intersection of the data line 5a and the scanning line 3a in the direction along the data line 5a and the direction along the scanning line 3a, the third capacitance electrode 8a has a large storage capacitance 55. Can be provided.

  The third capacitor electrode 8a and the relay electrode 8b are provided in the same layer. For this reason, since the 3rd capacity electrode 8a and the relay electrode 8b can be formed simultaneously, the number of manufacturing processes can be reduced.

  Further, in the interlayer insulating film 44 (third insulating film) provided between the first capacitor electrode 6a and the second capacitor electrode 7a, the first capacitor electrode 6a and the second capacitor electrode 7a at the bottom are the first dielectric. A through hole 44c is formed so as to overlap with the body layer 55e. Further, the second capacitor electrode 7a and the third capacitor electrode 8a overlap with each other through the second dielectric layer 55f on the bottom and side surfaces of the recess 7e reflecting the through hole 44c in the second capacitor electrode 7a. For this reason, since the corresponding area of the 2nd capacity electrode 7a and the 3rd capacity electrode 8a is wide, the retention capacity 55 with big electrostatic capacity can be constituted.

  In this embodiment, a thin insulating film 47 (fourth insulating film) made of boron, silicate, glass, or the like is formed between the interlayer insulating film 46 and the pixel electrode 9a, and an opening of the interlayer insulating film 47 is formed. Thus, the pixel electrode 9a and the conducting portion 8c of the relay electrode 8b are conducted. For this reason, the portion exposed from the pixel electrode 9a is made of boron silicate glass (insulating film 47) so that the liquid crystal layer 50 is deteriorated due to moisture, and the occurrence of unevenness in the pixel electrode 9a is efficiently prevented. Can do. That is, even if the insulating film 47 is not formed and the interlayer insulating film 46 (second insulating film) is made of boron silicate glass or the like, the liquid crystal layer 50 can be deteriorated due to moisture, but the boron silicate glass can be deteriorated. In this case, since the film thickness tends to vary, variations tend to occur in the process of performing chemical mechanical polishing on the interlayer insulating film 46 to expose the conductive portion 8c. However, in this embodiment, since the thin insulating film 47 (fourth insulating film) made of boron, silicate, glass, or the like is formed between the interlayer insulating film 46 and the pixel electrode 9a, the insulating film 47 causes the liquid crystal layer 50 to be formed by moisture. The process of exposing the conductive portion 8c can be stably performed by deteriorating and performing chemical mechanical polishing on the interlayer insulating film 46 made of a silicon oxide film or the like.

[Other embodiments]
In the above embodiment, the example in which the present invention is applied to the transmission type electro-optical device 100 has been described. However, the present invention may be applied to the reflection type electro-optical device 100.

  In the above embodiment, the example in which the present invention is applied to the electro-optical device 100 has been described. However, the present invention may be applied to the electro-optical device 100 other than the liquid crystal device, such as an organic electroluminescence device or an electrophoretic display panel. Good.

[Configuration example of electronic equipment]
(Configuration of projection display device)
FIG. 13 is a schematic configuration diagram of an aspect of a projection display device 110 (electronic apparatus) using the electro-optical device 100 to which the present invention is applied. In the following description, a plurality of electro-optical devices 100 to which light having different wavelength ranges are supplied are used. However, the electro-optical device 100 to which the present invention is applied is used for any of the electro-optical devices 100. It has been.

  A projection type display device 110 shown in FIG. 13 is a liquid crystal projector using the transmission type electro-optical device 100, and irradiates light to a projection member composed of a screen 111 or the like to display an image. The projection display device 110 includes an illumination device 160 along the device optical axis L, a plurality of electro-optical devices 100 (liquid crystal light valves 115 to 117) to which light emitted from the illumination device 160 is supplied, and a plurality of A cross dichroic prism 119 (light combining optical system) that combines and emits light emitted from the electro-optical device 100 and a projection optical system 118 that projects light combined by the cross dichroic prism 119 are provided. In addition, the projection display device 110 includes dichroic mirrors 113 and 114 and a relay system 120. In the projection display device 110, the electro-optical device 100 and the cross dichroic prism 119 constitute an optical unit 200.

  In the illumination device 160, along the device optical axis L, a light source unit 161, a first integrator lens 162 composed of a lens array such as a fly-eye lens, a second integrator lens 163 composed of a lens array such as a fly-eye lens, and a polarization conversion element 164 and a condenser lens 165 are arranged in this order. The light source unit 161 includes a light source 168 that emits white light including red light R, green light G, and blue light B, and a reflector 169. The light source 168 is configured by an ultra-high pressure mercury lamp or the like, and the reflector 169 has a parabolic cross section. The first integrator lens 162 and the second integrator lens 163 make the illuminance distribution of the light emitted from the light source unit 161 uniform. The polarization conversion element 164 turns the light emitted from the light source unit 161 into polarized light having a specific vibration direction such as s-polarized light.

  The dichroic mirror 113 transmits the red light R included in the light emitted from the illumination device 160 and reflects the green light G and the blue light B. The dichroic mirror 114 transmits the blue light B and reflects the green light G out of the green light G and the blue light B reflected by the dichroic mirror 113. As described above, the dichroic mirrors 113 and 114 constitute a color separation optical system that separates the light emitted from the illumination device 160 into red light R, green light G, and blue light B.

  The liquid crystal light valve 115 is a transmissive liquid crystal device that modulates the red light R transmitted through the dichroic mirror 113 and reflected by the reflection mirror 123 in accordance with an image signal. The liquid crystal light valve 115 includes a λ / 2 retardation plate 115a, a first polarizing plate 115b, an electro-optical device 100 (red electro-optical device 100R), and a second polarizing plate 115d. Here, the red light R incident on the liquid crystal light valve 115 remains as s-polarized light because the polarization of the light does not change even if it passes through the dichroic mirror 113.

  The λ / 2 phase difference plate 115a is an optical element that converts s-polarized light incident on the liquid crystal light valve 115 into p-polarized light. The first polarizing plate 115b is a polarizing plate that blocks s-polarized light and transmits p-polarized light. The electro-optical device 100 (red electro-optical device 100R) is configured to convert p-polarized light into s-polarized light (circularly polarized light or elliptically polarized light in the case of halftone) by modulation according to an image signal. The second polarizing plate 115d is a polarizing plate that blocks p-polarized light and transmits s-polarized light. Accordingly, the liquid crystal light valve 115 modulates the red light R according to the image signal, and emits the modulated red light R toward the cross dichroic prism 119. The λ / 2 phase difference plate 115a and the first polarizing plate 115b are arranged in contact with a light-transmitting glass plate 115e that does not convert the polarization, and the λ / 2 phase difference plate 115a and the first polarizing plate 115b are arranged. Distortion due to heat generation can be avoided.

  The liquid crystal light valve 116 is a transmissive liquid crystal device that modulates green light G reflected by the dichroic mirror 114 after being reflected by the dichroic mirror 113 in accordance with an image signal. As with the liquid crystal light valve 115, the liquid crystal light valve 116 includes a first polarizing plate 116b, an electro-optical device 100 (green electro-optical device 100G), and a second polarizing plate 116d. Green light G incident on the liquid crystal light valve 116 is s-polarized light that is reflected by the dichroic mirrors 113 and 114 and then incident. The first polarizing plate 116b is a polarizing plate that blocks p-polarized light and transmits s-polarized light. The electro-optical device 100 (green electro-optical device 100G) is configured to convert s-polarized light into p-polarized light (circularly polarized light or elliptically polarized light in the case of halftone) by modulation according to an image signal. The second polarizing plate 116d is a polarizing plate that blocks s-polarized light and transmits p-polarized light. Therefore, the liquid crystal light valve 116 modulates the green light G according to the image signal, and emits the modulated green light G toward the cross dichroic prism 119.

  The liquid crystal light valve 117 is a transmissive liquid crystal device that modulates the blue light B reflected by the dichroic mirror 113, transmitted through the dichroic mirror 114, and then passed through the relay system 120 in accordance with an image signal. Similarly to the liquid crystal light valves 115 and 116, the liquid crystal light valve 117 includes a λ / 2 phase difference plate 117a, a first polarizing plate 117b, an electro-optical device 100 (blue electro-optical device 100B), and a second polarizing plate 117d. I have. Since the blue light B incident on the liquid crystal light valve 117 is reflected by the dichroic mirror 113 and transmitted through the dichroic mirror 114 and then reflected by the two reflection mirrors 125a and 125b of the relay system 120, it is s-polarized light.

  The λ / 2 phase difference plate 117a is an optical element that converts s-polarized light incident on the liquid crystal light valve 117 into p-polarized light. The first polarizing plate 117b is a polarizing plate that blocks s-polarized light and transmits p-polarized light. The electro-optical device 100 (blue electro-optical device 100B) is configured to convert p-polarized light into s-polarized light (circularly polarized light or elliptically polarized light in the case of halftone) by modulation according to an image signal. The second polarizing plate 117d is a polarizing plate that blocks p-polarized light and transmits s-polarized light. Accordingly, the liquid crystal light valve 117 modulates the blue light B according to the image signal, and emits the modulated blue light B toward the cross dichroic prism 119. The λ / 2 phase difference plate 117a and the first polarizing plate 117b are arranged in contact with the glass plate 117e.

  The relay system 120 includes relay lenses 124a and 124b and reflection mirrors 125a and 125b. The relay lenses 124a and 124b are provided to prevent light loss due to the long optical path of the blue light B. The relay lens 124a is disposed between the dichroic mirror 114 and the reflection mirror 125a. The relay lens 124b is disposed between the reflection mirrors 125a and 125b. The reflection mirror 125a reflects the blue light B transmitted through the dichroic mirror 114 and emitted from the relay lens 124a toward the relay lens 124b. The reflection mirror 125b reflects the blue light B emitted from the relay lens 124b toward the liquid crystal light valve 117.

  The cross dichroic prism 119 is a color combining optical system in which two dichroic films 119a and 119b are arranged orthogonally in an X shape. The dichroic film 119a is a film that reflects blue light B and transmits green light G, and the dichroic film 119b is a film that reflects red light R and transmits green light G. Accordingly, the cross dichroic prism 119 combines the red light R, the green light G, and the blue light B that are modulated by the liquid crystal light valves 115 to 117, and emits the resultant light toward the projection optical system 118.

  Note that light incident on the cross dichroic prism 119 from the liquid crystal light valves 115 and 117 is s-polarized light, and light incident on the cross dichroic prism 119 from the liquid crystal light valve 116 is p-polarized light. Thus, by making the light incident on the cross dichroic prism 119 into different types of polarized light, the light incident from the liquid crystal light valves 115 to 117 can be synthesized in the cross dichroic prism 119. Here, in general, the dichroic films 119a and 119b are excellent in the reflection characteristics of s-polarized light. For this reason, red light R and blue light B reflected by the dichroic films 119a and 119b are s-polarized light, and green light G transmitted through the dichroic films 119a and 119b is p-polarized light. The projection optical system 118 has a projection lens (not shown), and projects the light combined by the cross dichroic prism 119 onto a projection target member such as the screen 111.

[Other projection display devices]
In the projection type display device, the transmission type electro-optical device 100 is used. However, the reflection type electro-optical device 100 may be used to form the projection type display device. In the projection display device, an LED light source that emits light of each color may be used as the light source unit, and the color light emitted from the LED light source may be supplied to another liquid crystal device. .

[Other electronic devices]
As for the electro-optical device 100 to which the present invention is applied, in addition to the above electronic devices, mobile phones, personal digital assistants (PDAs), digital cameras, liquid crystal televisions, car navigation devices, video phones, POS terminals In addition, it may be used as a direct-view display device in an electronic device such as a device provided with a touch panel.

1a Semiconductor layer, 1b source region, 1c drain region, 1g channel region, 2 gate insulating layer, 3a scanning line, 3c gate electrode, 4a source electrode, 4b first drain electrode, 5a data line, 5b second drain electrode, 5c Constant potential line, 6a first capacitor electrode, 7a second capacitor electrode, 7e recess, 8a third capacitor electrode, 8b relay electrode, 9a pixel electrode, 9a1 first pixel electrode, 9a2 second pixel electrode, 10 element substrate, 10f Inter-pixel region, 10g First inter-pixel region, 10h Second inter-pixel region, 20 counter substrate, 21 common electrode, 30 pixel transistor, 40 base insulating film, 41 interlayer insulating film, 41a contact hole, 41b contact hole, 42 interlayer Insulating film, 42a contact hole, 42b contact hole, 43 interlayer insulating film, 4 4 interlayer insulating film (third insulating film), 44a contact hole, 44b contact hole, 44c through hole, 45 interlayer insulating film (first insulating film), 45a contact hole, 45e convex portion, 45f convex end surface, 46 Interlayer insulating film (second insulating film), 47 insulating film (fourth insulating film), 47a opening, 50 liquid crystal layer, 50a liquid crystal capacitor, 55 holding capacitor, 55a first holding capacitor, 55b second holding capacitor, 55e first 1 dielectric layer, 55f 2nd dielectric layer, 91a 1st translucent conductive film, 91e, 92e overhang | projection part, 92a 2nd translucent conductive film, 96a Dielectric film for refractive index adjustment, 100 electro-optical apparatus, 100a pixel, 110 projection display device, 440, 460, 470 flat surface

Claims (12)

A first pixel electrode provided on one side of the substrate;
A pixel transistor provided between the first pixel electrode and the substrate;
A first capacitor electrode provided between the pixel transistor and the first pixel electrode, to which a constant potential is applied;
A second capacitive electrode provided between the first capacitive electrode and the first pixel electrode so as to overlap the first capacitive electrode in plan view;
A third capacitor electrode provided between the second capacitor electrode and the first pixel electrode so as to overlap the second capacitor electrode in a plan view and to which the constant potential is applied;
A first dielectric layer provided between the first capacitor electrode and the second capacitor electrode;
A second dielectric layer provided between the second capacitor electrode and the third capacitor electrode;
A first insulating film provided between the second capacitor electrode and the first pixel electrode, and having a convex portion protruding toward the first pixel electrode at a position overlapping the first pixel electrode in plan view; ,
A relay electrode that partially overlaps the tip surface of the convex portion, and the second capacitor electrode is electrically connected to a portion exposed from the first insulating film;
A second insulating film provided between the relay electrode and the first pixel electrode and having a flat surface on the first pixel electrode side;
Have
The relay electrode is at least partially exposed from the second insulating film among the portions overlapping the tip surface of the convex portion,
The electro-optical device, wherein the first pixel electrode is electrically connected to a portion where the relay electrode is exposed from the second insulating film. The electro-optical device according to claim 1.
A second pixel electrode adjacent to the first pixel electrode;
The electro-optical device, wherein the third capacitor electrode overlaps an inter-pixel region sandwiched between the first pixel electrode and the second pixel electrode in a plan view. The electro-optical device according to claim 2.
A data line provided between the substrate and the first capacitor electrode and electrically connected to the pixel transistor;
A scan line provided between the substrate and the first capacitor electrode, electrically connected to the pixel transistor, and extending in a direction intersecting the data line;
Have
The electro-optical device, wherein the third capacitor electrode extends in a direction along the data line and protrudes in a direction along the scanning line. The electro-optical device according to any one of claims 1 to 3,
The electro-optical device, wherein the third capacitor electrode and the relay electrode are provided in the same layer. The electro-optical device according to any one of claims 1 to 4,
A third insulating film provided between the first capacitor electrode and the second capacitor electrode;
The third insulating film includes a through hole provided so that the first capacitor electrode and the second capacitor electrode overlap with each other via the first dielectric layer,
The second capacitive electrode and the third capacitive electrode have a concave shape by the through hole, and overlap with the bottom and side surfaces of the concave shape through the second dielectric layer. apparatus. The electro-optical device according to claim 5.
The electro-optical device, wherein the second capacitor electrode is electrically connected to the pixel transistor through a contact hole formed in the third insulating film. The electro-optical device according to claim 6.
The electro-optical device, wherein the contact hole is formed at a position adjacent to the convex portion in plan view, or at a position overlapping the convex portion in plan view. The electro-optical device according to any one of claims 1 to 7,
A fourth insulating film provided between the second insulating film and the first pixel electrode;
The fourth insulating film is provided with an opening so that at least a portion of the portion overlapping the tip surface of the convex portion exposes the relay electrode,
The electro-optical device, wherein the first pixel electrode is electrically connected to the relay electrode through the opening. The electro-optical device according to any one of claims 1 to 8,
The electro-optical device, wherein the first pixel electrode includes at least a laminated film in which a first translucent conductive film, a refractive index adjusting dielectric film, and a second translucent conductive film are sequentially laminated. The electro-optical device according to claim 9,
The electro-optical device, wherein the first light-transmitting conductive film and the second light-transmitting conductive film protrude from an end portion of the refractive index adjusting dielectric film and are in contact with each other.   An electronic apparatus comprising the electro-optical device according to claim 1. The electronic device according to claim 11,
A light source unit that emits illumination light applied to the electro-optical device;
A projection optical system that projects light modulated by the electro-optical device;
An electronic device characterized by comprising:

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