JP2017076022A - Electro-optic device, method for manufacturing electro-optic device, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electro-optic device capable of reliably suppressing incidence of light oblique to a semiconductor layer from a substrate side, a method for manufacturing an electro-optic device, and an electronic apparatus.SOLUTION: In an element substrate 10 of an electro-optic device 100, a first recess 11 and a second recess 12 are disposed on either side in a Y direction of a semiconductor layer 1a extending in an X direction on one surface 10s of a substrate 10w. A gate electrode 3c as a second light-shielding film includes a first extending part 3c1 and a second extending part 3c2 passing inside the first recess 11 and inside the second recess 12, respectively, to extend to the opposite side to the semiconductor layer 1a, and to be in contact with a first light-shielding layer 4a inside a first opening 41a and inside a second opening 41b.SELECTED DRAWING: Figure 7

Description

  The present invention relates to an electro-optical device in which a switching element is provided on a substrate, a method for manufacturing the electro-optical device, and an electronic apparatus.

  There is known an electro-optical device including an electro-optical material (for example, liquid crystal) between an element substrate provided with a plurality of pixels and switching elements and a counter substrate disposed opposite to the element substrate. Examples of the electro-optical device include a liquid crystal device used as a liquid crystal light valve of a projection display device. In this case, strong light from a light source is incident on the liquid crystal light valve. At that time, when light is incident on the semiconductor layer constituting the switching element, a light leakage current is generated, and flicker and pixel unevenness are generated in the display image. Therefore, a structure in which a light shielding layer is provided on the lower layer side of the semiconductor layer is employed.

  On the other hand, in an electro-optical device such as a liquid crystal light valve, an improvement in the aperture ratio of a pixel region through which light is transmitted is required. As a result, light is easily incident in an oblique direction. Therefore, a recess is provided in a portion located on the side of the semiconductor layer on one side of the substrate, and an opening is provided in a position overlapping with the recess in the insulating layer interposed between the light shielding layer and the semiconductor layer. A structure has been proposed in which the gate electrode is extended inside the recess to cover the side surface of the recess on the semiconductor layer side (see Patent Document 1).

JP 2014-137526 A

  However, when the gate electrode is extended so as to overlap the side surface of the recess on the semiconductor layer side as in the structure described in Patent Document 1, it will be incident on the semiconductor layer obliquely from the side of the light shielding layer. There is a possibility that the light cannot be reliably blocked. Specifically, when forming a conductive film to be a gate electrode, it is difficult to form a conductive film on the side surface of the recess. Therefore, when the gate electrode is formed by patterning the conductive film, the gate electrode is a semiconductor having a recess. There is a possibility that it is not sufficiently formed on the side surface on the layer side. Further, even when the conductive film can be formed on the side surface of the recess, when the gate electrode is formed by patterning the conductive film, the gate electrode is not sufficiently formed on the side surface of the recess on the semiconductor layer side due to mask displacement or the like. There is a fear.

  In view of the above-described problems, an object of the present invention is to provide an electro-optical device, a method for manufacturing an electro-optical device, and an electronic device capable of well and reliably suppressing light from obliquely entering the semiconductor layer from the substrate side. To provide equipment.

  In order to solve the above-described problem, an aspect of the electro-optical device according to the invention includes a first light-shielding layer provided on one side of a substrate, and a side opposite to the substrate with respect to the first light-shielding layer. A first insulating layer provided; and a semiconductor layer provided in a position overlapping the first light-shielding layer on a side opposite to the substrate with respect to the first insulating layer in a plan view, and extending in a first direction; A second insulating layer provided on a side opposite to the substrate with respect to the semiconductor layer; and a position overlapping with the semiconductor layer on a side opposite to the substrate with respect to the second insulating layer in a plan view. A second light shielding layer, wherein the one surface of the substrate includes a first recess on a second direction side intersecting the first direction with respect to the semiconductor layer, and the first light shielding layer includes: A first portion located between the first recess and the semiconductor layer; and a position opposite to the semiconductor layer of the first recess. And the first insulating layer overlaps the first concave portion in plan view so that a part of each of the first portion and the second portion of the first light shielding layer is exposed. A first opening at a position, and the second light shielding layer extends from a position overlapping the semiconductor layer in plan view to the inside of the first recess, and the first portion of the first light shielding layer and It is in contact with the second part.

  In the electro-optical device according to the aspect of the invention, since the first light-shielding layer is provided on the substrate side with respect to the semiconductor layer, the light that enters the semiconductor layer from the substrate side is first shielded. Can be blocked by layers. In addition, on one side of the second direction of the semiconductor layer, a first recess is provided on one surface of the substrate, and the second light shielding layer extends to the inside of the first recess through the first opening of the insulating layer. And is in contact with the first portion and the second portion of the first light shielding layer. For this reason, the light which is about to enter obliquely from one side in the second direction toward the semiconductor layer from the substrate side can be blocked by the second light shielding layer. The second light shielding layer extends from the position overlapping the semiconductor layer in plan view to the inside of the second recess. For this reason, when the second light shielding layer is formed, a situation in which the second light shielding layer is difficult to be properly formed on the side surface of the concave portion, mask displacement in the second direction when the second light shielding layer is formed, or the like occurs. Even in this case, the second light shielding layer can be reliably provided inside the first recess. For this reason, the light which is going to enter diagonally from one side of the second direction toward the semiconductor layer from the substrate side can be surely blocked by the second light shielding layer. Therefore, in a switching element including a semiconductor layer and a gate insulating layer, generation of a light leakage current due to light incidence can be suppressed.

  In another aspect of the electro-optical device according to the invention, it is possible to adopt a configuration in which the second light shielding layer is a gate electrode.

  In another aspect of the electro-optical device according to the invention, it is possible to adopt a configuration in which the first light shielding layer is a back gate electrode.

  In another aspect of the electro-optical device according to the invention, the electro-optical device includes a third light-shielding layer provided on a side opposite to the substrate with respect to the second light-shielding layer. It is preferable to be located inside the first recess. According to such an aspect, light that is about to enter obliquely from one side in the second direction from the substrate side toward the semiconductor layer can be blocked by the third light shielding layer.

  In another aspect of the electro-optical device according to the invention, it is possible to employ a configuration in which the third light shielding layer is a data line.

  In another aspect of the electro-optical device according to the invention, the pixel electrode is electrically connected to the semiconductor layer, and the pixel electrode is electrically connected to the semiconductor layer through the third light shielding layer. It is possible to adopt a configuration that is used.

  In another aspect of the electro-optical device according to the invention, it is possible to adopt an aspect in which the first light shielding layer is not provided inside the first recess.

  In another aspect of the electro-optical device according to the aspect of the invention, a part of the first light shielding layer is provided in the first recess, and the first portion and the second portion of the first light shielding layer are It is preferable that the first light shielding layer is electrically connected through a portion provided inside the first recess.

  In another aspect of the electro-optical device according to the invention, the one surface of the substrate is provided with a second recess on the opposite side of the semiconductor layer from the first recess, and the first light-shielding layer includes: A third portion located between the first recess and the semiconductor layer, and a fourth portion located on the opposite side of the first recess from the semiconductor layer, the first insulating layer comprising: The second light shielding layer includes a second opening at a position overlapping the second recess in plan view so that a part of each of the third portion and the fourth portion of the first light shielding layer is exposed. It is preferable that the semiconductor layer extends from a position overlapping with the semiconductor layer in a plan view to the inside of the second recess and is in contact with the third portion and the fourth portion of the first light shielding layer. According to this configuration, light that is about to enter obliquely from the other side in the second direction from the substrate side toward the semiconductor layer can be blocked by the second light shielding layer.

  In another aspect of the electro-optical device according to the invention, it is possible to employ a configuration in which the first light shielding layer is a scanning line extending along the first direction.

  In another aspect of the electro-optical device according to the invention, one of the first light-shielding layer and the second light-shielding layer may be configured to be a scanning line extending along the second direction. it can.

  One aspect of the method for manufacturing an electro-optical device according to the invention includes a step of forming a first light-shielding layer partially separated on one side of a substrate, a step of forming a first insulating layer, and the first light-shielding layer. A step of forming a semiconductor layer extending in the first direction at a position overlapping the layer in plan view, a step of forming a second insulating layer, and a portion of the first light shielding layer on one side of the substrate spaced apart A step of forming a first recess, and a step of forming a second light shielding layer at a position overlapping the semiconductor layer in plan view. In the step of forming the first recess, the spaced apart first light shielding layer A part of each of the first light-shielding layer is located on a side of the second direction intersecting the first direction with respect to the semiconductor layer, and the second light-shielding layer is The first extending from the position overlapping the semiconductor layer in plan view to the inside of the first recess and spaced apart Characterized in that in contact respectively with the optical layer.

  Another aspect of the method for manufacturing an electro-optical device according to the present invention includes a step of forming a first light shielding layer partially separated on one surface side of the substrate, and a step of forming the first light shielding layer on the one surface side of the substrate. Forming a first recess in the separated portion, forming a first insulating layer, forming a semiconductor layer extending in a first direction at a position overlapping the first light shielding layer in plan view, A step of forming a second insulating layer, a step of forming a first opening so that a part of each of the spaced apart first light shielding layers is exposed at a position overlapping the first recess in plan view, Forming a second light-shielding layer at a position overlapping with the semiconductor layer in plan view, and the spaced apart portion of the first light-shielding layer intersects the first direction with respect to the semiconductor layer. The second light-shielding layer is located on the side of the first recess from the position overlapping the semiconductor layer in plan view. It extends to parts and, characterized in that in contact respectively with spaced first light-shielding layer.

  Still another aspect of the method for manufacturing the electro-optical device according to the invention includes a step of forming a first recess on one surface side of the substrate, and a position overlapping the first recess on the one surface side of the substrate in plan view. Forming a first light shielding layer so as to be partially separated, forming a first insulating layer, and forming a semiconductor layer extending in a first direction at a position overlapping the first light shielding layer in plan view Forming a second insulating layer, and forming a first opening so that a part of each of the spaced apart first light-shielding layers is exposed at a position overlapping the first recess in plan view. And a step of forming a second light-shielding layer at a position overlapping the semiconductor layer in plan view, the spaced apart portion of the first light-shielding layer intersecting the first direction with respect to the semiconductor layer The second light-shielding layer is located on the second direction side and overlaps the semiconductor layer in plan view. It extends to the inside of the first recess, and characterized in that in contact spaced and the first light-shielding layer, respectively.

  The electro-optical device according to the invention can be used in various electronic apparatuses. When the electronic apparatus is a projection display device, the projection display device includes a light source unit that emits light supplied to the electro-optical device, and a projection optical system that projects light modulated by the electro-optical device. Are provided.

FIG. 2 is a block diagram illustrating an aspect of the electrical configuration of the electro-optical device according to the first embodiment of the invention. 1 is a plan view schematically showing an aspect of an electro-optical device according to Embodiment 1 of the present invention. FIG. 3 is a cross-sectional view of the electro-optical device shown in FIG. FIG. 3 is a plan view illustrating one mode of adjacent pixels in the element substrate of the electro-optical device according to the first embodiment of the invention. It is sectional drawing of the pixel shown in FIG. FIG. 3 is a plan view illustrating an aspect of a light shielding structure for a pixel transistor in the electro-optical device according to the first embodiment of the invention. It is sectional drawing of the light-shielding structure shown in FIG. FIG. 6 is a process cross-sectional view illustrating a first example of a method for manufacturing an electro-optical device according to Embodiment 1 of the invention. FIG. 6 is a process cross-sectional view illustrating a first example of a method for manufacturing an electro-optical device according to Embodiment 1 of the invention. FIG. 10 is a process cross-sectional view illustrating a second example of the method for manufacturing the electro-optical device according to the first embodiment of the invention. FIG. 6 is a plan view illustrating one mode of adjacent pixels in an element substrate of an electro-optical device according to a second embodiment of the present invention. It is sectional drawing of the pixel shown in FIG. FIG. 10 is a plan view illustrating an aspect of a light shielding structure for a pixel transistor in an electro-optical device according to a second embodiment of the present invention. It is sectional drawing of the light-shielding structure shown in FIG. FIG. 10 is a cross-sectional view illustrating an aspect of a light shielding structure for a pixel transistor in an electro-optical device according to a third embodiment of the present invention. FIG. 10 is a process cross-sectional view illustrating a method for manufacturing an electro-optical device according to Embodiment 3 of the invention. FIG. 10 is a cross-sectional view illustrating an aspect of a light shielding structure for a pixel transistor in an electro-optical device according to a fourth embodiment of the present invention. 1 is a schematic configuration diagram of a projection display device (electronic device) using an electro-optical device to which the present invention is applied.

  As an embodiment of the present invention, an example in which the present invention is applied to an active matrix liquid crystal device and a manufacturing method among various electro-optical devices will be described. In the drawings to be referred to in the following description, the scales of the layers and the members are different from each other in order to make the layers and the members large enough to be recognized on the drawings. In addition, when the direction of the current flowing through the field effect transistor is reversed, the source and the drain are switched. In the following description, for convenience, the side to which the pixel electrode is connected is used as the drain and the data line is connected. The side will be described as a source. In describing the layers formed on the element substrate, the upper layer side or the surface side means the side opposite to the side of the element substrate where the substrate is located (the side where the counter substrate is located), and the lower layer side means the element It means the side where the substrate is located. In describing the layer formed on the counter substrate, the upper layer side or the surface side means the side opposite to the side where the substrate of the counter substrate is located (the side where the element substrate is located), and is opposed to the lower layer side. It means the side where the substrate is located.

  In the following description, among the directions along the substrate surface of the element substrate 10, the direction in which the scanning lines 3a extend is defined as the X direction, and the direction in which the data lines 6a extend is defined as the Y direction. A direction in which the layer 1a extends will be described as a first direction C, and a direction crossing the semiconductor layer will be described as a second direction D. Also, one side of the X direction, the Y direction, the first direction C, and the second direction D is set as one side X1, Y1, C1, and D1, respectively, and the X direction, the Y direction, the first direction C, and the second direction D The other side will be described as the other side X2, Y2, C2, and D2. Of the embodiments described below, in the first and third embodiments, the first direction C corresponds to the X direction, and the second direction D corresponds to the Y direction. On the other hand, in the second and fourth embodiments, the first direction C corresponds to the Y direction, and the second direction D corresponds to the X direction.

[Embodiment 1]
(overall structure)
FIG. 1 is a block diagram showing an aspect of the electrical configuration of the electro-optical device according to Embodiment 1 of the present invention. In FIG. 1, an electro-optical device 100 according to this embodiment is a liquid crystal device having a liquid crystal panel 100p in a TN (Twisted Nematic) mode or a VA (Vertical Alignment) mode, and the liquid crystal panel 100p includes a plurality of pixels in the central region. 100a includes an image display area 10a (pixel arrangement area / effective pixel area) arranged in a matrix. In the liquid crystal panel 100p, in an element substrate 10 (see FIG. 2 and the like) described later, a plurality of data lines 6a and a plurality of scanning lines 3a extend vertically and horizontally inside the image display region 10a, and cross each other. Correspondingly, a pixel 100a is configured. In each of the plurality of pixels 100a, a pixel transistor 30 including a field effect transistor (switching element) and a pixel electrode 9a described later are formed. The data line 6 a is electrically connected to the source of the pixel transistor 30, the scanning line 3 a is electrically connected to the gate of the pixel transistor 30, and the pixel electrode 9 a is electrically connected to the drain of the pixel transistor 30. Has been.

  In the element substrate 10, a scanning line driving circuit 104 and a data line driving circuit 101 are provided outside the image display region 10a. The data line driving circuit 101 is electrically connected to each data line 6a, and sequentially supplies the image signal supplied from the image processing circuit to each data line 6a. The scanning line driving circuit 104 is electrically connected to each scanning line 3a, and sequentially supplies a scanning signal to each scanning line 3a.

  In each pixel 100a, the pixel electrode 9a is opposed to a common electrode formed on a counter substrate 20 (see FIG. 2 and the like), which will be described later, via a liquid crystal layer, and constitutes a liquid crystal capacitor 50a. Further, a storage capacitor 55 is added to each pixel 100a in parallel with the liquid crystal capacitor 50a in order to prevent fluctuation of the image signal held in the liquid crystal capacitor 50a. In this embodiment, in order to form the storage capacitor 55, the element substrate 10 is formed with the capacitor line 5a extending across the plurality of pixels 100a, and the common potential Vcom is applied to the capacitor line 5a. Yes.

(Configuration of liquid crystal panel 100p and element substrate 10)
FIG. 2 is a plan view schematically showing one aspect of the electro-optical device 100 according to Embodiment 1 of the present invention. 3 is a cross-sectional view of the electro-optical device 100 shown in FIG.

  As shown in FIGS. 2 and 3, in the electro-optical device 100, the element substrate 10 and the counter substrate 20 are bonded together with a seal material 107 through a predetermined gap, and the seal material 107 is attached to the outer edge of the counter substrate 20. It is provided in a frame shape so as to follow. The sealing material 107 is an adhesive made of a photo-curing resin, a thermosetting resin, or the like, and is mixed with a gap material 107a such as glass fiber or glass beads for setting the distance between both substrates to a predetermined value. In the liquid crystal panel 100p, a liquid crystal layer 50 (electro-optical material layer) made of various liquid crystal materials (electro-optical materials) is formed in a region surrounded by the sealing material 107 between the element substrate 10 and the counter substrate 20. Is provided. In this embodiment, the sealing material 107 is formed with a discontinuous portion used as the liquid crystal injection port 107c, and the liquid crystal injection port 107c is sealed with the sealing material 108 after the liquid crystal material is injected.

  In the liquid crystal panel 100p, the element substrate 10 and the counter substrate 20 are both square, and the image display area 10a described with reference to FIG. 1 is provided as a square area in the approximate center of the liquid crystal panel 100p. Corresponding to this shape, the sealing material 107 is also provided in a substantially square shape, and the outer side of the image display area 10a is a rectangular frame-shaped outer peripheral area 10c.

  In the element substrate 10, the data line driving circuit 101 and a plurality of terminals 102 are formed along one side of the element substrate 10 in the outer peripheral region 10 c, and the scanning line driving circuit 104 is formed along another side adjacent to the one side. Is formed. A flexible wiring board (not shown) is connected to the terminal 102, and various potentials and various signals are input to the element substrate 10 through the flexible wiring board.

  As will be described in detail later with reference to FIGS. 4 and 5, the image display region 10 a is located on the side of the one surface 10 s facing the counter substrate 20 of the one surface 10 s and the other surface 10 t of the element substrate 10. The pixel transistor 30 described with reference to FIG. 1 and the pixel electrode 9a electrically connected to the pixel transistor 30 are formed in a matrix, and an alignment film 16 is formed on the upper side of the pixel electrode 9a. Yes. Further, on the one surface 10 s side of the element substrate 10, in the outer peripheral region 10 c outside the image display region 10 a, the rectangular frame-shaped peripheral region 10 b sandwiched between the image display region 10 a and the sealing material 107 includes pixels. A dummy pixel electrode 9b formed simultaneously with the electrode 9a is formed.

  A common electrode 21 is formed on the side of the one surface 20 s facing the element substrate 10 out of the one surface 20 s and the other surface 20 t of the counter substrate 20. The common electrode 21 is formed across the plurality of pixels 100a as substantially the entire surface of the counter substrate 20 or a plurality of strip electrodes. In this embodiment, the common electrode 21 is formed on substantially the entire surface of the counter substrate 20.

  A light shielding layer 29 is formed on the lower side of the common electrode 21 on the one surface 20 s side of the counter substrate 20, and an alignment film 26 is laminated on the surface of the common electrode 21. In this embodiment, the light shielding layer 29 is formed as a frame portion 29 a extending along the outer periphery of the image display region 10 a, and the image display region 10 a is defined by the inner periphery of the light shielding layer 29. The light shielding layer 29 is also formed as a black matrix portion 29b that overlaps the inter-pixel region 10f sandwiched between the adjacent pixel electrodes 9a.

  In the liquid crystal panel 100p, inter-substrate conduction electrodes 25 are formed on the four corners on the one surface 20s side of the counter substrate 20 outside the sealing material 107, and on the one surface 10s side of the element substrate 10. The inter-substrate conduction electrodes 19 are formed at positions facing the four corners of the counter substrate 20 (inter-substrate conduction electrodes 25). An inter-substrate conducting material 109 containing conductive particles is disposed between the inter-substrate conducting electrode 19 and the inter-substrate conducting electrode 25, and the common electrode 21 of the counter substrate 20 is connected to the inter-substrate conducting electrode 19. The element substrate 10 is electrically connected via the inter-substrate conductive material 109 and the inter-substrate conductive electrode 25. Therefore, the common potential Vcom is applied to the common electrode 21 from the element substrate 10 side.

  In this embodiment, the electro-optical device 100 is a transmissive liquid crystal device, and the pixel electrode 9a and the common electrode 21 are made of a light-transmitting conductive film such as an ITO (Indium Tin Oxide) film or an IZO (Indium Zinc Oxide) film. . In such a transmissive liquid crystal device (electro-optical device 100), light incident from the counter substrate 20 side is modulated while being transmitted through the element substrate 10 and emitted to display an image.

  The electro-optical device 100 can be used as a color display device of an electronic apparatus such as a mobile computer or a mobile phone. In this case, a color filter (not shown) is formed on the counter substrate 20 or the element substrate 10. The electro-optical device 100 can be used as an RGB light valve in a projection type display device (liquid crystal projector) described later. In this case, each of the RGB electro-optical devices 100 receives light of each color separated through RGB color separation dichroic mirrors as projection light, so that no color filter is formed. . When the electro-optical device 100 is used as an RGB light valve, a microlens may be formed on the element substrate 10 or the counter substrate 20 at a position overlapping the pixel electrode 9a.

(Specific pixel configuration)
FIG. 4 is a plan view showing an aspect of the adjacent pixels 100a in the element substrate 10 of the electro-optical device 100 according to Embodiment 1 of the present invention. 5 is a cross-sectional view of the pixel 100a shown in FIG. 4, and is a cross-sectional view when the electro-optical device 100 is cut at a position corresponding to the F1-F1 ′ line of FIG. Moreover, in FIG. 4, each area | region is represented with the following lines.

First light shielding layer 4a (first light shielding layer) = thin solid line Semiconductor layer 1a = thin one-dot chain line Gate electrode 3c (second light shielding layer) and scanning line 3a = thick solid line Third light shielding layer 6b (data line 6a) and drain electrode 6c = Thick one-dot chain line Capacitance electrode 7a = Thin two-dot chain line Capacitance line 5a = Thin and long broken line Pixel electrode 9a = Thick and short broken line First recess 11, second recess 12, first opening 41a and second opening 41b = Dotted line

  As shown in FIG. 4, a rectangular pixel electrode 9a is formed on each of the plurality of pixels 100a on the element substrate 10, and overlaps with a vertical and horizontal inter-pixel region 10f sandwiched between adjacent pixel electrodes 9a. A data line 6a and a scanning line 3a are formed along the line. Of the inter-pixel region 10f, the scanning line 3a extends along a region overlapping the first inter-pixel region 10g extending in the X direction, and along the region overlapping the second inter-pixel region 10h extending in the Y direction. The data line 6a extends. Each of the data line 6a and the scanning line 3a extends linearly, and a pixel transistor 30 is formed in a region where the data line 6a and the scanning line 3a intersect. The element substrate 10 has a capacitor line 5a so as to overlap the data line 6a.

  As shown in FIGS. 4 and 5, the element substrate 10 includes a light-transmitting substrate 10 w (substrate) such as a quartz substrate or a glass substrate. On one surface 10s side of the substrate 10w, a metal film such as Al (aluminum), Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), and Mo (molybdenum), a conductive polysilicon film A first light shielding layer 4a (first light shielding layer) made of a light shielding conductive film such as a metal silicide film or a metal compound is formed. As will be described later, the first light shielding layer 4a also functions as a back gate electrode for the pixel transistor 30. The first light shielding layer 4a is configured as a scanning line 3a, and extends in the first direction C (X direction).

  On the one surface 10s side of the substrate 10w, a first insulating layer 41 (first insulating layer) such as a silicon oxide film is formed on the upper layer side of the first light shielding layer 4a. On the side, a semiconductor layer 1a for forming the pixel transistor 30 is formed.

  The pixel transistor 30 includes a semiconductor layer 1a extending in the first direction C (X direction) along the scanning line 3a and a second direction intersecting the semiconductor layer 1a in the intersection region of the scanning line 3a and the data line 6a. A gate electrode 3c (second light shielding layer) that extends in D (Y direction) and overlaps the central portion in the length direction of the semiconductor layer 1a is provided. The pixel transistor 30 has a gate insulating layer 2 (second insulating layer) on the upper layer side of the semiconductor layer 1a, and has a gate electrode 3c (second light shielding layer) on the upper layer side of the gate insulating layer 2. . The semiconductor layer 1a includes a channel region 1g opposed to the gate electrode 3c via the gate insulating layer 2, and includes a source region 1b and a drain region 1c on both sides of the channel region 1g. In this embodiment, the pixel transistor 30 has an LDD (Lightly Doped Drain) structure. Therefore, each of the source region 1b and the drain region 1c includes the low concentration regions 1b1 and 1c1 on both sides of the channel region 1g, and the high concentration in the region adjacent to the low concentration regions 1b1 and 1c1 on the opposite side to the channel region 1g. Regions 1b2 and 1c2 are provided.

  The semiconductor layer 1a is composed of a polycrystalline silicon film or the like. The gate insulating layer 2 is, for example, a two-layer structure of a first gate insulating layer made of a silicon oxide film obtained by thermally oxidizing the semiconductor layer 1a and a second gate insulating layer made of a silicon oxide film formed by a CVD method or the like. Consists of.

  The gate electrode 3c is made of a light-shielding conductive film such as a metal film such as Al, Ti, Cr, W, Ta, or Mo, a conductive polysilicon film, a metal silicide film, or a metal compound. In this embodiment, as will be described later with reference to FIGS. 6 and 7, the gate electrode 3 c is a first electrode that penetrates the gate insulating layer 2 and the first insulating layer 41 on both sides in the second direction D of the semiconductor layer 1 a. The first light shielding layer 4a is in contact with the inside of the opening 41a and the inside of the second opening 41b.

  A translucent interlayer insulating film 42 (second insulating layer) made of a silicon oxide film or the like is formed on the upper layer side of the gate electrode 3c, and the third light shielding layer 6b and the drain are formed on the upper layer of the interlayer insulating film 42. The electrode 6c is formed of the same type of conductive film. The third light shielding layer 6b and the drain electrode 6c are made of a light shielding conductive film such as a metal film such as Al, Ti, Cr, W, Ta, and Mo, a conductive polysilicon film, a metal silicide film, or a metal compound. . The third light shielding layer 6b is electrically connected to the high concentration region 1b2 of the source region 1b through the contact hole 42a penetrating the interlayer insulating film 42 and the gate insulating layer 2. The drain electrode 6c is electrically connected to the high concentration region 1c2 of the drain region 1c through the contact hole 42b penetrating the interlayer insulating film 42 and the gate insulating layer 2. The third light shielding layer 6b is configured as a data line 6a, and extends in the second direction D (Y direction) intersecting the extending direction of the semiconductor layer 1a.

  A translucent interlayer insulating film 44 made of a silicon oxide film or the like is formed on the upper side of the third light shielding layer 6b and the drain electrode 6c. The surface of the interlayer insulating film 44 is a flat surface by a CMP (Chemical Mechanical Polishing) process or the like.

  A capacitor electrode 7a is formed on the upper layer side of the interlayer insulating film 44, and a dielectric layer 40 is formed on the upper layer side of the capacitor electrode 7a. On the upper layer side of the dielectric layer 40, a capacitor line 5a is formed. The capacitor line 5a includes a main line portion 5a1 extending in the Y direction so as to overlap the second inter-pixel region 10h (data line 6a) from the intersection between the data line 6a and the scan line 3a, and the data line 6a and the scan line 3a. And a protruding portion 5a2 protruding to the other side X2 so as to overlap the first inter-pixel region 10g (scanning line 3a). The capacitive electrode 7a includes a main line portion 7a1 extending from the intersection of the data line 6a and the scanning line 3a toward the other side Y2 in the Y direction so as to overlap the second inter-pixel region 10h (data line 6a), and the data Formed in an L shape with a protruding portion 7a2 protruding toward the other side X2 in the X direction so as to overlap the first inter-pixel region 10g (scanning line 3a) from the intersection of the line 6a and the scanning line 3a Has been. The capacitor electrode 7a and the capacitor line 5a are made of a light-shielding conductive film such as a metal film such as Al, Ti, Cr, W, Ta, and Mo, a conductive polysilicon film, a metal silicide film, or a metal compound. As the dielectric layer 40, a silicon compound such as a silicon oxide film or a silicon nitride film can be used, and an aluminum oxide film, a titanium oxide film, a tantalum oxide film, a niobium oxide film, a hafnium oxide film, a lanthanum oxide film, zirconium A dielectric layer having a high dielectric constant such as an oxide film can be used.

  A light-transmitting insulating film 46 such as a silicon oxide film is formed as an etching stopper layer between the capacitive electrode 7a and the end of the dielectric layer 40, and the insulating film 46 includes the capacitive electrode 7a. An opening 46a is formed in a region overlapping with. Therefore, the capacitor electrode 7a and the capacitor line 5a are opposed to each other through the dielectric layer 40 inside the opening 46a, and constitute a storage capacitor 55. Although not shown in FIG. 4, the opening 46a is directed toward the other side Y2 in the Y direction so as to overlap the second inter-pixel region 10h (data line 6a) from the intersection of the data line 6a and the scanning line 3a. An extended main line portion and a protruding portion protruding from the intersection of the data line 6a and the scanning line 3a toward the other side X2 in the X direction so as to overlap the first inter-pixel region 10g (scanning line 3a) It is formed in the L shape provided. The capacitive electrode 7a partially overlaps the drain electrode 6c in plan view, and is electrically connected to the drain electrode 6c through a contact hole 44a formed in the interlayer insulating film 44.

A translucent interlayer insulating film 45 is formed on the upper layer side of the capacitor line 5a, and a pixel electrode 9a made of a translucent conductive film such as an ITO film is formed on the upper layer side of the interlayer insulating film 45. Yes. The pixel electrode 9a partially overlaps the portion of the capacitor electrode 7a exposed from the capacitor line 5a in plan view, and is electrically connected to the capacitor electrode 7a through a contact hole 45a formed in the interlayer insulating film 45. doing. Accordingly, the pixel electrode 9a is electrically connected to the high concentration region 1c2 of the drain region 1c of the pixel transistor 30 via the capacitor electrode 7a and the drain electrode 6c.
An alignment film 16 is formed on the surface of the pixel electrode 9a. The alignment film 16 is made of a resin film such as polyimide or an oblique deposition film such as a silicon oxide film. In this embodiment, the alignment film 16 is an inorganic alignment film (vertical alignment film) made of an oblique vapor deposition film such as SiO _x (x <2) or SiO ₂ .

In the counter substrate 20, a common surface made of a light-transmitting conductive film such as an ITO film is provided on the surface of the light-transmitting substrate 20 w such as a quartz substrate or a glass substrate on the liquid crystal layer 50 side (surface facing the element substrate 10). An electrode 21 is formed, and an alignment film 26 is formed so as to cover the common electrode 21. Similar to the alignment film 16, the alignment film 26 is made of a resin film such as polyimide or an oblique deposition film such as a silicon oxide film. In this embodiment, the alignment film 26 is an inorganic alignment film (vertical alignment film) made of an oblique vapor deposition film of SiO _x (x <2), SiO ₂ or the like, like the alignment film 16. The alignment films 16 and 26 vertically align the nematic liquid crystal compound having negative dielectric anisotropy used for the liquid crystal layer 50, and the liquid crystal panel 100p operates as a normally black VA mode.

(Light shielding structure for the pixel transistor 30)
FIG. 6 is a plan view showing an aspect of the light shielding structure for the pixel transistor 30 in the electro-optical device 100 according to Embodiment 1 of the present invention. FIG. 7 is a cross-sectional view of the light shielding structure shown in FIG. 6, and is a cross-sectional view when the periphery of the pixel transistor 30 is cut at a position corresponding to the line G1-G1 ′ of FIG. 6 and 7, the substrate 10w, the first light shielding layer 4a, the first insulating layer 41, the semiconductor layer 1a, the gate insulating layer 2 (second insulating layer), the gate electrode 3c (second light shielding layer), Only the interlayer insulating film 42, the third light shielding layer 6b (data line 6a), and the drain electrode 6c are shown, and the upper layer side of the third light shielding layer 6b is not shown.

  In this embodiment, the upper light shielding layer such as the third light shielding layer 6b, the drain electrode 6c, the capacitor electrode 7a, and the capacitor line 5a overlaps the semiconductor layer 1a in plan view. For this reason, the light which is going to enter from the upper layer side with respect to the semiconductor layer 1a is interrupted | blocked by said light shielding layer.

  As shown in FIGS. 6 and 7, the element substrate 10 includes a conductive first light shielding layer 4a and a first layer provided on the upper side of the first light shielding layer 4a on the one surface 10s side of the substrate 10w. And an insulating layer 41 (insulating layer). The upper layer side of the first insulating layer 41 extends in the X direction (first direction) so as to overlap the first light shielding layer 4a in plan view. The semiconductor layer 1a is formed. The first light shielding layer 4a extends in the X direction with the same width dimension (dimension in the Y direction), and a portion intersecting with the data line 6a is a wide light shielding portion 4e. For this reason, light that is about to enter the channel region 1g of the semiconductor layer 1a, the low concentration region 1b1 of the source region 1b, and the low concentration region 1c1 of the drain region 1c from the substrate 10w side is blocked by the first light blocking layer 4a. It is done.

  Here, on one surface 10s of the substrate 10w, a first recess 11 is formed on one side D1 in the second direction D (one side Y1 in the Y direction) with respect to the semiconductor layer 1a. A second recess 12 is formed on the other side D2 in the two directions D (the other side Y2 in the Y direction). Accordingly, the first light shielding layer 4 a is not provided inside the first recess 11 and inside the second recess 12, and has a portion that is separated in the second direction D. More specifically, the first light shielding layer 4a includes a first portion 4a1 positioned between the first recess 11 and the semiconductor layer 1a and a second portion positioned on the opposite side of the first recess 11 from the semiconductor layer 1a. The edge of the first part 4a1 opposite to the semiconductor layer 1a and the edge of the second part 4a2 on the semiconductor layer 1a side overlap with the opening edge of the first recess 11 in plan view. Yes. Further, the first light shielding layer 4 a has a portion that is separated in the second direction D. The first light-shielding layer 4a includes a third portion 4a3 located between the second recess 12 and the semiconductor layer 1a and a fourth portion 4a4 located on the opposite side of the second recess 12 from the semiconductor layer 1a. The edge of the third portion 4a3 opposite to the semiconductor layer 1a and the edge of the fourth portion 4a4 on the semiconductor layer 1a side overlap with the opening edge of the second recess 12 in plan view.

  A first opening 41 a is formed in the first insulating layer 41 at a position overlapping the first recess 11 in plan view. In this embodiment, the first opening 41 a is formed so as to penetrate the gate insulating layer 2 and the first insulating layer 41. The first opening 41 a has a larger planar size than the first recess 11, and the opening edge of the first opening 41 a is located outside the opening edge of the first recess 11 in the first direction C. For this reason, the first opening 41a includes at least a part of the first part 4a1 of the first light shielding layer 4a (a part adjacent to the first recess 11) and at least a part of the second part 4a2 of the first light shielding layer 4a. (A portion adjacent to the first recess 11) is exposed.

  The first insulating layer 41 has a second opening 41b at a position overlapping the second recess 12 in plan view. In this embodiment, the second opening 41b is formed so as to penetrate the gate insulating layer 2 and the first insulating layer 41. The second opening 41 b has a larger planar size than the second recess 12, and the opening edge of the second opening 41 b is located outside the opening edge of the second recess 12 in the second direction D. Therefore, the second opening 41b includes at least a part of the third part 4a3 of the first light shielding layer 4a (a part adjacent to the second recess 12) and at least a part of the fourth part 4a4 of the first light shielding layer 4a. (A portion adjacent to the second recess 12) is exposed.

  The gate electrode 3c includes a first extending portion 3c1 extending from the position overlapping the semiconductor layer 1a in a plan view through the inside of the first recess 11 toward the one side Y1 in the Y direction from the first opening 41a, A second extending portion 3c2 extending from the second opening 41a toward the other side Y2 in the Y direction through the inside of the second recess 12 from a position overlapping the semiconductor layer 1a in plan view.

  The first extending portion 3c1 is in contact with the first portion 4a1 of the first light shielding layer 4a inside the first opening 41a, and further, on the other side Y2 of the first recess 11 in the Y direction inside the first recess 11. The second light shielding layer 4a extends along the side surface 11a, the bottom portion 11c of the first concave portion 11, and the side surface 11b on one side Y1 in the Y direction of the first concave portion 11 and inside the first opening 41a. It is in contact with the portion 4a2. The second extending portion 3c2 is in contact with the third portion 4a3 of the first light shielding layer 4a inside the second opening 41a, and further on the one side Y1 of the second recess 12 in the Y direction inside the second recess 12. The fourth side of the first light shielding layer 4a extends along the side surface 12a, the bottom portion 12c of the second concave portion 12, and the side surface 12b on the other side Y2 of the second concave portion 12 in the Y direction. It is in contact with the portion 4a4.

  The first extending portion 3c1 of the gate electrode 3c has a portion where the portion overlapping the bottom portion 11c of the first recess 11 is lower than the first light shielding layer 4a in the height direction with respect to the substrate 10w. The second extending portion 3c2 of 3c is located at a position lower than the first light shielding layer 4a in the height direction when the portion overlapping the bottom 12c of the second recess 12 is based on the substrate 10w.

  The third light shielding layer 6b extends in the Y direction, and overlaps the first opening 41a, the first recess 11, the second opening 41b, and the second recess 12 in plan view. Therefore, the third light shielding layer 6 b is formed to the inside of the first recess 11 through the first opening 41 a together with the interlayer insulating film 42, and the third light shielding layer 6 b is the bottom 11 c of the first recess 11. Is in a position lower than the first light-shielding layer 4a in the height direction with respect to the substrate 10w. The third light shielding layer 6b is formed to the inside of the second recess 12 through the second opening 41b together with the interlayer insulating film 42. The third light shielding layer 6b is connected to the bottom 12c of the second recess 12 and The overlapping portion is at a position lower than the first light shielding layer 4a in the height direction when the substrate 10w is used as a reference.

(Main effects of this form)
As described above, in this embodiment, on one side D1 in the second direction D of the semiconductor layer 1a, the first recess 11 is provided on the one surface 10s of the substrate 10w, and the gate electrode 3c (second light shielding layer). The first extending portion extends to the inside of the first recess 11 through the first opening 41a of the first insulating layer 41 and is in contact with the first portion 4a1 and the second portion 4a2 of the first light shielding layer 4a. 3c1 is provided. For this reason, light that is about to enter obliquely from one side C1 in the second direction C toward the semiconductor layer 1a from the substrate 10w side is blocked by the first extending portion 3c1 and the first light shielding layer 4a of the gate electrode 3c. Can do. Further, on the other side D2 of the semiconductor layer 1a in the second direction D, the second recess 12 is provided on the one surface 10s of the substrate 10w, and the second opening 41a of the first insulating layer 41 is provided in the gate electrode 3c. A second extending portion 3c2 that extends to the inside of the second concave portion 12 and contacts the third portion 4a3 and the fourth portion 4a4 of the first light shielding layer 4a is provided. For this reason, light that is about to enter obliquely from the other side D2 in the D direction toward the semiconductor layer 1a from the substrate 10w side can be blocked by the second extending portion 3c2 of the gate electrode 3c and the first light shielding layer 4a. .

  In particular, in this embodiment, since the low concentration region 1c1 of the drain region 1c of the semiconductor layer 1a is sandwiched between the first recess 11 and the second recess 12 in the second direction D, the low concentration region 1c1 of the semiconductor layer 1a On the other hand, light that is about to enter obliquely from the X direction toward the semiconductor layer 1a from the substrate 10w side can be blocked by the first extension portion 3c1 and the second extension portion 3c2 of the gate electrode 3c. Therefore, the pixel transistor 30 is unlikely to malfunction due to light leakage current.

  The first extending portion 3c1 of the gate electrode 3c extends from the first opening 41a to the side opposite to the semiconductor layer 1a (one side D1 in the second direction D) through the inside of the first recess 11. ing. The second extending portion 3c2 of the gate electrode 3c extends from the second opening 41b to the side opposite to the semiconductor layer 1a (the other side D2 in the second direction D) through the inside of the second recess 12. ing. For this reason, when forming the conductive film to be the gate electrode 3c, it is difficult to properly form the conductive film on the side surfaces of the first concave portion 11 and the second concave portion 12, and the second case of forming the gate electrode 3c. Even if mask misalignment or the like occurs in the direction D, the first extending portion 3c1 of the gate electrode 3c is reliably provided inside the first recess 11, and the second extending portion 3c2 of the gate electrode 3c is the second recess. 12 is securely provided inside. For this reason, the light that is about to enter obliquely from the X direction toward the semiconductor layer 1a from the substrate 10w side can be sufficiently blocked by the first extending portion 3c1 and the second extending portion 3c2 of the gate electrode 3c. Therefore, in the pixel transistor 30 including the semiconductor layer 1a, the gate insulating layer 2, and the gate electrode 3c, it is possible to suppress the occurrence of light leakage current caused by the incidence of light.

  Further, the first light shielding layer 4 a is formed of a part of the scanning line 3 a that overlaps the semiconductor layer 1 a with the first insulating layer 41 interposed therebetween. Therefore, the first light shielding layer 4a also functions as a back gate electrode, so that the operation characteristics of the pixel transistor 30 can be improved.

  The third light shielding layer 6 b is provided up to the inside of the first recess 11 and the inside of the second recess 12. For this reason, the data line 6a can block light that is about to enter obliquely from the X direction toward the semiconductor layer 1a from the substrate 10w side.

(First example of manufacturing method)
8 and 9 are process cross-sectional views illustrating a first example of a method for manufacturing the electro-optical device 100 according to Embodiment 1 of the present invention. FIG. 8 is an explanatory view showing the steps until the first concave portion 11 and the second concave portion 12 are formed. FIG. 9 shows the formation of the third light shielding film after the first concave portion 11 and the second concave portion 12 are formed. It is explanatory drawing which shows the process until it does.

  In this embodiment, in any of the manufacturing methods described below, the first recess 11 and the second recess 12 are formed on the one surface 10s of the substrate 10w in the recess forming step before the gate electrode 3c is formed. Further, before forming the gate electrode 3 c and before or after the recess forming step, the first opening 41 a and the second opening 41 b are formed in the first insulating layer 41 in the opening forming step. In the second light shielding layer forming step for forming the gate electrode 3c, the first extending portion 3c1 and the second extending portion 3c2 are provided on the gate electrode 3c.

  More specifically, first, in the first light shielding layer steps ST11 and ST12 shown in FIG. 8, after the first light shielding layer 4 is formed on the one surface 10s side of the substrate 10W, the surface of the first light shielding layer 4 is masked ( The first light-shielding layer 4 is etched in a state in which it is not shown. As a result, in the first light shielding layer 4, the first portion 4a1 (part) and the second portion 4a2 (part) are separated from each other on both sides in the second direction D of the region where the semiconductor layer 1a is to be formed. The part 4a3 (part) and the fourth part 4a4 (part) are separated from each other. Next, in the first insulating layer forming step ST13, the first insulating layer 41 is formed on the upper layer side of the first light shielding layer 4a.

  Next, in the semiconductor layer forming step ST14, after the semiconductor film is formed on the first insulating layer 41, the semiconductor film is etched in a state where a mask (not shown) is formed on the surface of the semiconductor film, and the first light shielding is performed. A semiconductor layer 1a extending in the first direction C is formed at a position overlapping the layer 4a in plan view. Next, the gate insulating layer 2 (second insulating layer) is formed on the upper layer side of the semiconductor layer 1a.

  Next, in the recess forming step ST15, the gate insulating layer 2 and the first insulating layer 41 are etched with a mask (not shown) formed on the surface of the gate insulating layer 2, and the semiconductor layer 1a of the first insulating layer 41 is etched. On both sides in the second direction D, the first opening 41a and the second opening 41b are formed in spaced apart portions of the first light shielding layer 4a. Subsequently, through the first opening 41a and the second opening 41b, the first recess 11 and the second recess 12 are formed by etching in a portion of the one surface 10s of the substrate 10w separated from the first light shielding layer 4a. To do. As a result, each part (the first part 4a1, the second part 4a2, the third part 4a3, and the part of the fourth part 4a4) spaced apart in the first light shielding layer 4a is exposed. Further, the separated portion of the first light shielding layer 4a is located on the second direction D side intersecting with the semiconductor layer 1a to be formed later. In the recess forming step ST15, the formation of the first opening 41a and the second opening 41b and the formation of the first recess 11 and the second recess 12 may be performed continuously or in separate steps. May be.

  Next, in the gate electrode formation step ST16 shown in FIG. 9, after the second light shielding layer 3 is formed on the surface of the gate insulating layer 2, a mask (not shown) is formed on the surface of the second light shielding layer 3. The second light shielding layer 3 is etched to form a gate electrode 3c at a position overlapping the semiconductor layer 1a. At that time, the gate electrode 3c is formed with a first extension portion 3c1 and a second extension portion 3c2 extending from the position overlapping the semiconductor layer 1a in plan view to the inside of the first recess 11 and the second recess 12. The gate electrode 3c is in contact with each part (the first part 4a1, the second part 4a2, the third part 4a3, and the part of the fourth part 4a4) spaced apart in the first light shielding layer 4a. Next, high-concentration impurities are implanted into the semiconductor layer 1a using the gate electrode 3c as a mask, and low-concentration impurities are implanted into the semiconductor layer 1a in a state where a mask that covers the gate electrode 3c is formed. A source region 1b, a channel region 1g, and a drain region 1c are formed in 1a.

  Next, an interlayer insulating film 42 is formed in the second insulating layer forming step ST17. Next, in the third light shielding layer forming step ST18, after the third light shielding layer 6 is formed on the surface of the interlayer insulating film 42, the third light shielding layer 6 is formed with a mask (not shown) formed on the surface of the third light shielding layer 6. The light shielding layer 6 is etched to form the third light shielding layer 6b (data line 6a) and the drain electrode 6c shown in FIG.

  Thereafter, the interlayer insulating film 44, the capacitor electrode 7a, the insulating film 46, the dielectric layer 40, the capacitor line 5a, the interlayer insulating film 45, the pixel electrode 9a, and the alignment film 16 shown in FIG. 5 are sequentially formed.

  According to such a method, after the first opening 41a and the second opening 41b are formed in the recess forming step ST15, the first light-shielding layer 4a is used as a mask to separate the first light-shielding layer 4a. On the other hand, the first concave portion 11 and the second concave portion 12 can be formed in a self-aligning manner.

(Second example of manufacturing method)
FIG. 10 is an explanatory diagram illustrating a second example of the method for manufacturing the electro-optical device 100 according to the first embodiment of the invention. In this embodiment, in the first light shielding layer steps ST11 and ST12 shown in FIG. 10, after the first light shielding layer 4 is formed on the one surface 10s side of the substrate 10W, a mask (not shown) is formed on the surface of the first light shielding layer 4. The first light shielding layer 4 is etched in a state where the film is formed. As a result, the first portion 4a1 (part) and the second portion 4a2 (part) are separated on both sides of the region where the semiconductor layer 1a is to be formed, and the third portion 4a3 (part) and the fourth portion 4a4 ( The first light-shielding layer 4a is formed apart from a part of the first light-shielding layer 4a.

  Subsequently, in the concave portion forming step ST23, the first concave portion 11 and the second concave portion 12 are formed in the separated portions of the first light shielding layer 4a. As a result, a part of each separated in the first light shielding layer 4a is exposed. Further, the separated portion of the first light shielding layer 4a is located on the second direction D side with respect to the semiconductor layer 1a to be formed later.

  Next, in the first insulating layer forming step ST23, the first insulating layer 41 is formed on the upper layer side of the first light shielding layer 4a. Next, in the semiconductor layer forming step ST24, after the semiconductor film is formed on the first insulating layer 41, the semiconductor film is etched in a state where a mask (not shown) is formed on the surface of the semiconductor film, and the first light shielding is performed. The semiconductor layer 1a is formed at a position overlapping with the layer 4a. Next, the gate insulating layer 2 (second insulating layer) is formed on the upper layer side of the semiconductor layer 1a.

  Next, in the opening forming step ST25, the gate insulating layer 2 and the first insulating layer 41 are etched with a mask (not shown) formed on the surface of the gate insulating layer 2, so that the gate insulating layer 2 and the first insulating layer are etched. A first opening 41a that overlaps the first recess 11 in a plan view and a second opening 41b that overlaps the second recess 12 in a plan view are formed on both sides of the semiconductor layer 1a in the second direction. As a result, each part (the first part 4a1, the second part 4a2, the third part 4a3, and the part of the fourth part 4a4) spaced apart in the first light shielding layer 4a is exposed.

  Thereafter, the gate electrode forming step ST16, the impurity implantation step, the second insulating layer forming step ST17, the third light shielding layer forming step ST18, etc. described with reference to FIG. 9 are performed.

[Embodiment 2]
(Specific pixel configuration)
FIG. 11 is a plan view showing an aspect of the adjacent pixels 100a in the element substrate 10 of the electro-optical device 100 according to Embodiment 2 of the present invention. 12 is a cross-sectional view of the pixel 100a shown in FIG. 11, and is a cross-sectional view when the electro-optical device 100 is cut at a position corresponding to the F2-F2 ′ line of FIG.

  FIG. 13 is a plan view showing an aspect of the light shielding structure for the pixel transistor 30 in the electro-optical device 100 according to Embodiment 2 of the present invention. 14 is a cross-sectional view of the light shielding structure shown in FIG. 13, and is a cross-sectional view when the periphery of the pixel transistor 30 is cut at a position corresponding to the line G2-G2 ′ of FIG. FIG. 12 shows the first light shielding layer 4a, the semiconductor layer 1a, the gate electrode 3c (second light shielding layer), the source electrode 6d, the third light shielding layer 6e (drain electrode), the data line 6a, and the like. 13 includes a substrate 10w, a first light shielding layer 4a, a first insulating layer 41, a semiconductor layer 1a, a gate insulating layer 2 (second insulating layer), a gate electrode 3c (second light shielding layer), an interlayer insulating film 42, and a source. An electrode 6d, a third light shielding layer 6e (drain electrode), and the like are shown. Since the basic configuration of this embodiment is the same as that of Embodiment 1, common portions are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 11, FIG. 12, FIG. 13 and FIG. 14, in this embodiment as well, in the same manner as in the first embodiment, on the one surface 10s side of the substrate 10w, a silicon oxide film or the like is formed on the upper side of the first light shielding layer 4a. The first insulating layer 41 (first insulating layer) is formed. A semiconductor layer 1 a for constituting the pixel transistor 30 is formed on the upper layer side of the first insulating layer 41.

  In this embodiment, the pixel transistor 30 extends along the data line 6a in the first direction C (Y direction) and in the second direction D (X direction) intersecting the semiconductor layer 1a. And a gate electrode 3c (second light shielding layer) overlapping the central portion of the semiconductor layer 1a in the length direction. The pixel transistor 30 has a gate insulating layer 2 on the upper layer side of the semiconductor layer 1a, and has a gate electrode 3c on the upper layer side of the gate insulating layer 2. The gate electrode 3c is located on both sides of the semiconductor layer 1a in the second direction D, inside the first opening 41a penetrating the gate insulating layer 2 and the first insulating layer 41 and inside the second opening 41b, and the first light shielding layer 4a. Is in contact with. In this embodiment, the first light shielding layer 4 a is a scanning line 3 a extending in the second direction D (X direction), and is also configured as a back gate for the pixel transistor 30.

  An interlayer insulating film 42 (second insulating layer) is formed on the upper layer side of the gate electrode 3c, and the source electrode 6d and the third light shielding layer 6e (drain electrode) are of the same type on the interlayer insulating film 42. It is formed of a conductive film. The source electrode 6d and the third light shielding layer 6e are made of a light shielding conductive film such as a metal film such as Al, Ti, Cr, W, Ta, and Mo, a conductive polysilicon film, a metal silicide film, or a metal compound. .

  The source electrode 6d is electrically connected to the high concentration region 1b2 of the source region 1b through the contact hole 42a penetrating the interlayer insulating film 42 and the gate insulating layer 2. The third light shielding layer 6e is electrically connected to the high concentration region 1c2 of the drain region 1c through the contact hole 42b penetrating the interlayer insulating film 42 and the gate insulating layer 2.

  A translucent interlayer insulating film 43 made of a silicon oxide film or the like is formed on the upper side of the source electrode 6d and the third light shielding layer 6e (drain electrode). The surface of the interlayer insulating film 43 is a flat surface by CMP processing or the like. A conductive film 8a extending in the first direction C (Y direction) is formed on the interlayer insulating film 43, and the data line 6a is configured by the conductive film 8a.

  A translucent interlayer insulating film 44 made of a silicon oxide film or the like is formed on the upper side of the data line 6a. The configuration of the upper layer side of the interlayer insulating film 44 is the same as that of the first embodiment, and the pixel electrode 9a is formed in the high concentration region 1c2 of the drain region 1c of the pixel transistor 30 via the capacitor electrode 7a and the third light shielding layer 6e. Conducted.

  Also in this embodiment, a light shielding structure similar to that in Embodiment 1 is provided as described below. First, the element substrate 10 includes the conductive first light shielding layer 4a and the first insulating layer 41 provided on the upper side of the first light shielding layer 4a on the one surface 10s side of the substrate 10w. On the upper layer side of the first insulating layer 41, the semiconductor layer 1a is formed so as to extend in the first direction C (Y direction) so as to substantially overlap the first light shielding layer 4a in plan view. The first light shielding layer 4a extends in the X direction with the same width dimension (dimension in the Y direction), and a portion intersecting with the data line 6a is a wide light shielding portion 4e. For this reason, light that is about to enter the channel region 1g of the semiconductor layer 1a, the low concentration region 1b1 of the source region 1b, and the low concentration region 1c1 of the drain region 1c from the substrate 10w side is blocked by the first light blocking layer 4a. It is done.

  Here, on one surface 10s of the substrate 10w, a first recess 11 is formed on one side D1 (one side X1) in the second direction D (X direction) with respect to the semiconductor layer 1a. A second recess 12 is formed on the other side D2 (the other side X2) of the second direction D (X direction). Therefore, the first light-shielding layer 4a includes a first portion 4a1 located between the first recess 11 and the semiconductor layer 1a and a second portion 4a2 located on the opposite side of the first recess 11 from the semiconductor layer 1a. The edge of the first portion 4a1 opposite to the semiconductor layer 1a and the edge of the second portion 4a2 on the semiconductor layer 1a side overlap with the opening edge of the first recess 11 in plan view. The first light-shielding layer 4a includes a third portion 4a3 located between the second recess 12 and the semiconductor layer 1a and a fourth portion 4a4 located on the opposite side of the second recess 12 from the semiconductor layer 1a. The edge of the third portion 4a3 opposite to the semiconductor layer 1a and the edge of the fourth portion 4a4 on the semiconductor layer 1a side overlap with the opening edge of the second recess 12 in plan view.

  A first opening 41a is formed in the first insulating layer 41 at a position overlapping the first recess 11 in plan view, and the first opening 41a is at least one of the first portions 4a1 of the first light shielding layer 4a. The portion (the portion adjacent to the first recess 11) and at least a part of the second portion 4a2 of the first light shielding layer 4a (the portion adjacent to the first recess 11) are exposed. The first insulating layer 41 has a second opening 41b at a position overlapping the second recess 12 in plan view. The second opening 41b includes at least part of the third part 4a3 of the first light shielding layer 4a (part adjacent to the second recess 12) and at least part of the fourth part 4a4 of the first light shielding layer 4a (second The portion adjacent to the recess 12) is exposed.

  The gate electrode 3c (second light shielding layer) extends from the first opening 41a toward the one side D1 in the second direction D through the inside of the first recess 11 from a position overlapping the semiconductor layer 1a in plan view. A second extension that extends from the second opening 41a toward the other side D2 in the second direction D through the inside of the second recess 12 from a position overlapping the first extension 3c1 and the semiconductor layer 1a in plan view. And a current portion 3c2. Therefore, the first extending portion 3c1 is in contact with the first portion 4a1 and the second portion 4a2 of the first light shielding layer 4a inside the first opening 41a. The second extending portion 3c2 is in contact with the third portion 4a3 and the fourth portion 4a4 of the first light shielding layer 4a inside the second opening 41a.

  The third light shielding layer 6e extends in the second direction D, is formed to the inside of the first recess 11 through the first opening 41a, and is formed to the inside of the second recess 12 through the second opening 41b. Has been. Here, the third light shielding layer 6e is a first light shielding layer in a height direction when a portion overlapping the bottom portion 11c of the first concave portion 11 and a portion overlapping the bottom portion 12c of the second concave portion 12 are based on the substrate 10w. It is in a position lower than 4a.

  Even in this configuration, similarly to the first embodiment, the first extending portion 3c1 of the gate electrode 3c receives light that is obliquely incident in the second direction D from the substrate 10w side toward the semiconductor layer 1a. In addition, the same effects as those of the first embodiment can be obtained, such as being able to be blocked by the second extending portion 3c2.

  In addition, said light shielding structure is realizable by the process demonstrated with reference to FIG.8, FIG.9 and FIG.10.

[Embodiment 3]
FIG. 15 is a cross-sectional view showing an aspect of the light shielding structure for the pixel transistor 30 in the electro-optical device 100 according to Embodiment 3 of the present invention, and is a cross-sectional view corresponding to FIG. FIG. 16 is a process cross-sectional view illustrating the method for manufacturing the electro-optical device 100 according to Embodiment 3 of the present invention. Since the basic configuration of this embodiment is the same as that of Embodiment 1, common portions are denoted by the same reference numerals and description thereof is omitted.

  In the first embodiment, the first light shielding layer 4a is not formed in the first concave portion 11 and in the second concave portion 12, but in the present embodiment, as shown in FIG. 11, the first light shielding layer 4a. Are also formed inside the first recess 11 and inside the second recess 12. For this reason, the first light shielding layer 4a is provided along the side surface 11a, the bottom portion 11c, and the side surface 11b inside the first concave portion 11, and the side surface 12a and the bottom portion 12c of the second concave portion 12 inside the second concave portion 12. And along the side surface 12b. Other configurations are the same as those in the first embodiment.

  According to this configuration, the first light shielding layer 4a and the gate electrode 3c extend from the first opening 41a to the side opposite to the semiconductor layer 1a through the inside of the first recess 11, and the second recess. 12 extends from the second opening 41b to the side opposite to the semiconductor layer 1a. For this reason, when forming the conductive film to be the gate electrode 3c, it is difficult to properly form the conductive film on the side surfaces of the first concave portion 11 and the second concave portion 12, and the second case of forming the gate electrode 3c. Even if mask misalignment or the like occurs in the direction D, the first extending portion 3c1 of the gate electrode 3c is reliably provided inside the first recess 11, and the second extending portion 3c2 of the gate electrode 3c is the second recess. 12 is securely provided inside. Therefore, it is possible to reliably block light that is about to enter obliquely from the X direction toward the semiconductor layer 1a from the substrate 10w side.

  When manufacturing the electro-optical device 100 of the present embodiment, as in the first embodiment, before forming the gate electrode 3c, in the recess forming step, the first recess 11 and the second recess 12 are formed on the one surface 10s of the substrate 10w. Form. Further, before forming the gate electrode 3 c and before or after the recess forming step, the first opening 41 a and the second opening 41 b are formed in the first insulating layer 41 in the opening forming step. In the second light shielding layer forming step for forming the gate electrode 3c, the first extending portion 3c1 and the second extending portion 3c2 are provided on the gate electrode 3c.

  More specifically, first, in the recess forming steps ST31 and ST32 shown in FIG. 12, first, the one surface 10s of the substrate 10w is etched with a mask (not shown) formed on the one surface 10s of the substrate 10w. The first recess 11 and the second recess 12 are formed on both sides of the region where the semiconductor layer 1a is to be formed.

  Next, in the light shielding layer forming step ST33, after the first light shielding layer 4 is formed on one surface 10s of the substrate 10w, the first light shielding layer is formed with a mask (not shown) formed on the surface of the first light shielding layer 4. 4 is etched. As a result, as shown in FIG. 15, the first light shielding layer 4 a is formed so as to be partially separated at a position overlapping the first recess 11 and the second recess 12 in plan view.

  Then, the formation process of the 1st insulating layer 41, the formation process of the semiconductor layer 1a, the formation process of the 2nd insulation layer 2, the formation process of the 1st opening part 41a and the 2nd opening part 41b, the gate electrode 3c (2nd light shielding layer) Steps similar to those in the second example of the manufacturing method of the first embodiment, such as the formation step of

[Embodiment 4]
FIG. 17 is a cross-sectional view showing an aspect of the light shielding structure for the pixel transistor in the electro-optical device according to Embodiment 4 of the present invention, and is a cross-sectional view corresponding to FIG. Since the basic configuration of this embodiment is the same as that of Embodiment 1, common portions are denoted by the same reference numerals and description thereof is omitted.

  In the second embodiment, the first light shielding layer 4a is not formed in the first recess 11 and in the second recess 12, but in this embodiment, as shown in FIG. Similarly, the first light shielding layer 4 a is also formed inside the first recess 11 and inside the second recess 12. For this reason, the first light shielding layer 4a is provided along the side surface 11a, the bottom portion 11c, and the side surface 11b inside the first concave portion 11, and the side surface 12a and the bottom portion 12c of the second concave portion 12 inside the second concave portion 12. And along the side surface 12b. Other configurations are the same as those in the second and third embodiments. According to such a configuration, the same effects as those of the second embodiment can be obtained, such as that light that is obliquely incident from the second direction D toward the semiconductor layer 1a from the substrate 10w side can be reliably blocked.

[Other embodiments]
In the second and fourth embodiments, the first light shielding layer 4a is a part of the scanning line 3a. However, the gate electrode 3c may be a part of the scanning line 3a.

  In the above embodiment, the gate electrode 3c is formed as the second light shielding layer. However, the insulating light shielding layer or the like is used as the second light shielding layer inside the first opening 41a and inside the second opening 41b. A configuration in contact with the one light shielding layer 4a may be employed.

[Example of mounting on electronic devices]
FIG. 18 is a schematic configuration diagram of a projection display device (electronic apparatus) using the electro-optical device 100 to which the present invention is applied. In the following description, a plurality of electro-optical devices 100 to which light having different wavelength ranges are supplied are used. However, the electro-optical device 100 to which the present invention is applied is used for any of the electro-optical devices 100. It has been.

  A projection type display device 110 shown in FIG. 18 is a liquid crystal projector using the transmission type electro-optical device 100, and irradiates the projection target member 111 made of a screen or the like with light to display an image. The projection display device 110 includes an illumination device 160 along the device optical axis L, a plurality of electro-optical devices 100 (liquid crystal light valves 115 to 117) to which light emitted from the illumination device 160 is supplied, and a plurality of A cross dichroic prism 119 (light combining optical system) that combines and emits light emitted from the electro-optical device 100 and a projection optical system 118 that projects light combined by the cross dichroic prism 119 are provided. In addition, the projection display device 110 includes dichroic mirrors 113 and 114 and a relay system 120. In the projection display device 110, the electro-optical device 100 and the cross dichroic prism 119 constitute an optical unit 200.

  In the illumination device 160, along the device optical axis L, a light source unit 161, a first integrator lens 162 composed of a lens array such as a fly-eye lens, a second integrator lens 163 composed of a lens array such as a fly-eye lens, and a polarization conversion element 164 and a condenser lens 165 are arranged in this order. The light source unit 161 includes a light source 168 that emits white light including red light R, green light G, and blue light B, and a reflector 169. The light source 168 is configured by an ultra-high pressure mercury lamp or the like, and the reflector 169 has a parabolic cross section. The first integrator lens 162 and the second integrator lens 163 make the illuminance distribution of the light emitted from the light source unit 161 uniform. The polarization conversion element 164 turns the light emitted from the light source unit 161 into polarized light having a specific vibration direction such as s-polarized light.

  The dichroic mirror 113 transmits the red light R included in the light emitted from the illumination device 160 and reflects the green light G and the blue light B. The dichroic mirror 114 transmits the blue light B and reflects the green light G out of the green light G and the blue light B reflected by the dichroic mirror 113. As described above, the dichroic mirrors 113 and 114 constitute a color separation optical system that separates the light emitted from the illumination device 160 into red light R, green light G, and blue light B.

  The liquid crystal light valve 115 is a transmissive liquid crystal device that modulates the red light R transmitted through the dichroic mirror 113 and reflected by the reflection mirror 123 in accordance with an image signal. The liquid crystal light valve 115 includes a λ / 2 retardation plate 115a, a first polarizing plate 115b, an electro-optical device 100 (red electro-optical device 100R), and a second polarizing plate 115d. Here, the red light R incident on the liquid crystal light valve 115 remains as s-polarized light because the polarization of the light does not change even if it passes through the dichroic mirror 113.

  The λ / 2 phase difference plate 115a is an optical element that converts s-polarized light incident on the liquid crystal light valve 115 into p-polarized light. The first polarizing plate 115b is a polarizing plate that blocks s-polarized light and transmits p-polarized light. The electro-optical device 100 (red electro-optical device 100R) is configured to convert p-polarized light into s-polarized light (circularly polarized light or elliptically polarized light in the case of halftone) by modulation according to an image signal. The second polarizing plate 115d is a polarizing plate that blocks p-polarized light and transmits s-polarized light. Accordingly, the liquid crystal light valve 115 modulates the red light R according to the image signal, and emits the modulated red light R toward the cross dichroic prism 119. The λ / 2 phase difference plate 115a and the first polarizing plate 115b are arranged in contact with a light-transmitting glass plate 115e that does not convert the polarization, and the λ / 2 phase difference plate 115a and the first polarizing plate 115b are arranged. Distortion due to heat generation can be avoided.

  The liquid crystal light valve 116 is a transmissive liquid crystal device that modulates green light G reflected by the dichroic mirror 114 after being reflected by the dichroic mirror 113 in accordance with an image signal. As with the liquid crystal light valve 115, the liquid crystal light valve 116 includes a first polarizing plate 116b, an electro-optical device 100 (green electro-optical device 100G), and a second polarizing plate 116d. Green light G incident on the liquid crystal light valve 116 is s-polarized light that is reflected by the dichroic mirrors 113 and 114 and then incident. The first polarizing plate 116b is a polarizing plate that blocks p-polarized light and transmits s-polarized light. The electro-optical device 100 (green electro-optical device 100G) is configured to convert s-polarized light into p-polarized light (circularly polarized light or elliptically polarized light in the case of halftone) by modulation according to an image signal. The second polarizing plate 116d is a polarizing plate that blocks s-polarized light and transmits p-polarized light. Therefore, the liquid crystal light valve 116 modulates the green light G according to the image signal, and emits the modulated green light G toward the cross dichroic prism 119.

  The liquid crystal light valve 117 is a transmissive liquid crystal device that modulates the blue light B reflected by the dichroic mirror 113, transmitted through the dichroic mirror 114, and then passed through the relay system 120 in accordance with an image signal. Similarly to the liquid crystal light valves 115 and 116, the liquid crystal light valve 117 includes a λ / 2 phase difference plate 117a, a first polarizing plate 117b, an electro-optical device 100 (blue electro-optical device 100B), and a second polarizing plate 117d. I have. Since the blue light B incident on the liquid crystal light valve 117 is reflected by the dichroic mirror 113 and transmitted through the dichroic mirror 114 and then reflected by the two reflection mirrors 125a and 125b of the relay system 120, it is s-polarized light.

  The λ / 2 phase difference plate 117a is an optical element that converts s-polarized light incident on the liquid crystal light valve 117 into p-polarized light. The first polarizing plate 117b is a polarizing plate that blocks s-polarized light and transmits p-polarized light. The electro-optical device 100 (blue electro-optical device 100B) is configured to convert p-polarized light into s-polarized light (circularly polarized light or elliptically polarized light in the case of halftone) by modulation according to an image signal. The second polarizing plate 117d is a polarizing plate that blocks p-polarized light and transmits s-polarized light. Accordingly, the liquid crystal light valve 117 modulates the blue light B according to the image signal, and emits the modulated blue light B toward the cross dichroic prism 119. The λ / 2 phase difference plate 117a and the first polarizing plate 117b are arranged in contact with the glass plate 117e.

  The relay system 120 includes relay lenses 124a and 124b and reflection mirrors 125a and 125b. The relay lenses 124a and 124b are provided to prevent light loss due to the long optical path of the blue light B. The relay lens 124a is disposed between the dichroic mirror 114 and the reflection mirror 125a. The relay lens 124b is disposed between the reflection mirrors 125a and 125b. The reflection mirror 125a reflects the blue light B transmitted through the dichroic mirror 114 and emitted from the relay lens 124a toward the relay lens 124b. The reflection mirror 125b reflects the blue light B emitted from the relay lens 124b toward the liquid crystal light valve 117.

  The cross dichroic prism 119 is a color combining optical system in which two dichroic films 119a and 119b are arranged orthogonally in an X shape. The dichroic film 119a is a film that reflects blue light B and transmits green light G, and the dichroic film 119b is a film that reflects red light R and transmits green light G. Accordingly, the cross dichroic prism 119 combines the red light R, the green light G, and the blue light B that are modulated by the liquid crystal light valves 115 to 117, and emits the resultant light toward the projection optical system 118.

  Note that light incident on the cross dichroic prism 119 from the liquid crystal light valves 115 and 117 is s-polarized light, and light incident on the cross dichroic prism 119 from the liquid crystal light valve 116 is p-polarized light. Thus, by making the light incident on the cross dichroic prism 119 into different types of polarized light, the light incident from the liquid crystal light valves 115 to 117 can be synthesized in the cross dichroic prism 119. Here, in general, the dichroic films 119a and 119b are excellent in the reflection characteristics of s-polarized light. For this reason, red light R and blue light B reflected by the dichroic films 119a and 119b are s-polarized light, and green light G transmitted through the dichroic films 119a and 119b is p-polarized light. The projection optical system 118 has a projection lens (not shown), and projects the light combined by the cross dichroic prism 119 onto a projection target 111 such as a screen.

[Other projection display devices]
In the projection type display device, the transmission type electro-optical device 100 is used. However, the reflection type electro-optical device 100 may be used to form the projection type display device. In the projection display device, an LED light source that emits light of each color may be used as the light source unit, and the color light emitted from the LED light source may be supplied to another liquid crystal device. .

[Other electronic devices]
Regarding the electro-optical device 100 to which the present invention is applied, in addition to the above-described electronic apparatus, a projection-type HUD (head-up display), a direct-view HMD (head-mounted display), a mobile phone, and a personal digital assistant (PDA: (Personal Digital Assistants), digital cameras, liquid crystal televisions, car navigation devices, videophones, and the like.

DESCRIPTION OF SYMBOLS 1a ... Semiconductor layer, 1b ... Source region, 1b1 ... Low concentration region, 1b2 ... High concentration region, 1c ... Drain region, 1c1 ... Low concentration region, 1c2 ... High concentration region, 1g ... Channel region, 2 ... Gate insulating layer ( 2nd insulating layer), 3a ... scanning line, 3c ... gate electrode (second light shielding layer), 3c1 ... first extending portion, 3c2 ... second extending portion, 4a ... first light shielding layer, 4a1 ... first portion. 4a2, 2nd part, 4a3 ... 3rd part, 4a4 ... 4th part, 5a ... capacitive line, 6a ... data line, 6b, 6e ... 3rd light shielding layer, 6c ... drain electrode, 6d ... source electrode, 7a ... Capacitance electrode, 9a ... pixel electrode, 10 ... element substrate, 10s ... one side, 10t ... other side, 10w ... substrate, 11 ... first recess, 11a, 11b ... side, 11c ... bottom, 12 ... second recess, 12a , 12b ... side, 12c ... bottom, 20 ... opposite Plate: 30 ... Pixel transistor, 41 ... First insulating layer, 41a ... First opening, 41b ... Second opening, 42, 43, 44, 45 ... Interlayer insulating film, 50 ... Liquid crystal layer, 55 ... Storage capacitor, 100a ... pixel, 100p ... liquid crystal panel, C ... first direction, D ... second direction

Claims (15)

A first light-shielding layer provided on one side of the substrate;
A first insulating layer provided on a side opposite to the substrate with respect to the first light shielding layer;
A semiconductor layer provided in a position overlapping the first light-shielding layer on a side opposite to the substrate with respect to the first insulating layer in plan view, and extending in a first direction;
A second insulating layer provided on the opposite side of the substrate from the semiconductor layer;
A second light-shielding layer provided at a position overlapping the semiconductor layer opposite to the substrate with respect to the second insulating layer in a plan view;
Have
The one surface of the substrate includes a first recess on a second direction side intersecting the first direction with respect to the semiconductor layer,
The first light shielding layer includes a first part located between the first recess and the semiconductor layer, and a second part located on the opposite side of the first recess from the semiconductor layer,
The first insulating layer includes a first opening at a position overlapping the first recess in plan view so that a part of each of the first portion and the second portion of the first light shielding layer is exposed.
The second light shielding layer extends from a position overlapping the semiconductor layer in plan view to the inside of the first recess, and is in contact with the first portion and the second portion of the first light shielding layer. An electro-optical device. The electro-optical device according to claim 1.
The electro-optical device, wherein the second light shielding layer is a gate electrode. The electro-optical device according to claim 1,
The electro-optical device, wherein the first light shielding layer is a back gate electrode. The electro-optical device according to any one of claims 1 to 3,
A third light-shielding layer provided on the opposite side of the substrate with respect to the second light-shielding layer;
The electro-optical device, wherein a part of the third light shielding layer is located inside the first recess. The electro-optical device according to claim 4.
The electro-optical device, wherein the third light shielding layer is a data line. The electro-optical device according to claim 4.
Having a pixel electrode electrically connected to the semiconductor layer;
The electro-optical device, wherein the pixel electrode is electrically connected to the semiconductor layer through the third light shielding layer. The electro-optical device according to any one of claims 1 to 6,
The electro-optical device, wherein the first light shielding layer is not provided in the first recess. The electro-optical device according to any one of claims 1 to 6,
A part of the first light shielding layer is provided inside the first recess,
The first portion and the second portion of the first light shielding layer are electrically connected via a portion provided inside the first recess of the first light shielding layer. Optical device. The electro-optical device according to any one of claims 1 to 8,
The one surface of the substrate is provided with a second recess on the opposite side of the semiconductor layer from the first recess,
The first light shielding layer includes a third portion positioned between the first recess and the semiconductor layer, and a fourth portion positioned on the opposite side of the first recess from the semiconductor layer,
The first insulating layer includes a second opening at a position overlapping the second recess in plan view so that a part of each of the third portion and the fourth portion of the first light shielding layer is exposed,
The second light shielding layer extends from a position overlapping the semiconductor layer in plan view to the inside of the second recess, and is in contact with the third portion and the fourth portion of the first light shielding layer. An electro-optical device. The electro-optical device according to any one of claims 1 to 9,
The electro-optical device, wherein the first light shielding layer is a scanning line extending along the first direction. The electro-optical device according to any one of claims 1 to 9,
One of the first light-shielding layer and the second light-shielding layer is a scanning line extending along the second direction. Forming a first light-shielding layer partly spaced on one side of the substrate;
Forming a first insulating layer;
Forming a semiconductor layer extending in a first direction at a position overlapping the first light shielding layer in plan view;
Forming a second insulating layer;
Forming a first recess in a spaced apart portion of the first light shielding layer on one side of the substrate;
Forming a second light shielding layer at a position overlapping the semiconductor layer in plan view,
In the step of forming the first recess, a part of each of the spaced apart first light shielding layers is exposed,
The spaced apart portion of the first light shielding layer is located on the second direction side intersecting the first direction with respect to the semiconductor layer,
The second light-shielding layer extends from a position overlapping the semiconductor layer in plan view to the inside of the first recess, and is in contact with each of the spaced apart first light-shielding layers. Manufacturing method. Forming a first light-shielding layer partly spaced on one side of the substrate;
Forming a first recess in a spaced apart portion of the first light shielding layer on one side of the substrate;
Forming a first insulating layer;
Forming a semiconductor layer extending in a first direction at a position overlapping the first light shielding layer in plan view;
Forming a second insulating layer;
Forming a first opening so that a part of each of the spaced apart first light shielding layers is exposed at a position overlapping the first recess in plan view;
Forming a second light shielding layer at a position overlapping the semiconductor layer in plan view,
The spaced apart portion of the first light shielding layer is located on the second direction side intersecting the first direction with respect to the semiconductor layer,
The second light-shielding layer extends from a position overlapping the semiconductor layer in plan view to the inside of the first recess, and is in contact with each of the spaced apart first light-shielding layers. Manufacturing method. Forming a first recess on one side of the substrate;
Forming a first light-shielding layer on the one surface side of the substrate so as to be partially separated at a position overlapping the first recess in plan view;
Forming a first insulating layer;
Forming a semiconductor layer extending in a first direction at a position overlapping the first light shielding layer in plan view;
Forming a second insulating layer;
Forming a first opening so that a part of each of the spaced apart first light shielding layers is exposed at a position overlapping the first recess in plan view;
Forming a second light shielding layer at a position overlapping the semiconductor layer in plan view,
The spaced apart portion of the first light shielding layer is located on the second direction side intersecting the first direction with respect to the semiconductor layer,
The second light-shielding layer extends from a position overlapping the semiconductor layer in plan view to the inside of the first recess, and is in contact with each of the spaced apart first light-shielding layers. Manufacturing method.   An electronic apparatus comprising the electro-optical device according to claim 1.

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