JP2012119646A - Nitride light-emitting element and nitride light-emitting element manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nitride light-emitting element which can improve reduction of an element lifetime caused by hydrogen shift.SOLUTION: A group-III nitride semiconductor region 13-1 includes a first region 13a-1 and a second region 13b-1. The second region 13b-1 extends along the first region 13a-1. The first region 13a-1 includes a ridge portion of p-type conductivity. The group-III nitride semiconductor region 13-1 includes a p-type dopant and hydrogen. An electrode 17-1 makes contact with a top face 13c-1 of the ridge portion of the first region 13a-1. A metal layer 19-1 has lattice defects which are present densely and enable hydrogen occlusion, and is provided on the second region 13b-1. A dielectric layer 21-1 is provided on the metal layer 19-1 and the dielectric layer 21-1 includes a silicon oxide film, a silicon nitride, a silicon oxynitride, a hafnium oxide, a tantalum oxide and the like.

Description

  The present invention relates to a nitride light emitting device and a method for manufacturing a nitride light emitting device.

Patent Document 1 describes a method for manufacturing an electrode. In this method, a hydrogen storage metal is deposited as an electrode on a p-type Al _X In _Y Ga _1-XY N semiconductor layer containing Mg. Patent Documents 2 and 3 and Non-Patent Document 1 describe the relationship between Mg dopant and hydrogen in a gallium nitride semiconductor. Non-Patent Document 2 describes experimental and analytical studies on the influence of interaction between hydrogen and crystal lattice defects on steel materials.

JP 11-340511 A Japanese Patent Laid-Open No. 05-183189 Japanese Patent Laid-Open No. 08-115880

Shuji Nakamura et al. “Hole Compensation Mechanism of P-Type GaN film,” Jpn. Appl. Phys. Vol. 31 (1992) pp1258-1266, Part 1, No.5A, May 1992 Atomistic study of hydrogen distribution and diffusion around a (112) [111] edge dislocation in alpha iron Acta Materialia 56 (15), 3761-3769, 2008-09

  As described in Patent Documents 2 and 3 and Non-Patent Document 1, Mg dopant and hydrogen are closely related to p-type activation in a gallium nitride based semiconductor. These documents describe several approaches for p-type activation with Mg dopants.

  In Mg-doped nitride semiconductor light emitting devices that are currently commercialized, hydrogen inevitably remains in the nitride semiconductor. This hydrogen is included in the nitride semiconductor not only in the form of a complex containing Mg—H bonds but also in the form of atomic and molecular hydrogen trapped by lattice defects existing in the semiconductor crystal. In an atmosphere containing hydrogen, hydrogen may enter the inside of the light-emitting element from the outside, and such hydrogen may react with the surface of the light-emitting element that is heated by laser oscillation. .

  As described above, hydrogen remains in various states inside the semiconductor layer after the nitride semiconductor element is formed, and thus affects the reliability of the nitride semiconductor element. In addition, in the crystal plasticity theory of metal materials, it is mentioned that hydrogen interacts with lattice defects. Non-Patent Document 2 described above shows that edge dislocations having strain existing in the crystal lattice in α-iron greatly influence the behavior of hydrogen.

  The present invention has been made in view of the above circumstances, and relates to a nitride light-emitting device in which the movement of hydrogen, which contributes to shortening the device life, is controlled by improving the device structure, and a method for manufacturing the same. .

The nitride light emitting device according to the present invention includes (a) an active layer made of a group III nitride semiconductor, and (b) at least one group III nitride semiconductor having different polarities on at least two surface sides of the active layer. A metal electrode having each polarity is formed on the surface of the two group III nitride semiconductors on the outermost layer and (c) the group III nitride semiconductor on at least one side includes a first region including a ridge portion, A second region extending along the first region, provided on the group III nitride semiconductor region provided on the active layer, and containing hydrogen and a p-type dopant, A metal layer provided on the second region of the group III nitride semiconductor region and having a crystal defect capable of capturing hydrogen liberated at least in an atomic or molecular state; and (e) the metal layer Joining the electrode and the metal layer And a dielectric layer provided between the. The electrode is in contact with the upper surface of the ridge portion.
The nitride light emitting device according to the present invention includes (a) an active layer made of a group III nitride semiconductor, (b) a first region including a p-type conductive ridge, and extending along the first region. A group III nitride semiconductor region containing hydrogen and a p-type dopant, and (c) provided on the first region and the second region of the group III nitride semiconductor region. An electrode; and (d) a metal layer provided on the second region of the group III nitride semiconductor region and having a crystal defect capable of capturing hydrogen liberated at least in an atomic or molecular state; and (e And a dielectric layer provided between the electrode and the metal layer. The group III nitride semiconductor region is provided on the active layer. The electrode is in contact with the upper surface of the ridge portion.

  According to this nitride light emitting device, the metal layer is provided on the second region as described above, and this metal layer has crystal defects capable of capturing hydrogen liberated at least in an atomic or molecular state. The group III nitride semiconductor region contains hydrogen, and the moving hydrogen is trapped through the interface when it reaches the metal layer. Since the metal layer is provided on the second region different from the ridge portion of the first region, the moving hydrogen is occluded in the metal layer separated from the interface between the ridge portion of the first region and the electrode. Further, since the electrode makes contact with the upper surface of the ridge portion in the first region and the ridge has p-type conductivity, a current path from the electrode is provided. The material of the electrode is determined independently of the material of the metal layer.

  In the nitride light emitting device according to the present invention, the metal layer is in contact with the upper surface of the second region of the group III nitride semiconductor region, and in order to effectively capture the free hydrogen, The contact area with the second region is preferably larger than the contact area between the upper surface of the ridge portion and the electrode.

  Further, according to the nitride light emitting device, the contact area between the metal layer and the second region is not limited to the contact area between the electrode and the semiconductor layer, and the contact between the upper surface of the ridge portion and the electrode. It is preferably larger than the area.

  In the nitride light emitting device according to the present invention, the metal layer can be in contact with the p-type semiconductor region of the second region. According to this nitride light-emitting device, the metal layer is decomposed by a thermal history in the case where a composite in which a p-type dopant and hydrogen in a p-type semiconductor region are combined is used in a later step or as a device for a long time. Even in this case, hydrogen liberated through the interface with the semiconductor layer can be captured.

  In the nitride light emitting device according to the present invention, the group III nitride semiconductor region may be doped with Mg. According to this nitride light emitting device, the metal layer can capture hydrogen when hydrogen is liberated from the Mg—H bond in the p-type semiconductor region.

  In the nitride light emitting device according to the present invention, the metal layer may include Ti, Mg, Mn, Zr, Ni, Ca, Nb, V, Pd and an alloy composed of at least two of these elements. According to this nitride light-emitting element, metals and alloys containing the above-listed elements can be used as a metal layer for capturing hydrogen.

  In the nitride light emitting device according to the present invention, the dielectric layer is provided between the electrode and the metal layer, and the dielectric layer includes a silicon oxide film, a silicon nitride, a silicon oxynitride, a hafnium oxide, It is preferable to include at least one of tantalum oxide, ferroelectric, and polyimide organic material.

  According to this nitride light emitting device, since the dielectric layer is provided between the electrode and the metal layer, hydrogen in the metal layer does not reach the electrode through the dielectric layer.

  The nitride light-emitting device according to the present invention can further include a support base made of a group III nitride and a group III nitride semiconductor layer provided on the main surface of the support base. The group III nitride semiconductor layer has n-type conductivity, and the active layer is provided between the group III nitride semiconductor layer and the group III nitride semiconductor region. In the nitride light emitting device according to the present invention, the main surface of the support base may be inclined at an angle in the range of not less than 63 degrees and not more than 80 degrees with respect to the c-axis of the group III nitride.

  In the nitride light emitting device according to the present invention, the metal layer is in contact with a side surface of the ridge portion and / or an upper surface of the second region of the group III nitride semiconductor region, and the dielectric layer is the metal layer. It is preferable to make contact with the side surface of the ridge portion so as to cover the upper surface of the ridge portion and to ensure electrical insulation between the metal layer and the electrode. According to this nitride light emitting device, the metal layer makes contact with the upper surface of the second region of the group III nitride semiconductor region and the side surface of the metal layer makes contact with the side surface of the ridge portion. The amount of hydrogen that reaches the contact interface between the electrode and the electrode can be reduced.

  In the nitride light emitting device according to the present invention, it is preferable that the metal layer is separated from a side surface of the ridge portion, and the dielectric layer covers the entire surface of the metal layer and contacts the side surface of the ridge portion. . According to this nitride light emitting device, free hydrogen in the semiconductor film is captured by the metal layer spaced from the side surface of the ridge portion. Therefore, a hydrogen concentration gradient that decreases toward the metal layer is formed in the semiconductor film.

  The present invention relates to a method for fabricating a nitride light emitting device. This method includes (a) a group III nitride semiconductor region having a first region including a ridge portion and a second region extending along the first region, and the second group III nitride semiconductor region. A step of producing a substrate product including a metal layer and a dielectric layer sequentially provided on the region, and an active layer; and (b) the ridge portion of the first region of the group III nitride semiconductor region. Forming an electrode on the upper surface and the dielectric layer. The electrode is in contact with the upper surface of the ridge portion, the group III nitride semiconductor region is formed on the active layer, and the metal layer captures hydrogen released at least in an atomic or molecular state. The III-nitride semiconductor region having crystal defects that can include hydrogen and a p-type dopant.

  According to this manufacturing method, the electrode is formed in contact with the upper surface of the ridge portion in the first region, and the metal layer is formed on the second region. This metal layer has crystal defects that can capture hydrogen liberated at least in an atomic or molecular state. The group III nitride semiconductor region contains hydrogen, but free hydrogen that reaches the metal layer is occluded in the metal layer. Since the metal layer is formed on the second region different from the ridge portion of the first region, the moving hydrogen is stored in the metal layer separated from the interface between the ridge portion of the first region and the electrode. . Further, since the electrode makes contact with the upper surface of the ridge portion in the first region and the ridge has p-type conductivity, a current path from the electrode is provided. The electrode material is determined independently of the metal layer material.

  In the manufacturing method according to the present invention, the step of manufacturing a substrate product includes a group III nitride semiconductor film for a p-type cladding layer and a group III group for a p-type contact layer above the active layer. A step of growing a nitride semiconductor film to form an epitaxial substrate; a step of forming a mask for a lift-off method on a main surface of the epitaxial substrate; and the first and second III using the mask. Etching the group nitride semiconductor film to form a ridge in the group III nitride semiconductor region; and sequentially using the mask to form the metal layer and the dielectric layer on the group III nitride semiconductor region. A step of growing, and a step of removing the mask by a lift-off method to form the substrate product. Each of the first group III nitride semiconductor film and the second group III nitride semiconductor film includes a p-type dopant, the group III nitride semiconductor region includes the p-type cladding layer and the p-type contact layer, The metal layer is in contact with the upper surface of the p-type cladding layer.

  According to this manufacturing method, the position of the ridge portion is defined using a mask for lift-off and etching, and films for the metal layer and the dielectric layer are deposited using this mask. After the deposition, the metal layer and the dielectric layer are formed in a self-aligned manner with respect to the ridge portion by removing the mask.

  In the manufacturing method according to the present invention, the metal layer contacts the side surface of the ridge portion, and the dielectric layer covers the upper surface of the metal layer and contacts the side surface of the ridge portion. The dielectric layer ensures electrical insulation between the metal layer and the electrode layer.

  In the manufacturing method according to the present invention, the metal layer is in contact with an upper surface of the second region of the group III nitride semiconductor region, and the second region and the metal layer in the substrate product are in contact with each other. The contact area is preferably larger than the contact area between the upper surface of the ridge portion and the electrode in the substrate product. According to this manufacturing method, the contact area between the metal layer and the second region can be made larger than the total contact area between the upper surface of the ridge portion and the electrode without being limited to the contact area between the electrode and the semiconductor layer.

  In the manufacturing method according to the present invention, the group III nitride semiconductor region may be doped with Mg. According to this manufacturing method, the metal layer can capture hydrogen liberated from Mg—H bonds in the p-type semiconductor region.

  In the manufacturing method according to the present invention, the metal layer may include Ti, Mg, Mn, Zr, Ni, Ca, Nb, V, Pd, and an alloy composed of at least two of these elements. According to this fabrication method, metals and alloys containing the above-listed elements can be used for the metal layer.

  In the manufacturing method according to the present invention, the substrate product includes a substrate made of a group III nitride and a group III nitride semiconductor layer grown on a main surface of the substrate, and the active layer includes the group III Grown on the group nitride semiconductor layer, the group III nitride semiconductor layer has n-type conductivity, and the active layer is provided between the group III nitride semiconductor layer and the group III nitride semiconductor region Can be done. In the manufacturing method according to the present invention, it is preferable that the main surface of the substrate is inclined at an angle in a range of 63 degrees to 80 degrees with respect to the c-axis of the group III nitride.

  In the manufacturing method according to the present invention, the dielectric layer is provided between the electrode and the metal layer, and the dielectric layer and the metal layer are deposited in a self-aligned manner with respect to the ridge portion. it can. The dielectric layer includes at least one of a silicon oxide film, silicon nitride, silicon oxynitride, hafnium oxide, tantalum oxide, a ferroelectric, and a polyimide organic material. According to this manufacturing method, since the dielectric layer is provided between the electrode and the metal layer, hydrogen in the metal layer does not reach the electrode through the dielectric layer.

The nitride light emitting device according to the present invention includes (a) an active layer made of a group III nitride semiconductor, and (b) at least one group III nitride semiconductor having different polarities on at least two surface sides of the active layer. A metal electrode having each polarity is formed on the surface of the two group III nitride semiconductors on the outermost layer and (c) a first region including a p-type conductive ridge portion and along the first region A group III nitride semiconductor region provided on the active layer, and (d) the first region and the second region of the group III nitride semiconductor region. An electrode that is in contact with the upper surface of the ridge portion, (e) a metal layer provided on the second region of the group III nitride semiconductor region, and (f) the metal layer And a dielectric layer forming a junction. The metal layer includes a region having a lattice defect density of 1 × 10 ¹¹ cm ⁻² or more, and the group III nitride semiconductor region includes hydrogen and a p-type dopant.

According to this nitride light emitting device, the electrode is in contact with the upper surface of the ridge portion in the first region, and the metal layer is provided on the second region. This metal layer includes a region having a lattice defect density of 1 × 10 ¹¹ cm ⁻² or more. The group III nitride semiconductor region contains hydrogen, and when the moving hydrogen reaches the metal layer, it is trapped in the region of the metal layer (region having a lattice defect density of 1 × 10 ¹¹ cm ⁻² or more). Since the metal layer is provided on the second region different from the ridge portion of the first region, the moving hydrogen is captured by the metal layer separated from the interface between the ridge portion of the first region and the electrode. Further, since the electrode makes contact with the upper surface of the ridge portion in the first region and the ridge has p-type conductivity, a current path from the electrode is provided. The material of the electrode is determined independently of the material of the metal layer.

  In the nitride light emitting device according to the present invention, the metal layer is in contact with the upper surface of the second region of the group III nitride semiconductor region, and in order to effectively capture the free hydrogen, The contact area with the second region is preferably larger than the contact area between the upper surface of the ridge portion and the electrode.

  Further, according to the nitride light emitting device, the contact area between the metal layer and the second region is not limited to the contact area between the electrode and the semiconductor layer, and the contact between the upper surface of the ridge portion and the electrode. It is preferably larger than the area.

  In the nitride light emitting device according to the present invention, the metal layer can be in contact with the p-type semiconductor region of the second region. According to this nitride light-emitting device, the metal layer is decomposed by a thermal history in the case where a composite in which the p-type dopant in the p-type semiconductor region and hydrogen are combined is used in a later process or as a device for a long time. Even in such a case, hydrogen liberated through the interface with the semiconductor layer can be captured.

  In the nitride light emitting device according to the present invention, the group III nitride semiconductor region may be doped with Mg. According to this nitride light emitting device, the metal layer can capture hydrogen when hydrogen is released from the Mg—H bond in the p-type semiconductor region.

In the nitride light emitting device according to the present invention, it is preferable that the lattice defects included in the metal layer include at least one of point defects, dislocations, stacking faults, and aggregates of these defects. According to this nitride light emitting device, the lattice defects can interact with hydrogen and trap hydrogen. In the nitride light emitting device according to the present invention, the region of the metal layer preferably has a lattice defect density of 1 × 10 ¹⁵ cm ⁻² or less. According to this nitride light emitting device, when the lattice defect density is not more than the above value, the deterioration of the metal layer due to the high defect density does not affect the device characteristics.

  In the nitride light emitting device according to the present invention, the dielectric layer is provided between the electrode and the metal layer, and the dielectric layer includes a silicon oxide film, a silicon nitride, a silicon oxynitride, a hafnium oxide, It is preferable to include at least one of tantalum oxide, ferroelectric, and polyimide organic material.

  According to this nitride light emitting device, since the dielectric layer is provided between the electrode and the metal layer, hydrogen in the metal layer does not reach the electrode through the dielectric layer.

  The nitride light-emitting device according to the present invention can further include a support base made of a group III nitride and a group III nitride semiconductor layer provided on the main surface of the support base. The group III nitride semiconductor layer has n-type conductivity, and the active layer is provided between the group III nitride semiconductor layer and the group III nitride semiconductor region. In the nitride light emitting device according to the present invention, the main surface of the support base may be inclined at an angle in the range of not less than 63 degrees and not more than 80 degrees with respect to the c-axis of the group III nitride.

  In the nitride light emitting device according to the present invention, the metal layer is in contact with a side surface of the ridge portion and / or an upper surface of the second region of the group III nitride semiconductor region, and the dielectric layer is the metal layer. Preferably, the metal layer and the electrode are in contact with the side surface of the ridge so that the metal layer and the electrode are electrically insulated. According to this nitride light emitting device, the metal layer makes contact with the upper surface of the second region of the group III nitride semiconductor region and the side surface of the metal layer makes contact with the side surface of the ridge portion. The amount of hydrogen that reaches the contact interface between the electrode and the electrode can be reduced.

  In the nitride light emitting device according to the present invention, it is preferable that the metal layer is separated from a side surface of the ridge portion, and the dielectric layer covers the entire surface of the metal layer and contacts the side surface of the ridge portion. . According to this nitride light emitting device, hydrogen in the semiconductor film is captured by the metal layer spaced from the side surface of the ridge portion. Therefore, a hydrogen concentration gradient that decreases toward the metal layer is formed in the semiconductor film.

The present invention relates to a method for fabricating a nitride light emitting device. The method includes: (a) a group III nitride semiconductor region having an active layer, a first region including a ridge portion, and a second region extending along the first region; and the group III nitride semiconductor region Forming a substrate product including a metal layer and a dielectric layer sequentially provided on the second region, and (b) forming the ridge portion of the first region of the group III nitride semiconductor region. Forming an electrode on the upper surface and the dielectric layer. The metal layer includes a region having a lattice defect density of 1 × 10 ¹¹ cm ⁻² or more, the electrode is in contact with the upper surface of the ridge portion, and the group III nitride semiconductor region is on the active layer. And the Group III nitride semiconductor region includes hydrogen and a p-type dopant.

According to this manufacturing method, the electrode is formed in contact with the upper surface of the ridge portion in the first region, and the metal layer is formed on the second region. This metal layer includes a region having a lattice defect density of 1 × 10 ¹¹ cm ⁻² or more, and the region can occlude hydrogen. Hydrogen that reaches the metal layer is trapped in the region. Since the metal layer is formed on the second region different from the ridge portion of the first region, hydrogen moving in the semiconductor is stored in the metal layer separated from the interface between the ridge portion of the first region and the electrode. It will be. Further, since the electrode makes contact with the upper surface of the ridge portion in the first region and the ridge has p-type conductivity, a current path from the electrode is provided. The electrode material is determined independently of the metal layer material.

  In the manufacturing method according to the present invention, the metal layer contacts the side surface of the ridge portion, and the dielectric layer covers the upper surface of the metal layer and contacts the side surface of the ridge portion. The dielectric layer ensures electrical insulation between the metal layer and the electrode layer.

  In the manufacturing method according to the present invention, the metal layer is in contact with an upper surface of the second region of the group III nitride semiconductor region, and the second region and the metal layer in the substrate product are in contact with each other. The contact area is preferably larger than the contact area between the upper surface of the ridge portion and the electrode in the substrate product. According to this manufacturing method, the contact area between the metal layer and the second region can be made larger than the contact area between the upper surface of the ridge portion and the electrode without being limited to the contact area between the electrode and the semiconductor layer.

  In the manufacturing method according to the present invention, the group III nitride semiconductor region may be doped with Mg. According to this manufacturing method, the metal layer can capture hydrogen liberated from Mg—H bonds in the p-type semiconductor region.

In the manufacturing method according to the present invention, it is preferable that the lattice defects included in the metal layer include at least one of point defects, dislocations, stacking faults, and aggregates of these defects. According to this nitride light-emitting device, the lattice defects can capture hydrogen by interacting with hydrogen. In the manufacturing method according to the present invention, the region of the metal layer preferably has a lattice defect density of 1 × 10 ¹⁵ cm ⁻² or less. According to this nitride light emitting device, when the lattice defect density is 1 × 10 ¹⁵ cm ⁻² or less, the deterioration of the metal layer due to the high defect density does not affect the device characteristics.

  In the manufacturing method according to the present invention, the substrate product includes a substrate made of a group III nitride and a group III nitride semiconductor layer grown on a main surface of the substrate, and the active layer includes the group III Grown on the group nitride semiconductor layer, the group III nitride semiconductor layer has n-type conductivity, and the active layer is provided between the group III nitride semiconductor layer and the group III nitride semiconductor region Can be done. In the manufacturing method according to the present invention, it is preferable that the main surface of the substrate is inclined at an angle in a range of 63 degrees to 80 degrees with respect to the c-axis of the group III nitride.

  In the manufacturing method according to the present invention, the dielectric layer is provided between the electrode and the metal layer, and the dielectric layer and the metal layer are deposited in a self-aligned manner with respect to the ridge portion. it can. The dielectric layer includes at least one of a silicon oxide film, silicon nitride, silicon oxynitride, hafnium oxide, tantalum oxide, a ferroelectric, and a polyimide organic material. According to this manufacturing method, since the dielectric layer is provided between the electrode and the metal layer, hydrogen in the metal layer does not reach the electrode through the dielectric layer.

  In the manufacturing method according to the present invention, the step of manufacturing a substrate product includes a group III nitride semiconductor film for a p-type cladding layer and a group III group for a p-type contact layer above the active layer. A step of growing a nitride semiconductor film to form an epitaxial substrate; a step of forming a mask for a lift-off method on a main surface of the epitaxial substrate; and the first and second III using the mask. Etching the group nitride semiconductor film to form the group III nitride semiconductor region, and using the mask to grow a metal film having a lattice defect on the group III nitride semiconductor region, or A step of growing a metal film, a step of introducing a lattice defect into the metal film, forming a metal layer having a lattice defect density larger than the lattice defect density of the metal film, and the mask A step of growing the dielectric layer on the metal layer you are, and removing the mask by a lift-off method, and a step of forming the substrate product. The lattice defects included in the metal layer include at least one of point defects, dislocations, stacking defects, and aggregates of these defects, the first group III nitride semiconductor film includes a p-type dopant, and the second group III The nitride semiconductor film includes a p-type dopant, the group III nitride semiconductor region includes the p-type cladding layer and the p-type contact layer, and the metal layer is in contact with an upper surface of the p-type cladding layer. Can do.

According to this manufacturing method, a step of growing a metal film having lattice defects on the group III nitride semiconductor region, or a process of introducing lattice defects into the metal film after the formation of the metal film, A metal layer having a lattice defect density greater than that of the metal film is formed. In this method, lattice defects for occlusion of hydrogen are formed during film formation. The lattice defects contained in the metal layer include at least one of point defects, dislocations, stacking faults, and aggregates of these defects. Further, the position of the ridge portion is defined using a mask for lift-off and etching, and films for the metal layer and the dielectric layer are deposited using this mask. After this deposition, by removing the mask, a metal layer and a dielectric layer having a lattice defect density of 1 × 10 ¹¹ cm ⁻² or more are formed in a self-aligned manner with respect to the ridge portion.

In the manufacturing method according to the present invention, the step of manufacturing a substrate product includes the step of forming a group III nitride semiconductor film for the p-type cladding layer and a group III group for the p-type contact layer on the active layer. A step of growing a nitride semiconductor film to form an epitaxial substrate; a step of forming a mask for a lift-off method on a main surface of the epitaxial substrate; and the first and second III using the mask. Etching a group nitride semiconductor film to form the group III nitride semiconductor region, and using the mask, the metal layer includes a region having a lattice defect density of 1 × 10 ¹¹ cm ⁻² or more. Growing a metal layer on the group III nitride semiconductor region, growing the dielectric layer on the metal layer using the mask, removing the mask by a lift-off method, substrate And a step of forming a product. The lattice defects included in the metal layer include at least one of point defects, dislocations, stacking defects, and aggregates of these defects, the first group III nitride semiconductor film includes a p-type dopant, and the second group III The nitride semiconductor film includes a p-type dopant, the group III nitride semiconductor region includes the p-type cladding layer and the p-type contact layer, and the metal layer is in contact with an upper surface of the p-type cladding layer. Can do.

According to this manufacturing method, a metal layer having a lattice defect density of 1 × 10 ¹¹ cm ⁻² or more is grown. In this manufacturing method, lattice defects for capturing hydrogen are formed during film formation. The lattice defects contained in the metal layer include at least one of point defects, dislocations, stacking faults, and aggregates of these defects. Further, the position of the ridge portion is defined using a mask for lift-off and etching, and films for the metal layer and the dielectric layer are deposited using this mask. After this deposition, by removing the mask, a metal layer and a dielectric layer having a lattice defect density higher than the above value are produced in a self-aligned manner with respect to the ridge portion.

  As described above, according to the present invention, a nitride light emitting device capable of improving the shortening of the device lifetime is provided. In addition, according to the present invention, there is provided a method for manufacturing a nitride light-emitting device that can improve the shortening of the device lifetime due to hydrogen migration.

FIG. 1 is a drawing schematically showing a structure of a nitride light emitting device according to the present embodiment. FIG. 2 is a drawing showing main steps in the manufacture of the semiconductor light emitting device according to the present embodiment. FIG. 3 is a drawing showing major steps in the manufacture of the semiconductor light emitting device according to the present embodiment. FIG. 4 is a drawing schematically showing main steps in the manufacture of the semiconductor light emitting device according to the present embodiment. FIG. 5 is a drawing schematically showing main steps in manufacturing the semiconductor light emitting device according to the present embodiment. FIG. 6 is a drawing schematically showing main steps in the manufacture of the semiconductor light emitting device according to the present embodiment. FIG. 7 is a drawing schematically showing main steps in the manufacture of the semiconductor light emitting device according to the present embodiment. FIG. 8 is a drawing schematically showing main steps in the manufacture of the semiconductor light emitting device according to the present embodiment. FIG. 9 is a drawing schematically showing the structure of the nitride light emitting device according to the present embodiment. FIG. 10 is a drawing showing main steps in the manufacture of the semiconductor light emitting device according to the present embodiment. FIG. 11 is a drawing showing main steps in the manufacture of the semiconductor light emitting device according to the present embodiment. FIG. 12 is a drawing schematically showing main steps in the manufacture of the semiconductor light emitting device according to the present embodiment. FIG. 13 is a drawing schematically showing main steps in the manufacture of the semiconductor light emitting device according to the present embodiment. FIG. 14 is a drawing schematically showing main steps in the manufacture of the semiconductor light emitting device according to the present embodiment. FIG. 15 is a drawing schematically showing main steps in the manufacture of the semiconductor light emitting device according to the present embodiment. FIG. 16 is a drawing schematically showing main steps in the manufacture of the semiconductor light emitting device according to the present embodiment.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, embodiments of the present invention relating to a nitride light emitting device and a method for manufacturing the nitride light emitting device will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals.

  (First Embodiment) FIG. 1 is a drawing schematically showing the structure of a nitride light emitting device according to the present embodiment. Although the structure of the nitride light emitting element has a structure suitable for a semiconductor laser, for example, this embodiment is not limited to the semiconductor laser. As shown in part (a) of FIG. 1, the nitride light emitting device 11 includes a group III nitride semiconductor region 13, an active layer 15, an electrode 17, a metal layer 19, and a dielectric layer 21. . As shown in FIG. 1B, the metal layer 19 and the dielectric layer 21 are included in the current guide region 23 including the insulating layer. The group III nitride semiconductor region 13 is provided above the active layer 15 and includes a first region 13a and a second region 13b. The second region 13b extends along the first region 13a. The first region 13a includes a ridge portion, and the ridge portion has p-type conductivity. The thickness T13a of the first region 13a is larger than the thickness T13b of the second region 13b. The group III nitride semiconductor region 13 contains a p-type dopant intentionally added, and also contains hydrogen that is contained in the film forming material and not intentionally added. The electrode 17 forms a contact JC1 with the upper surface 13c of the ridge portion of the first region 13a of the group III nitride semiconductor region 13. The active layer 15 is made of a group III nitride semiconductor. The metal layer 19 is provided on the second region 13 b of the group III nitride semiconductor region 13. Since the metal layer 19 is made of a material capable of forming a hydride, it functions as a hydrogen trapping layer. The dielectric layer 21 is provided on the metal layer 19. The current guide region 23 is located on the second region 13b and guides the current to the first region 13a having the ridge structure.

  According to the nitride light emitting device 11, the electrode 17 makes contact with the upper surface 13c of the ridge portion of the first region 13a, and the metal layer 19 is provided on the second region 13b. The metal layer 19 is made of a material capable of forming a hydride. The group III nitride semiconductor region 13 contains hydrogen, and hydrogen that has moved to reach the metal layer 19 according to environmental conditions is occluded in the metal layer 19. Since the dielectric layer 21 is provided on the metal layer 19, hydrogen cannot substantially move from the metal layer 19 to the dielectric layer 21 according to the amount of hydrogen in the metal layer 19. Since the metal layer 19 is provided on the second region 13b different from the ridge portion of the first region 13a, hydrogen moving in the semiconductor is separated from the interface between the ridge portion of the first region 13a and the electrode 17. It is stored in the metal layer 19. Furthermore, since the electrode 17 makes contact with the upper surface 13c of the ridge portion of the first region 13a and the ridge portion has p-type conductivity, a current path from the electrode 17 is provided. The material of the electrode 17 is determined independently of the material of the metal layer 19.

  In this embodiment, the electrode 17 forms not only a contact (ohmic contact) JC1 with the ridge structure upper surface 13c but also a junction JC2 with the main surface 23a of the current guide region 23. A pad electrode 18 is provided on the electrode 17. Referring to part (a) of FIG. 1, the pad electrode 18 is bonded to the upper surface of the dielectric layer 21.

  The nitride light emitting device 11 includes a group III nitride semiconductor region 25. The group III nitride semiconductor region 25 has a portion containing an intentionally added n-type dopant and has n-type conductivity.

The nitride light emitting device 11 includes a support base 27. The support base 27 can be made of, for example, a group III nitride. As this group III nitride, a gallium nitride based semiconductor such as GaN, AlGaN, InGaN, InAlGaN or AlN can be used, and In _X Al _Y Ga _1- XYN (0 ≦ X ≦ 1, 0 ≦ Y). <1) can be used. Further, the support base 27 can be made of, for example, InAlGaN, sapphire, SiC, or the like.

  Group III nitride semiconductor region 25 is provided on main surface 27 a of support base 27. The group III nitride semiconductor region 25 includes, for example, an n-type cladding layer, and the n-type cladding layer is made of, for example, an n-type group III nitride semiconductor, preferably an n-type gallium nitride semiconductor such as n-type AlGaN or n-type InAlGaN. Can do. An electrode 43 is provided on the back surface 27 b of the support base 27. When the electrode 43 is, for example, a cathode, the electrode 17 is, for example, an anode.

  A light emitting layer 29 is provided on the group III nitride semiconductor region 25. The light emitting layer 29 includes the active layer 15. If necessary, the light emitting layer 29 may include one or a plurality of semiconductor layers made of a group III nitride semiconductor, preferably a gallium nitride based semiconductor, between the active layer 15 and the group III nitride semiconductor region 25. For example, the semiconductor layer serves as the light guide layer 31. Further, the light emitting layer 29 includes one or a plurality of semiconductor layers made of a group III nitride semiconductor, preferably a gallium nitride based semiconductor, between the active layer 15 and the group III nitride semiconductor region 13 when necessary. The semiconductor layer functions as, for example, an electron block layer (eg, AlGaN) 33 or a light guide layer (eg, GaN, InGaN, InAlGaN) 35. The active layer 15 can include at least one well layer 15a, and the well layer 15a can be made of a group III nitride semiconductor containing indium, such as InGaN. The active layer 15 can include a barrier layer 15b. The barrier layer 15b can be made of a gallium nitride-based semiconductor such as GaN or InGaN, and the well layer and the barrier layer have an SQW or MQW structure. I can do it. The band gap of the barrier layer 15b is larger than the band gap of the well layer 15a. In the case of MQW, the well layers 15a and the barrier layers 15b are alternately arranged. The group III nitride semiconductor region 25, the light emitting layer 29 (active layer 15), and the group III nitride semiconductor region 13 are arranged in order in the normal direction of the major surface 27 a of the support base 27.

  In the nitride light emitting device 11, the main surface 27a of the support base 27 can be applied to any of a polar surface, a semipolar surface, and a nonpolar surface. In one embodiment of the nitride light emitting device 11, the main surface 27a of the support base 27 is inclined at an angle in the range of 63 degrees to 80 degrees with respect to the c-axis of the group III nitride of the main surface 27a. Can be. According to this nitride light emitting device, since it is semipolar and nonpolar, it is possible to suppress a decrease in light emission efficiency due to the piezo effect, and this is particularly effective in seeking to improve device characteristics at a blue-violet wavelength or longer.

  The group III nitride semiconductor region 13 is made of a p-type semiconductor, and can include, for example, a p-type cladding layer (eg, AlGaN, InAlGaN, etc.) 37 and a p-type contact layer (eg, GaN, AlGaN, InAlGaN, etc.) 39 Can be included. The group III nitride semiconductor region 13 can be doped with Mg. The metal layer 19 can capture hydrogen liberated from Mg—H bonds in the p-type semiconductor region.

  The metal layer 19 can include Ti, Mg, Mn, Zr, Ni, Ca, Nb, V, Pd, and an alloy composed of at least two of these elements. Metals and alloys containing these exemplary listed elements can be used for the metal layer 19. For example, the lower limit of the thickness of the metal layer 19 is estimated to be, for example, about 10 times the atomic radius of the elements constituting the metal layer 19, and the thickness of the film formation is stabilized. When the base is sufficiently flat, for example, when the metal layer 19 uses palladium (atomic radius: 0.14 nm), the lower limit of the thickness of the metal layer 19 is about 1 nm. From various estimates, the thickness of the metal layer 19 can be 10 angstroms (1.0 nm) or more.

  The metal layer 19 makes contact with the p-type semiconductor region of the second region 13b. Hydrogen liberated from the composite of the p-type dopant and hydrogen in the p-type semiconductor region is trapped in the metal layer. The metal layer 19 is in contact with the surface of the p-type semiconductor region. The surface roughness Ra of the surface of the p-type semiconductor region is preferably 3 nm or more. Since a large contact surface area can be secured, the removal efficiency of free hydrogen can be increased. Further, the surface roughness Ra of the surface of the p-type semiconductor region is preferably 20 nm or less, and the adhesion between the semiconductor layer and the metal layer can be ensured by adjusting the surface roughness during dry etching for ridge formation. The lower limit of the thickness of the metal layer 19 is larger than the surface roughness Ra of the surface of the p-type semiconductor region, and can be 1 nm or more in addition to the roughness value.

  The metal layer 19 is in contact with the upper surface 13d of the second region 13b of the group III nitride semiconductor region 13, and the contact area between the metal layer 19 and the second region 13b is that of the first region (ridge portion) 13a. The contact area between the upper surface 13c and the electrode 17 is preferably larger. According to the nitride light emitting device 11, the contact area between the metal layer 19 and the second region 13b is not limited to the contact area between the electrode 17 and the semiconductor surface 13c, and the contact area between the ridge portion upper surface 13c and the electrode 17 is not limited. Can be larger than the area. This contact area is specified, for example, by measuring dimensions using a scanning electron microscope or the like.

  The metal layer 19 can make contact with the side surface of the ridge portion of the first region 13a, and the dielectric layer 21 can cover the upper surface 19a of the metal layer 19 and can make contact with the side surface of the ridge portion of the first region 13a. Since the dielectric layer 21 covers the upper surface 19a of the metal layer 19, hydrogen can be efficiently transferred from the metal layer 19, and the transferred hydrogen can be effectively captured. Further, since the dielectric layer 21 makes contact with the side surface of the ridge portion, the metal layer 19 can be protected and the metal layer 19 can be electrically separated from the electrode 17. For example, the thickness of the dielectric layer 21 can be 1.0 nm or more, and the thickness of the dielectric layer 21 is flush with the ridge upper surface of the group III nitride semiconductor layer having the ridge on the upper surface of the dielectric layer. However, at least the metal layer 19 and the electrode can be insulated from each other.

  When there is a temperature history between room temperature and high temperature (temperature higher than room temperature) after performing the process of forming the hydrogen trap layer so as to be in contact with the upper surface 13d of the second region 13b of the group III nitride semiconductor region 13 Then, hydrogen trapped in various forms in the semiconductor is liberated. At this time, the hydrogen trapping layer takes incoming hydrogen to its saturation level, and volume expansion occurs in the hydrogen trapping layer. However, if there is a hydrogen concentration gradient in the hydrogen trapping layer, the hydrogen concentration gradient disappears in the layer. Thus, since the internal diffusion is performed, the entire metal layer absorbs the volume expansion, so that the device is not destroyed. When the temperature of the group III nitride semiconductor region 13 and the hydrogen trapping layer decreases, the element function is maintained in the group III nitride semiconductor region 13 because the amount of free hydrogen itself decreases according to the temperature. Therefore, the hydrogen trapping layer in contact with the upper surface 13d of the second region 13b is effective in suppressing the behavior of hydrogen related to long-term reliability as shown in the following description. It is also effective for hydrogen moving in the process.

The dielectric layer 21 is provided between the electrode 17 and the metal layer 19, and the dielectric layer 21 includes a silicon oxide film (for example, SiO ₂ ), silicon nitride (for example, Si ₃ N ₄ ), and silicon oxynitride (for example, It is preferable to include at least one of SiON), hafnium oxide (for example, HfO ₂ ), tantalum oxide (for example, Ta ₂ O ₅ ), ferroelectric (PZT, BST), polyimide-based organic material, and fluorine compound. According to the nitride light emitting device 11, since the dielectric layer 21 is provided between the electrode 17 and the metal layer 19, hydrogen in the metal layer 19 does not reach the electrode through the dielectric layer 21. For example, when an external voltage is applied to the dielectric layer 21 such as SiO _2, it is at least about 50 nm (assuming that the dielectric breakdown strength is 2 × 10 ⁶ V / cm) in order to exceed the withstand voltage of 10 volts or more.

The ferroelectric PZT is expressed as, for example, Pb (Zr, Ti) O ₃ , and the ferroelectric BST is expressed as Ba _0.8 Sr _0.2 TiO ₃ .

  As shown in part (b) of FIG. 1, the current guide region 23 can include a dielectric layer 21. The diffusion coefficient of hydrogen in the dielectric layer 21 is extremely smaller than the diffusion coefficient of hydrogen in the metal layer 19. The dielectric layer 21 has a higher resistivity than the metal layer 19, and more preferably has an insulating property. The thickness of at least one of the metal layer 19 and the dielectric layer 21 can be adjusted so that the total thickness of the metal layer 19 and the dielectric layer 21 matches the height of the ridge portion. If necessary, another dielectric layer can be added to the current guide region 23. For example, the material of the dielectric layer can be selected to make the adhesion between the dielectric layer and the electrode 17 better than the adhesion between the dielectric layer 21 and the electrode 17.

  In order to match the thickness of the current guide region 23 to the height of the ridge portion, the thickness of the metal layer 19 is smaller than the height of the ridge portion, and the thickness of the dielectric layer 21 is smaller than the height of the ridge portion.

  The metal layer 19 has an effect on hydrogen as follows. (1) Atomic or molecular free hydrogen remaining in the p-type semiconductor region in the semiconductor light emitting device 11 when the process for manufacturing the semiconductor light emitting device 11 is completed. When the p-type semiconductor region of the semiconductor light emitting device 11 is exposed in an atmosphere containing hydrogen in the manufacturing process, the hydrogen on the surface of the p-type semiconductor region is the amount of hydrogen dissolved through the exposed surface thermodynamically. Enters according to Sievert's law, which is proportional to the square root of the hydrogen partial pressure of the exposed atmosphere. (2) Atomic or molecular hydrogen that has been used for a long time after the semiconductor light-emitting element 11 has been distributed to the market and has been trapped at the trap site in the semiconductor light-emitting element 11 with its operation. This hydrogen is not hydrogen of the Mg—H complex that does not dissociate at the operating temperature, but is captured by crystal lattice defects such as impurity elements and dislocations that do not form a stable hydrogen complex. (3) Atomic hydrogen that enters the device from the outside of the device due to the environment in which the semiconductor light emitting device 11 is used after being distributed to the market. This hydrogen follows thermodynamically the Sievert's law, where the amount of hydrogen dissolved through the exposed surface in a high temperature atmosphere is proportional to the square root of the hydrogen partial pressure of the exposed atmosphere.

  The hydrogen remaining in the semiconductor light emitting element 11 is related to matters relating to the reliability of the element. Atomic hydrogen can be easily diffused and moved in the semiconductor, so in addition to deterioration in the electrode and at the electrode interface, it is trapped at the trap site at the interface of the semiconductor layer that constitutes the device, and atomic hydrogen is accumulated. Can form molecular hydrogen. This molecular hydrogen forms an interface defect to cause deterioration of the performance of the device and advance the deterioration of the performance.

  In order to capture hydrogen as described above, the metal layer 19 in contact with the semiconductor layer is useful. Further, the junction between the semiconductor region 13 and the metal layer 19 is different from that defined so as to satisfy the electrical characteristics such as the contact between the electrode 17 and the semiconductor surface 13c, and is wider than this contact. Suitable for hydrogen transfer. In addition, since the metal layer 19 contacts the semiconductor layer different from the ridge portion, hydrogen can be captured in a region different from the junction between the electrode and the semiconductor region.

  When the semiconductor light emitting device 11 is used over a long period of time or continuously operated, free hydrogen is generated in the semiconductor light emitting device 11 for various reasons. As can be understood from the above description, the metal layer 19 in direct contact with the semiconductor can reduce the amount of hydrogen moving in the semiconductor of the semiconductor light emitting device 11.

  2 and 3 are drawings showing main steps in the manufacture of the semiconductor light emitting device according to the present embodiment.

  In step S101, as shown in part (a) of FIG. 4, an epitaxial substrate E is produced using a growth furnace 10a. In the growth furnace 10a, a group III nitride semiconductor film is formed by, for example, metal organic vapor phase epitaxy. In this film formation, hydrogen resulting from the raw material for metal organic chemical vapor deposition is taken into the group III nitride semiconductor. In step S102, the substrate 51 is prepared. The substrate 51 can have a main surface 51a made of group III nitride, for example. In step S103, an n-conductive group III nitride semiconductor region 53 is grown on the main surface 51a of the substrate 51 while supplying an organic metal source and an n-type dopant gas to the growth reactor 10a. The group III nitride semiconductor region 53 includes one or more group III nitride semiconductor layers, and can include, for example, an n-type cladding layer. The n-type dopant can include, for example, silicon.

  In the subsequent process, the light emitting layer 55 is grown on the n-type group III nitride semiconductor region 53. In the production of the light emitting layer 55, in step S104, an n-side light guide layer is grown on the first conductivity type group III nitride semiconductor region 53 while supplying an organic metal source to the growth reactor 10a. In step S105, an active layer is grown on the light guide layer while supplying an organic metal raw material to the growth furnace 10a. In the growth of the active layer, the barrier layer is grown while supplying the organic metal source to the growth furnace 10a in step S106, and the well layer is grown while supplying the organic metal source to the growth reactor 10a in step S107. In the case of MQW, the growth of the barrier layer and the well layer is repeated as necessary. In steps S108 and S109, the electron block layer and the p-side light guide layer are grown while supplying the organic metal raw material to the growth reactor 10a.

  In step S110, the group III nitride semiconductor region 57 is grown on the main surface of the light emitting layer 55 while supplying the organic metal source and the p-type dopant gas to the growth reactor 10a. The group III nitride semiconductor region 57 includes hydrogen and a p-type dopant. In the formation of the p-type group III nitride semiconductor region 57, in step S111, a first group III nitride semiconductor film for the p-type cladding layer is grown on the main surface of the light-emitting layer 55. An epitaxial substrate E is formed by growing a second group III nitride semiconductor film for the p-type contact layer on the first group III nitride semiconductor film. The p-type dopant can include, for example, magnesium. In this case, these p-type semiconductor regions include a composite having an Mg—H bond.

  After the epitaxial substrate E is taken out from the growth furnace 10a, a substrate product is produced in step S113. For this purpose, in step S114, a mask for ridge formation is formed on the main surface of the epitaxial substrate E. In order to form this mask, first, as shown in FIG. 4B, a first metal mask film 59, a second metal mask film 61, and an insulating film are formed on the main surface of the epitaxial substrate E. After sequentially growing 63, a resist mask M1 that defines the width and orientation of the ridge structure is formed on the insulating film 63. The first metal mask film 59 is, for example, Mo or Ti, the second metal mask film 61 is, for example, Al, and the insulating film 63 is, for example, silicon oxide. Next, as shown in FIG. 5A, the first metal mask film 59, the second metal mask film 61, and the insulating film 63 are sequentially etched using the resist mask M1 to form a mask M2. To do. The mask M2 includes a first metal mask layer 59a, a second metal mask layer 61a, and an insulating layer 63a, and these layers 59a, 61a, 63a are arranged in order on the main surface of the epitaxial substrate E. After forming the mask M2, the resist mask M1 can be removed.

  In step S115, as shown in part (b) of FIG. 5, the p-type group III nitride semiconductor region 57 is dry-etched by the processing apparatus 10b using the mask M2, and the etched group III nitride semiconductor region is processed. 65 is formed. The group III nitride semiconductor region 65 includes a first region 65a and a second region 65b. The second region 65b is provided along the first region 65a extending in the direction of the axis Ax. The first region 65a includes a ridge portion, and the ridge portion has p-type conductivity. The thickness of the first region 65a is larger than the thickness of the second region 65b. The group III nitride semiconductor region 65 contains a p-type dopant intentionally added, and also contains an organic metal source or hydrogen resulting from the manufacturing process. The first regions 65a and the second regions 65b are alternately arranged in the extending direction of the main surface 51a of the substrate 51, and this arrangement is in a direction intersecting with the direction of the axis Ax. With an element width for one element, a single first region 65a including a ridge structure is provided between the second regions 65b. The mask M2 is left on the ridge portion upper surface 65c.

  In step S115, if necessary, the first metal mask layer 59a is selectively used with respect to the second metal mask layer 61a and the insulating layer 63a in the processing apparatus 10c, as shown in FIG. Etching is performed to form a first metal mask layer 59b. This etching can be performed by isotropic etching using, for example, RIE. The mask composed of the first metal mask layer 59b, the second metal mask layer 61a, and the insulating layer 63a will be continuously referred to as a mask M2.

  Subsequently, in step S116, as shown in part (b) of FIG. 6, the hydrogen trapping layer 67 is grown by the processing apparatus 10d using the mask M2. The hydrogen trapping layer 67 includes a first portion 67a grown on the mask M2 and a second portion 67b grown on the second region 65b of the group III nitride semiconductor region 65. The first portion 67a is separated from the second portion 67b by the height of the mask M2. The hydrogen trap layer 67 can include a metal layer capable of forming a hydride. The hydrogen trapping layer 67 can include Ti, Mg, Mn, Zr, Ni, Ca, Nb, V, Pd, and an alloy composed of at least two of these elements. Metals and alloys containing these exemplary enumerated elements can also be used for the hydrogen scavenging layer 67.

  In step S117, as shown in part (a) of FIG. 7, a dielectric layer 69 is grown by the processing apparatus 10e using the mask M2. Dielectric layer 69 includes a first portion 69a grown on mask M2 and a second portion 69b grown on second region 65b of group III nitride semiconductor region 65. The first portion 69a is separated from the second portion 69b by the thickness of the mask M2. For example, the thickness of the dielectric layer 69 can be 1.0 nm or more, and the thickness of the dielectric layer 69 is flush with the ridge upper surface of the group III nitride semiconductor layer having the ridge on the upper surface of the dielectric layer. However, at least the metal layer 19 and the electrode can be insulated from each other. The dielectric layer 69 can be, for example, a silicon oxide film, silicon nitride, silicon oxynitride, hafnium oxide, tantalum oxide, ferroelectric, or the like. For these film formations, for example, methods that are currently in general use, such as vacuum vapor deposition, sputtering vapor deposition, plasma PVD, and CVD, can be applied.

  The total thickness of the hydrogen capturing layer 67 and the dielectric layer 69 is preferably determined so as to match the height of the ridge portion. If necessary, after the dielectric layer 69 is grown, another dielectric layer can be further grown on the dielectric layer 69. In this embodiment, the total thickness of the hydrogen trapping layer 67, the dielectric layer 69, and the other dielectric layer is preferably determined so as to match the height of the ridge portion.

  After these steps S116 and S117, as shown in part (b) of FIG. 7, in step S118, the mask M2 is removed by the processing apparatus 10f by the lift-off method to produce the substrate product SP1. As a result, the portion 67a of the hydrogen capturing layer 67 and the portion 69a of the dielectric layer 69, which are sequentially provided on the mask M2, disappear. Substrate product SP1 includes a portion 67b of hydrogen trapping layer 67 (referred to as “hydrogen trapping layer 67b” in the following description) and dielectric layer 69 provided in sequence on second region 65b of group III nitride semiconductor region 65. Portion 69b (referred to as “dielectric layer 69b” in the following description).

  According to this manufacturing method, the position of the ridge portion is defined by using the mask M2 for lift-off and etching, and the film for the hydrogen capturing layer 67b and the dielectric layer 69b are used by using the mask M2. Film deposition is performed. After this deposition, the mask M2 is removed to form a dielectric layer. Therefore, the hydrogen capturing layer 67b and the dielectric layer are formed in a self-aligned manner with respect to the ridge portion. The hydrogen trapping layer 67b and the dielectric layer constitute a current guide region.

  In the production by the lift-off method, the dielectric layer 69 is formed of a silicon-based inorganic compound such as a silicon oxide film, silicon nitride, and silicon oxynitride, a metal oxide such as hafnium oxide and tantalum oxide, and a strong layer as described above. It is preferable to include at least one of dielectrics. Further, a polyimide organic material can be used as the dielectric layer 69. In this case, for example, a sputter deposition method can be used.

  In step S119, as shown in FIG. 8A, the anode electrode 71 forming the junction C1 is formed on the upper surface 65c of the ridge portion of the first region 65a of the group III nitride semiconductor region 65. As the anode electrode 71, a single metal such as Au, Ni, Pd, In, Pt, Al, Sn, or an alloy thereof can be used. Further, as shown in part (b) of FIG. 8, a cathode electrode can be formed on the electrode 71 and the pad electrode 73 provided on the current guide region and the back surface 51 b of the substrate 51. According to this manufacturing method, since the dielectric layer 69 is provided between the electrodes 71 and 73 and the metal layer 67, after the dielectric layer 69 is manufactured, hydrogen in the metal layer 67 is dielectrically changed during the manufacturing process. It does not reach the electrode through the body layer 69.

  According to this manufacturing method, it is possible to form the electrode 71 in contact with the ridge portion upper surface 65c of the first region 65a, while providing it on the second region 65b of the group III nitride semiconductor region 65 in the substrate product. A current guide region can be formed on the hydrogen trapping layer 67b by using the insulating dielectric layer 69b. The hydrogen trapping layer 67b has a crystal defect capable of trapping hydrogen liberated at least in an atomic or molecular state. The group III nitride semiconductor region 65 contains hydrogen, and the hydrogen trap layer 67b forms a junction C2 with the second region 65b different from the ridge portion of the first region 65a. Therefore, the moving hydrogen is captured by the hydrogen capturing layer 67b. A dielectric layer 69b is provided to form a junction C3 with the hydrogen trapping layer 67b. Since the hydrogen trap layer 67b is provided on the second region 65b different from the ridge portion of the first region 65a, the moving hydrogen is separated from the junction (interface) C1 between the upper surface 65c of the ridge portion and the electrode 73. It is attracted to 67b and stored. Furthermore, since the electrode 71 is in contact with the ridge portion upper surface 65c and the ridge has p-type conductivity, a current path from the electrode 71 is provided. The material of the electrode 71 is determined independently of the material of the hydrogen trapping layer 67b. The total contact area between the second region 65 a and the hydrogen trapping layer 67 b is larger than the total contact area between the ridge portion upper surface 65 c and the electrode 71.

  As described above, by providing a hydrogen trapping metal under the insulating dielectric layer, hydrogen desorbed from the Mg—H composite formed in the p-type cladding layer in the long-term CW oscillation, and the lower semiconductor layer The hydrogen trap metal below the dielectric layer absorbs atomic hydrogen derived from hydrogen diffusion from Furthermore, due to the formation of a concentration distribution inside the hydrogen trapping metal caused by hydrogen trapping in the hydrogen trapping metal, atomic hydrogen further moves in the hydrogen trapping metal. Hydrogen atom inflow into the p-type contact layer can be suppressed for a longer period of time, the recombination probability between magnesium and hydrogen can be reduced, and stable p-type ohmic contact can be maintained. As a result, the device life is extended.

(Second Embodiment) FIG. 9 schematically shows the structure of a nitride light-emitting device according to this embodiment. Although the structure of the nitride light emitting element has a structure suitable for a semiconductor laser, for example, this embodiment is not limited to the semiconductor laser. As shown in part (a) of FIG. 9, the nitride light emitting device 11-1 includes a group III nitride semiconductor region 13-1, an active layer 15-1, an electrode 17-1, and a metal layer 19-. 1 and a dielectric layer 21-1. As shown in FIG. 9B and FIG. 9C, the metal layer 19-1 and the dielectric layer 21-1 are included in the current guide region 23-1 including an insulating layer. The group III nitride semiconductor region 13-1 is provided above the active layer 15-1, and includes a first region 13a-1 and a second region 13b-1. The second region 13b-1 extends along the first region 13a-1. The first region 13a-1 includes a ridge portion, and the ridge portion has p-type conductivity. The thickness T13a-1 of the first region 13a-1 is larger than the thickness T13b-1 of the second region 13b-1. The group III nitride semiconductor region 13-1 includes a p-type dopant that is intentionally added, and also includes hydrogen that is included in the film-forming raw material and is not intentionally added. The electrode 17-1 forms a contact JC1-1 with the upper surface 13c-1 of the ridge portion of the first region 13a-1 of the group III nitride semiconductor region 13-1. The active layer 15-1 is made of a group III nitride semiconductor. The metal layer 19-1 is provided on the second region 13b-1 of the group III nitride semiconductor region 13-1. The metal layer 19-1 includes a region having a high defect density, and the lattice defects can capture hydrogen. Therefore, the metal layer 19-1 can serve as a layer for hydrogen capture. The metal layer 19-1 preferably includes a region having a lattice defect density of 1 × 10 ¹¹ cm ⁻² or more, for example. Such a metal layer 19-1 is made of a material capable of forming a hydride. Further, the dielectric layer 21-1 is provided on the metal layer 19. The current guide region 23-1 is located on the second region 13b-1, and guides the current to the first region 13a-1 having the ridge structure. As shown in FIG. 9B, the side end of the metal layer 19-1 can be in contact with the side surface of the ridge structure. Alternatively, as shown in FIG. 9C, the side end of the metal layer 19-1 can be separated from the side surface of the ridge structure.

According to the nitride light emitting device 11-1, the electrode 17-1 is in contact with the upper surface 13c-1 of the ridge portion of the first region 13a-1, and the metal layer 19-1 is on the second region 13b-1. Is provided. The metal layer 19-1 includes a region having a lattice defect density of 1 × 10 ¹¹ cm ⁻² or more. The group III nitride semiconductor region 13-1 contains hydrogen. When the group III nitride semiconductor region 13-1 moves and moves according to environmental conditions and reaches the metal layer 19-1, the high-defect region (1 × Occluded in a region having a lattice defect density of 10 ¹¹ cm ⁻² or more. Since the dielectric layer 21-1 is provided on the metal layer 19-1, hydrogen cannot substantially move from the metal layer 19-1 to the dielectric layer 21. Since the metal layer 19-1 is provided on the second region 13b-1 different from the ridge portion of the first region 13a-1, the hydrogen moving through the semiconductor is transferred to the ridge portion of the first region 13a-1 and the electrode 17. -1 stored in the metal layer 19-1 spaced from the interface with -1. Furthermore, since the electrode 17-1 is in contact with the upper surface 13c-1 of the ridge portion of the first region 13a-1 and the ridge portion has p-type conductivity, a current path from the electrode 17-1 is provided. The material of the electrode 17-1 is determined independently of the material of the metal layer 19-1.

Moreover, it is preferable that at least a part of the region in the metal layer 19-1 has a lattice defect density of 1 × 10 ¹⁵ cm ⁻² or less. When the lattice defect density is not more than the above value, the deterioration of the metal layer due to the high defect density does not affect the device characteristics.

  In this embodiment, the electrode 17-1 not only makes contact JC1-1 (ohmic contact) with the ridge structure upper surface 13c-1, but also has a junction JC2-1 on the main surface 23a-1 of the current guide region 23-1. Make it. A pad electrode 18-1 is provided on the electrode 17-1. Referring to FIG. 9A, the pad electrode 18-1 is bonded to the upper surface of the dielectric layer 21-1.

  The nitride light emitting device 11-1 includes a group III nitride semiconductor region 25-1. Group III nitride semiconductor region 25-1 has a portion containing an intentionally added n-type dopant and has n-type conductivity.

The nitride light emitting device 11-1 includes a support base 27-1. The support base 27-1 can be made of, for example, a group III nitride. As the group III nitride, a gallium nitride semiconductor such as GaN, AlGaN, InGaN, or InAlGaN, or AlN can be used, and In _X Al _Y Ga _1- XYN (0 ≦ X ≦ 1, 0 ≦ Y). <1) can be used. Further, the support base 27 can be made of, for example, InAlGaN, sapphire, SiC, or the like.

  Group III nitride semiconductor region 25-1 is provided on main surface 27a-1 of support base 27-1. The group III nitride semiconductor region 25-1 includes, for example, an n-type cladding layer, and the n-type cladding layer is made of, for example, an n-type group III nitride semiconductor, preferably an n-type gallium nitride semiconductor such as n-type AlGaN or n-type InAlGaN. Can be. An electrode 43-1 is provided on the back surface 27b-1 of the support base 27-1. When the electrode 43-1 is, for example, a cathode, the electrode 17-1 is, for example, an anode.

  A light emitting layer 29-1 is provided on the group III nitride semiconductor region 25-1. The light emitting layer 29-1 includes an active layer 15-1. If necessary, the light emitting layer 29-1 includes one or a plurality of group III nitride semiconductor layers, preferably a gallium nitride based semiconductor, between the active layer 15-1 and the group III nitride semiconductor region 25-1. The semiconductor layer serves as the light guide layer 31-1, for example. In addition, the light emitting layer 29-1 is formed of a group III nitride semiconductor layer, preferably a gallium nitride semiconductor, between the active layer 15-1 and the group III nitride semiconductor region 13-1, if necessary. Alternatively, a plurality of semiconductor layers can be included, and the semiconductor layer functions as, for example, an electron block layer 33-1 (for example, AlGaN) or a light guide layer 35-1 (for example, GaN, InGaN, InAlGaN). The active layer 15-1 can include at least one well layer 15a-1, and the well layer 15a-1 can be made of a group III nitride semiconductor containing indium, such as InGaN. Further, the active layer 15-1 can include a barrier layer 15b-1, and the barrier layer 15b-1 can be made of a gallium nitride-based semiconductor, for example, GaN, InGaN, or the like. The band gap of the barrier layer 15b-1 that can take the MQW structure is larger than the band gap of the well layer 15a-1, and in the case of MQW, the well layer 15a-1 and the barrier layer 15b-1 are alternately arranged. . The group III nitride semiconductor region 25, the light emitting layer 29-1 (active layer 15-1), and the group III nitride semiconductor region 13-1 are sequentially arranged in the normal direction of the main surface 27a-1 of the support base 27-1. Has been.

  In the nitride light emitting device 11-1, the main surface 27a-1 of the support base 27-1 can be applied to any of a polar surface, a semipolar surface, and a nonpolar surface of a gallium nitride semiconductor, for example. Further, in one embodiment of the nitride light emitting device 11-1, the main surface 27a-1 of the support base 27-1 is 63 degrees or more and 80 degrees or less with respect to the c-axis of the group III nitride of the main surface 27a-1. Can be inclined at an angle in the range of. According to this nitride light emitting device, since it is semipolar and nonpolar, it is possible to suppress a decrease in light emission efficiency due to the piezo effect, and this is particularly effective in seeking to improve device characteristics at a blue-violet wavelength or longer.

  The group III nitride semiconductor region 13-1 is made of a p-type semiconductor, and can include, for example, a p-type cladding layer 37-1 (eg, AlGaN, InAlGaN, etc.), and a p-type contact layer 39-1 (eg, GaN). , AlGaN, InAlGaN, etc.). The group III nitride semiconductor region 13-1 can be doped with Mg. The metal layer 19-1 can capture hydrogen liberated from Mg—H bonds in the p-type semiconductor region.

In the nitride light emitting device 11-1, it is preferable that the lattice defects contained in the metal layer 19-1 include at least one of point defects, dislocations, stacking faults, and aggregates of these defects. Since the lattice defect has lattice strain, it interacts with free H +. The amount of strain caused by lattice defects depends on the metal species (constituent atom size), the defect species (strain size), the defect density, and the like. The lattice defects can capture hydrogen by interacting with atomic hydrogen. The density of these types of lattice defects is preferably 1 × 10 ¹¹ cm ⁻² or more in a part or the whole of the metal layer 19-1. Such a lattice defect does not cause deterioration of the metal layer in a semiconductor in which free hydrogen exists. The density of lattice defects is preferably up to about 1.5 times, for example, 1 × 10 ¹¹ cm ⁻² in a part or all of the metal layer 19-1. This is because the lattice strain of the metal layer becomes too large if it is more than this, so that there is a possibility that the group III nitride semiconductor layer in contact therewith may be macro-deformed. The density of lattice defects is preferably up to about 1.3 times 1 × 10 ¹¹ cm ⁻² in a part or the whole of the metal layer 19-1. This is because peeling may occur at the connection end face with the group III nitride semiconductor layer in contact therewith. The lattice defect density can be estimated by a method such as a thin film X-ray diffraction method, a TEM, or an X-ray topography method for a sample manufactured simultaneously with a product under a predetermined condition.

Moreover, it is preferable that the density of a lattice defect has a lattice defect density of 1 * 10 ^{< 15} > cm ^<-2> or less, for example in part or whole of the metal layer 19-1. When the lattice defect density is not more than the above value, the deterioration of the metal layer due to the high defect density does not affect the device characteristics.

  As a material of the metal layer 19-1, a metal that does not easily form a compound with a semiconductor with which the metal layer 19-1 is in contact, or a metal that does not have a large difference in thermal expansion coefficient between the semiconductor and the metal layer 19-1 can be applied. . The metal layer 19-1 is made of, for example, Al, Mo, W, Ta, Au, Ge, Cr, Fe, Ti, Mg, Mn, Zr, Ni, Ca, Nb, V, Pd and at least two of these elements. Can be included. Metals and alloys containing these exemplary listed elements can be used for the metal layer 19-1. For example, the lower limit of the thickness of the metal layer 19-1 is estimated to be, for example, about 10 times the atomic radius of the elements constituting the metal layer 19, and the film formation structure is stabilized by this thickness. When the base is sufficiently flat, for example, when the metal layer 19-1 uses palladium (atomic radius: 0.14 nm), the lower limit of the thickness of the metal layer 19-1 is about 1 nm. In consideration of other technical matters, the thickness of the metal layer 19-1 can be 1 nm or more, and the upper limit thickness of the metal layer 19-1 can be reduced by forming a dielectric layer on the metal layer. The thickness can be designed to ensure electrical insulation from the electrode layer.

  The metal layer 19-1 is in contact with the p-type semiconductor region of the second region 13b-1. Hydrogen liberated from the composite of the p-type dopant and hydrogen in the p-type semiconductor region is trapped in the metal layer. The metal layer 19-1 is in contact with the surface of the p-type semiconductor region. The surface roughness Ra of the surface of the p-type semiconductor region is preferably 3 nm or more. Since a large contact surface area can be secured, the removal efficiency of free hydrogen can be increased. Further, the surface roughness Ra of the surface of the p-type semiconductor region is preferably 20 nm or less, and the adhesion between the semiconductor layer and the metal layer can be ensured by adjusting the surface roughness during dry etching for ridge formation. The lower limit of the thickness of the metal layer 19-1 is larger than the surface roughness Ra of the p-type semiconductor region surface, and can be 1 nm or more in addition to the roughness value.

  The metal layer 19-1 is in contact with the upper surface 13d-1 of the second region 13b-1 of the group III nitride semiconductor region 13-1, and the metal layer 19-1 and the second region 13b-1 are in contact with each other. The contact area is preferably larger than the contact area between the upper surface 13c-1 of the first region 13a-1 (ridge portion) and the electrode 17-1. According to the nitride light emitting device 11-1, the contact area between the metal layer 19-1 and the second region 13b-1 is not limited to the contact area between the electrode 17-1 and the semiconductor surface 13c-1. The contact area between the ridge portion upper surface 13c-1 and the electrode 17-1 can be made larger. This contact area is specified, for example, by measuring dimensions using a scanning electron microscope or the like.

  As shown in FIG. 9B, the metal layer 19-1 is in contact with the ridge side surface of the first region 13a-1, and the dielectric layer 21-1 is the upper surface 19a of the metal layer 19-1. -1 can be covered and the ridge portion side surface of the first region 13a-1 can be contacted. Since the dielectric layer 21-1 covers the upper surface 19a-1 of the metal layer 19-1, it is possible to effectively capture the transferred hydrogen. In addition, since the dielectric layer 21-1 is in contact with the side surface of the ridge portion, the metal layer 19-1 can be protected, and the metal layer 19-1 can be electrically separated from the electrode 17-1. For example, the thickness of the dielectric layer 21-1 can be 1.0 nm or more, and the thickness of the dielectric layer 21-1 is the ridge of the group III nitride semiconductor layer having the top surface of the dielectric layer having a ridge. The upper surface is preferably flush with the upper surface, but may have a thickness at which the metal layer 19-1 and the electrode are insulated.

  Between the room temperature and the high temperature (temperature higher than room temperature) after performing the process of forming the metal layer so as to be in contact with the upper surface 13d-1 of the second region 13b-1 of the group III nitride semiconductor region 13-1. When there is a temperature history, hydrogen trapped in various forms in the semiconductor is liberated. At this time, the metal layer takes incoming hydrogen to its saturation level. Further, when there is a hydrogen concentration gradient in the metal layer, hydrogen diffuses. Even if the temperature of the group III nitride semiconductor region 13-1 and the metal layer is lowered, the incorporated hydrogen is not released again. Therefore, the metal layer in contact with the upper surface 13d-1 of the second region 13b-1 is effective in suppressing the behavior of hydrogen related to long-term reliability as shown in the following description. It is also effective for hydrogen that moves in the manufacturing process of the element 11-1.

The dielectric layer 21-1 is provided between the electrode 17-1 and the metal layer 19-1, and the dielectric layer 21-1 includes a silicon oxide film (for example, SiO ₂ ) and a silicon nitride (for example, Si ₃ N _4). ), silicon oxynitride (e.g. SiON), hafnium oxide (e.g. _HfO 2), tantalum oxide (e.g., _Ta 2 _O 5), ferroelectric (PZT, BST), at least one of polyimide organics and fluorine compounds Is preferably included. According to the nitride light emitting device 11-1, since the dielectric layer 21-1 is provided between the electrode 17-1 and the metal layer 19-1, the hydrogen in the metal layer 19-1 is changed to the dielectric layer 21. -1 does not reach the electrode. For example, when the external voltage to the dielectric layer 21-1 such SiO ₂ is applied, in order to exceed 10 volts or more dielectric strength, at least 50nm approximately (dielectric breakdown strength and assumptions 2 × ¹⁰ 6 V / cm) is there.

The ferroelectric PZT is expressed as, for example, Pb (Zr, Ti) O ₃ , and the ferroelectric BST is expressed as, for example, Ba _0.8 Sr _0.2 TiO ₃ .

  As shown in part (b) and part (c) of FIG. 9, the current guide region 23-1 can include a dielectric layer 21-1. The diffusion coefficient of hydrogen in the dielectric layer 21-1 is extremely smaller than the diffusion coefficient of hydrogen in the metal layer 19-1. The dielectric layer 21-1 has a higher resistivity than the metal layer 19-1, and more preferably has an insulating property. Adjusting the thickness of at least one of the metal layer 19-1 and the dielectric layer 21-1 so that the total thickness of the metal layer 19-1 and the dielectric layer 21-1 matches the height of the ridge portion. Can do. If necessary, another dielectric layer can be added to the current guide region 23-1. For example, the material of the dielectric layer may be selected so that the adhesion between the dielectric layer and the electrode 17-1 is better than the adhesion between the dielectric layer 21-1 and the electrode 17-1. it can.

  In order to match the thickness of the current guide region 23-1 to the height of the ridge portion, the thickness of the metal layer 19-1 is smaller than the height of the ridge portion, and the thickness of the dielectric layer 21-1 is equal to the ridge portion. Less than the height of

The metal layer 19-1 has an effect on the following hydrogen.
(1) Atomic or molecular free hydrogen remaining in the p-type semiconductor region in the semiconductor light emitting device 11-1 when the process for manufacturing the semiconductor light emitting device 11-1 is completed.
(2) Atomic or molecular hydrogen that has been used for a long time after the semiconductor light emitting device 11-1 is distributed in the market and is trapped in the trap site in the semiconductor light emitting device 11-1 with its operation. This hydrogen is not Mg-H complex hydrogen that does not dissociate at the operating temperature. For example, in semiconductor light emitting devices, the lattice defects in the semiconductor layer have an adverse effect on the light emission characteristics, so the density of the remaining lattice defects is reduced as much as possible. It is weakly trapped by a lattice strain field such as an impurity element that does not form a stable hydrogen complex or a small amount of dislocations.
(3) Atomic hydrogen that enters the device from the outside of the device due to the environment in which the semiconductor light emitting device 11-1 is used after being distributed to the market. This hydrogen follows the Sievert's law where the amount of hydrogen dissolved through the exposed surface in a thermodynamic atmosphere is proportional to the square root of the hydrogen partial pressure of the exposed atmosphere.

  The hydrogen remaining in the semiconductor light emitting device 11-1 is related to the matter relating to the reliability of the device. Atomic hydrogen can be easily diffused and moved in the semiconductor, so that in addition to deterioration in the electrode and at the electrode interface, it is trapped at the trap site at the interface of the semiconductor layer that constitutes the device, and atomic hydrogen is accumulated. To form molecular hydrogen. This molecular hydrogen forms an interface defect to cause deterioration of the performance of the device and advance the deterioration of the performance.

  In order to capture hydrogen as described above, the metal layer 19-1 in contact with the semiconductor layer is useful. In addition, the junction between the semiconductor region 13-1 and the metal layer 19-1 is different from that defined so as to satisfy the electrical characteristics such as the contact between the electrode 17-1 and the semiconductor surface 13c-1. It is wider than that and suitable for the transfer of hydrogen from a semiconductor. Further, since the metal layer 19-1 is in contact with the semiconductor layer different from the ridge portion, hydrogen can be captured in a region different from the junction between the electrode and the semiconductor region.

  When the semiconductor light emitting device 11-1 is used for a long period of time or continuously operated, free hydrogen is generated in the semiconductor light emitting device 11-1 for various reasons. As can be understood from the above description, the metal layer 19-1 that is in direct contact with the semiconductor can reduce the amount of hydrogen that moves in the semiconductor of the semiconductor light emitting device 11-1.

  10 and 11 are drawings showing main steps in manufacturing the semiconductor light emitting device according to the present embodiment.

  In step S101-1, as shown in part (a) of FIG. 12, an epitaxial substrate E is produced using a growth furnace 10a-1. In the growth furnace 10a-1, a group III nitride semiconductor film is formed, for example, by metal organic vapor phase epitaxy. In this film formation, hydrogen resulting from the raw material for metal organic chemical vapor deposition is taken into the group III nitride semiconductor. In step S102-1, a substrate 51-1 is prepared. The substrate 51-1 can have a main surface 51a-1 made of, for example, a group III nitride. In step S103-1, an n-conducting group III nitride semiconductor region 53-1 is grown on the main surface 51a-1 of the substrate 51-1, while supplying an organic metal source and an n-type dopant gas to the growth reactor 10a. To do. The group III nitride semiconductor region 53-1 includes one or a plurality of group III nitride semiconductor layers, and may include, for example, an n-type cladding layer. The n-type dopant can include, for example, silicon.

  In the subsequent step, the light emitting layer 55-1 is grown on the n-type group III nitride semiconductor region 53-1. In the production of the light emitting layer 55-1, in Step S104-1, the n-side light guide layer is placed on the first conductivity type group III nitride semiconductor region 53-1, while supplying the organic metal raw material to the growth reactor 10a-1. grow up. In step S105-1, an active layer is grown on the light guide layer while supplying an organic metal raw material to the growth furnace 10a-1. In the growth of the active layer, the barrier layer is grown while supplying the organic metal source to the growth reactor 10a-1 in step S106-1, and the well is supplied while supplying the organic metal source to the growth reactor 10a-1 in step S107-1. Grow layers. In the case of MQW, the growth of the barrier layer and the well layer is repeated as necessary. In steps S108-1 and S109-1, the electron block layer and the p-side light guide layer are grown while supplying the organic metal raw material to the growth reactor 10a-1.

  In step S110-1, the group III nitride semiconductor region 57-1 is grown on the main surface of the light emitting layer 55-1 while supplying the organic metal raw material and the p-type dopant gas to the growth reactor 10a-1. The group III nitride semiconductor region 57-1 includes hydrogen and a p-type dopant. In forming the p-type group III nitride semiconductor region 57-1, in step S111-1, a first group III nitride semiconductor film for the p-type cladding layer is grown on the main surface of the light emitting layer 55-1. At the same time, in Step 112-1, a Group III nitride semiconductor film for the p-type contact layer is grown on the Group III nitride semiconductor film to form an epitaxial substrate E-1. The p-type dopant can include, for example, magnesium. In this case, these p-type semiconductor regions include a composite having an Mg—H bond.

  After the epitaxial substrate E-1 is taken out from the growth furnace 10a-1, a substrate product is produced in step S113-1 according to the process flow shown in part (a) of FIGS. For this purpose, in step S114-1, a mask for forming a ridge is formed on the main surface of the epitaxial substrate E-1. In order to form this mask, first, as shown in FIG. 12B, a first metal mask film 59-1, a second metal mask film are formed on the main surface of the epitaxial substrate E-1. After sequentially growing 61-1 and the insulating film 63-1, a resist mask M1-1 defining the width and direction of the ridge structure is formed on the insulating film 63-1. The first metal mask film 59-1 is, for example, Mo or Ti, the second metal mask film 61-1 is, for example, Al, and the insulating film 63-1 is, for example, silicon oxide. Next, as shown in FIG. 13A, the first metal mask film 59-1, the second metal mask film 61-1 and the insulating film 63-1 are sequentially formed using the resist mask M1-1. Etching is performed to form a mask M2-1. The mask M2-1 includes a first metal mask layer 59a-1, a second metal mask layer 61a-1, and an insulating layer 63a-1, and these layers 59a-1, 61a-1, and 63a-1 are epitaxial. It arranges in order on the main surface of the board | substrate E-1. After forming the mask M2-1, the resist mask M1-1 can be removed.

  In step S115-1, as shown in part (b) of FIG. 13, after the substrate to be processed is placed on the stage 12b-1 of the processing apparatus 10b-1, the p-type group III is used using the mask M2-1. The nitride semiconductor region 57-1 is dry-etched by the processing apparatus 10b-1 to form an etched group III nitride semiconductor region 65-1. The group III nitride semiconductor region 65-1 includes a first region 65a-1 and a second region 65b-1. The second region 65b-1 is provided along the first region 65a-1 extending in the direction of the axis Ax-1. The first region 65a-1 includes a ridge portion, and the ridge portion has p-type conductivity. The thickness of the first region 65a-1 is larger than the thickness of the second region 65b-1. The group III nitride semiconductor region 65-1 contains a p-type dopant intentionally added, and also contains hydrogen derived from an organic metal source. In the extending direction of the main surface 51a-1 of the substrate 51-1, the first regions 65a-1 and the second regions 65b-1 are alternately arranged, and this arrangement intersects the direction of the axis Ax-1. It becomes. With an element width of one element, a single first region 65a-1 including a ridge structure is provided between the second regions 65b-1. The mask M2-1 is left on the ridge portion upper surface 65c-1.

  In step S115-1, if necessary, after the substrate to be processed is placed on the stage 12c-1 of the processing apparatus 10c-1, as shown in FIG. One metal mask layer 59a-1 is selectively etched with respect to the second metal mask layer 61a-1 and the insulating layer 63a-1 to form a small-width metal mask layer 59b-1. This etching can be performed by isotropic etching using, for example, RIE. The mask composed of the first metal mask layer 59b-1, the second metal mask layer 61a-1, and the insulating layer 63a-1 will be referred to as a mask M2-1.

Subsequently, in step S116-1 shown in part (a) of FIG. 11, after the substrate to be processed is placed on the stage 12d-1 of the processing apparatus 10d-1, as shown in part (b) of FIG. The metal layer 67-1 is grown by the processing apparatus 10d-1 using the mask M2-1. The lattice defects contained in the metal layer 67-1 preferably include at least one of point defects, dislocations, stacking faults, and aggregates of these defects. Since the lattice defect has lattice strain, it interacts with free H +. The amount of strain caused by lattice defects depends on the metal species (constituent atom size), the defect species (strain size), the defect density, and the like. The lattice defects can capture hydrogen by interacting with atomic hydrogen. The density of these types of lattice defects is preferably 1 × 10 ¹¹ cm ⁻² or more in a part or the whole of the metal layer 67-1. Such a lattice defect does not cause deterioration of the metal layer in a semiconductor in which free hydrogen exists. The upper limit of the density of lattice defects is preferably about 1.5 times 1 × 10 ¹¹ cm ⁻² in a part or the whole of the metal layer 67-1. This is because the lattice strain of the metal layer becomes too large if it is more than this, so that there is a possibility that the group III nitride semiconductor layer in contact therewith may be macro-deformed. The upper limit of the density of lattice defects is preferably about 1.3 times 1 × 10 ¹¹ cm ⁻² in a part or the whole of the metal layer 67-1. This is because peeling may occur at the connection end face with the group III nitride semiconductor layer in contact therewith. Moreover, it is preferable that the density of a lattice defect has a lattice defect density of 1 × 10 ¹⁵ cm ⁻² or less, for example, in a part or the whole of the metal layer 67-1. When the lattice defect density is not more than the above value, the deterioration of the metal layer due to the high defect density does not affect the device characteristics. In addition, by introducing lattice defects having a desired density when forming the metal layer 67-1 rather than introducing lattice defects having a desired density after forming the metal layer 67-1, it is possible to reduce the number of lattice defects. There is an advantage that costs can be reduced.

The metal layer 67-1 can be produced, for example, by a metal quenching method. A film formation method in which deposited particles have a relatively high kinetic energy, such as a film formation in a physical vapor deposition method such as a resistance heating method, an electron beam heating method, or a sputtering method, is used for forming the metal layer 67-1. Is preferred. Referring to part (b) of FIG. 14, the substrate product SP0-1 is mounted on the stage 12d-1 of the processing apparatus 10d-1, and the substrate product SP0-1 is controlled by temperature control of the stage 12-1. Adjust the temperature. The stage temperature is, for example, room temperature (10 degrees Celsius) or less, and preferably the stage temperature is 0 degrees Celsius or less. By adjusting the temperature of the stage, the deposited particles are rapidly cooled on the surface of the substrate product, and distortion is generated due to a rapid temperature drop during deposition. Due to this strain generation, high-density lattice defects are formed in the metal deposit, and finally a metal layer 67-1 having a lattice defect density of 1 × 10 ¹¹ cm ⁻² or more can be formed. According to the inventor's knowledge, this lattice defect density does not exceed 1 × 10 ¹⁵ cm ⁻² , for example. Therefore, the deterioration of the metal layer due to the lattice defect density exceeding the above value does not affect the device characteristics.

  Alternatively, the metal layer 67-1 can be formed by performing vapor deposition for film formation and gas irradiation for cooling without adjusting the temperature of the stage 12d-1. If necessary, vapor deposition and gas irradiation can be repeated. In order to perform vapor deposition intermittently, an open / close shutter can be used in the path between the vapor deposition source and the stage. For example, it is preferable to perform vapor deposition after opening the open / close shutter and perform gas irradiation after closing the open / close shutter.

  The metal layer 67-1 includes a first portion 67a-1 grown on the mask M2-1 and a second portion 67b- grown on the second region 65b-1 of the group III nitride semiconductor region 65-1. 1 is included. The first portion 67a-1 is separated from the second portion 67b-1 by the height of the mask M2-1. The metal layer 67-1 can also include a metal layer capable of forming a hydride. The metal layer 67-1 is made of Al, Mo, W, Ta, Au, Ge, Cr, Fe, Ti, Mg, Mn, Zr, Ni, Ca, Nb, V, Pd and at least two of these elements. Alloys can be included. Metals and alloys containing these exemplary listed elements can be used for the metal layer 67-1.

  In step S117-1, as illustrated in part (a) of FIG. 15, after the substrate to be processed is placed on the stage 12e-1 of the processing apparatus 10e-1, the processing apparatus 10e- is used using the mask M2-1. 1 to grow a dielectric layer 69-1. The dielectric layer 69-1 includes a first portion 69a-1 grown on the mask M2-1 and a second portion 69b grown on the second region 65b-1 of the group III nitride semiconductor region 65-1. -1. The first portion 69a-1 is separated from the second portion 69b-1 by the thickness of the mask M2-1. For example, the thickness of the dielectric layer 69-1 can be 1.0 nm or more, and the thickness of the dielectric layer 69-1 is the ridge of the group III nitride semiconductor layer in which the top surface of the dielectric layer has a ridge. The upper surface is preferably flush with the upper surface, but may have a thickness at which at least the metal layer 19 and the electrode are insulated. The dielectric layer 69-1 can be, for example, a silicon oxide film, silicon nitride, silicon oxynitride, hafnium oxide, tantalum oxide, ferroelectric, or the like. For these film formations, for example, a method that is generally used at present can be applied, such as vacuum vapor deposition, sputter vapor deposition, plasma PVD, and CVD.

  The total thickness of the metal layer 67-1 and the dielectric layer 69-1 is preferably determined so as to match the height of the ridge portion.

  After these steps S116-1 and S117-1, the mask M2-1 is removed by the processing apparatus 10f-1 by the lift-off method in step S118-1 as shown in FIG. A product SP1-1 is produced. As a result, the portion 67a-1 of the metal layer 67-1 and the portion 69a-1 of the dielectric layer 69-1 that are sequentially provided on the mask M2-1 disappear. The substrate product SP1-1 is a portion 67b-1 of the metal layer 67-1 provided in order on the second region 65b-1 of the group III nitride semiconductor region 65-1 (in the following description, “metal layer 67b-1”). And a portion 69b-1 (referred to as "dielectric layer 69b-1" in the following description) of the dielectric layer 69-1.

  According to this manufacturing method, the position of the ridge portion is defined using the mask M2-1 for lift-off and etching, and the film and dielectric for the metal layer 67b-1 are used using the mask M2-1. Film deposition for layer 69b-1 is performed. After this deposition, the mask M2-1 is removed to form a dielectric layer. Therefore, the metal layer 67b-1 and the dielectric layer are manufactured in a self-aligned manner with respect to the ridge portion. The metal layer 67b-1 and the dielectric layer constitute a current guide region.

  In the production by the lift-off method, the dielectric layer 69-1 is formed of a silicon-based inorganic compound such as a silicon oxide film, silicon nitride, and silicon oxynitride, a metal oxide such as hafnium oxide and tantalum oxide, as already described. In addition, it is preferable to include at least one of ferroelectrics. Further, a polyimide organic material can be used as the dielectric layer 69-1. In this case, for example, a manufacturing method called a plasma assisted vacuum deposition method which is a general-purpose deposition method can be used.

  In step S119-1, as shown in FIG. 16A, a junction C1-1 is formed on the upper surface 65c-1 of the ridge portion of the first region 65a-1 of the group III nitride semiconductor region 65-1. An anode electrode 71-1 is formed. As the anode electrode 71-1, a single metal such as Au, Ni, Pd, In, Pt, Al, Sn, or an alloy thereof can be used. In addition, a cathode electrode can be formed on the electrode 71-1 and the pad electrode provided on the current guide region and the back surface 51 b-1 of the substrate 51-1. According to this manufacturing method, since the dielectric layer 69-1 is provided between the electrode 71-1 and the metal layer 67-1, the metal layer 69-1 is manufactured during the manufacturing process after the dielectric layer 69-1 is manufactured. The hydrogen in 67-1 does not reach the electrode through the dielectric layer 69-1.

According to this manufacturing method, while it is possible to form the electrode 71-1 in contact with the ridge portion upper surface 65c-1 of the first region 65a-1, the group III nitride semiconductor region 65-1 is formed in the substrate product. The current guide region can be formed on the metal layer 67b-1 by using the insulating dielectric layer 69b-1 provided on the second region 65b-1. The metal layer 67b-1 includes a region having a lattice defect density of 1 × 10 ¹¹ cm ⁻² or more, and this region can capture hydrogen. Group III nitride semiconductor region 65-1 contains hydrogen, and metal layer 67b-1 forms junction C2-1 with second region 65b-1 different from the ridge portion of first region 65a-1. Therefore, the moving hydrogen is trapped in the metal layer 67b-1. A dielectric layer 69b-1 is provided so as to form a junction C3-1 with the metal layer 67b-1. Since the metal layer 67b-1 is provided on the second region 65b-1 different from the ridge portion of the first region 65a-1, the moving hydrogen is a junction C1 between the ridge portion upper surface 65c-1 and the electrode 73-1. -1 (interface) and stored in the metal layer 67b-1. Furthermore, since the electrode 71-1 is in contact with the ridge portion upper surface 65c-1 and the ridge has p-type conductivity, a current path from the electrode 71-1 is provided. The material of the electrode 71-1 is determined independently of the material of the metal layer 67b-1. The total contact area between the second region 65a-1 and the metal layer 67b-1 is larger than the total contact area between the ridge portion upper surface 65c-1 and the electrode 71-1.

  Separately from the above embodiment, after the epitaxial substrate E is taken out from the growth furnace 10a-1, a substrate product is produced in step S113-1 according to the process flow shown in part (b) of FIGS. To do. In this process flow, steps S121-1 and S122-1 are performed instead of step S116-1.

Subsequent to step S115-1 shown in part (b) of FIG. 11, in step S121-1, the processing apparatus 10d-1 is used or in a processing apparatus similar to this, shown in part (b) of FIG. As described above, the metal film 75-1 is grown by the processing apparatus using the mask M2-1. The metal film 75-1 is grown on the first portion 75a-1 grown on the mask M2-1 by adjusting the stage temperature and the second region 65b-1 of the group III nitride semiconductor region 65-1. Second portion 75b-1. This metal film 75-1 is different from the metal layer 67-1 in terms of lattice defect density, and has a defect density of less than 1 × 10 ¹¹ cm ⁻² as a result of adjusting the stage temperature. Next, in step S122-1, a process of introducing lattice defects into the metal film 75-1 is performed, and a metal layer having a lattice defect density larger than that of the metal film 75-1 (this metal layer is a lattice defect). Is equivalent to the “metal layer 67b-1” in terms of density). Further, after the metal film 75-1 is formed, a lattice defect having a desired density can be formed by performing a process in addition to the film formation. When forming a structure in which the metal layer is separated from the side surface of the ridge structure, a general-purpose photolithography method can be applied to perform precise vapor deposition.

  As the precision vapor deposition method, for example, the metal film 75-1 can be formed by a physical vapor deposition method such as a resistance heating method, an electron beam heating method, or a sputtering method. A method for forming a metal layer having a lattice defect density higher than that of the metal film will be described.

(1) Nanoparticle irradiation method.
After the metal film 75-1 is formed, the surface of the metal film 75-1 is irradiated with nanoparticles (for example, alumina, SiC, etc.), and the surface is hit by the collision of the nanoparticles with the surface of the metal film 75-1. . By this irradiation, mechanical stress can be applied to the metal film 75-1 to increase the lattice defect density. Note that in order to perform selective irradiation, a mask formed using a photolithography method can be used.

(2) Splat quenching method.
Further, as in splat quenching, a mask plate having ridge holes aligned with the arrangement of the ridge regions is brought into contact with a substrate having the arrangement of ridge regions, and stress is applied to the metal film 75-1 between the ridge regions. As a result, the lattice defect density can be increased.

(3) Stress application by high frequency irradiation and cooling.
In addition, since the thickness of the metal film 75-1 is thinner than the thickness of the semiconductor epitaxial stack and the metal film 75-1 is softer than the semiconductor, an effect of applying stress occurs in the metal film.

After the metal film 75-1 is formed, the surface of the metal film 75-1 is irradiated with high frequency. The mode of irradiation can be continuous irradiation or pulsed irradiation. Irradiation generates an eddy current in the metal film 75-1. At this time, an inert gas such as argon (Ar) or nitrogen (N ₂ ) is irradiated as a cooling gas. By this irradiation, the metal film 75-1 can be rapidly cooled to increase lattice defects. Since the thickness of the metal film 75-1 is thinner than the thickness of the semiconductor epitaxial stack, high-density defects can be introduced into the metal film 75-1 by applying a high frequency for a short time.

(4) Application of stress by laser beam irradiation and cooling.
After the metal film 75-1 is formed, the substrate to be processed is placed on a coolable stage, and then the surface of the metal film 75-1 is irradiated with a laser beam. The irradiation time of the laser beam can be on the order of picoseconds to several seconds. Further, the mode of irradiation can be continuous irradiation or pulse irradiation. Since the metal film 75-1 is thin, it is possible to form a metal layer by introducing high-density lattice defects into the metal film 75-1 by quenching from a temperature range exceeding 1/2 of the melting point of the metal material.

Note that the metal film 75-1 may have a defect density of 1 × 10 ¹¹ cm ⁻² or more. At this time, in Step S122-1, lattice defects can be additionally introduced into the metal film, and the density of lattice defects in the metal film can be adjusted.

  As described above, by providing a metal layer capable of trapping hydrogen below the insulating dielectric layer, it is desorbed from the Mg—H composite produced in the p-type cladding layer in long-term CW oscillation. The metal layer below the dielectric layer captures and absorbs hydrogen and atomic hydrogen derived from hydrogen diffusion from the lower semiconductor layer. Furthermore, even when hydrogen concentration distribution inside the metal occurs due to the progress of hydrogen trapping and absorption, the concentration distribution is gradually uniformed by internal diffusion, so that atomic hydrogen can be further trapped in the metal. Therefore, the inflow of hydrogen atoms to the p-type contact layer can be suppressed for a longer period, the recombination probability between magnesium and hydrogen can be reduced, and stable p-type ohmic contact can be maintained. As a result, the device life is extended. In addition, this invention is not limited to the specific form described in this Embodiment.

  According to the present embodiment, a nitride light emitting device that can improve the shortening of the device lifetime due to the movement of hydrogen is provided. In addition, according to the present embodiment, a method for manufacturing a nitride light emitting device capable of improving the shortening of the device lifetime due to the movement of hydrogen is provided.

  DESCRIPTION OF SYMBOLS 11 ... Nitride light emitting element, 13 ... Group III nitride semiconductor region, 15 ... Active layer, 17 ... Electrode, 18 ... Pad electrode, 19 ... Metal layer, 21 ... Dielectric layer, 23 ... Current guide region, JC1 ... Contact (Ohmic contact), 25 ... Group III nitride semiconductor region, 27 ... Support base, 29 ... Light emitting layer, 31, 35 ... Light guide layer, 33 ... Electron blocking layer, 43 ... Electrode, E ... Epitaxial substrate, 51 ... Substrate 53 ... Group III nitride semiconductor region, 55 ... Light emitting layer, 57 ... Group III nitride semiconductor region, 59 ... First metal mask film, 61 ... Second metal mask film, 63 ... Insulating film, 59a ... 1 metal mask layer, 61a ... second metal mask layer, 63a ... insulating layer, 65 ... etched group III nitride semiconductor region, 67 ... hydrogen trapping layer, 69 ... dielectric layer, 71 ... anode electrode, M1 ... resist mask, M2 ... ma SP1, substrate product, 10a ... growth furnace, 10b-10g ... processing equipment, 11-1 ... nitride light emitting element, 13-1 ... group III nitride semiconductor region, 15-1 ... active layer, 17-1 ... Electrode, 18-1 ... Pad electrode, 19-1 ... Metal layer, 21-1 ... Dielectric layer, 23-1 ... Current guide region, JC1-1 ... Contact (ohmic contact), 25-1 ... Group III nitride Physical semiconductor region, 27-1 ... support base, 29-1 ... light emitting layer, 31-1, 35-1 ... light guide layer, 33-1 ... electron block layer, 43-1 ... electrode, E-1 ... epitaxial substrate 51-1 ... substrate, 53-1 ... group III nitride semiconductor region, 55-1 ... light emitting layer, 57-1 ... group III nitride semiconductor region, 59-1 ... first metal mask film, 61-1. ... 2nd metal mask film, 63-1 ... Insulating film, 59a-1 ... 1st metal mask layer, 61 -1 ... second metal mask layer, 63a-1 ... insulating layer, 65-1 ... etched group III nitride semiconductor region, 67-1 ... metal layer, 69-1 ... dielectric layer, 71-1 ... Anode electrode, 75-1 ... metal film, M1-1 ... resist mask, M2-1 ... mask, SP1-1 ... substrate product, 10a-1 ... growth furnace, 10b-1 to 10g-1 ... processing equipment.

Claims (23)

A nitride light emitting device,
An active layer made of a group III nitride semiconductor;
a first region including a p-type conductive ridge portion and a second region extending along the first region; a group III nitride semiconductor region including hydrogen and a p-type dopant;
Electrodes provided on the first region and the second region of the group III nitride semiconductor region;
A metal layer provided on the second region of the group III nitride semiconductor region and made of a material capable of forming a hydride;
Forming a bond to the metal layer, and comprising a dielectric layer provided between the electrode and the metal layer;
The group III nitride semiconductor region is provided on the active layer,
The nitride light emitting device, wherein the electrode is in contact with the upper surface of the ridge portion. The metal layer is in contact with the upper surface of the second region of the group III nitride semiconductor region, and is in contact with the p-type semiconductor region of the second region;
2. The nitride light emitting device according to claim 1, wherein a contact area between the metal layer and the second region is larger than a contact area between the upper surface of the ridge portion and the electrode.   The nitride light-emitting device according to claim 1, wherein the group III nitride semiconductor region is doped with Mg.   4. The metal layer according to claim 1, wherein the metal layer includes an element composed of at least two elements of Ti, Mg, Mn, Zr, Ni, Ca, Nb, V, and Pd and the element. The nitride light emitting device described in the item. The dielectric layer is provided between the electrode and the metal layer;
The dielectric layer includes at least one of a silicon oxide film, a silicon nitride, a silicon oxynitride, hafnium oxide, a tantalum oxide, a ferroelectric, and a polyimide organic material. A nitride light emitting device according to any one of the preceding claims. A support substrate made of group III nitride;
A group III nitride semiconductor layer provided on the main surface of the support substrate,
The group III nitride semiconductor layer has n-type conductivity,
6. The nitride light-emitting element according to claim 1, wherein the active layer is provided between the group III nitride semiconductor layer and the group III nitride semiconductor region.   The nitride light-emitting element according to claim 6, wherein the main surface of the support base is inclined at an angle in the range of not less than 63 degrees and not more than 80 degrees with respect to the c-axis of the group III nitride. The metal layer is in contact with the side surface of the ridge portion, or is separated from the side surface of the ridge portion,
8. The nitride light emitting device according to claim 1, wherein the dielectric layer covers an upper surface of the metal layer and contacts a side surface of the ridge portion. 9. A method for producing a nitride light emitting device, comprising:
A group III nitride semiconductor region having an active layer, a first region including a ridge portion, and a second region extending along the first region; and the second region of the group III nitride semiconductor region over the second region A step of producing a substrate product including a metal layer and a dielectric layer provided in order,
Forming an electrode on the top surface of the ridge portion and the dielectric layer in the first region of the group III nitride semiconductor region, and
The electrode is in contact with the upper surface of the ridge;
The group III nitride semiconductor region is formed on the active layer,
The metal layer is made of a material capable of forming a hydride,
A method of fabricating a nitride light emitting device, wherein the group III nitride semiconductor region contains hydrogen and a p-type dopant. Said step of producing a substrate product comprises:
Growing a first group III nitride semiconductor film for the p-type cladding layer and a second group III nitride semiconductor film for the p-type contact layer on the active layer to form an epitaxial substrate;
Forming a mask for a lift-off method on the main surface of the epitaxial substrate;
Etching the first and second group III nitride semiconductor films using the mask to form the group III nitride semiconductor region; and
Growing the metal layer and the dielectric layer sequentially on the group III nitride semiconductor region using the mask; and
Removing the mask by a lift-off method to form the substrate product,
The first group III nitride semiconductor film includes a p-type dopant,
The Group III nitride semiconductor film includes a p-type dopant,
The group III nitride semiconductor region includes the p-type cladding layer and the p-type contact layer,
The method for manufacturing a nitride light emitting device according to claim 9, wherein the metal layer is in contact with an upper surface of the p-type cladding layer. The metal layer is in contact with the upper surface of the second region of the group III nitride semiconductor region;
The sum of the contact areas between the second region and the metal layer in the substrate product is larger than the sum of contact areas between the upper surface of the ridge portion and the electrodes in the substrate product. A method for producing the nitride light-emitting device described in 1.   The method for producing a nitride light-emitting element according to claim 9, wherein the group III nitride semiconductor region is doped with Mg.   The metal layer includes any one of elements of Ti, Mg, Mn, Zr, Ni, Ca, Nb, V, and Pd and an alloy composed of at least two elements of the elements. A method for producing the nitride light-emitting element described in the item. The substrate product further includes a substrate made of group III nitride, and a group III nitride semiconductor layer grown on the main surface of the substrate,
The active layer is grown on the group III nitride semiconductor layer;
The group III nitride semiconductor layer has n-type conductivity,
The method for producing a nitride light-emitting element according to claim 9, wherein the active layer is provided between the group III nitride semiconductor layer and the group III nitride semiconductor region. .   The main surface of the substrate is inclined at an angle ranging from 63 degrees to 80 degrees with respect to the c-axis of the group III nitride. A method of manufacturing a nitride light emitting device. The dielectric layer is provided between the electrode and the metal layer;
The dielectric layer and the metal layer are deposited in a self-aligned manner with respect to the ridge portion,
The dielectric layer includes at least one of a silicon oxide film, a silicon nitride, a silicon oxynitride, hafnium oxide, a tantalum oxide, a ferroelectric, and a polyimide organic material. A method for producing the nitride light-emitting device according to claim 1. 9. The nitride light-emitting element according to claim 1, wherein the metal layer includes a region having a lattice defect density of 1 × 10 ¹¹ cm ⁻² or more.   18. The nitride light emitting device according to claim 17, wherein the lattice defects included in the metal layer include at least one of point defects, dislocations, stacking faults, and an assembly of these defects. 19. The nitride light-emitting element according to claim 17, wherein the region of the metal layer has a lattice defect density of 1 × 10 ¹⁵ cm ⁻² or less. The method for producing a nitride light-emitting element according to claim 9, wherein the metal layer includes a region having a lattice defect density of 1 × 10 ¹¹ cm ⁻² or more. 21. The method for producing a nitride light emitting device according to claim 20, wherein the region of the metal layer has a lattice defect density of 1 * 10 ^{< 15} > cm ^<-2> or less. Said step of producing a substrate product comprises:
Forming an epitaxial substrate by growing a first group III nitride semiconductor film for a p-type cladding layer and a second group III nitride semiconductor film for a p-type contact layer on the active layer;
Forming a mask for a lift-off method on the main surface of the epitaxial substrate;
Etching the first and second group III nitride semiconductor films using the mask to form the group III nitride semiconductor region; and
Growing a metal film on the group III nitride semiconductor region using the mask; and
Performing a process of introducing lattice defects into the metal film to form a metal layer having a lattice defect density larger than that of the metal film;
Growing the dielectric layer on the metal layer using the mask;
Removing the mask by a lift-off method to form the substrate product;
Including
The lattice defects contained in the metal layer include at least one of point defects, dislocations, stacking faults, and aggregates of these defects,
The first group III nitride semiconductor film includes a p-type dopant,
The Group III nitride semiconductor film includes a p-type dopant,
The group III nitride semiconductor region includes the p-type cladding layer and the p-type contact layer,
The method for producing a nitride light emitting device according to claim 20 or 21, wherein the metal layer is in contact with an upper surface of the p-type cladding layer. Said step of producing a substrate product comprises:
Forming an epitaxial substrate by growing a first group III nitride semiconductor film for a p-type cladding layer and a second group III nitride semiconductor film for a p-type contact layer on the active layer;
Forming a mask for a lift-off method on the main surface of the epitaxial substrate;
Etching the first and second group III nitride semiconductor films using the mask to form the group III nitride semiconductor region; and
Forming a metal layer including a region having a lattice defect density of 1 × 10 ¹¹ cm ⁻² or more on the group III nitride semiconductor region using the mask;
Growing the dielectric layer on the metal layer using the mask;
Removing the mask by a lift-off method to form the substrate product;
Including
The lattice defects contained in the metal layer include at least one of point defects, dislocations, stacking faults, and aggregates of these defects,
The first group III nitride semiconductor film includes a p-type dopant,
The Group III nitride semiconductor film includes a p-type dopant,
The group III nitride semiconductor region includes the p-type cladding layer and the p-type contact layer,
The method for producing a nitride light emitting device according to claim 20 or 21, wherein the metal layer is in contact with an upper surface of the p-type cladding layer.

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