JP2012104757A - Method for manufacturing semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor package capable of reducing positional deviation between a semiconductor chip and a wiring structure formed on a main surface of the semiconductor chip.SOLUTION: The method for manufacturing the semiconductor package comprises a first step for forming a supporting body in which a plurality of reference mark transfer sections are formed on its one surface; a second step for arranging a semiconductor chip 20 so that a surface of a circuit formation surface is opposed to the one surface; a third step for forming a sealing resin 30 covering the semiconductor chip 20 and a plurality of reference mark transfer sections on the one surface, and transferring the plurality of reference mark transfer sections on a main surface of the sealing resin 30 contacting with the supporting structure to form the plurality of reference marks; a forth step for removing the supporting structure to expose the circuit formation surface and the main surface; and a fifth step for forming a wiring structure having a wiring layer electrically connected to the semiconductor chip 20 based on a plurality of reference marks on the circuit formation surface and the main surface.

Description

  The present invention relates to a method for manufacturing a semiconductor package in which a wiring structure is formed on a main surface of a semiconductor chip.

  Conventionally, a semiconductor chip is covered with an insulating resin so that the main surface (circuit forming surface) is exposed, and insulating layers and wiring layers are alternately laminated on the main surface of the semiconductor chip using the insulating resin as a base. A semiconductor package in which a wiring structure is formed is known.

  An example of a method for manufacturing such a semiconductor package will be described below. 1 to 3 are diagrams illustrating a conventional semiconductor package manufacturing process. 1 to 3, (a) is a plan view, and (b) is a cross-sectional view taken along line AA in (a).

  First, in the process shown in FIG. 1, a semiconductor wafer is separated into a plurality of semiconductor chips 200. The plurality of semiconductor chips 200 are arranged on the one surface 500a of the support 500 so that the main surface 200a faces the one surface 500a of the support 500 (in a face-down state). The plurality of semiconductor chips 200 can be fixed on one surface 500a of the support 500 with, for example, an adhesive (not shown).

  Next, in the step shown in FIG. 2, a sealing resin 300 that covers the plurality of semiconductor chips 200 is formed on one surface 500a of the support 500 by compression molding or the like. Specifically, on the plurality of semiconductor chips 200 on the one surface 500 a of the support 500, a thermosetting insulating resin pellet or powder that is a material of the sealing resin 300 is placed. Then, the sealing resin 300 is formed by fluidizing and curing the placed insulating resin pellets or powder by heating and pressing.

  Next, in the step shown in FIG. 3, the support 500 is removed. The support 500 can be removed by, for example, melting by etching. Moreover, when the support body 500, the semiconductor chip 200, and the sealing resin 300 are fixed by the thermal peeling tape, the support body 500 can be removed by applying predetermined heat. Thereby, the main surface 200 a of the semiconductor chip 200 is exposed from the surface 300 a of the sealing resin 300.

  Next, the structure shown in FIG. 3B is turned upside down to form a wiring structure in which insulating layers and wiring layers are alternately stacked on the main surface 200 a of the semiconductor chip 200. Then, by dividing into pieces so as to include the semiconductor chip 200, a plurality of semiconductor packages in which a wiring structure is formed on the main surface 200a of the semiconductor chip 200 using an insulating resin as a base is manufactured.

International Publication No. 02/15266 Pamphlet International Publication No. 02/33751 Pamphlet

  However, after forming the wiring structure on the main surface 200a of the semiconductor chip 200 after the step of FIG. 3, there is no reference mark (alignment mark), so that there is no gap between the semiconductor chip 200 and the wiring structure. There has been a problem that misalignment occurs.

  As a countermeasure against this problem, a method of forming a reference mark in advance on the main surface 200a of the semiconductor chip 200 is also conceivable. However, in the process of forming the sealing resin 300 by compression molding or the like, each semiconductor chip 200 may be fixed at a position different from the original due to the flow of the resin. In this case, the reference mark itself is displaced. Therefore, the above problem cannot be solved.

  The present invention has been made in view of the above points, and provides a method for manufacturing a semiconductor package capable of reducing misalignment between a semiconductor chip and a wiring structure formed on a main surface of the semiconductor chip. The task is to do.

  In this method of manufacturing a semiconductor package, a first step of producing a support having a plurality of reference mark transfer portions formed on one surface, and a circuit formation surface facing the one surface on the one surface. A second step of disposing the semiconductor chip on the main surface, forming a sealing resin covering the semiconductor chip and the plurality of reference mark transfer portions on the one surface, and contacting the support surface of the sealing resin with the support A third step of transferring the plurality of reference mark transfer portions to form a plurality of reference marks, a fourth step of removing the support and exposing the circuit forming surface and the main surface, And a fifth step of forming a wiring structure including a wiring layer electrically connected to the semiconductor chip based on the plurality of reference marks on the circuit formation surface and the main surface. To do.

  According to the disclosed technology, it is possible to provide a method for manufacturing a semiconductor package capable of reducing a positional shift between a semiconductor chip and a wiring structure formed on the main surface of the semiconductor chip.

It is FIG. (The 1) which illustrates the manufacturing process of the conventional semiconductor package. It is FIG. (2) which illustrates the manufacturing process of the conventional semiconductor package. It is FIG. (The 3) which illustrates the manufacturing process of the conventional semiconductor package. 1 is a cross-sectional view illustrating a semiconductor package according to a first embodiment. FIG. 3 is a diagram (part 1) illustrating the manufacturing process of the semiconductor package according to the first embodiment; FIG. 6 is a second diagram illustrating a manufacturing process of the semiconductor package according to the first embodiment; FIG. 8 is a diagram (No. 3) for exemplifying the manufacturing process for the semiconductor package according to the first embodiment; FIG. 7 is a diagram (No. 4) for exemplifying the manufacturing process for the semiconductor package according to the first embodiment; FIG. 10 is a diagram (No. 5) for exemplifying the manufacturing process for the semiconductor package according to the first embodiment; FIG. 10 is a diagram (No. 6) for exemplifying the manufacturing process for the semiconductor package according to the first embodiment; FIG. 10 is a diagram (No. 7) for exemplifying the manufacturing process for the semiconductor package according to the first embodiment; FIG. 10 is a diagram (No. 8) for exemplifying the manufacturing process for the semiconductor package according to the first embodiment; FIG. 9 is a diagram (No. 9) for exemplifying the manufacturing process for the semiconductor package according to the first embodiment; FIG. 10 is a diagram (No. 10) for exemplifying the manufacturing process for the semiconductor package according to the first embodiment; FIG. 11 is a diagram (No. 11) for exemplifying the manufacturing process for the semiconductor package according to the first embodiment; FIG. 12 is a view (No. 12) illustrating the manufacturing process of the semiconductor package according to the first embodiment; It is a figure which illustrates the manufacturing process of the semiconductor package which concerns on the modification 1 of 1st Embodiment. It is FIG. (The 1) which illustrates the manufacturing process of the semiconductor package which concerns on the modification 2 of 1st Embodiment. It is FIG. (The 2) which illustrates the manufacturing process of the semiconductor package which concerns on the modification 2 of 1st Embodiment.

  Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In addition, in each drawing, the same code | symbol is attached | subjected to the same component and the overlapping description may be abbreviate | omitted. Further, in the plan view and the like described below, the same hatching as in the cross-sectional view may be applied for the purpose of clarifying the correspondence relationship with the cross-sectional view.

<First Embodiment>
[Structure of Semiconductor Package According to First Embodiment]
FIG. 4 is a cross-sectional view illustrating the semiconductor package according to the first embodiment. Referring to FIG. 4, the semiconductor package 10 includes a semiconductor chip 20 and a sealing resin 30 as a base, an ultrathin wiring structure 40 is formed thereon, and an external connection terminal 49 is provided on the wiring structure 40. It has a formed structure.

  The planar shape of the semiconductor package 10 is, for example, a rectangular shape, and the dimensions can be, for example, about 15 mm wide (X direction) × 15 mm deep (Y direction) × 0.6 mm thick (Z direction). Hereinafter, the semiconductor chip 20, the sealing resin 30, the wiring structure 40, and the external connection terminals 49 constituting the semiconductor package 10 will be described in detail.

  The semiconductor chip 20 has a semiconductor substrate 21, electrode pads 22, and protruding electrodes 23. The thickness of the semiconductor chip 20 can be, for example, about 300 to 500 μm.

  The semiconductor substrate 21 is obtained by forming a semiconductor integrated circuit (not shown) on a substrate made of, for example, silicon (Si) or germanium (Ge). The electrode pad 22 is formed on the circuit forming surface side of the semiconductor substrate 21 and is electrically connected to a semiconductor integrated circuit (not shown). As a material of the electrode pad 22, for example, aluminum (Al) or the like can be used. As a material of the electrode pad 22, copper (Cu) and aluminum (Al) laminated in this order, or copper (Cu), aluminum (Al) and silicon (Si) laminated in this order may be used. I do not care.

  The protruding electrode 23 is formed on the electrode pad 22. As the protruding electrode 23, for example, a cylindrical copper (Cu) post or the like can be used. The diameter of the protruding electrode 23 can be set to, for example, about 50 μm. The height of the protruding electrode 23 can be set to about 5 to 10 μm, for example. The pitch of the adjacent protruding electrodes 23 can be set to about 100 μm, for example. Note that the protruding electrode 23 may not be provided on the electrode pad 22. In this case, the electrode pad 22 itself is an electrode that is electrically connected to the first wiring layer 42 of the wiring structure 40.

  Hereinafter, in the semiconductor chip 20, the circuit formation surface may be referred to as a main surface. In the semiconductor chip 20, a surface substantially parallel to the main surface located on the opposite side of the main surface may be referred to as a back surface. In the semiconductor chip 20, a surface substantially perpendicular to the main surface and the back surface may be referred to as a side surface.

  The sealing resin 30 is formed so as to cover the back surface and side surfaces of the semiconductor chip 20. However, all or part of the back surface of the semiconductor chip 20 may be exposed from the sealing resin 30 in order to improve the heat dissipation performance of the semiconductor chip 20. A surface of the sealing resin 30 on the wiring structure 40 side (hereinafter referred to as a main surface of the sealing resin 30) is substantially flush with the main surface of the semiconductor chip 20.

As a material of the sealing resin 30, for example, an insulating resin such as an epoxy resin or a polyimide resin can be used. The width W ₁ of the portion of the sealing resin 30 that covers the side surface of the semiconductor chip 20 can be set to, for example, about 50 to ₁₀₀ μm. The thickness _{T 1} of the sealing resin 30 may be, for example 500~700μm about.

In the wiring structure 40, a first insulating layer 41, a first wiring layer 42, a second insulating layer 43, a second wiring layer 44, a third insulating layer 45, a third wiring layer 46, and a solder resist layer 47 are sequentially stacked. Has a structure. The thickness _{T 2} of the wiring structure 40 can be, for example, 30~50μm about. In Figure 4, the thickness T ₂ of the thickness T ₁ and the wiring structure 40 of the sealing resin 30 is depicted in the same extent, in practice, the wiring structure 40 thickness T ₂ are of the sealing resin 30 which is significantly thinner than the thickness T _1.

  The first insulating layer 41 is formed on the main surface of the semiconductor chip 20 and the main surface of the sealing resin 30 that are substantially flush with each other so as to cover the protruding electrodes 23 of the semiconductor chip 20. As a material of the first insulating layer 41, for example, an insulating resin such as an epoxy resin or a polyimide resin can be used. The thickness of the first insulating layer 41 can be, for example, about 10 μm.

  The first wiring layer 42 is formed on the first insulating layer 41. The first wiring layer 42 has a via wiring filled in the first via hole 41 x that penetrates the first insulating layer 41 and exposes the upper surface of the protruding electrode 23, and a wiring pattern formed on the first insulating layer 41. . The first wiring layer 42 is electrically connected to the protruding electrode 23 exposed at the bottom of the first via hole 41x. As a material of the first wiring layer 42, for example, copper (Cu) or the like can be used. The thickness of the wiring pattern constituting the first wiring layer 42 can be set to about 5 μm, for example. As described above, the semiconductor package 10 does not use bumps for electrical connection between the semiconductor chip 20 and the wiring structure 40.

  The second insulating layer 43 is formed on the first insulating layer 41 so as to cover the first wiring layer 42. The material and thickness of the second insulating layer 43 can be the same as those of the first insulating layer 41.

  The second wiring layer 44 is formed on the second insulating layer 43. The second wiring layer 44 includes a via wiring filled in the second via hole 43x that penetrates the second insulating layer 43 and exposes the upper surface of the first wiring layer 42, and a wiring pattern formed on the second insulating layer 43. Have The second wiring layer 44 is electrically connected to the first wiring layer 42 exposed at the bottom of the second via hole 43x. The material and thickness of the second wiring layer 44 can be the same as those of the first wiring layer 42.

  The third insulating layer 45 is formed on the second insulating layer 43 so as to cover the second wiring layer 44. The material and thickness of the third insulating layer 45 can be the same as those of the first insulating layer 41.

  The third wiring layer 46 is formed on the third insulating layer 45. The third wiring layer 46 includes a via wiring filled in the third via hole 45x that penetrates the third insulating layer 45 and exposes the upper surface of the second wiring layer 44, and a wiring pattern formed on the third insulating layer 45. Have The third wiring layer 46 is electrically connected to the second wiring layer 44 exposed at the bottom of the third via hole 45x. The material and thickness of the third wiring layer 46 can be the same as those of the first wiring layer 42.

  The solder resist layer 47 is formed on the third insulating layer 45 so as to cover the third wiring layer 46. The solder resist layer 47 has an opening 47 x, and a part of the third wiring layer 46 is exposed at the bottom of the opening 47 x of the solder resist layer 47. As a material of the solder resist layer 47, for example, a photosensitive resin composition containing an epoxy resin, an imide resin, or the like can be used. The thickness of the solder resist layer 47 can be, for example, about 10 μm.

  If necessary, a metal layer may be formed on the third wiring layer 46 exposed at the bottom of the opening 47x. Examples of metal layers include an Au layer, a Ni / Au layer (a metal layer in which an Ni layer and an Au layer are stacked in this order), and a Ni / Pd / Au layer (a Ni layer, a Pd layer, and an Au layer in this order). And a laminated metal layer).

  The external connection terminal 49 is formed on the third wiring layer 46 exposed at the bottom of the opening 47x (on the metal layer when a metal layer is formed on the third wiring layer 46). . In the present embodiment, the semiconductor package 10 has a so-called fan-out structure in which the region where the external connection terminals 49 are formed is extended around the region immediately above the semiconductor chip 20. That is, the wiring layer is routed so that the external connection terminal 49 is positioned above the main surface of the sealing resin 30. The pitch of the adjacent external connection terminals 49 can be larger than the pitch of the adjacent protruding electrodes 23 (for example, about 100 μm), and can be, for example, about 200 μm. However, the semiconductor package 10 may have a so-called fan-in structure depending on the purpose.

  The external connection terminal 49 functions as a terminal electrically connected to a pad provided on a mounting board (not shown) such as a mother board. As the external connection terminal 49, for example, a solder ball or the like can be used. As a material of the solder ball, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu can be used. A lead pin or the like may be used as the external connection terminal 49.

  However, although the external connection terminal 49 is formed in this embodiment, the external connection terminal 49 is not necessarily formed. In short, it is sufficient that a part of the third wiring layer 46 is exposed from the solder resist layer 47 so that the external connection terminals 49 can be formed when necessary.

In the present embodiment, the width W ₁ of the sealing resin 30 is exemplified as 50 to ₁₀₀ μm. However, when realizing a semiconductor package multiterminal by the fan-out structure, the width W ₁ of the sealing resin 30 is about 0.5 to 6 mm, above the main surface of the sealing resin 30, a larger number of external connection terminals 49 may be provided.

  The above is the structure of the semiconductor package 10 in which the extremely thin wiring structure 40 is formed on the main surface of the semiconductor chip 20 and the main surface of the sealing resin 30.

[Method of Manufacturing Semiconductor Package According to First Embodiment]
Next, a method for manufacturing the semiconductor package according to the first embodiment will be described. 5 to 16 are diagrams illustrating the manufacturing process of the semiconductor package according to the first embodiment. 5-9, (a) is a top view, (b) is sectional drawing which follows the BB line of (a).

  First, in the process shown in FIGS. 5 and 6, the support body 50 in which a plurality of concave portions 51 x are formed on one surface covered with the adhesive layer 51 is produced. The concave portion 51x is a typical example of the reference mark transfer portion according to the present invention.

  More specifically, first, in the step shown in FIG. 5, a support body 50 is prepared, and a plurality of through holes 50 x are formed in the prepared support body 50. The through hole 50x is a typical example of the transfer part manufacturing part according to the present invention. The through hole 50x is preferably formed outside the region that is finally separated into pieces and becomes the semiconductor package 10, and can be formed, for example, in the vicinity of the outer edge portion of the support 50. However, if the through hole 50x is a region that does not affect the formation of the wiring structure 40 (for example, in the vicinity of the outermost edge portion of the semiconductor package 10), the through hole 50x is finally separated into a region that becomes the semiconductor package 10 You may form in. In FIG. 5, two through holes 50x are formed, but three or more through holes 50x may be formed.

  As the support body 50, for example, a copper plate can be used. The support 50 is not necessarily limited to a copper plate, and other metal plates such as iron and nickel, a glass plate, a silicon plate, and the like can be used. In the step of removing the support 50 described later (see FIG. 9). It is preferable to use a copper plate that can be easily removed by etching.

  The planar shape of the support 50 can be, for example, a circle having a diameter of about 200 mm. The thickness of the support body 50 can be about 300-800 micrometers, for example. In the present embodiment, the case where the planar shape of the support 50 is circular is illustrated, but the planar shape of the support 50 may be a rectangle, an ellipse, or the like.

  The through hole 50x can be formed by, for example, etching or pressing. The diameter of the through hole 50x can be, for example, about 30 to 300 μm. When the through-hole 50x is formed by etching, one surface of the support 50 excluding a place where etching is performed is covered with a mask (not shown) such as a photosensitive material, and the support 50 in a portion not covered with the mask. Remove. When the support 50 is a copper plate, for example, etching can be performed using a ferric chloride aqueous solution, a cupric chloride aqueous solution, an ammonium persulfate aqueous solution, or the like.

  Next, in the step shown in FIG. 6, one surface of the support body 50 including the plurality of through holes 50 x is covered with the adhesive layer 51, and the adhesive layer 51 is pressed against one surface side of the support body 50 while heating. (So-called laminate), a plurality of recesses 51 x corresponding to the plurality of through holes 50 x are formed on one surface of the support 50. The recess 51x is formed by pressing a part of the adhesive layer 51 softened by heating and entering the through hole 50x. As the adhesive layer 51, for example, a film on which an acrylic adhesive material or a polyimide adhesive material is formed can be used. The thickness of the adhesion layer 51 can be about 50-70 micrometers, for example. The depth of the recess 51x can be set to about 30 μm, for example.

  Next, in the step shown in FIG. 7, a plurality of individual semiconductor chips 20 are prepared. Each semiconductor chip 20 includes a semiconductor substrate 21, an electrode pad 22, and a protruding electrode 23. The electrode pad 22 and the protruding electrode 23 are formed on the main surface side (circuit forming surface side) of each semiconductor chip 20. Yes. And each prepared semiconductor chip 20 is arrange | positioned so that the main surface may oppose one surface of the support body 50 through the adhesion layer 51 in the area | region in which the recessed part 51x of one surface of the support body 50 is not formed. Then, it is pressed to one surface side of the support 50. Thereby, each semiconductor chip 20 is temporarily fixed on one surface of the support body 50 through the adhesive layer 51 in a face-down state.

Next, in the process shown in FIG. 8, the sealing resin 30 that covers the back surface and side surfaces of each semiconductor chip 20 and the plurality of recesses 51 via the adhesive layer 51 on one surface of the support 50 by compression molding. Form. Specifically, the structure shown in FIG. 7 is placed on a lower mold (not shown), and a sealing resin is formed on the adhesive layer 51, the back and side surfaces of each semiconductor chip 20, and the plurality of recesses 51. 30 pellets and powders of insulating resin such as epoxy resin and polyimide resin, which are 30 materials, are placed. Then, the placed insulating resin pellets or powder is heated and fluidized, and is pressed and homogenized by pressing from the opposite side of the lower mold (not shown) with an upper mold (not shown), and sealed. A stop resin 30 is formed. Since the upper mold (not shown) is in contact with the outermost edge portion of the adhesive layer 51, an area where the sealing resin 30 is not formed is formed at the outermost edge portion of the adhesive layer 51. Heating can be performed at 150 ° C. for about 5 minutes, for example. The thickness _{T 1} of the sealing resin 30 may be, for example 500~700μm about. Instead of compression molding, the sealing resin 30 may be formed by a transfer molding method or the like.

  Next, in the step shown in FIG. 9, the support 50 and the adhesive layer 51 shown in FIG. 8 are removed. 9 is shown upside down from FIGS. 5 to 8 for convenience. When the support 50 is a copper plate, it can be removed by etching using, for example, a ferric chloride aqueous solution, a cupric chloride aqueous solution, an ammonium persulfate aqueous solution, or the like. The adhesive layer 51 can be removed by mechanically peeling after removing the support 50.

  Thereby, the main surface of each semiconductor chip 20 and the main surface of the sealing resin 30 on which the plurality of concave portions 51x are transferred and the plurality of convex portions 30x are formed (the same surface as the main surface of each semiconductor chip 20). Is exposed. Further, the back surface and the side surface of each semiconductor chip 20 are covered with the sealing resin 30, and the main surface of each semiconductor chip 20 and the main surface of the sealing resin 30 are substantially flush with each other.

  The plurality of convex portions 30 x to which the plurality of concave portions 51 x are transferred are formed in the vicinity of the outer edge portion of the main surface of the sealing resin 30. The height of each convex portion 30x corresponds to the depth of each concave portion 51x, and can be, for example, about 30 μm. Each convex portion 30x can be used as a reference mark (alignment mark) when forming a wiring pattern or the like in the steps after FIG. In the case of forming two protrusions 30x, it is preferable that the lines connecting the two protrusions 30x are arranged so as to have a predetermined inclination angle with respect to the arrangement direction of the semiconductor chips 20.

  Each convex portion 30x can also be used as a reference mark for examining the shift amount of each semiconductor chip 20 due to the flow of the resin when the sealing resin 30 is formed. Here, the shift amount of each semiconductor chip 20 is a difference between a position (design value) where each semiconductor chip 20 should be originally fixed and a position where each semiconductor chip 20 is actually fixed. By examining the shift amount of each semiconductor chip 20, it becomes possible to grasp the shrinkage amount of the resin when the sealing resin 30 is formed, and this information can be fed back to the manufacturing process of the semiconductor package 10.

  Next, in the step shown in FIG. 10, the first insulation that covers the main surface of each semiconductor chip 20 and the main surface of the sealing resin 30 covers the protruding electrode 23 provided on the main surface side of each semiconductor chip 20. Layer 41 is formed. As a material of the first insulating layer 41, for example, an insulating resin such as a thermosetting sheet-like epoxy resin or a polyimide resin, or a thermosetting liquid or paste epoxy resin or a polyimide resin is used. An insulating resin such as a resin can be used.

The first insulating layer 41 is excellent in workability containing a filler such as silica (SiO ₂ ), for example, in order to make it easy to form the first via hole 41x by a laser processing method or the like in a process described later (see FIG. 11). It is preferable to use a resin material. The linear expansion coefficient of the first insulating layer 41 can be adjusted by adjusting the amount of filler contained in the first insulating layer 41. The same applies to the other insulating layers. The thickness of the first insulating layer 41 can be, for example, about 10 μm.

  When a thermosetting sheet-like epoxy resin or polyimide resin is used as the material of the first insulating layer 41, on the main surface of each semiconductor chip 20 and the main surface of the sealing resin 30, A sheet-like first insulating layer 41 is laminated so as to cover the protruding electrodes 23 of the semiconductor chip 20. Then, the laminated first insulating layer 41 is cured by being heated above the curing temperature while being pressed. In addition, by laminating the first insulating layer 41 in a vacuum atmosphere, it is possible to prevent the void from being caught in the first insulating layer 41.

  When a thermosetting liquid or paste-like epoxy resin or polyimide resin is used as the material of the first insulating layer 41, the main surface of each semiconductor chip 20 and the main surface of the sealing resin 30 are used. Then, a liquid or paste-like first insulating layer 41 is applied by, for example, a spin coating method so as to cover the protruding electrodes 23 of the semiconductor chip 20. Then, the applied first insulating layer 41 is heated to the curing temperature or higher to be cured.

  Since the first insulating layer 41 transmits light to some extent, the convex portion 30x serving as a reference mark can be recognized through the first insulating layer 41.

Next, in the step shown in FIG. 11, a first via hole 41 x that penetrates the first insulating layer 41 and exposes the upper surface of the protruding electrode 23 is formed in the first insulating layer 41. The first via hole 41x can be formed by a laser processing method using, for example, a CO ₂ laser. At this time, the formation position of the first via hole 41x with respect to the upper surface of the protruding electrode 23 can be determined based on the positions of the plurality of convex portions 30x serving as reference marks.

  The first via hole 41x formed by the laser processing method is opened on the side where the second insulating layer 43 is formed, and the bottom surface is formed by the top surface of the protruding electrode 23. The area of the opening is larger than the area of the bottom surface. It becomes a truncated-cone-shaped concave part. Other via holes are formed in the same shape when formed by laser processing. When the first via hole 41x is formed by a laser processing method, a desmear process is performed to remove the resin residue of the first insulating layer 41 attached to the upper surface of the protruding electrode 23 exposed at the bottom of the first via hole 41x. preferable. The same applies when other via holes are formed by laser processing.

  The first via hole 41x may be formed by using a photosensitive resin as the first insulating layer 41 and patterning the first insulating layer 41 by a photolithography method. At this time, a plurality of convex portions 30x can be used as a reference mark for patterning. The first via hole 41x may be formed by printing and curing a paste-like resin through a screen mask that masks a position corresponding to the first via hole 41x.

  Next, in the step shown in FIG. 12, the first wiring layer 42 is formed on the first insulating layer 41. The first wiring layer 42 includes a via wiring filled in the first via hole 41 x and a wiring pattern formed on the first insulating layer 41. The first wiring layer 42 is directly electrically connected to the protruding electrode 23 exposed at the bottom of the first via hole 41x. At this time, the position where the first wiring layer 42 is formed with respect to the upper surface of the protruding electrode 23 exposed at the bottom of the first via hole 41x can be determined with reference to the positions of the plurality of convex portions 30x serving as reference marks. As a material of the first wiring layer 42, for example, copper (Cu) or the like can be used. The first wiring layer 42 can be formed using various wiring forming methods such as a semi-additive method and a subtractive method. As an example, a method of forming the first wiring layer 42 using the semi-additive method is described below. Shown in

  First, a seed made of copper (Cu) or the like is formed on the first insulating layer 41 including the upper surface of the protruding electrode 23 exposed at the bottom of the first via hole 41x and the inner wall of the first via hole 41x by electroless plating or sputtering. A layer (not shown) is formed. Further, a resist layer (not shown) is formed on the seed layer, and the formed resist layer (not shown) is exposed and developed to form an opening corresponding to the first wiring layer 42. At this time, the exposure apparatus detects the positions of the plurality of convex portions 30x serving as the reference marks, and the openings to the protruding electrodes 23 exposed at the bottom of the first via hole 41x with reference to the detected positions of the plurality of convex portions 30x. The formation area (area to be exposed and developed) can be determined.

  Then, a wiring layer (not shown) made of copper (Cu) or the like is formed in the opening of the resist layer by an electrolytic plating method using the seed layer as a power feeding layer. Subsequently, after removing the resist layer, the seed layer not covered with the wiring layer is removed by etching using the wiring layer as a mask. As a result, the first wiring layer 42 aligned with the protruding electrode 23 exposed at the bottom of the first via hole 41x is positioned on the first insulating layer 41 with reference to the positions of the plurality of convex portions 30x serving as reference marks. Formed.

  Next, in the process shown in FIG. 13, the second insulating layer 43, the second wiring layer 44, the third insulating layer 45, and the third wiring layer 46 are stacked by repeating the same processes as in FIGS. 10 to 12. To do. That is, after forming the second insulating layer 43 covering the first wiring layer 42, the second via hole 43 x is formed in the portion of the second insulating layer 43 on the first wiring layer 42. When forming the second via hole 43x, the convex portion 30x can be used as a reference mark. That is, since each insulating layer transmits light to some extent, the convex portion 30x can be detected by an image recognition device or the like and used for alignment.

  However, there is a case where it is difficult to recognize the convex portion 30x serving as the reference mark because the first insulating layer 41 and the second insulating layer 43 are already laminated. In that case, when the first wiring layer 42 is formed on the first insulating layer 41, a new reference mark as a part of the first wiring layer 42 is formed on the first insulating layer 41 with the convex portion 30x as a reference. It only has to be formed. The same applies to the reference marks used when forming the following via holes and wiring patterns. That is, when it is difficult to recognize the convex portion 30x serving as a reference mark through a plurality of layers, a new reference mark is formed on an arbitrary layer using the convex portion 30x as a reference, and the newly formed reference mark is used as a reference. The via hole, the wiring layer, etc. may be positioned.

  Further, a second wiring layer 44 connected to the first wiring layer 42 through the second via hole 43x is formed on the second insulating layer 43. As the second wiring layer 44, for example, copper (Cu) or the like can be used. The second wiring layer 44 is formed by, for example, a semi-additive method.

  Further, after forming the third insulating layer 45 covering the second wiring layer 44, a third via hole 45 x is formed in the portion of the third insulating layer 45 on the second wiring layer 44. Further, a third wiring layer 46 connected to the second wiring layer 44 through the third via hole 45x is formed on the third insulating layer 45. As the third wiring layer 46, for example, copper (Cu) or the like can be used. The third wiring layer 46 is formed by, for example, a semi-additive method.

  10 to 13, three build-up wiring layers (a first wiring layer 42, a second wiring layer 44, and a third wiring layer are formed on the main surface of each semiconductor chip 20 and the main surface of the sealing resin 30. A wiring layer 46) is formed. The build-up wiring layer may be one layer or two layers, and after the step of FIG. 13, the steps of FIGS. 10 to 12 are repeated as many times as necessary to form four or more build-up wiring layers. Also good.

  Next, in the step shown in FIG. 14, a solder resist layer 47 having an opening 47 x is formed on the third insulating layer 45 so as to cover the third wiring layer 46. Specifically, a solder resist made of a photosensitive resin including, for example, an epoxy resin or an imide resin is applied on the third insulating layer 45 so as to cover the third wiring layer 46. Then, the applied solder resist is exposed and developed to form the opening 47x. Thereby, the solder resist layer 47 having the opening 47x is formed. A part of the third wiring layer 46 is exposed at the bottom of the opening 47 x of the solder resist layer 47. Note that the area where the opening 47x is formed (exposure and development area) is the position of the protrusion 30x serving as a reference mark (or a reference mark newly formed on an arbitrary layer with the protrusion 30x as a reference). Is determined by detecting.

  If necessary, a metal layer may be formed on the third wiring layer 46 exposed at the bottom of the opening 47x. Examples of metal layers include an Au layer, a Ni / Au layer (a metal layer in which an Ni layer and an Au layer are stacked in this order), and a Ni / Pd / Au layer (a Ni layer, a Pd layer, and an Au layer in this order). And a laminated metal layer). These metal layers can be formed by, for example, an electroless plating method.

  10-14, each semiconductor chip is electrically connected to the main surface of each semiconductor chip 20 and the main surface of the sealing resin 30 (on the same side as the main surface of each semiconductor chip 20). A wiring structure 40 including a wiring layer to be connected is formed.

  Next, in the step shown in FIG. 15, on the third wiring layer 46 exposed at the bottom of the opening 47x (on the metal layer if a metal layer is formed on the third wiring layer 46). External connection terminals 49 are formed. In the present embodiment, the semiconductor package 10 has a so-called fan-out structure in which the region where the external connection terminals 49 are formed is extended around the region immediately above the semiconductor chip 20. However, the semiconductor package 10 may have a so-called fan-in structure depending on the purpose.

  The external connection terminal 49 functions as a terminal electrically connected to a pad provided on a mounting board (not shown) such as a mother board. As the external connection terminal 49, for example, a solder ball or the like can be used. As a material of the solder ball, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu can be used.

  The external connection terminal 49 is, for example, after applying a flux as a surface treatment agent on the third wiring layer 46 (on the metal layer when a metal layer is formed on the third wiring layer 46), It can be formed by mounting solder balls, reflowing at a temperature of about 240 ° C. to 260 ° C., and then cleaning the surface to remove the flux. However, a lead pin or the like may be used as the external connection terminal 49.

  However, although the external connection terminal 49 is formed in this embodiment, the external connection terminal 49 is not necessarily formed. In short, it is sufficient that a part of the third wiring layer 46 is exposed from the opening 47x of the solder resist layer 47 so that the external connection terminals can be formed when necessary.

  Next, in the step shown in FIG. 16, the structure shown in FIG. 15 is cut at a predetermined position, whereby the sealing resin 30 and the wiring structure 40 are separated into pieces, and the semiconductor package 10 is completed. The structure shown in FIG. 15 can be cut by dicing using a dicing blade 57 or the like. In addition, although the singulation is performed by cutting the sealing resin 30 and the wiring structure 40 between the adjacent semiconductor chips 20, it may be cut so as to have a plurality of semiconductor chips 20. In that case, a semiconductor package having a plurality of semiconductor chips 20 is produced.

  As described above, according to the first embodiment, a plurality of reference marks are formed on the outer edge portion or the like of the main surface of the sealing resin before separation (the surface on the same side as the main surface of the semiconductor chip). Thus, when forming a wiring structure including a wiring layer electrically connected to the semiconductor chip on the main surface of the semiconductor chip before separation and on the main surface of the sealing resin, The position where the wiring layer is formed with respect to the semiconductor chip can be determined on the basis of the position. Further, the shift amount of the semiconductor chip due to the flow of the resin at the time of forming the sealing resin can be examined on the basis of the positions of the plurality of reference marks, and the shrinkage amount of the resin at the time of forming the sealing resin can be grasped.

<Variation 1 of the first embodiment>
In the first embodiment, an example in which a plurality of through holes 50x are formed in the support body 50 in the step shown in FIG. In the first modification of the first embodiment, an example in which a plurality of recesses 50y are formed in the support body 50 is shown. In the first modification of the first embodiment, description of the same components as those in the first embodiment is omitted.

  FIG. 17 is a diagram illustrating a manufacturing process of the semiconductor package according to the first modification of the first embodiment. In addition, in FIG. 17, (a) is a top view, (b) is sectional drawing which follows the BB line of (a).

  In the process shown in FIG. 17, a support body 50 is prepared, and a plurality of recesses 50 y are formed in the prepared support body 50. The concave portion 50y is a typical example of the transfer portion manufacturing portion according to the present invention. The recess 50y is preferably formed outside the region that is finally separated into pieces and becomes the semiconductor package 10, and can be formed, for example, in the vicinity of the outer edge of the support 50.

  However, if the recess 50 y is a region that does not affect the formation of the wiring structure 40 (for example, in the vicinity of the outermost edge portion of the semiconductor package 10), the recess 50 y is finally separated into a region that becomes the semiconductor package 10. It may be formed. In FIG. 17, two concave portions 50y are formed, but three or more concave portions 50y may be formed.

  The recess 50y can be formed by, for example, half-etching or pressing. The diameter of the recessed part 50y can be about 30-300 micrometers, for example. The depth of the recess 50y can be set to about 30 μm, for example.

  When the recess 50y is formed by half-etching, one surface of the support 50 excluding the place where half-etching is performed is covered with a mask (not shown) such as a photosensitive material, and the support in a portion not covered with the mask. 50 is removed from one surface side to the middle in the thickness direction. That is, the portion of the support 50 that is not covered with the mask is removed to an arbitrary thickness without penetrating from one surface where etching is started to the other surface. When the material of the support 50 is copper (Cu), for example, half etching can be performed using a ferric chloride aqueous solution, a cupric chloride aqueous solution, an ammonium persulfate aqueous solution, or the like.

  Next, the semiconductor package 10 shown in FIG. 4 is completed by performing the same processes as in FIGS.

  As described above, according to the first modification of the first embodiment, by forming the plurality of recesses 50y in the support body 50 in place of the plurality of through holes 50x, the same effect as the first embodiment is obtained. Play.

<Modification 2 of the first embodiment>
In the first embodiment, an example in which a plurality of through holes 50x are formed in the support body 50 in the step shown in FIG. In the first modification of the first embodiment, an example in which a plurality of recesses 50y are formed in the support 50 has been described. Modification 2 of the first embodiment shows an example in which a plurality of convex portions 50z are formed on the support body 50. In the second modification of the first embodiment, description of the same components as those in the first embodiment is omitted.

  18 and 19 are diagrams illustrating the manufacturing process of the semiconductor package according to the second modification of the first embodiment. 18 and 19, (a) is a plan view, and (b) is a cross-sectional view taken along the line BB in (a).

  First, in the step shown in FIG. 18, a support body 50 is prepared, and a plurality of convex portions 50 z are formed on the prepared support body 50. In addition, the convex part 50z is a typical example of the transfer part preparation part which concerns on this invention. The convex portion 50z is preferably formed outside the region that is finally separated into pieces and becomes the semiconductor package 10, and can be formed, for example, in the vicinity of the outer edge portion of the support 50.

  However, if the convex portion 50z is a region that does not affect the formation of the wiring structure 40 (for example, in the vicinity of the outermost edge portion of the semiconductor package 10), the convex portion 50z is finally separated into a region that becomes the semiconductor package 10 You may form in. In FIG. 18, two convex portions 50z are formed, but three or more convex portions 50z may be formed.

  The convex portion 50z can be formed by, for example, an electrolytic plating method or an electroless plating method. The diameter of the convex part 50z can be about 30-300 micrometers, for example. The height of the convex portion 50z can be set to about 30 μm, for example.

  When the convex portion 50z is formed by an electrolytic plating method, one surface of the support 50 excluding a place where electrolytic plating is performed is covered with a mask (not shown) such as a photosensitive material, and the portion not covered with the mask is covered. For example, copper is electrolytically plated on one surface of the support 50 using the support 50 as a plating power feeding layer to form the convex portion 50z. However, when the support 50 is used for the plating power feeding layer, the support 50 needs to be made of a metal such as copper (Cu).

  Next, the same steps as in FIGS. 6 to 8 are performed. However, here, a convex portion corresponding to the convex portion 50z is formed on one surface of the support body 50 in place of the concave portion 51x shown in FIGS.

  Next, in the step shown in FIG. 19, the support 50 and the adhesive layer 51 shown in FIG. 18 are removed in the same manner as the step shown in FIG. Thereby, the main surface of each semiconductor chip 20 and the main surface of the sealing resin 30 in which the plurality of convex portions 50z are transferred and the plurality of concave portions 30z are formed (the same surface as the main surface of each semiconductor chip 20). Is exposed. Further, the back surface and the side surface of each semiconductor chip 20 are covered with the sealing resin 30, and the main surface of each semiconductor chip 20 and the main surface of the sealing resin 30 are substantially flush with each other. The depth of the concave portion 30z corresponds to the height of the convex portion 50z, and can be about 30 μm, for example.

  Next, the semiconductor package 10 shown in FIG. 4 is completed by performing the same processes as in FIGS.

  Thus, according to the modification 2 of 1st Embodiment, it replaces with the several through-hole 50x in the support body 50, and forms the several convex part 50z, It is the same as that of 1st Embodiment. There is an effect.

  The preferred embodiment and its modification have been described in detail above, but the present invention is not limited to the above-described embodiment and its modification, and the above-described implementation is performed without departing from the scope described in the claims. Various modifications and substitutions can be added to the embodiment and its modifications.

  For example, after the step shown in FIG. 8, the back side of the semiconductor chip of the sealing resin may be polished to expose the back side of the semiconductor chip. Thereby, the heat dissipation of a semiconductor chip can be improved. Further, a heat radiating component such as a heat spreader may be joined to the back surface of the semiconductor chip. Thereby, the heat dissipation of the semiconductor chip can be further improved.

  Further, when the back surface side of the semiconductor chip of the sealing resin is polished, the back surface side of the semiconductor chip may also be polished to make the semiconductor chip thinner.

  The planar shape of the reference mark is not limited to a circle, and may be an arbitrary shape such as a rectangle or a cross. That is, the planar shapes such as the through hole 50x, the concave portion 50y, and the convex portion 50z that are the basis of the reference mark are not limited to a circular shape, and may be an arbitrary shape such as a rectangular shape or a cross shape.

DESCRIPTION OF SYMBOLS 10 Semiconductor package 20 Semiconductor chip 21 Semiconductor substrate 22 Electrode pad 23 Protruding electrode 30 Sealing resin 30x, 50z Convex part 30z, 50y, 51x Concave part 40 Wiring structure 41 1st insulating layer 41x 1st via hole 42 1st wiring layer 43 1st 2 insulating layer 43x second via hole 44 second wiring layer 45 third insulating layer 45x third via hole 46 third wiring layer 47 solder resist layer 47x opening 49 external connection terminal 50 support 50x through hole 51 adhesive layer 57 dicing blade T ₁ , T ₂ thickness W ₁ width

Claims (8)

A first step of producing a support having a plurality of reference mark transfer portions formed on one surface;
A second step of disposing a semiconductor chip on the one surface such that a circuit forming surface faces the one surface;
A sealing resin that covers the semiconductor chip and the plurality of reference mark transfer portions is formed on the one surface, and the plurality of reference mark transfer portions are transferred to a main surface of the sealing resin that contacts the support. A third step of forming a plurality of reference marks,
A fourth step of removing the support and exposing the circuit forming surface and the main surface;
Forming a wiring structure including a wiring layer electrically connected to the semiconductor chip based on the plurality of reference marks on the circuit forming surface and the main surface. Production method. The first step includes a first A step of forming, on the support, a plurality of transfer portion preparation portions for forming the plurality of reference mark transfer portions,
The one surface of the support including the plurality of transfer portion preparation portions is covered with an adhesive layer, and the adhesive layer is pressed to correspond to the plurality of transfer portion preparation portions on the one surface of the support. A first B step of forming a plurality of reference mark transfer portions,
The method of manufacturing a semiconductor package according to claim 1, wherein in the second step, the semiconductor chip is disposed via the adhesive layer.   3. The method of manufacturing a semiconductor package according to claim 2, wherein, in the first A step, a plurality of through holes that penetrate the support are formed as the plurality of transfer portion manufacturing portions.   3. The method of manufacturing a semiconductor package according to claim 2, wherein in the first step A, a plurality of concave portions are formed on one surface side of the support as the plurality of transfer portion manufacturing portions.   3. The method of manufacturing a semiconductor package according to claim 2, wherein in the first step A, a plurality of convex portions are formed on one surface side of the support as the plurality of transfer portion manufacturing portions. In the fifth step, a 5A step of forming an insulating layer covering the electrode provided on the circuit forming surface side on the circuit forming surface and the main surface;
A 5B step of forming a through-hole exposing the upper surface of the electrode in the insulating layer;
Forming a wiring layer including a via wiring filled in the through hole and a wiring pattern formed on the insulating layer; and
In the step 5B, with reference to the positions of the plurality of reference marks, the formation position of the through hole with respect to the electrode is determined,
6. The method of manufacturing a semiconductor package according to claim 1, wherein, in the step 5C, a formation position of the wiring layer with respect to the electrode is determined based on positions of the plurality of reference marks.   The method of manufacturing a semiconductor package according to claim 6, wherein, in the step 5C, a new reference mark is formed as a part of the wiring layer on the insulating layer with reference to the positions of the plurality of reference marks. In the two steps, a plurality of semiconductor chips are arranged in a region where the plurality of reference mark transfer portions on the one surface are not formed so that each circuit formation surface faces the one surface,
8. The wiring structure including a wiring layer electrically connected to each semiconductor chip is formed on each circuit formation surface and the main surface of the plurality of semiconductor chips in the fifth step. A manufacturing method of a semiconductor package given in any 1 paragraph.

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