JP5647492B2 - Manufacturing method of semiconductor package - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor package having a semiconductor chip and a resin portion covering the semiconductor chip.

  Conventionally, a semiconductor package having a semiconductor chip and a resin portion covering the semiconductor chip is known.

  In an example of such a semiconductor package, the side surface of the semiconductor chip is covered with a resin portion. The active surface of the semiconductor chip, that is, the circuit formation surface, is substantially flush with the surface of the resin portion on the same side as the active surface of the semiconductor chip. A wiring structure in which a wiring layer and an insulating layer are laminated is formed on the active surface of the semiconductor chip and the surface of the resin portion on the same side as the active surface of the semiconductor chip.

  As an example of a method for manufacturing such a semiconductor package, the following manufacturing method is known.

  For example, the semiconductor chip is mounted on the support so that the active surface of the semiconductor chip is in contact with the surface of the support, the semiconductor chip is sealed with a resin portion, and then the support is removed. Thereafter, a semiconductor package is manufactured by laminating a wiring layer and an insulating layer on the active surface and the resin portion of the semiconductor chip.

International Publication No. 02/33751 Pamphlet International Publication No. 02/15266 Pamphlet

  However, in the conventional semiconductor package manufacturing process, no positioning device has been devised when placing the semiconductor chip on the support. For this reason, there is a concern that the semiconductor chip cannot be aligned with high accuracy.

  When the semiconductor chip cannot be aligned with high accuracy, the mutual positional accuracy between the wiring layer formed on the semiconductor chip and the semiconductor chip is also lowered. Therefore, there is a possibility that a fine and high-density wiring layer cannot be formed.

  In view of the above points, an object of the present invention is to provide a method of manufacturing a semiconductor package that can be accurately aligned when a semiconductor chip is arranged on a support and can form fine wiring.

The manufacturing method of the semiconductor package includes a first step of forming an alignment mark made of a recess formed integrally with the support on one surface of the support, and a semiconductor chip aligned with the alignment mark. A second step of disposing the semiconductor chip on the support so that a circuit forming surface of the semiconductor chip faces the one surface and covers the alignment mark; and the semiconductor disposed on the support possess a third step of forming a resin portion for sealing the chip, and a fourth step of removing the support, wherein the first step includes forming a resist having an opening in said one surface And a step of removing a part of the support exposed in the opening by etching and a step of removing the resist .

  According to the disclosed technology, it is possible to provide a method for manufacturing a semiconductor package capable of accurately aligning a semiconductor chip on a support and capable of forming fine wiring.

It is a figure which illustrates the semiconductor package which concerns on 1st Embodiment. FIG. 3 is a diagram (part 1) illustrating the manufacturing process of the semiconductor package according to the first embodiment; FIG. 6 is a second diagram illustrating a manufacturing process of the semiconductor package according to the first embodiment; FIG. 8 is a diagram (No. 3) for exemplifying the manufacturing process for the semiconductor package according to the first embodiment; FIG. 7 is a diagram (No. 4) for exemplifying the manufacturing process for the semiconductor package according to the first embodiment; FIG. 10 is a diagram (No. 5) for exemplifying the manufacturing process for the semiconductor package according to the first embodiment; FIG. 10 is a diagram (No. 6) for exemplifying the manufacturing process for the semiconductor package according to the first embodiment; FIG. 10 is a diagram (No. 7) for exemplifying the manufacturing process for the semiconductor package according to the first embodiment; FIG. 10 is a diagram (No. 8) for exemplifying the manufacturing process for the semiconductor package according to the first embodiment; FIG. 9 is a diagram (No. 9) for exemplifying the manufacturing process for the semiconductor package according to the first embodiment; FIG. 10 is a diagram (No. 10) for exemplifying the manufacturing process for the semiconductor package according to the first embodiment; FIG. 11 is a diagram (No. 11) for exemplifying the manufacturing process for the semiconductor package according to the first embodiment; FIG. 12 is a view (No. 12) illustrating the manufacturing process of the semiconductor package according to the first embodiment; FIG. 18 is a view (No. 13) illustrating the manufacturing process of the semiconductor package according to the first embodiment; FIG. 14 is a diagram (No. 14) for exemplifying the manufacturing process for the semiconductor package according to the first embodiment; FIG. 15 is a view (No. 15) illustrating the manufacturing step of the semiconductor package according to the first embodiment; FIG. 16 is a view (No. 16) illustrating the manufacturing step of the semiconductor package according to the first embodiment; FIG. 17 is a view (No. 17) illustrating the manufacturing step of the semiconductor package according to the first embodiment; FIG. 18 is a view (No. 18) illustrating the manufacturing step of the semiconductor package according to the first embodiment; FIG. 19 is a diagram (19) illustrating the manufacturing process of the semiconductor package according to the first embodiment; It is sectional drawing which illustrates the semiconductor package which concerns on a comparative example. It is FIG. (The 1) which illustrates the manufacturing process of the semiconductor package which concerns on a comparative example. It is FIG. (2) which illustrates the manufacturing process of the semiconductor package which concerns on a comparative example. FIG. 10 is a third diagram illustrating a manufacturing process of a semiconductor package according to a comparative example; It is FIG. (The 4) which illustrates the manufacturing process of the semiconductor package which concerns on a comparative example. It is FIG. (The 5) which illustrates the manufacturing process of the semiconductor package which concerns on a comparative example. It is a figure which illustrates the manufacturing process of the semiconductor package which concerns on the modification of 1st Embodiment. It is FIG. (The 1) which illustrates the manufacturing process of the semiconductor package which concerns on 2nd Embodiment. FIG. 9 is a second diagram illustrating a manufacturing process of a semiconductor package according to the second embodiment; FIG. 10 is a diagram (No. 3) for exemplifying the manufacturing process for the semiconductor package according to the second embodiment; FIG. 11 is a diagram (No. 4) for exemplifying the manufacturing process for the semiconductor package according to the second embodiment; FIG. 10 is a diagram (No. 5) for exemplifying the manufacturing process for the semiconductor package according to the second embodiment; FIG. 10 is a diagram (No. 6) for exemplifying the manufacturing process for the semiconductor package according to the second embodiment; FIG. 13 is a diagram (No. 7) for exemplifying the manufacturing process for the semiconductor package according to the second embodiment; It is FIG. (The 8) which illustrates the manufacturing process of the semiconductor package which concerns on 2nd Embodiment.

  Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. Note that in the plan view or the bottom view described below, the same hatching as that of the cross-sectional view may be applied for the purpose of clarifying the correspondence with the cross-sectional view.

<First Embodiment>
[Structure of Semiconductor Package According to First Embodiment]
FIG. 1 is a diagram illustrating a semiconductor package according to the first embodiment. 1A is a cross-sectional view, and FIG. 1B is a bottom view. Referring to FIG. 1, the semiconductor package 10 includes a semiconductor chip 20, a resin portion 30, and a wiring structure 40.

The semiconductor chip 20 includes a semiconductor substrate 21, a semiconductor integrated circuit 22, a plurality of electrode pads 23, and a protective film 24. The size (plan view) of the semiconductor chip 20 can be about 5 mm × 10 mm, for example. The thickness T ₁ of the semiconductor chip 20 can be set to, for example, about 800 μm (applicable range: 100 to 800 μm). Hereinafter, in the semiconductor chip 20, the surface 20a on the side where the electrode pads 23 are formed may be referred to as a circuit formation surface.

  The semiconductor substrate 21 can be a Si substrate, for example. The semiconductor integrated circuit 22 includes a diffusion layer, an insulating layer, a via, a wiring, and the like (not shown). The electrode pad 23 is provided on the semiconductor integrated circuit 22 and is electrically connected to the semiconductor integrated circuit 22. As a material of the electrode pad 23, for example, Al or the like can be used. As the material of the electrode pad 23, a material in which an Al layer is formed on a Cu layer, a material in which an Si layer is formed on a Cu layer, and an Al layer is further formed thereon may be used.

  The protective film 24 is provided on the semiconductor integrated circuit 22. The protective film 24 is a film for protecting the semiconductor integrated circuit 22 and may be referred to as a passivation film. As the protective film 24, for example, a SiN film, a PSG film, or the like can be used. Further, a layer made of polyimide or the like may be further laminated on a layer made of SiN film or PSG film. The surface 24 a of the protective film 24 is substantially flush with the surface 23 a of the electrode pad 23.

The resin part 30 is formed so as to cover the surface 20 c (side surface) of the semiconductor chip 20. In the semiconductor chip 20, the surface 20b (back surface) is a surface opposite to the circuit forming surface 20a. The surface 30 a of the resin portion 30 is substantially flush with the surface 24 a of the protective film 24 of the semiconductor chip 20. The width _{W 1} of the resin portion 30 is, for example, 2.5mm approximately (applicable range: 2 to 5 mm) can be.

  The wiring structure 40 includes a first wiring layer 41, a second wiring layer 42, a third wiring layer 43, a first insulating layer 44, a second insulating layer 45, a third insulating layer 46, and a solder resist layer. 47.

The wiring structure 40 has the semiconductor chip 20 and the resin portion 30 covering the surface 20c (side surface) of the semiconductor chip 20 as a base, on the circuit formation surface 20a of the semiconductor chip 20 and on the same side as the circuit formation surface 20a of the resin portion 30. It is formed on the surface 30a. The thickness _{T 2} of the interconnect structure 40, for example, 50μm approximately (applicable range: 50 to 100 [mu] m) can be. That is, the thickness T ₁ (applicable range: 100 to 800) of the semiconductor chip 20 thickness _{T 2} (applicable range: 50 to 100 [mu] m) of the wiring structure 40 compared to being very thin.

  The first insulating layer 44 is formed on the surface 23 a of the electrode pad 23 of the semiconductor chip 20, the surface 24 a of the protective film 24, and the surface 30 a of the resin portion 30. The first wiring layer 41 is formed on the first insulating layer 44 and is electrically connected to the electrode pad 23 of the semiconductor chip 20 through a first via hole 44 x that penetrates the first insulating layer 44. The second insulating layer 45 is formed on the first insulating layer 44 so as to cover the first wiring layer 41. The second wiring layer 42 is formed on the second insulating layer 45 and is electrically connected to the first wiring layer 41 through a second via hole 45 x that penetrates the second insulating layer 45. The third insulating layer 46 is formed on the second insulating layer 45 so as to cover the second wiring layer 42. The third wiring layer 43 is formed on the third insulating layer 46 and is electrically connected to the second wiring layer 42 via a third via hole 46 x that penetrates the third insulating layer 46.

  The solder resist layer 47 is formed on the third insulating layer 46 so as to cover the third wiring layer 43. The solder resist layer 47 has an opening 47x, and a part of the third wiring layer 43 is exposed in the opening 47x. The third wiring layer 43 exposed in the opening 47x of the solder resist layer 47 functions as an electrode pad connected to a mother board or the like.

  A metal layer may be formed on the third wiring layer 43 exposed in the opening 47x of the solder resist layer 47. Examples of the metal layer include an Au layer, a Ni / Au layer in which a Ni layer and an Au layer are laminated in this order, a Ni / Pd / Au layer in which a Ni layer, a Pd layer, and an Au layer are laminated in this order, and the like. be able to. Instead of the metal layer, an OSP (Organic Solderability Preservative) process may be performed on the third wiring layer 43 exposed in the opening 47x of the solder resist layer 47.

[Method of Manufacturing Semiconductor Package According to First Embodiment]
Next, a method for manufacturing the semiconductor package according to the first embodiment will be described. 2 to 20 are diagrams illustrating the manufacturing process of the semiconductor package according to the first embodiment. 2 to 20, parts that are the same as those shown in FIG. 1 are given the same reference numerals, and explanation thereof is omitted. 2 to 8 and 10 to 11, (a) is a plan view, and (b) is a cross-sectional view taken along the line DD in (a). 3 to 8 and 10 to 19, E indicates a position at which the structure shown in FIG. 19 is cut in the process shown in FIG. 20 described later.

First, in the process shown in FIG. 2, a semiconductor wafer 11 (semiconductor substrate 21) having a plurality of semiconductor chips 20 is prepared. In the semiconductor wafer 11, B is a scribe region (hereinafter referred to as “scribe region B”) for separating a plurality of semiconductor chips 20, and C is a position where a dicing blade or the like cuts the semiconductor wafer 11 (hereinafter referred to as “cutting position C”). ). Diameter phi ₁ of the semiconductor wafer 11 can be, for example, about 200 mm. Further, the thickness T ₁ of the semiconductor wafer 11 (thickness of the semiconductor chip 20) can be set to, for example, about 800 μm (applicable range: 100 to 800 μm). The details of the semiconductor chip 20 are as described above.

Next, in the steps shown in FIGS. 3 to 5, an alignment mark 51 is prepared as an example of an alignment mark for preparing the support 50 and aligning the semiconductor chip 20 to be arranged on the surface 50 a of the prepared support 50. Form. As a material of the support body 50, for example, metals such as copper (Cu), iron (Fe), nickel (Ni), ceramics, and other various materials can be used. The thickness _{T 3} of the support 50 can be, for example, 200μm approximately. Also, two alignment marks 51 can be formed on the support 50 for each semiconductor chip 20, for example.

  Further, the shape of the alignment mark 51 in a plan view can be various shapes such as an ellipse, a rectangle, and a cross in addition to a circle.

  In the following description, a case where copper (Cu) is used as the support 50 is taken as an example.

First, in the step shown in FIG. 3, a resist layer 52 having an opening 52 x is formed on the surface 50 a of the support 50. Specifically, a resist solution is applied on the surface 50a of the support 50, and the applied resist solution is exposed and developed to form the resist layer 52 having the openings 52x. The resist layer 52 having the opening 52x may be formed by laminating a sheet-like resist (dry film resist). As a material of the resist layer 52, for example, a photosensitive resin composition containing an epoxy resin, an imide resin, or the like can be used. The thickness of the resist layer 52 _{T 4} may be, for example 50~100μm about. Further, the opening 52x can have, for example, a circular shape in plan view, and the inner diameter of the opening 52x at this time can be set to, for example, about 30 μm. The opening 52x is a surface 50a of the support 50 in a later step, and is a portion 50b covered with the semiconductor chip 20 disposed on the surface 50a, that is, the surface 20b (back surface) and the bottom surface of the semiconductor chip 20. It forms in the part 50b which overlaps in view.

  Next, in the step shown in FIG. 4, the surface 50a of the support 50 at the portion of the opening 52x shown in FIG. 3 is removed by etching. The surface 50a of the support 50 at the opening 52x can be removed by etching using, for example, an aqueous ferric chloride solution.

  Next, in the step shown in FIG. 5, the resist layer 52 shown in FIG. 4 is removed. The resist layer 52 can be removed by a peeling process using an alkaline solution such as sodium hydroxide (NaOH). Thereby, the alignment mark 51 which consists of the recessed part 51a can be formed in the surface 50a of the support body 50. FIG. In addition, it is preferable that the recessed part 51a does not penetrate to the surface opposite to the surface 50a of the support body 50. Thereby, when forming the adhesion layer 53 on the surface 50a of the support body 50 in a later process, the material of the adhesion layer 53 leaks to the opposite surface side of the surface 50a of the support body 50 through the through hole. Can be prevented.

  As described above, the opening 52x is formed in the portion 50b overlapping the surface 20b (back surface) of the semiconductor chip 20 disposed on the surface 50a of the support body 50 in a later step in the bottom view. Therefore, the alignment mark 51 formed of the recess 51a is formed on the surface 50a of the support 50, which is a portion 50b covered with the semiconductor chip 20 disposed on the surface 50a of the support 50 in a later step.

  The alignment mark 51 formed on the surface 50a of the support 50 may not be a concave portion, but may be a convex portion, for example, which is formed by changing the color of the surface by, for example, etching or sputtering. Also good.

  If the alignment mark is formed on, for example, an adhesive layer 53 to be described later, other than the support 50, the adhesive layer 53 is in a semi-cured state, so it is difficult to form the alignment mark with high positional accuracy. On the other hand, when the alignment mark 51 is formed on the support 50 having a stable shape such as metal or ceramic, the alignment mark 51 can be formed with high positional accuracy, and when the semiconductor chip 20 is disposed on the support 50. The alignment accuracy can be improved.

Next, in the process illustrated in FIG. 6, a film such as a polyimide resin is attached to the surface 50 a of the support body 50 on which the alignment mark 51 is formed to form the adhesive layer 53. Specifically, the adhesive layer 53 can be formed by laminating and pasting the above-described film on the surface 50a of the support 50. The thickness _{T 5} of the adhesive layer 53 may be, for example, 25μm approximately.

  Next, in the process shown in FIG. 7, the semiconductor wafer 11 shown in FIG. 2 is cut at a cutting position C by a dicing blade or the like to separate the semiconductor chips 20 into individual pieces. And each semiconductor chip 20 is arrange | positioned on the surface 50a of the support body 50 through the adhesion layer 53. As shown in FIG. Specifically, the semiconductor chip 20 is aligned with reference to the alignment mark 51 formed on the surface 50 a of the support 50, and the circuit formation surface 20 a of the aligned semiconductor chip 20 faces the surface 53 a of the adhesive layer 53. Thus, it arrange | positions on the surface 50a of the support body 50 through the adhesion layer 53. As shown in FIG. Then, the arranged semiconductor chips 20 are pressurized. Thereby, each semiconductor chip 20 is fixed on the surface 50a of the support body 50 through the adhesive layer 53 in a face-down state.

  For example, the alignment mark 51 can be detected by a chip mounter, and the semiconductor chip 20 can be mounted on the surface 50 a of the support 50.

  Further, as described above, the alignment mark 51 is formed on the surface 50a of the support body 50 and the portion 50b covered with the semiconductor chip 20 disposed on the surface 50a. Therefore, the aligned semiconductor chip 20 can be disposed on the surface 50 a of the support 50 so that the circuit forming surface 20 a faces the surface 53 a of the adhesive layer 53 and covers the alignment mark 51.

  Further, as shown in FIG. 6, even when the concave portion 53 b is formed on the surface 53 a of the adhesive layer 53 corresponding to the alignment mark 51, the aligned semiconductor chip 20 is covered so as to cover the concave portion 53 b. It can be disposed on the surface 50 a of the support 50. Therefore, as shown in FIG. 7, after the semiconductor chip 20 is disposed on the surface 50a of the support 50, the recess 53b, that is, the alignment mark 51 is prevented from being exposed to the surface (surface 50a) of the support 50. Can do.

  The interval between adjacent semiconductor chips 20 may be arbitrary.

Next, in the step shown in FIG. 8, the resin portion 30 that seals the semiconductor chip 20 is formed on the surface 53 a of the adhesive layer 53 by compression molding or the like. Specifically, as shown in FIG. 9, the structure shown in FIG. 7 is placed on the lower mold 18, and the material of the resin portion 30 so as to cover the semiconductor chip 20 on the surface 53 a of the adhesive layer 53. Place tablets and powders such as epoxy resin. And the epoxy resin etc. which are the materials of the resin part 30 are heated, and it pressurizes from the opposite side of the lower metal mold | die 18 with the upper metal mold | die 19, and it makes it harden | cure. Thereby, the resin part 30 can be formed so that the surface 20b on the opposite side to the circuit formation surface 20a of the semiconductor chip 20 arrange | positioned on the support body 50 may be covered. Heating can be performed at 150 ° C. for about 5 minutes, for example. The thickness _{T 6} from the surface 53a to the surface 30b of the resin portion 30 of the adhesive layer 53 may be, for example 900μm or more.

  As described above, the concave portion 53 b, that is, the alignment mark 51 is not exposed on the surface (surface 50 a) of the support body 50. Therefore, as shown in FIG. 8, the shape of the alignment mark 51 is transferred to the surface 30a on the same side as the circuit forming surface 20a of the resin portion 30 via the concave portion 53b, thereby preventing the convex portion from being formed. .

  Next, in the steps shown in FIGS. 10 and 11, the support 50 and the adhesive layer 53 shown in FIG. 8 are removed.

  First, in the step shown in FIG. 10, the support 50 shown in FIG. 8 is removed. When the support 50 is made of, for example, copper (Cu), it can be removed by etching using, for example, an aqueous ferric chloride solution.

  Next, in the step shown in FIG. 11, the adhesive layer 53 is removed. The adhesive layer 53 can be removed from the surface 30a on the same side as the circuit formation surface 20a of the semiconductor chip 20 and the circuit formation surface 20a of the resin portion 30 by, for example, mechanical peeling. Thereby, the resin part 30 is formed so that the surface 20c (side surface) and the surface 20b (back surface) of the semiconductor chip 20 may be covered. In addition, FIG. 11 has shown the state in the middle of the adhesive layer 53 being peeled off.

  As described above, the shape of the alignment mark 51 is not transferred to the surface 30 a on the same side as the circuit forming surface 20 a of the resin portion 30. Therefore, as shown in FIG. 11, it is possible to prevent the flatness of the surface 30a on the same side as the circuit forming surface 20a of the semiconductor chip 20 of the resin part 30 from being lowered after the support 50 and the adhesive layer 53 are removed.

  Next, in the steps shown in FIG. 12 to FIG. 17, the wiring electrically connected to the semiconductor chip 20 on the circuit forming surface 20 a of the semiconductor chip 20 and the surface 30 a on the same side as the circuit forming surface 20 a of the resin portion 30. A structure 40 can be formed.

  First, in the step shown in FIG. 12, the first insulating layer 44 is formed on the surface 23 a of the electrode pad 23, the surface 24 a of the protective film 24, and the surface 30 a of the resin portion 30. As a material of the first insulating layer 44, a resin material such as an epoxy resin or a polyimide resin can be used. The first insulating layer 44 is formed by, for example, laminating a resin film on the surface 23a of the electrode pad 23, the surface 24a of the protective film 24, and the surface 30a of the resin portion 30, and then pressing (pressing) the resin film. It can be formed by heat treatment at a temperature of about 0 ° C. and curing. 12 to 20 are shown upside down from FIG. 11 for convenience.

  Next, in a step shown in FIG. 13, a first via hole 44x that penetrates the first insulating layer 44 is formed in the first insulating layer 44 by using a laser processing method or the like so that the electrode pad 23 is exposed. Alternatively, a method may be used in which a photosensitive resin film is used as the first insulating layer 44 and is patterned by photolithography to form the first via hole 44x, or a resin film provided with an opening is patterned by screen printing. Alternatively, a method of forming the first via hole 44x may be used.

  Next, in a step shown in FIG. 14, a first wiring layer 41 that is electrically connected to the electrode pad 23 exposed in the first via hole 44 x is formed on the first insulating layer 44. As a material of the first wiring layer 41, for example, copper (Cu) or the like can be used. The first wiring layer 41 is formed by, for example, a semi-additive method. The first wiring layer 41 includes a via conductor in the first via hole 44 x and a wiring pattern on the first insulating layer 44.

  An example in which the first wiring layer 41 is formed by a semi-additive method will be described in more detail. First, a Cu seed layer (not shown) is formed on the inner wall of the first via hole 44x and the first insulating layer 44 by electroless plating or sputtering, and then the first is formed on the Cu seed layer (not shown). A resist layer (not shown) having an opening corresponding to the wiring layer 41 is formed. Next, a Cu layer pattern (not shown) is formed in the opening of the resist layer by electrolytic plating using the Cu seed layer as a power feeding layer. Subsequently, after removing the resist layer, the first wiring layer 41 is obtained by etching the Cu seed layer using the Cu layer pattern as a mask. In addition, as a formation method of the 1st wiring layer 41, various wiring formation methods, such as a subtractive method other than the semi-additive method mentioned above, can be used.

  Next, in the process shown in FIG. 15, the first wiring layer 41 to the third wiring layer 43 and the first insulating layer 44 to the third insulating layer 46 are stacked by repeating the same process as described above. That is, after forming the second insulating layer 45 covering the first wiring layer 41, the second via hole 45 x is formed in the portion of the second insulating layer 45 on the first wiring layer 41.

  Further, the second wiring layer 42 connected to the first wiring layer 41 through the second via hole 45x is formed on the second insulating layer 45. As the second wiring layer 42, for example, copper (Cu) or the like can be used. The second wiring layer 42 is formed by, for example, a semi-additive method.

  Further, after forming the third insulating layer 46 that covers the second wiring layer 42, the third via hole 46 x is formed in the portion of the third insulating layer 46 on the second wiring layer 42. Further, a third wiring layer 43 connected to the second wiring layer 42 through the third via hole 46x is formed on the third insulating layer 46. As the third wiring layer 43, for example, copper (Cu) or the like can be used. The third wiring layer 43 is formed by, for example, a semi-additive method.

  In this way, a predetermined buildup wiring layer is formed on the surface 23 a of the electrode pad 23, the surface 24 a of the protective film 24, and the surface 30 a of the resin portion 30. In this embodiment, three build-up wiring layers (first wiring layer 41 to third wiring layer 43) are formed. However, even if an n-layer (n is an integer of 1 or more) build-up wiring layer is formed. Good.

  Next, in a step shown in FIG. 16, a solder resist is applied on the third insulating layer 46 so as to cover the third wiring layer 43, thereby forming a solder resist layer 47. As a material of the solder resist layer 47, for example, a photosensitive resin composition containing an epoxy resin, an imide resin, or the like can be used.

  Next, in a step shown in FIG. 17, the opening 47x is formed by exposing and developing the solder resist layer 47. Thereby, a part of the third wiring layer 43 is exposed in the opening 47 x of the solder resist layer 47. The third wiring layer 43 exposed in the opening 47x of the solder resist layer 47 functions as an electrode pad connected to a mother board or the like.

  A metal layer may be formed on the third wiring layer 43 exposed in the opening 47x of the solder resist layer 47. Examples of the metal layer include an Au layer, a Ni / Au layer in which a Ni layer and an Au layer are laminated in this order, a Ni / Pd / Au layer in which a Ni layer, a Pd layer, and an Au layer are laminated in this order, and the like. be able to. For example, these metal layers can be provided by electroless plating. Instead of the metal layer, an OSP (Organic Solderability Preservative) process may be performed on the third wiring layer 43 exposed in the opening 47x of the solder resist layer 47.

  Next, in the step shown in FIG. 18, the surface 30b of the resin portion 30 shown in FIG. 17 is ground until the surface 20b of the semiconductor chip 20 is exposed. For example, a grinder or the like can be used for grinding the resin portion 30.

  Note that the step shown in FIG. 18 may be omitted. That is, in the semiconductor package, the surface 20 b of the semiconductor chip 20 may be covered with the resin portion 30.

  Next, in the step shown in FIG. 19, the solder ball 48 is mounted on the third wiring layer 43 exposed in the opening 47 x of the solder resist layer 47.

  The third wiring layer 43 exposed in the opening 47x without mounting the solder ball 48 may be used as an external connection terminal for electrically connecting to the outside.

  Next, in the step shown in FIG. 20, the structure shown in FIG. 19 is cut into pieces, for example, at the position E. Thereby, the semiconductor package 10 shown in FIG. 1 is completed.

  Next, according to the method for manufacturing a semiconductor package according to the first embodiment, it is possible to manufacture a semiconductor package that can be accurately aligned when a semiconductor chip is placed on a support and can form fine wiring. Will be described in comparison with a comparative example.

  In order to accurately align the semiconductor chip on the support, it is preferable to form an alignment mark for aligning the semiconductor chip on the support. However, if the alignment mark is simply formed on the support, the flatness of the resin part deteriorates, and it is difficult to form a fine and highly accurate wiring. Accordingly, the present inventors have found the present invention in which a semiconductor chip is arranged on a support so as to cover an alignment mark formed on the support.

  Note that a manufacturing method of a semiconductor package according to a comparative example described below is also a manufacturing method that the present inventors are comparatively examining.

  FIG. 21 is a cross-sectional view illustrating a semiconductor package according to a comparative example. Referring to FIG. 21, the semiconductor package 100 includes a semiconductor chip 200, a resin part 300, and a wiring structure 400.

  The semiconductor chip 200 has a chip body 210 and electrode pads 220. The chip body 210 is obtained by forming a semiconductor integrated circuit (not shown) or the like on a thinned semiconductor substrate (not shown) made of silicon or the like. The electrode pad 220 is formed on the chip body 210, and the surface 220 a of the electrode pad 220 is exposed from the surface 200 a that is the surface of the chip body 210. The electrode pad 220 is electrically connected to a semiconductor integrated circuit (not shown) of the chip body 210.

  The resin part 300 is provided so as to cover the surface 200 b that is the side surface of the semiconductor chip 200. The resin part 300 is not provided on the surface 200a of the semiconductor chip 200 and the surface 200c opposite to the surface 200a, and the surfaces 200a and 200c of the semiconductor chip 200 are exposed from the resin part 300. The surface 300 a of the resin part 300 is substantially flush with the surface 200 a of the semiconductor chip 200. Further, the surface 300 b of the resin part 300 is substantially flush with the surface 200 c of the semiconductor chip 200. In the semiconductor chip 200, the surface 200a may be referred to as a circuit formation surface, the surface 200b may be referred to as a side surface, and the surface 200c may be referred to as a back surface.

  The wiring structure 400 includes a first wiring layer 410, a second wiring layer 420, a third wiring layer 430, a first insulating layer 440, a second insulating layer 450, a third insulating layer 460, and a solder resist layer. 470.

  The first insulating layer 440 is formed on the surface 200 a of the semiconductor chip 200 and the surface 300 a of the resin part 300. The first wiring layer 410 is formed on the first insulating layer 440 and is electrically connected to the electrode pad 220 of the semiconductor chip 200 through the first via hole 440x penetrating the first insulating layer 440. The second insulating layer 450 is formed on the first insulating layer 440 so as to cover the first wiring layer 410. The second wiring layer 420 is formed on the second insulating layer 450 and is electrically connected to the first wiring layer 410 through the second via hole 450x penetrating the second insulating layer 450. The third insulating layer 460 is formed on the second insulating layer 450 so as to cover the second wiring layer 420. The third wiring layer 430 is formed on the third insulating layer 460 and is electrically connected to the second wiring layer 420 via a third via hole 460x that penetrates the third insulating layer 460.

  The solder resist layer 470 is formed on the third insulating layer 460 so as to cover the third wiring layer 430. The solder resist layer 470 has an opening 470x, and a part of the third wiring layer 430 is exposed in the opening 470x. The third wiring layer 430 exposed in the opening 470x of the solder resist layer 470 functions as an electrode pad connected to a motherboard or the like.

  22 to 26 are diagrams illustrating a semiconductor package manufacturing process according to a comparative example. 22 to 26, the same portions as those in FIG. 21 are denoted by the same reference numerals, and the description thereof may be omitted. 22 to 25, (a) is a plan view, and (b) is a cross-sectional view taken along line AA of (a). Hereinafter, a conventional process for manufacturing a semiconductor package will be described with reference to FIGS. 22 to 25, the electrode pad 220 is omitted.

  First, in the process shown in FIG. 22, the semiconductor wafer is separated into a plurality of semiconductor chips 200. Then, the plurality of semiconductor chips 200 are arranged on the surface 500a of the support 500 such that the surface 200a (circuit formation surface) faces the surface 500a of the support 500. An alignment mark 510 is formed on the surface 500 a of the support 500 as an example of an alignment mark for aligning the semiconductor chip 200. The alignment mark 510 is a concave or convex portion formed on the surface 500a of the support 500, and has a shape having a step with the surface 500a of the support 500. An adhesive layer 530 is formed on the surface 500a of the support 500 on which the alignment mark 510 is formed. The semiconductor chip 200 is aligned with reference to the alignment mark 510 formed on the surface 500a of the support 500, and the aligned semiconductor chip 200 is adhered so that the circuit forming surface 200a faces the surface 530a of the adhesive layer 530. It is arranged on the surface 500 a of the support 500 through the layer 530. And each semiconductor chip 200 arrange | positioned is pressurized.

  Next, in the process shown in FIG. 23, the resin portion 300 is formed on the surface 530a of the adhesive layer 530 by compression molding or the like so as to cover the plurality of semiconductor chips 200. Specifically, on the surface 530a of the adhesive layer 530, a tablet or powder such as an epoxy resin that is a material of the resin part 300 is disposed so as to cover the plurality of semiconductor chips 200. Then, the epoxy resin or the like is cured by heating and pressing to form the resin portion 300.

  Next, in the step shown in FIG. 24, the support 500 is removed. The support 500 can be removed by etching, for example. As a result, the surface 200 a of the semiconductor chip 200 is exposed from the surface 300 a of the resin part 300.

  Next, in the process shown in FIG. 25, the portion of the resin portion 300 covering the surface 200c of the semiconductor chip 200 is removed, and the surface 200c of the semiconductor chip 200 is exposed from the surface 300b of the resin portion 300. Thereby, the resin part 300 contacts only the surface 200b (side surface) of the semiconductor chip 200, and the surfaces 200a and 200c are exposed from the resin part 300.

  Next, in the process illustrated in FIG. 26, the first insulating layer 440, the first wiring layer 410, the second insulating layer 450, the second wiring layer 420, the second wiring layer 420, and the second wiring layer 420 are formed on the surface 200 a of the semiconductor chip 200 and the surface 300 a of the resin portion 300. A solder resist layer 470 having three insulating layers 460, a third wiring layer 430, and an opening 470x is sequentially formed. Then, after the step shown in FIG. 26, the structure shown in FIG. 26 is cut at the cutting position C to complete the semiconductor package 100 shown in FIG.

  In the semiconductor package manufacturing method according to the comparative example, as shown in FIG. 22, the alignment mark 510 is a concave portion or a convex portion or the like formed on the surface 500 a of the support 500, and a step difference from the surface 500 a of the support 500. It has the shape provided with. A concave portion 530 b is formed on the surface 530 a of the adhesive layer 530 corresponding to the alignment mark 510. Therefore, as shown in FIGS. 23 to 26, the shape of the alignment mark 510 is transferred to the surface 300a on the same side as the circuit forming surface 200a of the semiconductor chip 200 of the resin portion 300 via the recess 530b. Part 300c is formed. As a result, after removing the support 500, the flatness of the surface 300a on the same side as the circuit formation surface 200a of the semiconductor chip 200 of the resin portion 300 may be reduced.

  In order to prevent the flatness of the surface 300a of the resin part 300 from being lowered, a method of forming an alignment mark on a part of the surface 500a of the support 500 that is away from the part where the semiconductor chip 200 is disposed, such as a peripheral part. Can be considered. However, if the alignment mark is formed on the peripheral edge or the like, the distance between the alignment mark and the portion where the semiconductor chip 200 is disposed increases, and there is a possibility that the alignment cannot be performed accurately when the semiconductor chip 200 is disposed.

  On the other hand, according to the first embodiment, the semiconductor chip is arranged on the support so as to cover the alignment mark. Thereby, after removing the support, the shape of the alignment mark can be prevented from being transferred to the resin portion, and the flatness of the surface of the resin portion on the same side as the circuit formation surface of the semiconductor chip can be improved. it can. Since the flatness of the surface 30a of the resin part 30 is improved, fine wiring can be formed with high accuracy and high density.

  In the first embodiment, in the steps shown in FIGS. 12 to 17, the semiconductor chip 20 is formed on the circuit formation surface 20 a of the semiconductor chip 20 and the surface 30 a on the same side as the circuit formation surface 20 a of the resin portion 30. The example of forming the wiring structure 40 electrically connected to the device has been described. However, the semiconductor package may be manufactured by performing various processes such as bonding the semiconductor chip 20 and the resin portion 30 that have been completed up to the process illustrated in FIG. 11 onto, for example, a separately prepared wiring board.

<Modification of First Embodiment>
In the first embodiment, in the method of manufacturing a semiconductor package, after removing the support 50, the adhesive layer 53 is peeled from the same side as the circuit formation surface 20a of the semiconductor chip 20 and the circuit formation surface 20a of the resin portion 30. An example is shown. However, the adhesive layer 53 may not necessarily be peeled after the support 50 is removed. Therefore, in the modification of the first embodiment, an example in which the support 50 and the adhesive layer 53 are peeled off at the same time is shown. In the modification of the first embodiment, the description of the parts common to the first embodiment will be omitted, and the parts different from the first embodiment will be mainly described.

  The semiconductor package according to the modification of the first embodiment is the same as the semiconductor package 10 shown in FIG.

  Further, the semiconductor package manufacturing method according to the modification of the first embodiment is the same as that of the semiconductor package according to the first embodiment described with reference to FIGS. This is the same as the method, and a description of the same steps is omitted.

  In the modification of the first embodiment, the process shown in FIG. 27 is performed instead of the process shown in FIGS.

  FIG. 27 is a diagram illustrating a manufacturing process of the semiconductor package according to the modification of the first embodiment. In FIG. 27, the same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof may be omitted. In FIG. 27, (a) is a plan view, and (b) is a sectional view taken along the line DD of (a). Moreover, in FIG. 27, E has shown the position which cut | disconnects the structure shown in FIG. 19 in the process shown in FIG.

  In the step shown in FIG. 27, the support 50 and the adhesive layer 53 shown in FIG. 8 are simultaneously peeled and removed. Specifically, for example, the circuit formation surface 20a side of the semiconductor chip 20 and the circuit formation of the resin portion 30 are started from the interface (the portion indicated by the arrow I) between the surface 30a of the resin portion 30 and the adhesive layer 53 shown in FIG. The support 50 and the adhesive layer 53 can be removed simultaneously by mechanically peeling from the surface 30a on the same side as the surface 20a. Thereby, the process of removing the support body 50, for example by an etching, can be skipped.

  Also in the modification of the first embodiment, by performing various processes such as bonding the semiconductor chip 20 and the resin part 30 that have been completed up to the process shown in FIG. 27 onto a separately prepared wiring board, for example. A semiconductor package may be manufactured.

<Second Embodiment>
In the first embodiment, the example in which the alignment mark 51 including the recess 51a is formed on the surface 50a of the support body 50 in the semiconductor package manufacturing method has been described. However, the alignment mark 51 does not necessarily have to be a recess. Therefore, in the second embodiment, an example in which an alignment mark 54a made of a plating film is formed on the surface 50a of the support 50 will be described. In the second embodiment, description of parts common to the first embodiment is omitted, and parts different from the first embodiment are mainly described.

[Structure of Semiconductor Package According to Second Embodiment]
The semiconductor package according to the second embodiment is the same as the semiconductor package shown in FIG.

[Method of Manufacturing Semiconductor Package According to Second Embodiment]
Next, a method for manufacturing a semiconductor package according to the second embodiment will be described. 28 to 35 are diagrams illustrating the manufacturing process of the semiconductor package according to the second embodiment. 28 to 35, the same portions as those in FIG. 1 are denoted by the same reference numerals, and the description thereof may be omitted. 28 to 35, (a) is a plan view, and (b) is a cross-sectional view taken along the line DD of (a).

  First, before the step shown in FIG. 28, the same step as the step shown in FIG. 2 described in the first embodiment is performed to prepare the semiconductor wafer 11 having a plurality of semiconductor chips 20.

Next, in the steps shown in FIGS. 28 to 30, the support body 50 is prepared, and an alignment mark 54 a as an example of an alignment mark for aligning the semiconductor chip 20 to be arranged on the surface 50 a of the prepared support body 50. Form. As a material of the support body 50, for example, metals such as copper (Cu), iron (Fe), nickel (Ni), ceramics, and other various materials can be used. The thickness _{T 3} of the support 50 can be, for example, 200μm approximately. Further, two alignment marks 54a can be formed on the support 50 for each semiconductor chip 20 to be arranged, for example.

  Note that, similarly to the first embodiment, the following description will be made with an example in which copper (Cu) is used as the support 50.

  First, in a step shown in FIG. 28, a resist layer 55 is formed on the surface 50a of the support 50. The method of forming the resist layer 55 can be the same as the process shown in FIG. 3 in the first embodiment.

  Next, in a step shown in FIG. 29, the formed resist layer 55 is exposed and developed to form a mask portion 55a having an opening 55b. The method for forming the mask portion 55a having the opening 55b can be the same as the process shown in FIG. 3 in the first embodiment. Note that the mask portion 55a is a surface 50a of the support 50 in a later step and is a portion 50b covered with the semiconductor chip 20 disposed on the surface 50a, that is, the surface 20b (back surface) and the bottom surface of the semiconductor chip 20. It forms in the part 50b which overlaps visually.

  Next, in the step shown in FIG. 30, a plating film that becomes the alignment mark 54a is deposited on the surface of the support 50 exposed at the opening 55b by electrolytic plating using the support 50 as a power feeding layer. As a material of the plating film, for example, copper (Cu) can be used. The thickness of the plating film can be about several μm, for example. Note that the thickness of the alignment mark 54 a is preferably equal to the thickness of the plating film and is thick enough to be embedded in the adhesive layer 53.

  Next, in a step shown in FIG. 31, the resist layer 55 shown in FIG. 30 is removed. The resist layer 55 can be removed by a peeling process using an alkaline solution such as sodium hydroxide (NaOH). Thereby, the alignment mark 54a which consists of a plating film can be formed in the surface 50a of the support body 50. FIG.

Next, in the step shown in FIG. 32, the adhesive layer 53 is formed on the surface 50a of the support 50 on which the alignment mark 54a is formed. The method for forming the adhesive layer 53 can be the same as that shown in FIG. 6 in the first embodiment. As a material of the adhesive layer 53, for example, a polyimide resin or the like can be used. The thickness _{T 5} of the adhesive layer 53 may be, for example, 25μm approximately.

  Next, in a step shown in FIG. 33, the semiconductor wafer 11 shown in FIG. 2 is cut at a cutting position C by a dicing blade or the like to divide the semiconductor chip 20 into individual pieces. And each semiconductor chip 20 is arrange | positioned on the surface 50a of the support body 50 through the adhesion layer 53. As shown in FIG. A specific arrangement method can be the same as the process shown in FIG. 7 in the first embodiment. Thereby, each semiconductor chip 20 is fixed on the surface 50a of the support body 50 through the adhesive layer 53 in a face-down state.

  Further, as described above, the alignment mark 54a is formed on the surface 50a of the support body 50 and the portion 50b covered with the semiconductor chip 20 disposed on the surface 50a. Therefore, the aligned semiconductor chip 20 can be disposed on the surface 50a of the support 50 so that the circuit forming surface 20a faces the surface 53a of the adhesive layer 53 and covers the alignment mark 54a.

  Further, even if the surface 53a of the adhesive layer 53 has irregularities corresponding to the alignment mark 54a, the aligned semiconductor chip 20 is placed on the surface 50a of the support 50 so as to cover the alignment mark 54a. Can be arranged. Therefore, as shown in FIG. 33, after the semiconductor chip 20 is disposed on the surface 50a of the support 50, the alignment mark 54a can be prevented from being exposed to the surface (surface 50a) of the support 50.

  Next, in the step shown in FIG. 34, the resin portion 30 for sealing the semiconductor chip 20 is formed on the surface 53a of the adhesive layer 53 by compression molding or the like. A specific method for forming the resin portion 30 can be the same as the steps shown in FIGS. 8 and 9 in the first embodiment. Thereby, the resin part 30 can be formed so that the surface 20b on the opposite side to the circuit formation surface 20a of the semiconductor chip 20 arrange | positioned on the support body 50 may be covered.

  As described above, the alignment mark 54a is not exposed on the surface (surface 50a) of the support 50. Therefore, as shown in FIG. 34, it is possible to prevent the shape of the alignment mark 54a from being transferred to the surface 30a on the same side as the circuit forming surface 20a of the resin portion 30.

  Next, in the step shown in FIG. 35, the support 50 and the adhesive layer 53 shown in FIG. 34 are removed. A specific method of removing the support 50 and the adhesive layer 53 can be the same as the steps shown in FIGS. 10 and 11 in the first embodiment.

  As described above, the shape of the alignment mark 54a is not transferred to the surface 30a on the same side as the circuit forming surface 20a of the resin portion 30. Therefore, as shown in FIG. 35, it is possible to prevent the flatness of the surface 30a on the same side as the circuit forming surface 20a of the semiconductor chip 20 of the resin part 30 from being lowered after the support 50 and the adhesive layer 53 are removed.

  Thereafter, steps similar to those shown in FIGS. 12 to 20 are performed in the first embodiment, the wiring structure 40 is formed, the resin portion 30 is ground, the solder balls 48 are mounted, and separated. . Thereby, the semiconductor package 10 shown in FIG. 1 is completed.

  Thus, according to the second embodiment, the alignment mark is formed, and the semiconductor chip is arranged on the support so as to cover the alignment mark. Thereby, after removing the support, the shape of the alignment mark can be prevented from being transferred to the resin portion, and the flatness of the surface of the resin portion on the same side as the circuit formation surface of the semiconductor chip can be improved. it can. Since the flatness of the surface 30a of the resin part 30 is improved, fine wiring can be formed with high accuracy and high density. As a result, the same effects as those of the first embodiment are obtained.

  In the second embodiment, the support 50 and the adhesive layer 53 may be simultaneously peeled off and removed in the same manner as the process shown in FIG. 27 in the modification of the first embodiment. In that case, the same effect as the modification of the first embodiment is obtained.

  Also in the second embodiment, the semiconductor package is obtained by performing various processes such as bonding the semiconductor chip 20 and the resin part 30 that have been completed up to the process shown in FIG. May be manufactured.

  The preferred embodiment has been described in detail above. However, the present invention is not limited to the above-described embodiment, and various modifications and replacements are made to the above-described embodiment without departing from the scope described in the claims. Can be added.

DESCRIPTION OF SYMBOLS 10 Semiconductor package 11 Semiconductor wafer 20 Semiconductor chip 20a, 20b, 20c, 23a, 24a, 30a, 30b, 50a, 53a Surface 21 Semiconductor substrate 22 Semiconductor integrated circuit 23 Electrode pad 24 Protective film 30 Resin part 40 Wiring structure 41-43 Wiring Layers 44 to 46 Insulating layer 47 Solder resist layer 50 Support 51, 54a Alignment mark 51a, 53b Recess 52, 55 Resist layer 53 Adhesive layer

Claims (5)

A first step of forming, on one surface of the support, an alignment mark made of a recess formed integrally with the support;
A second step of disposing the semiconductor chip aligned by the alignment mark on the support so that a circuit formation surface of the semiconductor chip faces the one surface and covers the alignment mark; ,
A third step of forming a resin portion for sealing the semiconductor chip disposed on the support;
Have a, a fourth step of removing the support,
The first step includes
Forming a resist having an opening on the one surface;
Removing a part of the support exposed in the opening by etching;
And a step of removing the resist . A first step of forming an alignment mark made of a convex portion on one surface of a metal support;
A second step of disposing the semiconductor chip aligned by the alignment mark on the support so that a circuit formation surface of the semiconductor chip faces the one surface and covers the alignment mark; ,
A third step of forming a resin portion for sealing the semiconductor chip disposed on the support;
Have a, a fourth step of removing the support,
The first step includes
Forming a mask portion having an opening on the one surface;
A step of depositing a plating film serving as the alignment mark on the one surface exposed in the opening by electrolytic plating using the support as a power feeding layer;
And a step of removing the mask portion . In the second step, the semiconductor chip is disposed via an adhesive layer formed on the one surface,
  The said 4th process WHEREIN: The said support body and the said adhesion layer are mechanically peeled simultaneously from the said circuit formation surface side of the said semiconductor chip, and the surface on the same side as the said circuit formation surface of the said resin part. Semiconductor package manufacturing method. In the second step, the semiconductor chip is disposed via an adhesive layer formed on the one surface,
In the fourth step, after it said supporting member was removed, according to claim 1 or 2, wherein peeling the adhesive layer from the surface of the circuit forming surface of the same side of the circuit forming surface side and the resin portion of the semiconductor chip Semiconductor package manufacturing method.   5. A fifth step of forming a wiring structure electrically connected to the semiconductor chip on the circuit forming surface of the semiconductor chip and on the same side of the resin portion as the circuit forming surface. 5. A method for manufacturing a semiconductor package according to claim 4.

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