JP2012099510A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form an n-type impurity region composed of carriers of ultra-shallow and high concentration in a Ge semiconductor layer.SOLUTION: A semiconductor device comprises: a semiconductor substrate having one conductivity type of n type or p type; a pair of impurity diffusion regions that are selectively provided on a surface of the semiconductor substrate and have a different conductivity type from the one conductivity type; a gate insulating layer that is sandwiched between the pair of the impurity diffusion regions and is provided on the semiconductor substrate; and a gate electrode provided on the gate insulating layer. A portion of the pair of the impurity diffusion regions has the same conductivity type as the impurity containing the substrate and has a higher impurity concentration than that of the substrate.

Description

  The present invention relates to a semiconductor device having a channel region containing Ge as a main component.

In next-generation LSI development, Ge is expected as a semiconductor substrate to replace Si. This is because the bulk mobility of electrons and holes is higher than that of Si. Therefore, if a Ge substrate is used, it is expected that a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a high surface mobility can be realized. In practice, a Ge pMISFET is a Si pMISFET. Higher mobility is shown. However, on the other hand, there is no example that Ge nMISFET has confirmed higher mobility than Si nMISFET. This is because an nMISFET has a high contact resistance between a metal and n ⁺ Ge, so that the performance of the original nMISFET cannot be sufficiently obtained.

There are several reasons why the contact resistance between the metal and n ⁺ Ge is high. One of them is that n ⁺ Ge with a high carrier (electron) concentration cannot be formed. The n-type impurity in Ge diffuses very quickly for the reason described in detail later, and the impurity cannot be maintained at a high concentration by heat treatment, so that the electron concentration cannot be increased. The contact resistance Rc has a relationship represented by the following equation with the electron concentration n.

Rc∝exp (C / (n ^1/2 )) (1)
Here, C is a constant that does not depend on the electron concentration. As can be seen from this equation, if the electron concentration n cannot be increased, the contact resistance Rc between the metal and n ⁺ Ge increases. In order to develop a Ge nMISFET, it is necessary to form an extremely shallow and high carrier concentration n ⁺ Ge, and for this purpose, diffusion of n-type impurities in Ge must be sufficiently suppressed.

As a related technique, in the solid phase diffusion method, a method is known in which an impurity layer having a desired concentration, depth, or conductivity type of the diffusion layer is formed in a controlled manner by changing the impurity diffusion coefficient ( Patent Document 1). The feature of this patent document lies in the method of solid phase diffusion, utilizing the property that As is difficult to diffuse when As-doped SiO ₂ contains hydrogen, and As is easily diffused when reduced by oxidation. Yes.

For example, when hydrogen is contained in SiO ₂ doped with As and B, As is difficult to diffuse when Si is diffused in a solid phase, B diffuses more than As. Since As is also easily diffused by oxidizing the SiO ₂ , n ⁺ Si due to As is formed on the surface side of Si, and p ⁻ Si due to B is formed on the inner side, that is, n ⁺ Si / p ⁻ Si. Will be formed.

However, this Patent Document 1 only shows an example of impurity diffusion in Si, and the characteristic n-type impurity diffusion in Ge is fast, p-type impurity diffusion is slow, No consideration is given to the suppression of diffusion of n-type impurities. The finally formed structure is n ⁺ Si / p ^- Si. Furthermore, since the method is limited to solid phase diffusion that requires high temperatures, the concentration profile of p-type impurities always increases as it approaches the surface, which is undesirable for forming an n ⁺ layer. Therefore, even if this method alone is applied to Ge as it is, it is difficult to form n ⁺ Ge on the pGe layer made of ultra-shallow and high-concentration electrons.

Japanese Patent No. 3131436

  The present invention has been made based on the above circumstances, and it is an object of the present invention to provide a semiconductor device having an n-type impurity diffusion region having a very shallow and high carrier concentration in a Ge layer, and a manufacturing method enabling the same. And

A semiconductor device according to one embodiment of the present invention includes a semiconductor substrate of one conductivity type of n-type and p-type,
A pair of impurity diffusion regions of a conductivity type different from the one conductivity type, selectively provided on the surface of the semiconductor substrate, and a gate insulating layer provided on the semiconductor substrate sandwiched between the pair of impurity diffusion regions; A gate electrode provided on the gate insulating layer, wherein at least part of the impurity diffusion region has the same conductivity type as the impurity contained in the substrate and has an impurity concentration higher than the impurity concentration of the substrate. It is characterized by having.

  A method for manufacturing a semiconductor device according to the second aspect of the present invention is a method for forming a high-concentration impurity diffusion region on the surface of a semiconductor layer containing Ge as a main component. A step of introducing an n-type impurity and a p-type impurity, and a step of introducing a heat treatment after introducing the n-type impurity and the p-type impurity to form an n-type impurity diffusion region in the semiconductor layer. And

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device by which the n-type impurity diffusion area | region which consists of ultra-shallow and high carrier (electron) density | concentration was formed in Ge layer can be provided, and its manufacturing method.

FIG. 6 is a schematic diagram of an impurity concentration profile for explaining a method of forming a n ⁺ Ge region made of shallow and high-concentration electrons by suppressing diffusion of P by B. (a) is before heat treatment, and (b) is after heat treatment. Show. The figure which shows before and after heat processing of the impurity concentration profile of P in Ge substrate. The carrier concentration profile corresponding to the impurity concentration profile of FIG. The figure which shows before and after heat processing of the impurity concentration profile in case P and B exist in Ge substrate. The impurity profile of P of FIG. 2 is a diagram comparing the diffusion distance when B is not present and when B is over the entire substrate. The carrier concentration profile corresponding to the impurity concentration profile of FIG. The figure which shows before and after the heat processing of an impurity concentration profile in case B exists in the area | region of the fixed depth of Ge substrate. FIG. 8 is a graph comparing the diffusion distances in the impurity profile of P in FIG. 2 when B is absent and when B is part of the substrate (FIG. 7). The carrier concentration profile corresponding to the impurity concentration profile of FIG. The figure shows the effect of B on the impurity concentration profile of P in a Ge substrate, with a diffusion time of 3 seconds. FIG. 10 is a diagram showing the influence of B on the impurity concentration profile of P in the Ge substrate, corresponding to the case without B in FIG. The carrier concentration profile corresponding to the impurity concentration profile of FIG. The carrier concentration profile corresponding to the impurity concentration profile of FIG. The figure shows the effect of B on the impurity concentration profile of P in a Ge substrate, with a diffusion time of 95 seconds. 14 is a diagram showing the influence of B on the impurity concentration profile of P in the Ge substrate, corresponding to the case without B in FIG. The carrier concentration profile corresponding to the impurity concentration profile of FIG. The carrier concentration profile corresponding to the impurity concentration profile of FIG. The figure shows the effect of B on the impurity concentration profile of P in a Ge substrate, with a diffusion time of 100 seconds. FIG. 19 is a diagram showing the influence of B on the impurity concentration profile of P in a Ge substrate, corresponding to the case without B in FIG. The carrier concentration profile corresponding to the impurity concentration profile of FIG. The carrier concentration profile corresponding to the impurity concentration profile of FIG. The figure shows the effect of B on the impurity concentration profile of P in a Ge substrate, with a diffusion time of 10 seconds. 22 shows the influence of B on the impurity concentration profile of P in the Ge substrate, corresponding to the case without B in FIG. The carrier concentration profile corresponding to the impurity concentration profile of FIG. The carrier concentration profile corresponding to the impurity concentration profile of FIG. In the carrier concentration profile of the Ge substrate formed by introducing both P and B, (a) shows a dose amount of B of 2 × 10 ¹⁴ cm ⁻² , and (b) shows 1 × 10 ¹⁵ cm ⁻² . Sectional drawing for demonstrating the method using ion implantation with the method of forming the n ^<+> Ge layer concerning 2nd Embodiment. FIG. 28 is a sectional view of a step following FIG. 27. FIG. 29 is a sectional view of a step following FIG. 28. FIG. 30 is a sectional view of a step following FIG. 29; FIG. 31 is a sectional view of a step following FIG. 30. In the method of forming the n ⁺ Ge layer according to the third embodiment, cross-sectional view for explaining a method using CVD. FIG. 33 is a sectional view of a step following FIG. 32. FIG. 34 is a sectional view of a step following FIG. 33. FIG. 35 is a sectional view of a step following FIG. 34. Sectional drawing of the MIS transistor which concerns on the 4th Embodiment of this invention. Sectional drawing of CMISFET concerning the 5th Embodiment of this invention. The perspective view of FinMISFET which concerns on the 6th Embodiment of this invention. The perspective view for demonstrating the method of forming the element area | region which concerns on 6th Embodiment. FIG. 40 is a perspective view showing a step subsequent to FIG. 39. The figure showing the impurity concentration (SIMS) profile in the state which ion-implanted P in Ge substrate. The figure showing the impurity concentration (SIMS) profile at the time of ion-implanting P in a Ge substrate, and heat-processing. The schematic diagram explaining the impurity concentration profile of B and P in the Ge substrate of FIG. 42, and the conductivity type profile of the semiconductor formed in that case. The schematic diagram explaining that the diffusion of P is suppressed by the high concentration B in the Ge substrate and the profile of the conductivity type of the semiconductor formed at that time.

Before describing the embodiments of the present invention, the background to the present invention will be described. As described above, in order to form n ⁺ Ge having a very shallow and high electron concentration, a technique for preventing the diffusion of n-type impurities during heat treatment is required.

The mechanism of diffusion of n-type impurities in Ge is explained as follows (for example, see H. Bracht, Phys. Rev. B 75, 035210 (2007)). The diffusion of the n-type impurity A in Ge is caused by positive ions A ⁺ _S at a substitutional site and a vacancy V ²⁻ having a divalent negative charge.
A ⁺ _S + V ^2- ⇔ (AV) ^- (2)
Are paired by the reaction expressed by the chemical equilibrium [the law of mass action] and diffuse in the form of (AV) ⁻ (dopant-vacancy pair). That is, no direct diffusion by A ⁺ _S, (AV) ^- indirectly diffuses through form (Diffusion vehicle) that. When considered as diffusion by A ⁺ _S , the diffusion equation is expressed by the following equations (3) and (4) having an effective diffusion coefficient D _eff .

Here, C _s ⁺ (x, t) is the concentration of positive ions of the n-type impurity at the lattice substitution position, and x is the coordinate of the n-type impurity (defined as the depth from the substrate surface in this specification), t is a diffusion time, n (x, t) is an electron concentration, ni (x, t; T) is an intrinsic carrier concentration (dependent on temperature T), and D ^* (ni) is a coefficient depending on ni. Thus, the effective diffusion coefficient of the n-type impurity has a dependence on the square of the electron concentration n. This is due to the difference in charge states between A ⁺ _S and (AV) ⁻ . The n-type impurity in Ge exhibits a peculiar diffusion phenomenon due to the dependence of D _eff on the square of the electron concentration. When there is only n-type impurity in Ge, it can be considered that the higher the impurity concentration, the higher the electron concentration. Therefore, from equation (4), D _eff increases when the impurity concentration is high, and D _eff decreases when the impurity concentration is low.

FIG. 41 shows an impurity concentration profile analyzed by SIMS when phosphorus (P) is ion-implanted into Ge and heat-treated. The dose amount of P is 5 × 10 ¹⁵ cm ⁻² , the acceleration energy is 30 keV, and heat treatment is performed in a nitrogen atmosphere at 600 ° C. for 30 minutes. For comparison, a simulation result before heat treatment, that is, only ion implantation is also shown. Before the heat treatment, the peak concentration is about 10 ²¹ cm ^−3, and the depth at which the concentration is 1 × 10 ¹⁹ cm ⁻³ is about 100 nm.

On the other hand, after the heat treatment, greatly reduced by 2 × 10 approximately ¹⁹ cm ^-3 at the peak concentration and the depth concentration of 1 × 10 ¹⁹ cm ^-3 is diffuses more than the 400 nm. What is characteristic here is the shape of the profile that should be called a box. The concentration gradually decreases from the surface to about 400 nm, but the concentration decreases sharply when the depth becomes deeper than that. This is because D _eff is proportional to n ² . That is, when the concentration is high, D _eff is large, so that diffusion is fast, and when the concentration is low, D _eff becomes small, so that it can be explained that a characteristic box profile is obtained.

Thus, if the diffusion of the n-type impurity in Ge diffuses through the form (AV) ⁻ and has a diffusion coefficient that depends on the square n ^{2 of the} electron concentration, the diffusion can be suppressed by canceling this negative charge. The present inventors thought that it might be possible. Therefore, boron (B) was selected as a p-type impurity to compensate for the n-type impurity and introduced into the Ge substrate to confirm whether P diffusion could be suppressed. The result is shown in FIG. The impurity profile of P in Ge into which B was introduced was determined by SIMS analysis. After introducing B into the Ge substrate at a dose of 5 × 10 ¹⁵ cm ⁻² and an acceleration energy of 30 keV, P is introduced and heat-treated under the same conditions as in FIG.

According to the results, first, the peak concentration of B is about 1 × 10 ²¹ cm ⁻³ , and it can be seen from the profile that it does not diffuse even when heat treatment is applied. There has been a report that BF ₂ is not diffused at all even when BF ₂ is ion-implanted into Ge at a dose of 4 × 10 ¹⁵ cm ⁻² and an acceleration energy of 20 keV and subjected to a heat treatment at 650 ° C. for 10 seconds. (See CO Chui et al., Appl. Phys. Lett. 83, 3275 (2003))), consistent with the results of the present invention.

The depth at which the P concentration is 1 × 10 ¹⁹ cm ⁻³ is about 100 nm, which is the same as the profile before the heat treatment. That is, P is not diffused at all. In the absence of B, the concentration of P decreased to 2 × 10 ¹⁹ cm ⁻³ (FIG. 41), but in the presence of B, P peaked as high as about 7 × 10 ²⁰ cm ^−3. Concentration is maintained. The reason why the concentration in the vicinity of the surface of P is slightly lower than that before the heat treatment is that P is diffused outward from the substrate surface, and diffusion to the back side in the substrate is suppressed. Yes. If an appropriate cap layer is formed on the substrate surface, the outward diffusion of P can be suppressed, and the impurity concentration of P can be maintained as high as before the heat treatment, so that a high electron concentration can be achieved.

Thus, based on the diffusion mechanism of the n-type impurity in Ge, it was found that the diffusion of the n-type impurity can be completely suppressed if the p-type impurity is introduced so as to cancel the (PV) ⁻ which is the diffusion form of the n-type impurity. . However, although diffusion of P is completely suppressed by B, as can be seen from FIG. 43, since the concentration of B is higher than P in the whole substrate, p ⁺ Ge is formed. Even if the diffusion of P can be suppressed, it is meaningless if n ⁺ Ge is not formed.

As a method of forming n ⁺ Ge while suppressing the diffusion of P, for example, a method as shown in FIG. 44 is conceivable. B is introduced as a p-type impurity at a high concentration in the back of the substrate, and P is introduced near the surface of the substrate as an n-type impurity. When heat treatment is applied, B does not diffuse, but P diffuses deep into the substrate. If the concentration of B is sufficiently higher than the concentration of P, diffusion of P is suppressed by B. Since the impurity concentration of P can be increased, the electron concentration can also be increased, and n ⁺ Ge is formed on the surface of the substrate. However, in this structure, n ⁺ Ge may be formed, but p ⁺ Ge is also formed at the same time because high concentration of B exists. That is, an n ⁺ Ge / p ⁺ Ge structure is formed, which cannot be applied to the source / drain.

The present inventors have solved the problems associated with the above discovery and found a method of forming an n ⁺ Ge structure having a very shallow and high carrier (electron) concentration without the presence of p ⁺ Ge. Moreover, an ideal n ⁺ Ge structure formed thereby could be found. This will be described below as an embodiment. While embodiments of the present invention will be described with reference to the drawings, common components are denoted by the same reference numerals throughout the embodiments, and redundant descriptions are omitted. In addition, in each drawing, there is a schematic diagram for facilitating the explanation and understanding of the present invention. Even if the shape, size, ratio, etc. are different from the actual device, these are the following explanation and publicly known. The design can be changed as appropriate in consideration of this technology.

In this specification, “mainly containing Ge” means that the Ge content is 85 at. % Or more. For example, in Semicond. Sci. Technol. 12 (1997) 1515-1549, the minimum value of the Si conduction band is the Δ point, the minimum value of the Ge conduction band is the L point, and SiGe depends on the composition ratio. In the case of Si _x Ge _1-x , it is reported that Δ <0.85 and L point when x> 0.85.

(First embodiment)
Here, a semiconductor device (substrate) having an n ⁺ Ge layer having a very shallow and high electron concentration according to the first embodiment of the present invention and a manufacturing method thereof will be described. FIG. 1 is a schematic diagram showing an impurity profile in a Ge substrate.

Fig.1 (a) has shown before heat processing. Two substrates, n-type impurity and p-type impurity, which are higher in concentration than the substrate concentration, are introduced into a substrate containing a constant and low concentration p-type impurity. At that time, the p-type impurity is introduced into the back side of the substrate, and the n-type impurity is introduced into the surface side of the substrate. Here, as a typical example, P is selected as the n-type impurity and B is selected as the p-type impurity. At this time, if each impurity in Ge is electrically activated, an n ⁺ Ge / p ⁺ Ge / p ⁻ Ge structure is formed as shown in the figure. It is not necessary that the impurities are electrically activated before the heat treatment. Unlike the case of FIG. 41, the concentration of each impurity is characterized in that the peak concentration of P is sufficiently higher than that of B.

When heat treatment is applied to this structure, as described above, P diffuses but B does not diffuse due to the characteristics of the n-type and p-type impurities in Ge. Further, since P in Ge diffuses indirectly through the form (PV) ⁻ , the profile is box-shaped and the concentration changes sharply. When P diffuses in a region where B is present at a high concentration, the negative charge is canceled by B. Therefore, diffusion in the form of (PV) ⁻ is less likely to occur, and the diffusion of P is delayed. When the heat treatment is further continued, P diffuses throughout the region where B is present at a high concentration as shown in FIG. Since the concentration of P can always be higher than that of B in Ge, n ⁺ Ge can be formed.

That is, first suppresses the diffusion of the n-type impurity with a p-type impurity, since the final n-type impurity can be made higher than the p-type impurity, without leaving the p ⁺ Ge region, from shallow high electron density N ⁺ Ge structure can be formed.

Next, how n ⁺ Ge according to the present invention is quantitatively formed and what kind of structure will be described. As described above, the diffusion of the n-type impurity in Ge is expressed by the diffusion equations (2) to (4). When p-type impurities coexist, the following may be considered in addition to them. First, it is assumed that the p-type impurity does not diffuse even after heat treatment. Further, it is assumed that Ge satisfies the equation (5) which is a charge neutral condition.

n + (N _A −p _A ) = p + (N _D −n _D ) (5)
Here, n is the electron concentration, p is the hole concentration, N _A is the p-type impurity concentration, N _D is the n-type impurity concentration, p _A is the hole density existing at the acceptor level, and n _D is the donor existing at the donor level. Density. Let n, p, p _A , and n _D be expressed by the statistical mechanics of a normal equilibrium system. Using this equation (5), the n-type impurity diffusion in Ge was calculated by the equation (3) while obtaining n at each coordinate of the Ge substrate and each time of diffusion. The influence of the p-type impurity coexisting with the n-type impurity is reflected through n determined from the equation (5).

<When only n-type impurities are present in the n ⁺ Ge layer>
FIG. 2 is an example of calculating the process of forming n ⁺ Ge according to the present embodiment, and shows the relationship between the impurity concentration and the depth. The calculation requires diffusion coefficients and the like, which were obtained by fitting with experimental values. FIG. 2 shows a case where only n-type impurities are present in Ge. Here, P was selected as an example of an n-type impurity. The initial profile (profile before heat treatment) of P is a Gaussian distribution with a projected range Rp of 5.0 nm from the Ge substrate surface, a standard deviation of 1.0 nm, and a dose of 1 × 10 ¹⁵ cm ^−2. Assumed. The heat treatment is assumed to be spike annealing for a short time (1 second). The temperature is 773K. The time evolution during the heat treatment was sufficiently (0, 0.1, 0.2,..., 1.0), and the change with time in the impurity concentration profile of P was shown.

When there is no B as in this example, as can be seen from the time-dependent change in the profile of FIG. The position where the concentration is 1 × 10 ¹⁹ cm ⁻³ before the heat treatment is 3.5 nm from Rp, but after 0.1 seconds, it spreads to 13.2 nm, and after 0.2 seconds, 16.8 nm and 0.3 seconds. Later, it spreads to 19.0 nm and diffuses to 27.2 nm after 1 second.

FIG. 3 shows the electron concentration profile under the same conditions as FIG. Similar to FIG. 2, the change in the electron concentration profile of P was shown with the time evolution during the heat treatment being fully divided. As can be seen from a comparison of FIG. 3 with FIG. 2, the impurity concentration and the electron concentration are almost the same at 7 × 10 ¹⁷ cm ⁻³ or more. This is because only P, which is an n-type dopant, is present in Ge, which is n ⁺ Ge consisting of only electrons from the surface to a depth of about 33 nm.

Note that the electron concentration here is that at a temperature at which impurities of 773 K diffuse. Therefore, it is considered that the impurity concentration is almost the same as the electron concentration, that is, almost 100% ionized. On the other hand, at room temperature, impurities may cause incomplete ionization, and the electron concentration may be lower than the impurity concentration. However, when the impurity concentration is high, there is no incomplete ionization of the impurity due to metal-insulator transition, that is, the impurity concentration and the electron concentration may be considered to be almost the same even at room temperature. The constant region where the electron concentration is 7 × 10 ¹⁷ cm ⁻³ is due to the intrinsic carrier concentration ni, which is lower than the substrate concentration at room temperature. If the substrate is a p-type with a normal concentration, the constant hole concentration region is Appears at room temperature.

<When n-type impurity and p-type impurity are present simultaneously in the n ⁺ Ge layer>
FIG. 4 shows a case where a p-type impurity is present simultaneously with an n-type impurity. In addition to the case of FIG. 2, p-type impurities coexist at a high concentration of 2.5 × 10 ²⁰ cm ^{−3 in} the entire Ge substrate. Here, B was selected as an example of the p-type impurity.

Even when B is present on the entire Ge substrate, as in the case where B is not present, it diffuses largely at the beginning and gradually diffuses slowly. However, when B is present, the diffusion rate is relatively slower than when B is absent. The position where the concentration is 1 × 10 ¹⁹ cm ⁻³ before the heat treatment is Rp et al. 3.5 nm, and after 0.1 second, it expands to 9.0 nm, after 0.2 second 10.6 nm, after 0.3 second Spreads to 11.4 nm and diffuses to 14.2 nm after 1 second.

FIG. 5 compares the diffusion distance of P when B is not present (FIG. 2) and when it is present (FIG. 4). When the concentration is 1 × 10 ¹⁹ cm ⁻³ , the respective diffusion distances at the same diffusion time (depth when Rp is taken as the origin) are plotted. As is apparent from the figure, the presence of B shortens the diffusion distance, and the difference increases as the distance increases, in other words, as the diffusion time increases. Thus, it can be seen that the presence of B suppresses diffusion.

FIG. 6 shows the same electron density profile as in FIG. Since B exists in the entire Ge substrate at a high concentration of 2.5 × 10 ²⁰ cm ⁻³ , the electron concentration is 2.8 × 10 ¹⁵ cm at a place where the P concentration is lower than the B concentration before the heat treatment. ^-3 . As can be seen from the equation (4), the effective diffusion coefficient is proportional to the square of the electron concentration, so that the lower the electron concentration, the slower the diffusion. When there is no B, it is 8.4 × 10 ¹⁷ cm ⁻³ , but when B is present, it is 2.8 × 10 ¹⁵ cm ⁻³ , and the electron concentration is reduced by two orders of magnitude or more. Therefore, the presence of B reduces the effective diffusion coefficient and slows diffusion.

Thus, the presence of B makes it possible to suppress the diffusion of P, and a shallower and higher concentration of n ⁺ Ge is formed on the surface than when there is no B. However, as can be seen from FIG. 4, since there is a region where the concentration of B is higher than that of P, this is n ⁺ Ge / p ⁺ Ge. The hole concentration p in p ⁺ Ge is obtained from the relational expression of FIG. 6 and the law of mass action np = ni ² (n is the electron concentration), which is 1.75 × 10 ²⁰ [= (7 × 10 ¹⁷ ) ² / (2.8 × 10 ¹⁵ )] cm ⁻³ . Furthermore, even if a high concentration of P exists, it is compensated by B, so that the electron concentration is lower than the impurity concentration of P.

<Method of forming n ⁺ Ge without forming p ⁺ Ge layer>
In order to form a shallow n ⁺ Ge with a high electron concentration without forming a p ⁺ Ge layer and without reducing the electron concentration on the surface, the profile of B may be adjusted. FIG. 7 shows the B profile adjusted. As shown in FIG. 3, B is not included in the whole, and the condition that the concentration is constant at 2.5 × 10 ²⁰ cm ⁻³ remains the same, and B is only at a depth of 7.3 nm to 18.9 nm from the surface. To exist. As can be seen from FIG. 7, the profile of P is almost the same as the profile of P in FIG. Further, FIG. 8 shows a comparison of the diffusion distance of P in the case where B is present only in part and in the case where B is not present, which is almost the same as FIG. That is, even if B is not included in the entire substrate but only in a part, it means that the effect of suppressing the diffusion of P is almost the same. Since B is included only in part, as can be seen from FIG. 4, the concentration of the P profile finally obtained after the heat treatment can be higher than that of B over the entire substrate.

FIG. 9 shows the same electron density profile as in FIG. In the similar drawings after FIG. 9, the notes before and after the heat treatment are omitted, but as in FIG. 2, the parabolic curve shows the pre-heat treatment, and the terrace-like curve shows the heat treatment. Unlike FIG. 6, the intrinsic carrier concentration is on the inner back side of the substrate, which is the same as FIG. That is, it can be seen that the inner side of the substrate is not p ⁺ Ge but a state of the original Ge substrate, for example, a pGe substrate containing a normal level of impurities. Further, compared with FIG. 6, the electron concentration is higher on the surface side. This is because B does not exist on the surface, so that the electron concentration does not decrease or lose, and therefore the electron concentration is almost the same as the impurity concentration of P. Since a high impurity concentration is maintained for P due to the diffusion suppressing effect of B, a higher electron concentration is realized than when P is not present.

In this way, if B is not introduced into the surface and the inner side of the substrate and introduced at an optimal concentration at an optimal concentration, diffusion of P is suppressed by B, and p ⁺ Ge is not left even if B exists. Further, it is possible to form an n ⁺ Ge layer composed of shallow and high-concentration electrons without reducing the surface electron concentration.

<Concentration of p-type impurity necessary for suppressing n-type impurity>
Next, how much p-type impurities are necessary to suppress n-type impurities will be described. Again, P was selected as the n-type impurity and B was selected as the p-type impurity. The initial profile of P (profile before heat treatment) was assumed to be a Gaussian distribution with a Rp of 5.0 nm, a standard deviation of 1.0 nm, and a dose of 1 × 10 ¹⁴ cm ⁻² from the surface of the Ge substrate. The diffusion temperature is 773K. The case where the density | concentration of B was changed in three ways was shown. B assumed the case where it did not exist from the Ge substrate surface to the position of Rp of P.

First, FIG. 10 shows a case where B is added at a concentration of 5 × 10 ¹⁹ cm ⁻³ from Rp (5 nm) to 10 nm. The diffusion time was 3 seconds. For example, the position where the P concentration is 1 × 10 ¹⁸ cm ⁻³ was 8.8 nm before the heat treatment, but diffused to 10.4 nm after the heat treatment, and only 1.6 nm due to the difference before and after the heat treatment. It is spreading.

FIG. 11 shows the case where only B is removed from the case of FIG. The position where the P concentration is 1 × 10 ¹⁸ cm ⁻³ is the same 8.8 nm before the heat treatment and diffuses to 14.8 nm after the heat treatment. The diffused distance is 6.0 nm. That is, in the absence of B, diffusion is performed by 6.0 nm, but due to the presence of B of 5 × 10 ¹⁹ cm ⁻³ , the diffusion is suppressed by only 1.6 nm.

The electron concentration profiles corresponding to the impurity concentration profiles of FIGS. 10 and 11 at this time are FIGS. 12 and 13, respectively. In the absence of B (FIG. 13), the position where the electron concentration is 1 × 10 ¹⁸ cm ⁻³ is 10.4 nm, corresponding to the impurity concentration profile (FIG. 11). On the other hand, when B is present (FIG. 12), the n ⁺ Ge region extends to 14.8 nm corresponding to the impurity concentration profile (FIG. 10). Further, as can be seen from the figure, the electron concentration is lower than the intrinsic carrier concentration (the hole concentration is higher), that is, p ⁺ Ge is formed since it is compensated by B during the diffusion. At that time, since the electron concentration is low, it diffuses slowly, and finally there is no region where the electron concentration is lower than the intrinsic carrier concentration, that is, there is no p ⁺ Ge region, and n ⁺ Ge consisting of an extremely shallow and high electron concentration. Only formed.

FIG. 14 shows a case where the B concentration is reduced to 1 × 10 ¹⁹ cm ⁻³ as compared with FIG. B was added from Rp to 25.3 nm. As expected from the contents so far, the lower the B concentration, the wider the region where P diffuses, so it is better to widen the region where B is inserted. The diffusion time was 95 seconds. For example, the position where the P concentration is 1 × 10 ¹⁸ cm ⁻³ was 8.8 nm before the heat treatment, but diffused to 25.4 nm after the heat treatment, and the difference between before and after the heat treatment is only 17.0 nm. It is spreading.

FIG. 15 shows the case where only B is removed from the case of FIG. The position where the P concentration is 1 × 10 ¹⁸ cm ⁻³ is the same 8.4 nm before the heat treatment and diffuses to 32.2 nm after the heat treatment. The diffused distance is 23.2 nm. In other words, when there is no B, it diffuses 23.2 nm, but with the presence of B of 1 × 10 ¹⁹ cm ⁻³ , it is suppressed only by 17.0 nm.

The electron concentration profiles corresponding to the impurity concentration profiles of FIGS. 14 and 15 at this time are FIGS. 16 and 17, respectively. In the absence of B (FIG. 17), the position where the electron concentration is 1 × 10 ¹⁸ cm ⁻³ is 32.2 nm, corresponding to the impurity concentration profile (FIG. 15).

On the other hand, when B exists (FIG. 16), the n ⁺ Ge region extends to 25.4 nm corresponding to the impurity concentration profile (FIG. 14). Further, as can be seen from the figure, the electron concentration is lower than the intrinsic carrier concentration (the hole concentration is higher), that is, p ⁺ Ge is formed since it is compensated by B during the diffusion. At that time, since the electron concentration is low, it diffuses slowly, and finally there is no region where the electron concentration is lower than the intrinsic carrier concentration, that is, there is no p ⁺ Ge region, and n ⁺ Ge consisting of an extremely shallow and high electron concentration. Only formed.

FIG. 18 shows a case where the B concentration is further reduced to 1 × 10 ¹⁸ cm ⁻³ as compared with FIGS. 10 and 14. B is contained from Rp to 31.8 nm. As described above, the lower the B concentration, the wider the region where P diffuses, so it is better to widen the region where B is inserted. The diffusion time was 100 seconds. For example, the position where the P concentration is 1 × 10 ¹⁸ cm ⁻³ was 8.8 nm before the heat treatment, but diffused to 31.6 nm after the heat treatment, and the difference between before and after the heat treatment is only 22.8 nm. It is spreading.

FIG. 19 shows only the case where B is omitted from the case of FIG. The position where the P concentration is 1 × 10 ¹⁸ cm ⁻³ is the same 8.8 nm before the heat treatment and diffuses to 32.6 nm after the heat treatment. The diffused distance is 23.8 nm. In other words, when there is no B, the diffusion is 23.8 nm, but the presence of B of 1 × 10 ¹⁸ cm ⁻³ is suppressed only by the diffusion of 22.8 nm.

The electron concentration profiles corresponding to the impurity concentration profiles of FIGS. 18 and 19 at this time are FIGS. 20 and 21, respectively. In the absence of B (FIG. 21), the position where the electron concentration is 1 × 10 ¹⁸ cm ⁻³ is 32.6 nm, corresponding to the impurity concentration profile (FIG. 19). On the other hand, when B is present (FIG. 20), the position where the electron concentration is 1 × 10 ¹⁸ cm ⁻³ is 31.6 nm corresponding to the impurity concentration profile (FIG. 18). Further, as can be seen from the figure, the electron concentration n is lower (the hole concentration p is higher) than the intrinsic carrier concentration ni, that is, p ⁺ Ge is formed since it is compensated by B during the diffusion. At that time, since the electron concentration is low, it diffuses slowly, and finally there is no region where the electron concentration is lower than the intrinsic carrier concentration, that is, there is no p ⁺ Ge region, and n ⁺ Ge consisting of an extremely shallow and high electron concentration. Only formed.

Thus, in order to shorten the P diffusion distance, the higher the B concentration, the better. The upper limit of the B concentration for suppressing the diffusion of P to form n ⁺ Ge is extremely lower than the concentration Cn (x, 0) of P before the heat treatment (Cn (x, 0)). > Cp (x, 0)), or diffused after heat treatment so that the P concentration is higher than B (Cn (x, t)> Cp (x, t)). Here, Cn (x, t) and Cp (x, t) are impurity concentrations at a depth x and a diffusion time t of P and B, respectively. Before the heat treatment, the B concentration may be higher than P as long as it is in the direction of diffusion. Further, the minimum B concentration Cp (x, 0) for suppressing the diffusion of P is effective if it is higher than the intrinsic carrier concentration ni (x, 0; T) at the diffusion temperature T (Cp (x, 0)> ni (x, 0; T)).

A rectangular region having a constant concentration is considered as a profile of B for suppressing the diffusion of P. As described above, this is a region where the profile of the n-type impurity is a constant concentration due to the n-type impurity diffusion mechanism in Ge. This is because the density decreases steeply from a so-called box profile. More desirably, when the profile of the p-type impurity is brought close to the profile of the n-type impurity to be finally obtained, n ⁺ Ge composed of shallower and high-concentration electrons can be formed.

So far, the example of the time when the diffusion suppression of P by B is most suitable has been shown. Here, it is shown how the profile of P becomes when the optimum time is greatly exceeded. FIG. 22 shows a case where only the diffusion time is different from FIG. In FIG. 10, the diffusion time is 3 seconds, but in FIG. 22, it is 10 seconds. As can be seen from FIG. 22, the diffusion of P is advanced from FIG. For example, the position where the P concentration is 1 × 10 ¹⁸ cm ⁻³ was 8.8 nm before the heat treatment, but moved to 13.8 nm after the heat treatment. It is spreading.

In FIG. 22, 23 is obtained by eliminating only B. The position where the P concentration is 1 × 10 ¹⁸ cm ⁻³ is the same 8.4 nm before the heat treatment and diffuses to 18.9 nm after the heat treatment. The diffused distance is 10.5 nm. In other words, in the absence of B, 10.5 nm is diffused, but due to the presence of B of 1 × 10 ¹⁹ cm ⁻³ , it is suppressed only by 5.0 nm diffusion. What should be noted here is that, as is clear from FIG. 22, even if P diffuses far beyond a region where B is present, the concentration of B does not exceed the concentration of P.

The electron concentration profiles corresponding to the impurity concentration profiles of FIGS. 22 and 23 are FIGS. 24 and 25, respectively. In the absence of B (FIG. 25), the position where the electron concentration is 1 × 10 ¹⁸ cm ⁻³ is 18.9 nm, corresponding to the impurity concentration profile (FIG. 23). On the other hand, when B is present (FIG. 24), the n ⁺ Ge region extends to 13.8 nm corresponding to the impurity concentration profile (FIG. 22). Further, as can be seen from the figure, the electron concentration is lower than the intrinsic carrier concentration (the hole concentration is higher), that is, p ⁺ Ge is formed since it is compensated by B during the diffusion. At that time, since the electron concentration is low, it diffuses slowly, and finally there is no region where the electron concentration is lower than the intrinsic carrier concentration. In this case, P further diffuses into a region on the inner side of the substrate where there is no B. However, since the concentration of P is low at this position, the diffusion of P is slow.

  Further, although a slight decrease in electron concentration is observed at a place where B transitions from a region to a region where B does not exist, the electron concentration is still higher than the intrinsic carrier concentration and sufficiently higher than the substrate concentration at room temperature. This is because a B profile that sharply drops from a high concentration to zero is assumed. In reality, since the concentration continuously changes, the electron concentration does not specifically decrease in this way. .

In this way, even when the optimum time for suppressing the diffusion of P is greatly exceeded, p ⁺ Ge is not formed, and there is a sufficient effect of suppressing the diffusion as compared with the case without B. Only n ⁺ Ge having a high electron concentration can be formed.

<Carrier concentration profile of Ge with P and B introduced>
FIG. 26 shows a carrier concentration profile of Ge formed by introducing P and B. Obtained by Spreading resistance probe analysis. The dose amount of P is 5 × 10 ¹⁵ cm ⁻² , and heat treatment is performed for 30 minutes in a nitrogen atmosphere. In FIGS. 26A and 26B, the dose amount of B is 2 × 10 ¹⁴ and 1 × 10 ¹⁵ cm ⁻² , respectively. The heat treatment temperature was 400, 500, and 600 ° C. Also, the carrier concentration profile in the absence of B was examined under all conditions. Carriers present at a high concentration on the substrate surface side are all electrons, and a constant concentration region existing on the inner side of the substrate is a hole generated by impurities (Ga) contained in the substrate.

First, it can be seen from FIGS. 26A and 26B that as the temperature is increased to 400, 500, and 600 ° C., a region where electrons are present at a higher concentration spreads inwardly of the substrate. Moreover, when the case with B is compared with the case without B, the diffusion with B is suppressed. The tendency strongly depends on the dose amount of B. When the dose amount of B is 1 × 10 ¹⁵ cm ⁻² rather than 2 × 10 ¹⁴ cm ⁻² , diffusion is suppressed at each heat treatment temperature. Further, all the high concentration regions are electrons, and even if B is present, n ⁺ Ge without p ⁺ Ge can be formed.

(Second Embodiment)
In the second embodiment, an embodiment of a method for forming an n-type impurity layer will be described. First, B ions are implanted into the p-type Ge substrate 1 (FIG. 27). At this time, the acceleration energy of the ion implantation is adjusted, and the ion implantation is performed inward from the substrate surface. As a result, a high-concentration layer 2 of B is formed on the inner side from the surface of the p-type Ge substrate 1 (FIG. 28). Subsequently, P ions are implanted into the p-type Ge substrate 1 (FIG. 29). The acceleration energy is adjusted, and the surface is implanted on the surface side of the B high concentration layer 2. On the p-type Ge substrate 1, a high-concentration layer 3 of P is formed on the surface side, and a high-concentration layer 4 of B is formed on the back side of the substrate (FIG. 30). When this substrate is heat-treated, P diffuses but is suppressed by B. Eventually, since P has a higher concentration than B, the p ⁺ Ge region is eliminated, and the shallow and high electron concentration is increased. An n ⁺ Ge layer is formed (FIG. 31). This n ⁺ Ge layer contains more p-type impurities than those contained in the substrate 1.

(Third embodiment)
In the third embodiment, another method for forming an n-type impurity diffusion layer will be described. First, Ge doped with B is deposited on the p-type Ge substrate 1 by CVD (FIG. 32). Then, a p ⁺ Ge layer 6 is formed on the surface of the p-type Ge substrate 1 (FIG. 33). Subsequently, Ge doped with P is deposited by CVD. An n ⁺ Ge layer 7 is formed on the p ⁺ Ge layer 6 (FIG. 34). At this time, when the substrate is heated or deposited and then heat-treated, an n ⁺ Ge layer 8 composed of shallow and high-concentration electrons is formed by the above-described effect (FIG. 35). In this process, if the n ⁺ Ge layer 7 in FIG. 34 is deposited without forming the p ⁺ Ge 6 in FIG. 33, the n-type impurity diffuses quickly, so that it diffuses into the inner side of the p-type Ge substrate 1. put away, shallow n ⁺ GE8 made of a high concentration of electrons can not be formed. If the p + Ge layer 6 is formed as in this process, it is possible to prevent P from diffusing to the back of the substrate when depositing Ge doped with P.

  As described above, according to the first to third embodiments, by controlling the concentration and distribution of the p-type impurity, it is possible to form an n-type region that is extremely shallow and has a high concentration carrier density.

(Fourth embodiment)
FIG. 36 is a schematic cross-sectional view of a semiconductor device (MISFET) using the above-described n ⁺ Ge layer. The semiconductor device according to the fourth embodiment includes a p-type semiconductor 10 mainly composed of Ge formed on a substrate, a gate insulating layer 12 formed on the p-type semiconductor 10, and a gate insulating layer 12. A pair of n-type selectively formed on the surface of the p-type semiconductor 10 so as to sandwich a boundary region between the gate electrode 14 formed on the gate electrode 12 and the gate insulating layer 12 of the p-type semiconductor 10 from both sides in the gate length direction. Impurity diffusion regions (source / drain regions) 18 are provided. This semiconductor device contains n-type impurities in all or part of the n-type impurity diffusion region 18 and at the same time contains a higher concentration of p-type impurities than that contained in the p-type semiconductor. A contact electrode 16 is joined to the surface of the n-type impurity diffusion region.

  In the p-type semiconductor 10, the entire substrate is Ge, or at least the substrate surface is mainly composed of Ge, and contains p-type impurities. Further, the p-type impurity may be present in the entire n-type impurity region, but it is preferable that the p-type impurity is not present on the substrate surface in order to increase the electron concentration and reduce the contact resistance. Furthermore, a so-called LDD, n-type extension, or halo layer may be formed around the n-type impurity region.

  According to the present embodiment, the n-type source / drain region 18 having a very shallow and high concentration carrier density can be formed by controlling the concentration and distribution of the p-type impurity. As a result, in the fine Ge channel semiconductor device, it is possible to suppress the short channel effect and reduce the parasitic resistance, and it is possible to provide a MISFET having a high current driving capability.

(Fifth embodiment)
FIG. 37 is a schematic sectional view of a CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor) using the above-described n ⁺ Ge layer and p ⁺ Ge layer.

More specifically, FIG. 37 shows a cross-sectional view in the gate length direction of a CMISFET having a Ge channel. A p-type well region 102 and an n-type well region 104 made of Ge are formed on the upper surface (main surface) of the substrate 100 by being electrically separated by an element isolation layer 106. The substrate 100 may be a Ge substrate, an Si substrate, an Si substrate formed with a Ge layer, an SiGe layer intermediate layer formed on an Si substrate, and a Ge layer formed thereon. Good. The element isolation layer 106 is made of, for example, SiO ₂ . An n-channel MIS transistor is formed in the p-type well region 102, and a p-channel MIS transistor is formed in the n-type well region 104.

  As a configuration of the n-channel MIS transistor, a pair of n-type extension regions 108 are formed on both sides of the gate length of a region (channel region) serving as a current path in the p-type well region 102, and a pair of n-type extension regions are formed outside these regions. A deep region 110 is formed. On the upper surface of the p-type well region 102, a gate insulating film 116 is formed on the channel region so as to cover the ends of the opposing n-type extension regions 108 and 108 on the inner side in the gate length direction. A gate electrode 118 is stacked on the upper surface of the gate insulating film 116. Gate sidewalls 124 are formed on both sides of the gate insulating film 116 and the gate electrode 118.

  The n-type deep region 110 is configured such that the junction depth with the p-type well region 102 is deeper than the n-type extension region 108. The n-type extension region 108 and the n-type deep region 110 become the source / drain regions of the n-channel MIS transistor.

  Similarly, the p-channel MIS transistor has a configuration in which a pair of p-type extension regions 112 are formed in the n-type well region 104 on both sides in the gate length direction of a region serving as a current path (channel region). A pair of p-type deep regions 114 are formed. On the upper surface of the n-type well region 104, a gate insulating film 120 is formed on the channel region so as to cover the ends of the pair of p-type extension regions 112, 112 on the inner side in the gate length direction. A gate electrode 122 is stacked on the upper surface of the gate insulating film 120. Gate sidewall insulating films 126 are formed on both sides of the gate insulating film 120 and the gate electrode 122.

  The p-type deep region 114 is configured so that the junction depth with the n-type well region 104 is deeper than the p-type extension region 112. The p-type extension region 112 and the p-type deep region 114 become the source / drain regions of the p-channel MIS transistor.

The n-channel MIS transistor and the p-channel MIS transistor are covered with an interlayer insulating film 130.

  In the present embodiment, either or both of the n-type extension region 108 and the n-type deep region 110 are formed according to the above-described embodiment, and include a p-type dopant. The p-type dopant may be the same as the p-type dopant contained in the p-type extension region 112 and the p-type deep region 114.

  Next, a method for manufacturing the CMISFET will be described with reference to FIG. First, the element isolation layer 106 is formed on the main surface of the substrate 100. The substrate may be a Ge substrate, a Si substrate, a Si substrate formed with a Ge layer, or a Si substrate with an intermediate layer of the SiGe layer sandwiched between them. The formation method of the element isolation layer 106 may be a local oxidation method or an STI (Shallow Trench Isolation) method, and the shape of the element isolation layer 106 may be a mesa type. After forming the element isolation layer 106, the p-type well region 102 and the n-type well region 104 are formed. For forming the p-type well region 102 and the n-type well region 104, a normal ion implantation method for the Ge layer may be used, or ion implantation may be performed after the Ge layer is epitaxially grown.

  Next, gate insulating films 116 and 120 are formed on the upper surfaces of the p-type well region 102 and the n-type well region 104. As for the method of forming the gate insulating films 116 and 120, for example, a Ge oxide film may be formed by a thermal oxidation method, a Ge oxynitride film may be formed by a plasma oxynitride method, or Hf, Zr, La A high dielectric constant film made of an oxide containing a metal element selected from Y, Y, Al, etc. may be deposited by a CVD (Chemical Vapor Deposition) method. Thereafter, a single-layer or multilayer conductive film to be the gate electrodes 118 and 122 is formed on the upper surfaces of the gate insulating films 116 and 120 by using an existing film formation technique. Here, the following method is used as an example. Tantalum carbide is formed on the gate electrode 118 (for n-channel MIS transistor), tungsten is formed on the gate electrode 122 (for p-channel MIS transistor), and a film of 10 nm is formed by PVD (Physical Vapor Deposition). Thereafter, a titanium nitride film is formed to a thickness of 10 nm on the upper surface by PVD. Further, after that, a polycrystalline Si layer is formed to a thickness of 50 nm on the upper surface by a low pressure CVD method.

  For the gate electrode 118 (for n-channel MIS transistor), tantalum silicide, tantalum nitride silicide, titanium nitride silicide, tungsten silicide, tungsten nitride silicide, or the like can be used. For the gate electrode 122 (for p-channel MIS transistor), ruthenium, titanium nitride, titanium aluminum nitride, platinum, platinum iridium, or the like can be used.

  Thereafter, patterning is performed by photolithography, unnecessary films are removed by anisotropic etching, and gate electrodes 118 and 122 are formed. Thereafter, for example, the sidewall insulating film 124, the n-type extension region 108, and the n-type deep region 110 are formed using the method according to the above-described embodiment.

  Next, source / drain regions of the p-channel MIS transistor are formed by a self-aligned gate method. Here, the “self-aligned gate method” is a method of first forming a gate stack and then forming source / drain regions by ion implantation or the like. That is, boron (B) ions are implanted using the gate electrode 122 as an umbrella to form the p-type extension region 112 of the p-channel MIS transistor. Thereafter, a sidewall insulating film 124 is formed for insulation between the gate electrode 122 and the source / drain regions (p-type extension region 112 and p-type deep region 114). Thereafter, boron (B) is ion-implanted with a larger acceleration voltage than when the p-type extension region 112 is formed, and the p-type deep region 114 is formed.

  As an activation process temperature of the source / drain regions (n-type extension region 108, n-type deep region 110, p-type extension region 112, and p-type deep region 114), a gate stacked portion (gate insulating film 116, gate electrode 118) is used. The gate insulating film 120 and the gate electrode 122) and the temperature at which the characteristics of the np junctions of the source / drain regions are not deteriorated are desirable, for example, 600 ° C.

  As a method for activating the source / drain regions, flash lamp annealing, laser annealing, or the like can be used. According to these, since the activation of impurities in the semiconductor can be realized in a shorter processing time, the gate electrodes 118, 122 / gate insulating film 116, 120 / semiconductor (p-type well region 102, n-type well region 104, Deterioration due to heat of the semiconductor device having the structure of the n-type extension region 108, the n-type deep region 110, the p-type extension region 112, and the p-type deep region 114) can be reduced.

Thereafter, a Si oxide film to be the interlayer insulating film 130 is deposited by low pressure CVD, and the upper ends of the gate electrodes 118 and 122 are exposed by CMP (Chemical Mechanical Planarization). Thereafter, a nickel layer is formed to a thickness of 50 nm on the upper surfaces of the gate electrodes 118 and 122 by sputtering or the like. Thereafter, by performing a low-temperature heat treatment at 500 ° C., silicide is formed from the interface region between nickel and polycrystalline Si, and Ni ₂ Si is formed. Here, in the present embodiment, all of the polycrystalline Si is converted into silicide. However, only a part of the polycrystalline Si may be silicided by reducing the film thickness of Ni. Thereafter, unreacted Ni is removed using a mixed solution of sulfuric acid and hydrogen peroxide solution or the like.

  A CMOSFET semiconductor device having the structure shown in FIG. 37 is manufactured by the manufacturing method described above. By controlling the concentration and distribution of the p-type dopant, it is possible to form n-type source / drain regions (n-type extension region 108 and n-type deep region 110) that are extremely shallow and have a high concentration of carrier density. As a result, in the fine Ge channel semiconductor device, it is possible to suppress the short channel effect and reduce the parasitic resistance, and the current driving capability is increased.

(Sixth embodiment)
FIG. 38 is a schematic perspective view of a FinMISFET according to the sixth embodiment. The present embodiment is an example in which the above-described n ⁺ Ge / pGe structure is applied to a FinMISFET. More specifically, in FIG. 38, 208 is a support substrate, 209 is an insulating layer, 210 is a Ge layer, and 208 to 210 form a GOI (Germanium on Insulator) substrate 211. A linear (cuboid) element region 202 is formed by processing the GOI layer 210. A gate electrode 204 is formed in the central portion of the element region 202 through a gate insulating film 203. The portion of the element region 202 sandwiching the gate electrode 204 becomes the source / drain region 205.

Next, a method for manufacturing the FinMISFET of this embodiment will be described. First, as shown in FIG. 39, for example, B ions are implanted into the GOI layer 210 at 100 keV and 2.0 × 10 ¹² cm ⁻² , and then, for example, a thermal process is performed at 500 ° C. for 30 seconds. Subsequently, for example, by performing anisotropic etching such as RIE (reactive ion etching), the GOI layer 210 in a region other than the device region 202 is removed, and the device region 202 is formed.

Next, as shown in FIG. 39, for example, a HfO ₂ film 212 having a thickness of, for example, 5 nm is formed by using a method such as a CVD method (chemical vapor deposition method). Next, as shown in FIG. 40, a refractory metal film such as tungsten having a thickness of 100 nm, for example, is deposited on the HfO ₂ film 212 by, eg, CVD, and anisotropic etching such as RIE is performed. As a result, the refractory metal film is processed to form the gate electrode 204. Subsequently, the HfO ₂ film 212 is processed to form a gate insulating film 203 by performing anisotropic etching such as RIE.

Next, as in the first embodiment, for example, B is implanted into the entire surface from above the substrate, and then P is implanted. The order of implantation of P and B may be reversed. At this time, after the P implantation, the gate electrode 204 and the gate insulating film 212 may be further finely processed by the RIE method or the like. If B is subsequently implanted, only B can be introduced into the channel side of the GOI layer 210. Then, if the source / drain region 5 made of n ⁺ Ge is formed by a thermal process, a MOSFET is formed. In this way, the surface can be made of n ⁺ Ge with a high carrier concentration, and since P diffusion can be suppressed, lateral diffusion into the channel region can also be suppressed. Thereafter, the semiconductor device is formed through a normal interlayer insulating film forming process, a wiring hole opening process, a wiring process, and the like.

According to the present embodiment, the source / drain region 5 made of n ⁺ Ge can be formed extremely shallow and with a high carrier concentration, and a high-performance FinMISFET can be provided.

  Note that P is taken as an example of the n-type impurity throughout the embodiment, but other types may be used, for example, one or more of As, Sb, Bi, and the like. The p-type impurity is the same, and may be other, for example, one or more of B, Al, Ga, In and the like. In the present invention, the temperature 773K at which B does not diffuse is assumed. However, if the diffusion is slower than P, the temperature is effective even at a high temperature at which B diffuses. Although examples of CVD and ion implantation have been shown as methods for introducing impurities, other methods may be used.

  The substrate is a p-type semiconductor mainly composed of Ge, but may be an n-type semiconductor or another semiconductor such as a compound semiconductor. What becomes an n-type impurity for the semiconductor is paired with a vacancy like the diffusion mechanism of the n-type impurity in Ge described in the present invention, and cancels the charge if it is charged. If p-type impurities are used in the same manner as in the present invention, the same effects as in the present invention can be obtained, diffusion of n-type impurities can be suppressed, and an extremely shallow n-type impurity region with a high carrier concentration can be formed.

  In addition, as a semiconductor, a semiconductor containing Ge as a main component has been described as an example, but a compound semiconductor may be used. Examples of compound semiconductors include III-V semiconductors such as GaAs, InP, InSb, GaN, and InGaAs. In GaAs, Zn is used as a p-type dopant, and Si is used as an n-type dopant, for example. The diffusion of Zn in GaAs is explained by the kick-out mechanism expressed by the following chemical equilibrium [see, for example, H. Bracht et al., Physica B, 308, 831 (2001)].

Zn ⁺ _i ⇔ Zn ^- _Ga + I ²⁺ _Ga (6)
Where Zn ⁺ _i Is interstitial Zn, Zn ⁻ _Ga is Zn occupying Ga site, and I ²⁺ _Ga is self-interstitial Ga. Zn ⁺ _i Diffuses between the lattices, Ga is kicked out between the lattices (I ²⁺ _Ga ), and Zn enters the vacant site of _Ga (Zn ⁻ _Ga ). Although there is a report that Zn follows a kink-and-tail mechanism at a high concentration exceeding 10 ²⁰ cm ⁻³ , in any case, in order to prevent diffusion of Zn acting as a p-type dopant, the charge is compensated, that is, canceled. Thus, Si that works as an n-type dopant may be introduced. Since the diffusion coefficient of Zn is large, when combined with Si having a small diffusion coefficient, by the effect of the present invention, the diffusion of Zn is initially suppressed by Si, and finally, shallow and high carrier concentration p ⁺ GaAs can be formed. .

Further, the case where the p-type impurity layer is formed on the inner side of the Ge substrate has been described. However, the p-type impurity layer is formed on the surface side of the p-type semiconductor substrate, and the n-type impurity is diffused outward during the heat treatment. That is, it can also be used as a barrier layer that suppresses diffusion from the surface to the outside. At this time, the p-type impurity layer may be Ge containing p-type impurities, Si, or SiO ₂ . After the heat treatment, the p-type impurity layer may be removed.

Further, the p-type impurity layer may be formed not only to suppress the diffusion of n-type impurities into the back side of the substrate but also to suppress the diffusion in the lateral direction with the channel. In that case, a p-type impurity is contained on the channel side of the n-type impurity diffusion layer. Further, p-type impurities may be used so as to prevent n-type impurities from escaping in the element isolation direction and lowering the impurity concentration. In that case, the n-type impurity diffusion layer has a structure including a p-type impurity on the element isolation side. As described above, the p-type impurity is formed in a direction to prevent the diffusion of the n-type impurity, and after suppressing the diffusion, the n-type impurity can be compensated so that only n ⁺ Ge is formed.

In addition, the above description can be applied not only to the formation of the n ⁺ layer but also to the formation of the p ⁺ layer as long as n and p are reversed and the signs of the positive and negative signs are reversed. If the n-type impurity diffuses faster than the p-type impurity, the p-type impurity can be used to suppress the diffusion of the n-type impurity, and conversely if the p-type impurity diffuses faster than the n-type impurity, the n-type impurity becomes p This is because it can be used to suppress diffusion of type impurities. That is, by using a low-diffusion impurity to suppress diffusion of a fast-diffusion impurity, it is possible to form a shallow and high-carrier concentration impurity diffusion layer made of a fast-diffusion impurity.

  The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. In other words, those specific examples that have been appropriately modified by those skilled in the art are also included in the scope of the present invention as long as they have the characteristics of the present invention. For example, the elements included in each of the specific examples described above and their arrangement, materials, conditions, shapes, sizes, and the like are not limited to those illustrated, but can be changed as appropriate.

  The above-described embodiments can be combined as far as technically possible, and combinations thereof are also included in the scope of the present invention as long as they include the features of the present invention.

DESCRIPTION OF SYMBOLS 1 ... p-type Ge board | substrate, 2 ... Ge layer where high concentration B exists, 3 ... Ge layer where high concentration P exists 4 ... Ge layer where high concentration P and B coexist, 5 ... p-type impurity Including n ⁺ Ge layer, 6 ... p ⁺ Ge layer,
7 ... n ⁺ Ge layer, 8 ... n ⁺ Ge layer containing p-type impurities, 10 ... p-type semiconductor substrate, 12 ... gate insulating layer, 14 ... gate electrode, 16 ... contact electrode, 18 ... n-type impurity diffusion region, DESCRIPTION OF SYMBOLS 100 ... Substrate, 102 ... p-type well region, 104 ... n-type well region, 106 ... Element isolation layer, 108 ... n-type extension region, 110 ... n-type deep region, 112 ... p-type extension region, 114 ... p-type deep Region 116, gate insulating film 118, gate electrode 120, gate insulating film 122, gate electrode 124, 126, gate sidewall insulating film 130, interlayer insulating film 202, element (semiconductor) region 203, gate Insulating film, 204 ... gate electrode, 205 ... source / drain region, 208 ... support substrate, 209 ... embedded insulating layer, 210 ... Ge layer, 211 ... GO Board, 212 ... HfO ₂ film

Claims (8)

a semiconductor substrate of one of n-type and p-type conductivity,
A pair of impurity diffusion regions selectively provided on the semiconductor substrate surface and having a conductivity type different from the one conductivity type;
A gate insulating layer provided on the semiconductor substrate sandwiched between the pair of impurity diffusion regions;
A gate electrode provided on the gate insulating layer;
And at least a part of the impurity diffusion region has the same conductivity type as the impurity contained in the substrate and has an impurity concentration higher than the impurity concentration of the substrate. A p-type semiconductor layer mainly composed of Ge;
A pair of n-type impurity diffusion regions selectively provided on the surface of the p-type semiconductor layer;
A gate insulating film provided on the p-type semiconductor layer sandwiched between the pair of n-type impurity diffusion regions;
A gate electrode provided on the gate insulating film;
And at least part of the n-type impurity diffusion region has a p-type impurity concentration higher than a p-type impurity concentration of the p-type semiconductor.   3. The semiconductor device according to claim 2, wherein the concentration of the p-type impurity contained in the n-type impurity diffusion region is higher on the inner side than on the surface side of the n-type diffusion region. A method of forming a high-concentration impurity diffusion region on the surface of a semiconductor layer containing Ge as a main component,
Introducing n-type impurities and p-type impurities into the surface of the semiconductor layer;
Forming an n-type impurity diffusion region in the semiconductor layer by introducing a heat treatment after introducing the n-type impurity and the p-type impurity;
A method for manufacturing a semiconductor device, comprising:   5. The semiconductor according to claim 4, wherein in the step of introducing the n-type impurity and the p-type impurity, the n-type impurity is formed on a surface side of the semiconductor layer as compared with the p-type impurity. Device manufacturing method.   5. The method of manufacturing a semiconductor device according to claim 4, wherein in the step of introducing the n-type impurity and the p-type impurity, the p-type impurity is introduced after the n-type impurity is introduced.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the p-type impurity contained in the n-type impurity diffusion region is higher than an intrinsic carrier concentration at the temperature of the heat treatment.   5. The semiconductor layer according to claim 4, wherein the semiconductor layer contains a p-type impurity, and at least a part of the n-type impurity diffusion region has a p-type impurity concentration higher than a p-type impurity concentration of the semiconductor layer. Semiconductor device manufacturing method.

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