WO2010103687A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

Info

Publication number
WO2010103687A1
WO2010103687A1 PCT/JP2009/067423 JP2009067423W WO2010103687A1 WO 2010103687 A1 WO2010103687 A1 WO 2010103687A1 JP 2009067423 W JP2009067423 W JP 2009067423W WO 2010103687 A1 WO2010103687 A1 WO 2010103687A1
Authority
WO
WIPO (PCT)
Prior art keywords
concentration
type
diffusion
type impurity
impurity
Prior art date
Application number
PCT/JP2009/067423
Other languages
French (fr)
Japanese (ja)
Inventor
正浩 小池
光介 辰村
大輔 萩島
Original Assignee
株式会社 東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社 東芝 filed Critical 株式会社 東芝
Publication of WO2010103687A1 publication Critical patent/WO2010103687A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Definitions

  • the present invention relates to a semiconductor device having a channel region whose main component is Ge.
  • Ge is expected as a semiconductor substrate replacing Si. This is because the bulk mobility of electrons and holes is higher than that of Si. Therefore, if a Ge substrate is used, it is expected that a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a high surface mobility can be realized, and a Ge pMISFET is actually a Si pMISFET. Higher mobility is indicated.
  • a MISFET Metal Insulator Semiconductor Field Effect Transistor
  • the contact resistance between metal and n + Ge is high, but one of them is because n + Ge with high carrier (electron) concentration can not be formed.
  • the n-type impurity in Ge has a very rapid diffusion for the reason to be described in detail later, and can not maintain the impurity at a high concentration when heat-treated, so the electron concentration can not be high.
  • the contact resistance Rc is in the relationship shown by the following equation with the electron concentration n.
  • Patent Document 1 a method of controllably forming an impurity layer having a desired concentration, depth or conductivity of a diffusion layer in a solid phase diffusion method by changing the diffusion coefficient of the impurity.
  • Patent Document 1 The feature of this patent document is the method of solid phase diffusion, which utilizes the property that As becomes difficult to diffuse when As-doped SiO 2 contains hydrogen, and As becomes easy to diffuse when it is reduced by oxidation. There is.
  • n + Si by As is formed on the surface side of Si, and p ⁇ Si by B is formed on the inner side, ie, n + Si / p ⁇ Si Will be formed.
  • this patent document 1 only shows an example of the diffusion of the impurity in Si, and that the characteristic diffusion of the n-type impurity in Ge is fast, the diffusion of the p-type impurity is slow, and the p-type impurity is No consideration is given to the suppression of the diffusion of n-type impurities.
  • the finally formed structure is n + Si / p - Si.
  • the concentration profile of p-type impurities will necessarily be higher near the surface, which is undesirable for forming an n + layer. Therefore, it is difficult to form n + Ge on a pGe layer consisting of extremely shallow and high concentration electrons even if this method is applied to Ge as it is.
  • the present invention has been made based on the above-described circumstances, and an object of the present invention is to provide a semiconductor device having an extremely shallow and high carrier concentration n-type impurity diffusion region in a Ge layer, and a manufacturing method that enables the same. I assume.
  • a semiconductor device includes a semiconductor substrate of one of n-type and p-type conductivity types, and a pair of impurity diffusion regions selectively provided on the surface of the semiconductor substrate and the other conductivity type.
  • a gate insulating layer provided on the semiconductor substrate sandwiched by the pair of impurity diffusion regions, and a gate electrode provided on the gate insulating layer, at least a part of the impurity diffusion regions being It is characterized in that it has the one conductivity type and has an impurity concentration higher than the impurity concentration of the substrate.
  • a method of manufacturing a semiconductor device is a method of forming a high concentration impurity diffusion region on the surface of a semiconductor layer containing Ge as a main component, wherein the surface of the semiconductor layer is formed. And the steps of: introducing n-type impurities and p-type impurities; and forming an n-type impurity diffusion region in the semiconductor layer by heat treatment after introducing the n-type impurities and p-type impurities.
  • the present invention it is possible to provide a semiconductor device in which an n-type impurity diffusion region having extremely shallow and high carrier (electron) concentration is formed in a Ge layer, and a method of manufacturing the same.
  • FIG. 2B is a schematic diagram of an impurity concentration profile illustrating a method of suppressing the diffusion of P by B and forming an n + Ge region composed of shallow and high-concentration electrons, showing a state before heat treatment. It is a schematic diagram of the impurity concentration profile explaining the method of suppressing the diffusion of P by B and forming an n + Ge region composed of shallow and high concentration electrons, and shows a state after heat treatment. It is a figure which shows the heat processing back and front of the impurity concentration profile of P in a Ge board
  • the impurity concentration profile in the absence of B in the Ge substrate corresponds to the absence of B in FIG.
  • the impurity concentration profile in the absence of B corresponds to the absence of B in FIG. It is a carrier concentration profile corresponding to the impurity concentration profile of FIG. It is a carrier concentration profile corresponding to the impurity concentration profile of FIG.
  • the carrier concentration profile of Ge substrate formed by introducing both P and B the case where the dose amount of B is 2 ⁇ 10 14 cm ⁇ 2 is shown.
  • the carrier concentration profile of a Ge substrate formed by introducing both P and B shows the case where the dose amount of B is 1 ⁇ 10 15 cm ⁇ 2 .
  • FIG. 28 is a cross-sectional view at a step subsequent to FIG. 27.
  • FIG. 29 is a cross-sectional view in the process following FIG. 28.
  • FIG. 30 is a cross-sectional view at a step subsequent to FIG. 29.
  • FIG. 31 is a cross-sectional view in the process following FIG. 30. It is sectional drawing of the semiconductor substrate for demonstrating the method using CVD by the method of forming n ⁇ +> Ge layer which concerns on 3rd Embodiment.
  • FIG. 33 is a cross-sectional view at a step subsequent to FIG. 32.
  • FIG. 34 is a cross-sectional view in the process following FIG.
  • FIG. 35 is a cross-sectional view at a step subsequent to FIG. 34.
  • FIG. 40 is a perspective view at the next step of FIG. 39.
  • P exists in Ge board
  • FIG. 50 is a cross-sectional view at a step subsequent to FIG. 50.
  • FIG. 52 is a cross-sectional view in a step subsequent to FIG. 51;
  • FIG. 52 is a cross-sectional view at a step subsequent to FIG. 52.
  • FIG. 50 is a cross-sectional view at a step subsequent to FIG. 50.
  • FIG. 56 is a cross-sectional view at a step subsequent to FIG. 54.
  • FIG. 56 is a cross-sectional view at a step subsequent to FIG. 55.
  • FIG. 56 is a cross-sectional view at a step subsequent to FIG. 56.
  • It is sectional drawing of the semiconductor substrate for demonstrating the method to form n ⁇ +> Ge layer which concerns on 12th Embodiment.
  • FIG. 58 is a cross-sectional view at a step subsequent to FIG. 58.
  • FIG. 60 is a cross-sectional view in the process following FIG. 59.
  • FIG. 61 is a cross-sectional view at a step subsequent to FIG. 60.
  • FIG. 61 is a cross-sectional view in a step subsequent to FIG.
  • C s + (x, t) is the concentration of the positive ion of the n-type impurity at the lattice substitution position
  • x is the coordinate of the n-type impurity (herein defined as the depth from the substrate surface)
  • t is a diffusion time
  • n (x, t) is an electron concentration
  • ni (x, t; T) is an intrinsic carrier concentration (depends on temperature T)
  • D * (ni) is a coefficient depending on ni.
  • the effective diffusion coefficient of the n-type impurity has the dependence of the square of the electron concentration n. This is derived from the difference in charge state of A + s and (AV) ⁇ .
  • the n-type impurity in Ge exhibits an unusual diffusion phenomenon due to the dependence of the electron concentration of D eff on the square.
  • D eff when high impurity concentration is increased, D eff when the impurity concentration is low is reduced.
  • FIG. 63 shows the result of SIMS analysis of the impurity concentration profile when phosphorus (P) is ion-implanted into Ge and heat-treated.
  • the dose amount of P is 5 ⁇ 10 15 cm ⁇ 2
  • the acceleration energy is 30 keV
  • heat treatment is performed at 600 ° C. for 30 minutes in a nitrogen atmosphere.
  • simulation results before heat treatment that is, in the case of only ion implantation are also shown.
  • the peak concentration is approximately 10 21 cm ⁇ 3 and the depth is 1 ⁇ 10 19 cm ⁇ 3 at a concentration of approximately 100 nm.
  • boron (B) was selected as a p-type impurity to compensate for the n-type impurity and introduced into a Ge substrate to check whether the diffusion of P can be suppressed.
  • the impurity profile of P in Ge introduced B was determined by SIMS analysis. After introducing B into a Ge substrate with a dose of 5 ⁇ 10 15 cm ⁇ 2 and an acceleration energy of 30 keV, P is introduced and heat-treated under the same conditions as FIG.
  • the peak concentration of B is about 1 ⁇ 10 21 cm ⁇ 3 , and it is understood from the profile that the peak concentration is not diffused even when heat treatment is applied. It has been reported that B does not diffuse at all even when ion-implanting BF 2 into Ge at a dose of 4 ⁇ 10 15 cm ⁇ 2 and acceleration energy of 20 keV and heat treatment at 650 ° C. for 10 seconds. (See, CO Chui et al., Appl. Phys. Lett. 83, 3275 (2003)), consistent with the results of the present invention.
  • the depth at which the concentration of P is 1 ⁇ 10 19 cm ⁇ 3 is about 100 nm, which is the same as the profile before heat treatment. That is, P is not diffused at all.
  • the concentration of P decreased to 2 ⁇ 10 19 cm -3 (Fig. 63), but in the presence of B, P peaked at about 7 ⁇ 10 20 cm -3 at the peak. The concentration is maintained.
  • n-type impurity a diffusion form of n-type impurity (PV) -
  • PV n-type impurity
  • a method as shown in FIG. 66 can be considered.
  • B is introduced at a high concentration to the back of the substrate as a p-type impurity
  • P is introduced near the surface of the substrate as an n-type impurity.
  • B does not diffuse, but P diffuses to the back of the substrate, and if the concentration of B is sufficiently high compared to the concentration of P, B suppresses the diffusion of P. Since the impurity concentration of P can be increased, the electron concentration can also be increased, and n + Ge is formed on the surface of the substrate.
  • n + Ge may be formed, but p + Ge will be formed at the same time due to the presence of a high concentration of B. That is, an n + Ge / p + Ge structure is formed, which is not applicable to the source / drain.
  • the present inventors have solved the problems associated with the above discovery and have found a method for forming an n + Ge structure which is an extremely shallow and high carrier (electron) concentration without the presence of p + Ge. It was also possible to find the ideal n + Ge structure formed thereby. This will be described below as an embodiment. Although the embodiments of the present invention will be described with reference to the drawings, the same reference numerals are given to the same components throughout the embodiments, and the redundant description will be omitted. Further, in each of the drawings, there is a schematic view for explaining the present invention and promoting its understanding, and even if there are places where its shape, size, ratio, etc. are different from the actual device, these will be described below. The design can be changed as appropriate in consideration of the technique of
  • “having Ge as a main component” means that the content of Ge is 85 at. It means that it is% or more.
  • the minimum value of the conduction band of Si is the ⁇ point
  • the minimum value of the conduction band of Ge is the L point
  • SiGe depends on the composition ratio
  • FIG. 1A and 1B are schematic views showing impurity profiles in a Ge substrate.
  • FIG. 1A shows the state before heat treatment.
  • An n-type impurity and a p-type impurity which are higher in concentration than the substrate concentration, are introduced into a substrate containing a constant, low-concentration p-type impurity.
  • the p-type impurity is introduced to the inner side of the substrate, and the n-type impurity is introduced to the surface side more than that.
  • n-type impurity was selected as P
  • p-type impurity as B.
  • the concentration of each impurity is characterized in that the peak concentration of P is sufficiently higher than that of B.
  • p-type impurities are used to suppress the diffusion of n-type impurities, and finally n-type impurities can be made higher than p-type impurities, so the p + Ge region is left shallow and shallow and high electron concentration N + Ge structure can be formed.
  • n + Ge according to the present invention is formed quantitatively and what kind of structure it takes.
  • the diffusion of n-type impurities in Ge is expressed by the diffusion equations (2) to (4).
  • p-type impurities also coexist, the following may be taken into consideration in addition to them.
  • p-type impurities do not diffuse even by heat treatment.
  • Ge satisfies the charge neutral condition (5).
  • n + (N A- p A ) p + (N D- n D ) (5)
  • n is an electron concentration
  • p is a hole concentration
  • N A is a p-type impurity concentration
  • N D is an n-type impurity concentration
  • p A is a hole density at the acceptor level
  • n D is a donor at the donor level It is a density.
  • n, p, p A and n D be expressed by the statistical mechanics of a normal equilibrium system.
  • the diffusion of n-type impurities in Ge was calculated by the equation (3) while obtaining the coordinates of the Ge substrate and n at each diffusion time using the equation (5).
  • the influence of the p-type impurity coexisting with the n-type impurity is reflected through n determined from the equation (5).
  • FIG. 2 is an example of calculating the process of forming n + Ge according to the present embodiment, and shows the relationship between the impurity concentration and the depth. In order to calculate, the diffusion coefficient etc. are required, and they were found by fitting with the experimental values.
  • FIG. 2 shows the case where only n-type impurities are present in Ge.
  • P was selected as an example of the n-type impurity.
  • the initial profile of P (profile before heat treatment) is a Gaussian distribution with a Projected Range Rp of 5.0 nm, a standard deviation of 1.0 nm, and a dose of 1 ⁇ 10 15 cm ⁇ 2 from the Ge substrate surface I assumed.
  • the heat treatment assumes spike annealing for a short time (1 second).
  • the temperature is 773K.
  • the time evolution during heat treatment was made equal (0, 0.1, 0.2, ..., 1.0) to show the change with time of the impurity concentration profile of P.
  • the light first diffuses and then gradually spreads gradually.
  • the concentration is 1 ⁇ 10 19 cm -3 from Rp to 3.5 nm, but after 0.1 sec, it spreads to 13.2 nm, and after 0.2 sec, 16.8 nm, 0.3 sec After that, it spreads to 19.0 nm, and diffuses to 27.2 nm after one second.
  • FIG. 3 shows the electron concentration profile under the same conditions as FIG. Similar to FIG. 2, the time evolution during the heat treatment was made sufficiently equal to show the change of the electron concentration profile of P.
  • the impurity and electron concentrations almost coincide with each other at 7 ⁇ 10 17 cm ⁇ 3 or more. This is because only P, which is an n-type dopant, is present in Ge, and is n + Ge consisting only of electrons up to a depth of about 33 nm from the surface.
  • the electron concentration is at a temperature at which the impurity of 773 K diffuses. Therefore, it is considered that the impurity concentration is approximately the same as the electron concentration, that is, approximately 100% ionized.
  • the impurity may cause incomplete ionization, and the electron concentration may be lower than the impurity concentration.
  • the concentration of the impurity is high, there is no incomplete ionization of the impurity due to metal-insulator transition, that is, the impurity concentration and the electron concentration may be considered to be almost the same even at room temperature.
  • the constant region with an electron concentration of 7 ⁇ 10 17 cm -3 is due to the intrinsic carrier concentration ni, which is lower than the substrate concentration at room temperature, and the region with a constant hole concentration is Appears at room temperature.
  • FIG. 4 shows the case where a p-type impurity is also present simultaneously with the n-type impurity.
  • p-type impurities coexist in the entire Ge substrate at a high concentration of 2.5 ⁇ 10 20 cm ⁇ 3 .
  • B was selected as an example of the p-type impurity.
  • FIG. 5 compares the diffusion distances of P without B (FIG. 2) and with P (FIG. 4). Each diffusion distance (depth when taking Rp as the origin) at the same diffusion time when the concentration is 1 ⁇ 10 19 cm ⁇ 3 was plotted. As apparent from the figure, the presence of B shortens the diffusion distance, and the larger the distance, in other words, the longer the diffusion time, the larger the difference. Thus, it can be seen that the presence of B suppresses diffusion.
  • FIG. 6 shows the electron concentration profile under the same conditions as FIG. Since B is present at a high concentration of 2.5 ⁇ 10 20 cm -3 throughout the Ge substrate, the electron concentration is 2.8 ⁇ 10 15 cm at a place where the P concentration is lower than the B concentration before the heat treatment. It becomes -3 .
  • the effective diffusion coefficient is proportional to the square of the electron concentration, so the lower the electron concentration, the slower the diffusion. In the absence of B, it is 8.4 ⁇ 10 17 cm ⁇ 3 , but in the presence of B, it is 2.8 ⁇ 10 15 cm ⁇ 3 , and the electron concentration decreases by two digits or more. Therefore, the presence of B reduces the effective diffusion coefficient and makes diffusion slower.
  • n + Ge / p + Ge because there is a region where the concentration of B is higher than P.
  • the electron concentration is lower than the impurity concentration of P.
  • the profile of B may be adjusted in order to form a high concentration n + Ge of electrons without forming ap + Ge layer and without reducing the electron concentration at the surface and forming a shallow electron.
  • FIG. 7 is an adjustment of the profile of B. As shown in FIG. 3, B does not enter entirely, and the condition of constant concentration of 2.5 ⁇ 10 20 cm -3 is the same, B is only from the surface to a depth of 7.3 nm to 18.9 nm. It was made to exist.
  • the profile of P is almost the same as the profile of P in FIG. 4, as can be seen from FIG. Moreover, although FIG.
  • FIG. 9 shows the electron concentration profile under the same conditions as FIG.
  • the parabolic curve shows the heat treatment before and the terrace curve shows the heat treatment after the heat treatment as in FIG.
  • the inner side of the substrate has an intrinsic carrier concentration, which is the same as FIG. 3 when B is absent. That is, it can be seen that the inner side of the substrate is not the p + Ge, but the original Ge substrate state, for example, a pGe substrate containing impurities at a normal level. Also, compared to FIG. 6, the electron concentration is higher on the surface side.
  • FIG. 10 shows the case where B is introduced from Rp (5 nm) to 10 nm at a concentration of 5 ⁇ 10 19 cm ⁇ 3 .
  • the diffusion time was 3 seconds.
  • the position of P concentration of 1 ⁇ 10 18 cm -3 was 8.8 nm before heat treatment, but diffused to 10.4 nm after heat treatment, and the difference between before and after heat treatment is only 1.6 nm. It is spreading.
  • FIG. 11 which eliminated only B from the case of FIG.
  • the position of P concentration of 1 ⁇ 10 18 cm ⁇ 3 is the same 8.8 nm before the heat treatment, and diffused to 14.8 nm after the heat treatment.
  • the diffused distance is 6.0 nm. That is, when B is absent, the light is diffused by 6.0 nm, but when 5 ⁇ 10 19 cm -3 is present, the diffusion is suppressed only by 1.6 nm.
  • FIGS. 12 and 13 The electron concentration profiles corresponding to the impurity concentration profiles in FIGS. 10 and 11 at this time are shown in FIGS. 12 and 13, respectively.
  • B When B is not present (FIG. 13), the position at an electron concentration of 1 ⁇ 10 18 cm ⁇ 3 is 10.4 nm, corresponding to the impurity concentration profile (FIG. 11).
  • B when B is present (FIG. 12), the n + Ge region is expanded to 14.8 nm corresponding to the impurity concentration profile (FIG. 10).
  • the electron concentration is lower than the intrinsic carrier concentration (the hole concentration is high), that is, p + Ge is formed.
  • FIG. 14 shows the case where the B concentration is reduced to 1 ⁇ 10 19 cm ⁇ 3 as compared with FIG. B was loaded from Rp to 25.3 nm.
  • the lower the B concentration the wider the region to which P diffuses, so it is better to widen the region into which B is to be inserted.
  • the diffusion time was 95 seconds.
  • the position of P concentration of 1 ⁇ 10 18 cm -3 was 8.8 nm before heat treatment, but diffused to 25.4 nm after heat treatment, and the difference between before and after heat treatment is only 17.0 nm. It is spreading.
  • FIG. 15 which eliminated only B from the case of FIG.
  • the position of P concentration of 1 ⁇ 10 18 cm ⁇ 3 is the same 8.4 nm before the heat treatment, and diffused to 32.2 nm after the heat treatment.
  • the diffused distance is 23.2 nm. That is, when B is not present, 23.2 nm is diffused, but because 1 ⁇ 10 19 cm ⁇ 3 of B is present, it is suppressed only by 17.0 nm.
  • FIGS. 16 and 17 The electron concentration profiles corresponding to the impurity concentration profiles in FIGS. 14 and 15 at this time are shown in FIGS. 16 and 17, respectively.
  • B When B is not present (FIG. 17), the position of the electron concentration of 1 ⁇ 10 18 cm ⁇ 3 is 32.2 nm, corresponding to the impurity concentration profile (FIG. 15).
  • the n + Ge region extends up to 25.4 nm, corresponding to the impurity concentration profile (FIG. 14).
  • the electron concentration is lower than the intrinsic carrier concentration (the hole concentration is high), that is, p + Ge is formed.
  • the electron concentration is low, it diffuses slowly and finally there is no region where the electron concentration is lower than the intrinsic carrier concentration, that is, there is no p + Ge region, and n + Ge consisting of extremely shallow and high electron concentration Only can be formed.
  • FIG. 18 shows the case where the B concentration is further reduced to 1 ⁇ 10 18 cm ⁇ 3 as compared with FIGS. 10 and 14.
  • B is from Rp to 31.8 nm.
  • the diffusion time was 100 seconds.
  • the position of P concentration of 1 ⁇ 10 18 cm -3 was 8.8 nm before heat treatment, but diffused to 31.6 nm after heat treatment, and the difference between before and after heat treatment is only 22.8 nm It is spreading.
  • FIG. 19 which eliminated only B from the case of FIG.
  • the position of P concentration of 1 ⁇ 10 18 cm ⁇ 3 is the same 8.8 nm before the heat treatment, and diffused to 32.6 nm after the heat treatment.
  • the diffused distance is 23.8 nm. That is, when B is not present, 23.8 nm is diffused, but because 1 ⁇ 10 18 cm -3 of B is present, it is suppressed only by 22.8 nm.
  • FIGS. 20 and 21 The electron concentration profiles corresponding to the impurity concentration profiles in FIGS. 18 and 19 at this time are shown in FIGS. 20 and 21, respectively.
  • B When B is absent (FIG. 21), the position of the electron concentration of 1 ⁇ 10 18 cm ⁇ 3 is 32.6 nm, corresponding to the impurity concentration profile (FIG. 19).
  • B when B is present (FIG. 20), the position of the electron concentration of 1 ⁇ 10 18 cm ⁇ 3 is 31.6 nm, corresponding to the impurity concentration profile (FIG. 18).
  • the electron concentration n is lower than the intrinsic carrier concentration ni (the hole concentration p is high), that is, p + Ge is formed.
  • the upper limit of the B concentration that suppresses the diffusion of P to form n + Ge is, in the extreme, slightly lower than the concentration Cn (x, 0) of P before heat treatment (Cn (x, 0) > Cp (x, 0)), or diffuse after heat treatment so that the P concentration becomes higher than B (Cn (x, t)> Cp (x, t)).
  • Cn (x, t) and Cp (x, t) are impurity concentrations at depth x and diffusion time t of P and B, respectively.
  • the B concentration may be higher than P as long as it is a diffusion direction.
  • the minimum B concentration Cp (x, 0) for suppressing the diffusion of P is effective if it is higher than the intrinsic carrier concentration ni (x, 0; T) at the diffusion temperature T (Cp (x, 0)> ni (x, 0; T)).
  • n + Ge can be formed which is shallower and has a high concentration of electrons.
  • FIG. 22 shows the case where only the diffusion time is different from FIG. The diffusion time was 3 seconds in FIG. 10, but 10 seconds in FIG. As can be seen from FIG. 22, the diffusion of P is advanced from FIG. For example, the position of P concentration of 1 ⁇ 10 18 cm -3 was 8.8 nm before heat treatment, but moved to 13.8 nm after heat treatment, and the difference between before and after heat treatment is 5.0 nm. It is spreading.
  • FIG. 23 which eliminated only B from the case of FIG.
  • the position of P concentration of 1 ⁇ 10 18 cm ⁇ 3 is the same 8.4 nm before the heat treatment, and diffused to 18.9 nm after the heat treatment.
  • the diffused distance is 10.5 nm. That is, when B is not present, 10.5 nm is diffused, but due to the presence of 1 ⁇ 10 19 cm -3 B, only 5.0 nm is suppressed. It should be noted here that, as apparent from FIG. 22, the concentration of B does not exceed the concentration of P even if P diffuses far beyond the region where B is present.
  • the electron concentration profiles corresponding to the impurity concentration profiles of FIGS. 22 and 23 are FIGS. 24 and 25, respectively.
  • the position of the electron concentration of 1 ⁇ 10 18 cm ⁇ 3 is 18.9 nm, corresponding to the impurity concentration profile (FIG. 23).
  • the n + Ge region extends to 13.8 nm, corresponding to the impurity concentration profile (FIG. 22).
  • the electron concentration is lower than the intrinsic carrier concentration (the hole concentration is high), that is, p + Ge is formed.
  • n + Ge consisting of electron concentration of concentration can be formed.
  • ⁇ Carrier concentration profile of Ge introduced P and B> 26A and 26B show carrier concentration profiles of Ge formed by introducing two of P and B.
  • FIG. It was determined by spreading resistance probe analysis.
  • the dose amount of P is 5 ⁇ 10 15 cm ⁇ 2 and is heat treated for 30 minutes in a nitrogen atmosphere.
  • the dose amount of B is 2 ⁇ 10 14 and 1 ⁇ 10 15 cm ⁇ 2 , respectively.
  • the heat treatment temperature was three ways of 400, 500 and 600 ° C.
  • the carrier concentration profile in the absence of B was also examined.
  • the carriers present at high concentration on the substrate surface side are all electrons, and the constant concentration region present on the inner side of the substrate is holes generated by impurities (Ga) contained in the substrate.
  • Second Embodiment an embodiment of a method of forming an n-type impurity layer will be described.
  • B is ion implanted into the p-type Ge substrate 1 (FIG. 27).
  • the acceleration energy of ion implantation is adjusted, and implantation is performed on the inner side of the substrate surface.
  • the B high concentration layer 2 is formed on the inner side of the surface of the p-type Ge substrate 1 (FIG. 28).
  • P is ion-implanted into the p-type Ge substrate 1 (FIG. 29). The acceleration energy is adjusted and injected on the surface side of the high concentration layer 2 of B.
  • the high concentration layer 3 of P is formed on the surface side of the p-type Ge substrate 1, and the high concentration layer 4 of B is formed on the back side of the substrate (FIG. 30). Then, when this substrate is heat-treated, P diffuses but B suppresses diffusion, and finally P becomes higher in concentration than B, so the p + Ge region disappears, and the shallow and high concentration electron concentration An n + Ge layer is formed (FIG. 31).
  • the n + Ge layer contains more p-type impurities than contained in the substrate 1.
  • the third embodiment shows another method of forming an n-type impurity diffusion layer.
  • Ge doped with B is deposited by CVD on the p-type Ge substrate 1 (FIG. 32).
  • ap + Ge layer 6 is formed on the surface of the p-type Ge substrate 1 (FIG. 33).
  • P-doped Ge is deposited by CVD.
  • An n + Ge layer 7 is formed on the p + Ge layer 6 (FIG. 34).
  • an n + Ge layer 8 of shallow and high concentration electrons is formed by the above-described effect (FIG. 35). In this process, if the n + Ge layer 7 of FIG.
  • n + Ge layer 8 consisting of shallow, high concentration electrons. If the p + Ge layer 6 is formed as in this process, diffusion of P to the back side of the substrate can be prevented when depositing P-doped Ge.
  • FIG. 36 is a schematic cross-sectional view of a semiconductor device (MISFET) using the n + Ge layer described above.
  • the semiconductor device according to the fourth embodiment includes a p-type semiconductor layer 10 mainly composed of Ge formed on a substrate, a gate insulating layer 12 formed on the p-type semiconductor layer 10, and a gate insulating layer.
  • a pair selectively formed on the surface of the p-type semiconductor layer 10 so as to sandwich the boundary region between the gate electrode 14 formed on the gate electrode 12 and the gate insulating layer 12 of the p-type semiconductor 10 from both sides in the gate length direction.
  • This semiconductor device contains an n-type impurity in all or part of the n-type impurity diffusion region 18 and also contains a higher concentration of p-type impurity than contained in the p-type semiconductor layer 10.
  • a contact electrode 16 is bonded to the surface of the n-type impurity diffusion region.
  • the whole substrate is Ge, or at least the surface is a surface layer of the substrate mainly containing Ge, and contains a p-type impurity.
  • the p-type impurity may be present in the entire n-type impurity region, it is desirable that the p-type impurity is not present on the substrate surface in order to increase the electron concentration to reduce the contact resistance.
  • a so-called LDD, an n-type extension, or a halo layer may be formed around the n-type impurity region.
  • the n-type source / drain region 18 which is extremely shallow and has a high carrier density.
  • the fine Ge channel semiconductor device it is possible to suppress the short channel effect and reduce the parasitic resistance, and it is possible to provide a MISFET with a high current driving capability.
  • FIG. 37 is a schematic cross-sectional view of a CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor) using the n + Ge layer and the p + Ge layer described above.
  • CMISFET Complementary Metal Insulator Semiconductor Field Effect Transistor
  • FIG. 37 shows a cross section in the gate length direction of a CMISFET having a Ge channel.
  • a p-type well region 102 and an n-type well region 104 made of Ge are electrically separated by an element isolation layer 106.
  • the substrate 100 may be a Ge substrate, a Si substrate, a substrate on which a Ge layer is formed on a Si substrate, or a substrate on which an intermediate layer of a SiGe layer is formed on a Si substrate and a Ge layer is further formed thereon.
  • the element isolation layer 106 is formed of SiO 2 , for example.
  • an n-channel MIS transistor is formed, and in the n-type well region 104, a p-channel MIS transistor is formed.
  • n-type extension regions 108 are formed in the p-type well region 102 on both sides of the gate length of the region (channel region) to be a current path. Deep regions 110 are formed.
  • a gate insulating film 116 is formed on the channel region on the upper surface of the p-type well region 102 in such a manner that the gate insulating film 116 is applied to the inner end in the gate length direction of the opposing n-type extension regions 108.
  • a gate electrode 118 is stacked on the upper surface of the gate insulating film 116.
  • Gate sidewalls 124 are formed on both sides of the gate insulating film 116 and the gate electrode 118.
  • the n-type deep region 110 is configured such that the junction depth with the p-type well region 102 is deeper than the n-type extension region 108.
  • the n-type extension region 108 and the n-type deep region 110 become source / drain regions of the n-channel MIS transistor.
  • a pair of p-type extension regions 112 are formed on both sides in the gate length direction of a region (channel region) serving as a current path in the n-type well region 104.
  • a pair of p-type deep regions 114 are formed.
  • a gate insulating film 120 is formed on the channel region on the upper surface of the n-type well region 104 in such a manner that the gate insulating film 120 is applied to the inner end in the gate length direction of the pair of p-type extension regions 112.
  • a gate electrode 122 is stacked on the upper surface of the gate insulating film 120.
  • Gate sidewall insulating films 126 are formed on both sides of the gate insulating film 120 and the gate electrode 122.
  • the p-type deep region 114 is configured such that the junction depth with the n-type well region 104 is deeper than the p-type extension region 112.
  • the p-type extension region 112 and the p-type deep region 114 become source / drain regions of the p-channel MIS transistor.
  • the n-channel MIS transistor and the p-channel MIS transistor are covered by an interlayer insulating film 130.
  • one or both of the n-type extension region 108 and the n-type deep region 110 are formed by the above-described embodiment and include a p-type dopant.
  • the p-type dopant can also be the same as the p-type dopant contained in the p-type extension region 112 and the p-type deep region 114.
  • the element isolation layer 106 is formed on the main surface of the substrate 100.
  • the substrate may be a Ge substrate, a Si substrate, a substrate in which a Ge layer is formed on a Si substrate, or a substrate in which a Ge layer is formed on a Si substrate with an intermediate layer of a SiGe layer.
  • the formation method of the element isolation layer 106 may be a local oxidation method or an STI (Shallow Trench Isolation) method, and the shape of the element isolation layer 106 may be a mesa.
  • the p-type well region 102 and the n-type well region 104 are formed.
  • a conventional ion implantation method for the Ge layer may be used, or the ion implantation may be performed after the Ge layer is epitaxially grown.
  • gate insulating films 116 and 120 are formed on the upper surfaces of p type well region 102 and n type well region 104.
  • a method of forming the gate insulating films 116 and 120 for example, a Ge oxide film may be formed by a thermal oxidation method, or a Ge oxynitride film may be formed by a plasma oxynitridation method. Hf, Zr, La , Y, Al or the like may be deposited by a CVD (Chemical Vapor Deposition) method.
  • CVD Chemical Vapor Deposition
  • Tantalum carbide is formed on the gate electrode 118 (for n-channel MIS transistor), and tungsten is formed on the gate electrode 122 (for p-channel MIS transistor) to a film thickness of 10 nm by physical vapor deposition (PVD). Thereafter, titanium nitride is deposited to a thickness of 10 nm on the upper surface by PVD. After that, a polycrystalline Si layer is deposited to a thickness of 50 nm on the upper surface by a low pressure CVD method.
  • tantalum silicide, tantalum nitride silicide, titanium nitride silicide, tungsten silicide, tungsten nitride silicide, or the like can be used.
  • ruthenium, titanium nitride, titanium aluminum nitride, platinum, platinum iridium, or the like can be used for the gate electrode 122 (for p-channel MIS transistor).
  • gate electrodes 118 and 122 Thereafter, patterning by photolithography is performed, and an unnecessary film is removed by anisotropic etching to form gate electrodes 118 and 122. Thereafter, for example, the sidewall insulating film 124, the n-type extension region 108, and the n-type deep region 110 are formed by using the method according to the above-described embodiment.
  • source / drain regions of the p-channel MIS transistor are formed by a self-aligned gate method.
  • the “self-aligned gate method” is a method in which a gate stack is first formed and then source / drain regions are formed by ion implantation or the like. That is, ion implantation of boron (B) is performed using the gate electrode 122 as an umbrella to form the p-type extension region 112 of the p-channel MIS transistor. Thereafter, a sidewall insulating film 124 for insulation between the gate electrode 122 and the source / drain regions (p-type extension region 112 and p-type deep region 114) is formed. Thereafter, boron (B) ions are implanted at an acceleration voltage higher than in the case where the p-type extension region 112 is formed, to form the p-type deep region 114.
  • the activation process temperature of the source / drain region is the gate laminate portion (gate insulating film 116, gate electrode 118).
  • a temperature which does not degrade the characteristics of the gate insulating film 120 and the np junction of the gate electrode 122) and the source / drain region is desirable, for example, 600.degree.
  • flash lamp annealing, laser annealing, or the like can also be used as a method for activating the source / drain regions.
  • activation of the impurities in the semiconductor can be realized by processing in a shorter time, so the gate electrode 118, 122 / gate insulating film 116, 120 / semiconductor (p-type well region 102, n-type well region 104, Thermal degradation of a semiconductor device having a structure of n-type extension region 108, n-type deep region 110, p-type extension region 112, and p-type deep region 114) can be reduced.
  • a Si oxide film to be the interlayer insulating film 130 is deposited by low pressure CVD, and the upper ends of the gate electrodes 118 and 122 are exposed by CMP (Chemical Mechanical Planarization). Thereafter, a 50 nm thick nickel layer is formed on the upper surfaces of the gate electrodes 118 and 122 by sputtering or the like. Thereafter, by performing a low temperature heat treatment at 500 ° C., a silicide is formed from the interface region of nickel and polycrystalline Si, and Ni 2 Si is formed.
  • a silicide is formed from the interface region of nickel and polycrystalline Si, and Ni 2 Si is formed.
  • Ni 2 Si is formed from the interface region of nickel and polycrystalline Si, and Ni 2 Si is formed.
  • all polycrystalline Si is converted to silicide in the present embodiment, only part of polycrystalline Si may be silicided by making the film thickness of Ni thinner. After that, unreacted Ni is removed using a mixed solution of sulfuric acid and hydrogen peroxide solution or the like.
  • the CMOSFET semiconductor device having the structure shown in FIG. 37 is manufactured by the manufacturing method described above.
  • By controlling the concentration and distribution of the p-type dopant it is possible to form an n-type source / drain region (n-type extension region 108 and n-type deep region 110) which is extremely shallow and has a high carrier density.
  • n-type source / drain region n-type extension region 108 and n-type deep region 110
  • FIG. 38 is a schematic perspective view of FinMISFET according to the sixth embodiment.
  • the present embodiment is an example in which the n + Ge / pGe structure described above is applied to FinMISFET.
  • 208 is a support substrate
  • 209 is an insulating layer
  • 210 is a Ge layer
  • 208 to 210 form a GOI (Germanium on Insulator) substrate 211.
  • the GOI layer 210 is processed to form a linear (rectangular) element region 202.
  • a gate electrode 204 is formed in the central portion of the element region 202 with the gate insulating film 203 interposed therebetween. Portions of the element region 202 sandwiching the gate electrode 204 become source / drain regions 205.
  • a HfO 2 film 212 with a thickness of 5 nm, for example, is formed by using a method such as CVD (chemical vapor deposition).
  • CVD chemical vapor deposition
  • a refractory metal film of, eg, 100 nm thickness, eg, tungsten is deposited by, eg, CVD method, and anisotropic etching, eg, RIE method, etc.
  • the high melting point metal film is processed to form the gate electrode 204.
  • the HfO 2 film 212 is processed by performing anisotropic etching such as RIE, for example, to form the gate insulating film 203.
  • B is implanted over the entire surface of the substrate, and then P is implanted.
  • the order of injection of P and B may be reversed.
  • the gate electrode 204 and the gate insulating film 212 may be further thinned by RIE or the like after P implantation.
  • RIE reactive ion etching
  • a source / drain region 5 made of n + Ge is formed by a thermal process to form a MOSFET.
  • the surface can be made of n + Ge having a high carrier concentration, and the diffusion of P can be suppressed, so that the lateral diffusion into the channel region can also be suppressed.
  • the semiconductor device is formed through a normal interlayer insulating film forming process, a wiring hole forming process, a wiring process and the like.
  • the source / drain region 5 made of n + Ge can be formed to be extremely shallow and have a high carrier concentration, and a high performance Fin MISFET can be provided.
  • the seventh embodiment another method of forming a shallow n-type diffusion layer will be described.
  • a method of making the n-type diffusion layer shallow so far, a method of introducing a p-type impurity (B) into the inside of the substrate has been shown.
  • the p-type impurity suppresses the diffusion of the n-type impurity to the back side (inward) of the substrate. That is, it was thought only to suppress the inward diffusion of the n-type impurity (P).
  • P n-type impurity
  • FIG. 41 shows an impurity profile of P in Ge, in which out diffusion occurs, and the maximum amount of the out diffusion is controlled by some method described later. There is nothing to prevent the outward diffusion on the surface, and the case of outward diffusion to vacuum is considered to be the upper limit of the amount of outward diffusion.
  • the conditions are the same as in FIG. 2 except for the presence or absence of outward diffusion.
  • the physical quantity representing the outward diffusion is defined as the number of atoms of impurities released outward from the outermost surface of the substrate per unit time and unit area. At that time, equation (3) is changed as equation (6).
  • J (cm -2 s -1 ) determines the maximum amount of out diffusion, and when the surface concentration is high, only J diffuses out at the surface, and when the surface concentration is low, An amount smaller than J diffuses out.
  • J 1 ⁇ 10 15 cm ⁇ 2 s ⁇ 1 .
  • the concentration is 1 ⁇ 10 19 cm -3 from Rp to 3.5 nm, and after 0.1 seconds it spreads to 12.7 nm, after 0.2 seconds 15.1 nm, after 0.3 seconds Spreads to 16.6 nm and diffuses to 21.6 nm after one second.
  • the concentration on the surface side decreases as compared with the case where there is no outward diffusion. This is because impurities present at the outermost surface escape to the outside of the surface.
  • the outward diffusion J in this case is 1 ⁇ 10 15 cm ⁇ 2 s ⁇ 1 . Since the impurity concentration at the outermost surface and the back of the substrate is high at first, the same amount of impurity as J is eliminated. Therefore, the reduction of the impurity concentration on the surface is fast at first. However, as time passes, the inward diffusion of the impurity also proceeds, and the impurity concentration at the outermost surface and the back of the substrate decreases.
  • outward diffusion is also affected by inward diffusion. The less the inward diffusion, the more the outward diffusion, and the more the inward diffusion, the less the outward diffusion.
  • FIG. 42 compares the diffusion distances of P in the case of no outward diffusion (FIG. 2) and in the case of presence (FIG. 41). Respective inward diffusion distances (depths with Rp taken as the origin) at the same diffusion time when the concentration is 1 ⁇ 10 19 cm ⁇ 3 were plotted. As apparent from the figure, the inward diffusion distance is shortened by causing the outward diffusion, and the difference becomes larger as the distance becomes longer, that is, as the diffusion time becomes longer. As described above, it can be understood that inward diffusion can be suppressed by intentionally causing outward diffusion as compared with the case where outward diffusion is suppressed.
  • FIG. 43 shows the electron concentration profile under the same conditions as FIG. As in FIG. 3, since there is only n-type dopant in this case, the electron concentration is in agreement with the impurity concentration at the intrinsic carrier concentration ni or more at 773 K (> 7 ⁇ 10 17 cm ⁇ 3) . Thus, it is understood that 26.6 nm from the surface is n + Ge, and a shallow n + Ge layer can be formed as compared with the case without out diffusion.
  • the effect of the inward diffusion suppression by the outward diffusion is more effective if it is used together with the effect of suppressing the diffusion of the n-type impurity by the p-type impurity of the present invention, and the effect is more than a mere combination.
  • a p-type impurity is simultaneously present in the Ge substrate together with the n-type impurity, and it is shown what kind of difference appears in the diffusion of the n-type impurity when comparing the case of the out diffusion and the case of the out diffusion.
  • FIG. 44 shows the case where the n-type impurity P and the p-type impurity B coexist and there is no out diffusion.
  • B is present at a depth of 7.5 to 17.5 nm from the surface of the Ge substrate.
  • P diffuses far beyond the region where B is distributed.
  • FIG. 45 is a comparison of the diffusion distance of P in the case without B (FIG. 2) and in the case with (FIG. 44), both of which are cases where there is no outward diffusion.
  • Each diffusion distance (depth when taking Rp as the origin) at the same diffusion time when the concentration is 1 ⁇ 10 19 cm ⁇ 3 was plotted. As apparent from the figure, even if P greatly exceeds the area where B is distributed, the diffusion distance is shorter than when B is not present.
  • FIG. 46 shows the electron concentration profile under the same conditions as FIG. It turns out that the whole becomes n ⁇ +> Ge similarly to what was mentioned above.
  • FIG. 47 shows the impurity profile when B is present in the Ge substrate and further outward diffusion is present.
  • the outward diffusion amount J is 1 ⁇ 10 15 cm ⁇ 2 s ⁇ 1 .
  • FIG. 44 shows the diffusion behavior in the case where there is no outward diffusion (FIG. 1) or the case where B is inherent (FIG. 44). In this case, outward and inward diffusion occur simultaneously.
  • the inward diffusion of P slows down in the region where B is present. If there is no outward diffusion, P can not escape from the surface, so it will be repelled in an inward manner. Therefore, in the case of FIG. 44, a large amount of P passes through the region where B exists and diffuses inward of the substrate.
  • P can diffuse toward the surface at the same time as it diffuses slowly in the region where B exists, and can escape outward from the surface. That is, by diffusing outward from the surface so as not to diffuse too far into the substrate, it is possible to suppress the inward diffusion by using the diffusion suppression effect of B.
  • the concentration is 1 ⁇ 10 19 cm -3 from Rp to 3.5 nm, and after 0.1 seconds it spreads to 8.9 nm, after 0.2 seconds 10.3 nm, after 0.3 seconds Spreads to 11.0 nm, and diffuses to 12.2 nm after one second.
  • FIG. 48 compares the diffusion distances of P in the case where B exists in the Ge substrate and there is no outward diffusion (FIG. 44) and in the case where it is present (FIG. 47). Respective inward diffusion distances (depths with Rp taken as the origin) at the same diffusion time when the concentration is 1 ⁇ 10 19 cm ⁇ 3 were plotted. As apparent from the figure, the inward diffusion distance is shortened by causing the outward diffusion, and the difference becomes larger as the distance becomes longer, that is, as the diffusion time becomes longer. As described above, it can be understood that inward diffusion can be suppressed by intentionally causing outward diffusion as compared with the case where outward diffusion is suppressed.
  • FIG. 49 shows the electron concentration profile under the same conditions as FIG. Since B is present at a high concentration of 2.5 ⁇ 10 20 cm -3 in the range of 7.5 to 17.5 nm from the surface of the Ge substrate, a place where the P concentration is lower than the B concentration before the heat treatment Then, the electron concentration is 2.8 ⁇ 10 15 cm ⁇ 3 .
  • the effective diffusion coefficient is proportional to the square of the electron concentration, so the lower the electron concentration, the slower the diffusion. In this case, the diffusion is faster because the electron concentration is higher when going outward. Unlike the case of FIG. 46, since there is outward diffusion, it does not significantly exceed the region where B is present.
  • the surface of the p-type Ge substrate 1 is pretreated, for example, with a halogen acid such as HF or HCl. Then, normally, a protective film or the like formed before ion implantation is not formed, and P is ion implanted into the p-type Ge substrate 1 in a state where nothing is formed on the surface (FIG. 50). Then, a high concentration layer 3 of P is formed in the vicinity of the surface of the p-type Ge substrate 1 (FIG. 51). Subsequently, when the substrate is heat-treated, inward diffusion and outward diffusion of P occur (FIG.
  • a halogen acid such as HF or HCl
  • n + Ge layer is formed although it is lower than the ion implanted dose (FIG. 53).
  • Ions may be implanted in a state in which a protective film or the like is present on the surface, and then pretreatment of the surface may be performed to cause outward diffusion while nothing is formed on the surface.
  • FIGS. 54 to 57 Eleventh Embodiment Subsequently, another embodiment of the method for forming the n-type impurity layer will be described with reference to FIGS. 54 to 57.
  • P ions are implanted into the surface of the p-type Ge substrate 1 (FIG. 54).
  • the protective film may or may not be present on the surface.
  • a SiOx thin film 20 is deposited on the Ge surface by a method such as CVD. It may be formed before ion implantation.
  • P is ion-implanted into the p-type Ge substrate (FIG. 55). Subsequently, when the substrate is heat-treated, inward diffusion and outward diffusion of P occur (FIG. 56).
  • the amount of outward diffusion can be reduced as compared with the case where the SiOx thin film is not present. Further, the amount of outward diffusion can also be controlled by adjusting the film thickness.
  • the film thickness is desirably in the range of 0 to 3 nm.
  • an n + Ge layer 7 can be formed which is shallow and has a high concentration of electrons.
  • a part or all of P may be trapped in the SiOx or the SiOx / Ge interface. If SiOx is, for example, porous, P can be incorporated into the membrane. There is no problem if Si or O remains near the substrate surface without removing SiOx. It is preferable that Si and O be left since the influence of the metal of the contact being pinned to the charge neutrality level of the Ge substrate surface is reduced.
  • the GeOx thin film 22 is deposited on the surface of the Ge substrate or formed in an oxygen atmosphere.
  • Ge has the property of being desorbed in the form of GeO, but since desorption is suppressed in a high pressure oxygen atmosphere, deposition of GeO x and maintenance of film thickness are possible.
  • the substrate is heat treated, inward diffusion and outward diffusion of P occur.
  • the amount of out-diffusion can be reduced as compared with the case where the GeOx thin film is absent. Further, the amount of outward diffusion can also be controlled by adjusting the film thickness.
  • the film thickness is desirably in the range of 0 to 3 nm.
  • GeOx is removed from the surface of the Ge substrate by halogen acid pretreatment such as HF treatment.
  • the GeOx layer is released by heat treatment from an oxygen atmosphere to another atmosphere, for example, in a nitrogen atmosphere or vacuum.
  • an n + Ge layer having a shallow and high electron concentration can be formed.
  • the membrane that suppresses the outward diffusion need not always be present during the heat treatment.
  • those films may not be present at the beginning of the heat treatment and may be formed on the way, or may be present at the beginning of the heat treatment and eliminated on the way.
  • a GeOx layer is always present on the surface during heat treatment, but this may not be the case.
  • the pressure of oxygen is performed in a high pressure atmosphere of, for example, 70 atm. Then, desorption of the GeOx layer does not occur, and growth can also be performed.
  • the pressure is lowered in the middle of the heat treatment, for example, when atmospheric pressure or vacuum is applied under oxygen or other atmosphere, desorption of GeO occurs, so that the GeOx layer can be removed.
  • the surface can be made empty by applying atmospheric pressure or vacuum in oxygen or other atmosphere.
  • the heat treatment is performed in an atmosphere at a high pressure of, for example, 70 atm under the pressure of oxygen. Then, since desorption of the GeOx layer does not occur, a GeOx layer can be formed on the surface.
  • SiOx and GeOx have been described above, other films may be used as long as the effect of out diffusion is obtained.
  • a thin film insulator such as SiON, SiGeO, GeON, HfOx, LaOx, AlOx, TiOx, TaOx, or ZrOx may be used, or a semiconductor thin film such as Si or SiGe may be used. These may be left near the n + Ge substrate surface. Note that the composition ratio of the constituent elements of the film is optional even in the case where it is not displayed using x.
  • P is ion implanted into the surface of the p-type Ge substrate 1 (FIG. 58). Then, a Ni thin film 24 is deposited on the surface of the Ge substrate (FIG. 59). Alternatively, P may be ion-implanted after the Ni thin film is formed. Subsequently, heat treatment of this substrate causes inward diffusion and outward diffusion of P (FIG. 60).
  • the NiGe layer 26 is formed, and the amount of outward diffusion can be reduced as compared with the case where the Ni thin film is not present. Further, the amount of outward diffusion can also be controlled by adjusting the film thickness. Since it is better to be thinner, the thickness T Ni of the Ni layer 24 before heat treatment should satisfy the range of 0 ⁇ T Ni ⁇ 5 nm, and the thickness T NiGe of the formed NiGe layer 26 satisfy the range of 0 ⁇ T NiGe ⁇ 10 nm Desirable (FIG. 61). After the heat treatment, unreacted Ni is removed with, for example, HCl (FIG. 62).
  • an n + Ge layer can be formed which is shallow and has a concentration of electrons.
  • P may be present in the region where NiGe exists.
  • Ni may react with Ge at low temperature and have a low resistivity.
  • Such materials include Fe, Co, Pd, Pt, Cu, etc. which react at 150 to 360 ° C. and have a low resistance phase of 22 to 129 ⁇ cm (S. Gaudet et al., International SiGe Technology and Devices Meeting , 18 (2006); J. Appl. Phys. 100, 034306 (2006). One or more of these may be used.
  • P is taken as an example of the n-type impurity throughout the embodiment, other elements may be used, for example, one or more of As, Sb, Bi and the like.
  • the p-type impurity is also the same, and may be another one, for example, one or more of B, Al, Ga, In and the like.
  • a temperature 773 K at which B does not diffuse is assumed. However, if the diffusion is slower than P, it is effective even at a high temperature at which B diffuses, and of course it is effective even at a low temperature, and the temperature is not limited.
  • examples of CVD and ion implantation have been shown as methods of introducing impurities, other methods may be used.
  • a p-type semiconductor mainly composed of Ge has been described as an example of the substrate, it may be an n-type semiconductor or another semiconductor such as a compound semiconductor. What becomes an n-type impurity for the semiconductor is paired with a vacancy and, if it is charged, cancels the charge, similarly to the diffusion mechanism of the n-type impurity in Ge described in the present invention If p-type impurities are used in the same manner as in the present invention, the same effects as in the present invention can be obtained, diffusion of n-type impurities can be suppressed, and extremely shallow n-type impurity regions with high carrier concentration can be formed.
  • a semiconductor containing Ge as a main component is exemplified, but a compound semiconductor may be used.
  • compound semiconductors include III-V semiconductors, such as GaAs, InP, InSb, GaN, and InGaAs.
  • GaAs for example, Zn is used as a p-type dopant, and Si is used as an n-type dopant.
  • the diffusion of Zn in GaAs is explained by the kick-out mechanism represented by the following chemical equilibrium (see, for example, H. Bracht et al., Physica B, 308, 831 (2001)) .
  • Zn - Ga is a Zn occupying Ga site
  • I 2 + Ga is a self-interstitial Ga.
  • Zn + i is diffused between the lattice
  • Ga is kick out between the lattice (I 2+ Ga)
  • the p-type impurity layer is formed on the inner side of the Ge substrate, the p-type impurity layer is formed on the surface side of the p-type semiconductor substrate, and the outward diffusion of the n-type impurity occurs during heat treatment. That is, it can also be used as a barrier layer which suppresses the diffusion from the surface to the outside.
  • the p-type impurity layer may be Ge containing p-type impurities, may be Si, or may be SiO 2 or the like. After the heat treatment, the p-type impurity layer may be removed.
  • the p-type impurity layer may be formed not only to suppress the diffusion of the n-type impurity to the deep side in the substrate but also to suppress the diffusion in the lateral direction with the channel.
  • the p-type impurity is contained on the channel side of the n-type impurity diffusion layer.
  • a p-type impurity may be used to prevent the n-type impurity from escaping in the direction of element isolation to reduce the impurity concentration.
  • the n-type impurity diffusion layer has a structure including the p-type impurity on the element isolation side.
  • the p-type impurity can be formed in the direction to prevent the diffusion of the n-type impurity, and after suppressing the diffusion, can be used to compensate for the n-type impurity to form only n + Ge.
  • the above description can be applied not only to the formation of n + layer but also to the formation of p + layer.
  • the p-type impurity can be used to suppress the diffusion of the n-type impurity.
  • the n-type impurity It is because it can be utilized for the diffusion suppression of the type impurity. That is, by suppressing the diffusion of the fast diffusion impurity using the slow diffusion impurity, it is possible to form a shallow, high carrier concentration impurity diffusion layer made of the fast diffusion impurity.
  • substrate substrate, 102 ... p-type well area, 104 ... n-type well area, 106 ... element separation layer, 108 ... n-type extension area 110 ... n-type deep region, 112 ... p-type extension region, 114 ... p-type deep region, 116 ... gate insulating film, 118 ... gate electrode, 120 ... gate insulating film, 122 ... gate electrode, 124, 126 ...
  • gate sidewall Insulating film 130 interlayer insulating film 202: element (semiconductor) region 203: gate insulating film 204: gate electrode 205: source / drain region , 208: supporting substrate, 209: embedded insulating layer, 210: Ge layer, 211: GOI substrate, 212: HfO 2 film

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)

Abstract

Disclosed is a semiconductor device wherein an n-type impurity region, which is extremely shallow and composed of high-density carriers, is formed in a Ge semiconductor layer. The semiconductor device comprises: a semiconductor substrate which has either n-type or p-type conductivity; a pair of impurity diffusion regions which are selectively formed in the surface of the semiconductor substrate and have the other conductivity type; a gate insulating layer which is formed on the semiconductor substrate part sandwiched between the pair of impurity diffusion regions; and a gate electrode formed on the gate insulating layer. At least a part of the impurity diffusion regions has the conductivity type of the substrate, while having an impurity concentration higher than the impurity concentration of the substrate.

Description

半導体装置およびその製造方法Semiconductor device and method of manufacturing the same
　本発明は、Ｇｅを主成分としたチャネル領域を有する半導体装置に関する。 The present invention relates to a semiconductor device having a channel region whose main component is Ge.
　次世代ＬＳＩ開発において、Ｓｉにかわる半導体基板としてＧｅが期待されている。Ｓｉに較べて、電子およびホールのバルク移動度が高いからである。それゆえ、Ｇｅ基板を用いれば、表面移動度の高いＭＩＳＦＥＴ（Metal Insulator Semiconductor Field Effect Transistor：金属／絶縁体／半導体型電界効果トランジスタ）が実現できると予想され、実際にＧｅのｐＭＩＳＦＥＴではＳｉのｐＭＩＳＦＥＴよりも高い移動度が示されている。しかし、その一方で、ＧｅのｎＭＩＳＦＥＴでは、まだＳｉのｎＭＩＳＦＥＴよりも高い移動度を確認したという例がない。これは、ｎＭＩＳＦＥＴでは、金属とｎ＋Ｇｅのコンタクト抵抗が高いため、本来のｎＭＩＳＦＥＴの性能が充分に引き出せていないからである。 In the next-generation LSI development, Ge is expected as a semiconductor substrate replacing Si. This is because the bulk mobility of electrons and holes is higher than that of Si. Therefore, if a Ge substrate is used, it is expected that a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a high surface mobility can be realized, and a Ge pMISFET is actually a Si pMISFET. Higher mobility is indicated. However, on the other hand, there is no example in which the mobility of Ge n-type MISFET is higher than that of Si n-MISFET. This is because, in the nMISFET, since the contact resistance between the metal and the n + Ge is high, the performance of the original nMISFET can not be sufficiently extracted.
　金属とｎ＋Ｇｅのコンタクト抵抗が高くなる理由はいくつかあるが、そのうちのひとつは、高キャリア（電子）濃度のｎ＋Ｇｅが形成できないためである。Ｇｅ中のｎ型不純物は、後に詳述する理由により、拡散が非常に速く、熱処理すると高濃度に不純物を維持できず、そのため電子濃度が高くできない。コンタクト抵抗Ｒｃは、電子濃度ｎと次式で示される関係にある。 There are several reasons why the contact resistance between metal and n + Ge is high, but one of them is because n + Ge with high carrier (electron) concentration can not be formed. The n-type impurity in Ge has a very rapid diffusion for the reason to be described in detail later, and can not maintain the impurity at a high concentration when heat-treated, so the electron concentration can not be high. The contact resistance Rc is in the relationship shown by the following equation with the electron concentration n.
　　　 Ｒｃ∝ｅｘｐ（Ｃ／(ｎ１／２)）　　　　　　　…　　 （１）
ここで、Ｃは電子濃度によらない定数である。この式からわかるように、電子濃度ｎを高くできないと、金属とｎ＋Ｇｅのコンタクト抵抗Ｒｃが高くなる。ＧｅのｎＭＩＳＦＥＴを開発するには、極浅かつ高キャリア濃度のｎ＋Ｇｅを形成する必要があり、そのためにはＧｅにおけるｎ型不純物の拡散を充分に抑制しなければならない。 Rc∝exp (C / (n 1/2 )) (1)
Here, C is a constant independent of the electron concentration. As can be understood from this equation, if the electron concentration n can not be increased, the contact resistance Rc of the metal and n + Ge becomes high. In order to develop a Ge nMISFET, it is necessary to form an extremely shallow and high carrier concentration n + Ge, and for this purpose, the diffusion of n-type impurities in Ge must be sufficiently suppressed.
　なお、関連技術として、固相拡散法において、不純物の拡散係数を変えることによって、拡散層の所望の濃度、深さ、あるいは導電型を有する不純物層を制御よく形成する方法が知られている（特許文献１参照）。この特許文献の特徴は、固相拡散の方法にあり、ＡｓドープしたＳｉＯ２が水素を含むとＡｓが拡散しにくくなり、酸化によって還元されるとＡｓが拡散しやすくなるという性質を利用している。 As a related art, there is known a method of controllably forming an impurity layer having a desired concentration, depth or conductivity of a diffusion layer in a solid phase diffusion method by changing the diffusion coefficient of the impurity ( Patent Document 1). The feature of this patent document is the method of solid phase diffusion, which utilizes the property that As becomes difficult to diffuse when As-doped SiO 2 contains hydrogen, and As becomes easy to diffuse when it is reduced by oxidation. There is.
　たとえば、ＡｓとＢをドープしたＳｉＯ２に水素が含まれる場合、Ｓｉに固相拡散させるとＡｓは拡散しにくいので、ＡｓよりもＢが拡散される。そして、そのＳｉＯ２を酸化することによりＡｓも拡散されやすくなるため、Ｓｉの表面側にＡｓによるｎ＋Ｓｉ，内奥側にＢによるｐ－Ｓｉが形成され、つまりｎ＋Ｓｉ／ｐ－Ｓｉが形成されることになる。 For example, when hydrogen is contained in SiO 2 doped with As and B, B diffuses more than As because As is hard to diffuse in solid phase diffusion into Si. Then, As is also easily diffused by oxidizing the SiO 2 , n + Si by As is formed on the surface side of Si, and p − Si by B is formed on the inner side, ie, n + Si / p − Si Will be formed.
　しかしながら、この特許文献１では、Ｓｉにおける不純物の拡散の実施例を示しただけであり、Ｇｅにおいて特徴的なｎ型不純物の拡散が速いことやｐ型不純物の拡散が遅いこと、ｐ型不純物によってｎ型不純物の拡散が抑制されることなどを全く考慮していない。また最終的に形成される構造がｎ＋Ｓｉ／ｐ－Ｓｉとある。さらに、高温が必要な固相拡散に限定される方法のため、ｐ型不純物の濃度プロファイルは必ず表面に近くなるほど高くなり、ｎ＋層を形成するのに望ましくない。それゆえ、この方法だけではそのままＧｅに適用しても、極浅かつ高濃度の電子からなるｐＧｅ層上のｎ＋Ｇｅを形成することは難しい。 However, this patent document 1 only shows an example of the diffusion of the impurity in Si, and that the characteristic diffusion of the n-type impurity in Ge is fast, the diffusion of the p-type impurity is slow, and the p-type impurity is No consideration is given to the suppression of the diffusion of n-type impurities. In addition, the finally formed structure is n + Si / p - Si. Furthermore, due to the method being limited to solid phase diffusion where high temperatures are required, the concentration profile of p-type impurities will necessarily be higher near the surface, which is undesirable for forming an n + layer. Therefore, it is difficult to form n + Ge on a pGe layer consisting of extremely shallow and high concentration electrons even if this method is applied to Ge as it is.
特許第３１３１４３６号公報Patent No. 3131436
　本発明は、上記の事情に基づいてなされたものであり、Ｇｅ層に極浅かつ高キャリア濃度のｎ型不純物拡散領域を有する半導体装置、およびそれを可能にする製造方法を提供することを課題とする。 The present invention has been made based on the above-described circumstances, and an object of the present invention is to provide a semiconductor device having an extremely shallow and high carrier concentration n-type impurity diffusion region in a Ge layer, and a manufacturing method that enables the same. I assume.
　本発明の１態様に係る半導体装置は、ｎ型とｐ型のうちの一方の導電型の半導体基板と、前記半導体基板表面に選択的に設けられ、他方の導電型の一対の不純物拡散領域と、前記一対の不純物拡散領域により挟まれた前記半導体基板上に設けられたゲート絶縁層と、前記ゲート絶縁層の上に設けられたゲート電極とを備え、前記不純物拡散領域の少なくとも一部は、前記一方の導電型を有し、かつ前記基板の不純物濃度より高い不純物濃度を有していることを特徴とする。 A semiconductor device according to one aspect of the present invention includes a semiconductor substrate of one of n-type and p-type conductivity types, and a pair of impurity diffusion regions selectively provided on the surface of the semiconductor substrate and the other conductivity type. A gate insulating layer provided on the semiconductor substrate sandwiched by the pair of impurity diffusion regions, and a gate electrode provided on the gate insulating layer, at least a part of the impurity diffusion regions being It is characterized in that it has the one conductivity type and has an impurity concentration higher than the impurity concentration of the substrate.
　また、本発明の第２の態様に係る半導体装置の製造方法は、Ｇｅを主成分とする半導体層の表面に、高濃度の不純物拡散領域を形成する方法であって、前記半導体層の表面に、ｎ型不純物およびｐ型不純物を導入する工程と、前記ｎ型不純物とｐ型不純物を導入後、熱処理して、前記半導体層内にｎ型不純物拡散領域を形成する工程とを含むことを特徴とする。 A method of manufacturing a semiconductor device according to a second aspect of the present invention is a method of forming a high concentration impurity diffusion region on the surface of a semiconductor layer containing Ge as a main component, wherein the surface of the semiconductor layer is formed. And the steps of: introducing n-type impurities and p-type impurities; and forming an n-type impurity diffusion region in the semiconductor layer by heat treatment after introducing the n-type impurities and p-type impurities. I assume.
　本発明によれば、Ｇｅ層に極浅かつ高キャリア（電子）濃度からなるｎ型不純物拡散領域が形成された半導体装置およびその製造方法を提供することができる。 According to the present invention, it is possible to provide a semiconductor device in which an n-type impurity diffusion region having extremely shallow and high carrier (electron) concentration is formed in a Ge layer, and a method of manufacturing the same.
ＢによってＰの拡散を抑制し、浅くて高濃度の電子からなるｎ＋Ｇｅ領域を形成する方法を説明する不純物濃度プロファイルの模式図で、熱処理前の状態を示す。FIG. 2B is a schematic diagram of an impurity concentration profile illustrating a method of suppressing the diffusion of P by B and forming an n + Ge region composed of shallow and high-concentration electrons, showing a state before heat treatment. ＢによってＰの拡散を抑制し、浅くて高濃度の電子からなるｎ＋Ｇｅ領域を形成する方法を説明する不純物濃度プロファイルの模式図で、熱処理後の状態を示す。It is a schematic diagram of the impurity concentration profile explaining the method of suppressing the diffusion of P by B and forming an n + Ge region composed of shallow and high concentration electrons, and shows a state after heat treatment. Ｇｅ基板におけるＰの不純物濃度プロファイルの熱処理前後を示す図である。It is a figure which shows the heat processing back and front of the impurity concentration profile of P in a Ge board | substrate. 図２の不純物濃度プロファイルに対応するキャリア濃度プロファイルである。It is a carrier concentration profile corresponding to the impurity concentration profile of FIG. Ｇｅ基板にＰとＢが存在する場合の不純物濃度プロファイルの熱処理前後を示す図である。It is a figure which shows the heat processing back and front of the impurity concentration profile in case P and B exist in Ge board | substrate. 図２のＰの不純物プロファイルで、Ｂが無い場合とＢが基板全体にある場合の拡散距離を比較した図である。It is the figure which compared the diffusion distance in the case where there is no B, and B in the whole board | substrate, with the impurity profile of P of FIG. 図２の不純物濃度プロファイルに対応するキャリア濃度プロファイルである。It is a carrier concentration profile corresponding to the impurity concentration profile of FIG. Ｇｅ基板の一定深さの領域にＢが存在する場合における、不純物濃度プロファイルの熱処理前後を示す図である。It is a figure which shows the heat processing back and front of impurity concentration profile in, when B exists in the area | region of fixed depth of Ge board | substrate. 図２のＰの不純物プロファイルで、Ｂが無い場合とＢが基板の一部にある場合（図７）の拡散距離を比較した図である。It is the figure which compared the diffusion distance in the case where there is no B, and B in a part of board | substrate (FIG. 7) by the impurity profile of P of FIG. 図７の不純物濃度プロファイルに対応するキャリア濃度プロファイルである。It is a carrier concentration profile corresponding to the impurity concentration profile of FIG. Ｇｅ基板においてＢがＰの不純物濃度プロファイルに及ぼす影響を示す図で、拡散時間が３秒の場合である。It is a figure which shows the influence which B exerts on the impurity concentration profile of P in Ge board | substrate, and is a case where diffusion time is 3 second. Ｇｅ基板においてＢがＰの不純物濃度プロファイルに及ぼす影響を示す図で、図１０のＢが無いものに対応する。It is a figure which shows the influence which B exerts on the impurity concentration profile of P in Ge board | substrate, and respond | corresponds to what there is no B of FIG. 図１０の不純物濃度プロファイルに対応するキャリア濃度プロファイルである。It is a carrier concentration profile corresponding to the impurity concentration profile of FIG. 図１１の不純物濃度プロファイルに対応するキャリア濃度プロファイルである。It is a carrier concentration profile corresponding to the impurity concentration profile of FIG. Ｇｅ基板においてＢがＰの不純物濃度プロファイルに及ぼす影響を示す図で、拡散時間９５秒の場合である。It is a figure which shows the influence which B exerts on the impurity concentration profile of P in Ge board | substrate, and is a case of 95 second of diffusion times. Ｇｅ基板においてＢが無い場合の不純物濃度プロファイルで、図１４のＢが無いものに相当する。In the Ge substrate, the impurity concentration profile in the absence of B corresponds to the absence of B in FIG. 図１４の不純物濃度プロファイルに対応するキャリア濃度プロファイルである。It is a carrier concentration profile corresponding to the impurity concentration profile of FIG. 図１５の不純物濃度プロファイルに対応するキャリア濃度プロファイルである。It is a carrier concentration profile corresponding to the impurity concentration profile of FIG. Ｇｅ基板においてＢがＰの不純物濃度プロファイルに及ぼす影響を示す図で、拡散時間１００秒の場合である。It is a figure which shows the influence which B exerts on the impurity concentration profile of P in Ge board | substrate, and is the case of 100 second of diffusion times. Ｇｅ基板においてＢが無い場合の不純物濃度プロファイルで、図１８のＢが無いものに相当する。The impurity concentration profile in the absence of B in the Ge substrate corresponds to the absence of B in FIG. 図１８の不純物濃度プロファイルに対応するキャリア濃度プロファイルである。It is a carrier concentration profile corresponding to the impurity concentration profile of FIG. 図１９の不純物濃度プロファイルに対応するキャリア濃度プロファイルである。It is a carrier concentration profile corresponding to the impurity concentration profile of FIG. Ｇｅ基板においてＢがＰの不純物濃度プロファイルに及ぼす影響を示す図で、拡散時間が１０秒の場合である。It is a figure which shows the influence which B exerts on the impurity concentration profile of P in Ge board | substrate, and is a case where diffusion time is 10 second. Ｇｅ基板においてＢが無い場合の不純物濃度プロファイルで、図２２のＢが無いものに相当する。In the Ge substrate, the impurity concentration profile in the absence of B corresponds to the absence of B in FIG. 図２２の不純物濃度プロファイルに対応するキャリア濃度プロファイルである。It is a carrier concentration profile corresponding to the impurity concentration profile of FIG. 図２３の不純物濃度プロファイルに対応するキャリア濃度プロファイルである。It is a carrier concentration profile corresponding to the impurity concentration profile of FIG. ＰとＢの両方を導入して形成したＧｅ基板のキャリア濃度プロファイルで、Ｂのドーズ量が２×１０１４ｃｍ－２の場合を示す。In the carrier concentration profile of Ge substrate formed by introducing both P and B, the case where the dose amount of B is 2 × 10 14 cm −2 is shown. ＰとＢの両方を導入して形成したＧｅ基板のキャリア濃度プロファイルで、Ｂのドーズ量が１×１０１５ｃｍ－２の場合を示す。The carrier concentration profile of a Ge substrate formed by introducing both P and B shows the case where the dose amount of B is 1 × 10 15 cm −2 . 第２の実施形態に係るｎ＋Ｇｅ層を形成する方法で、イオン注入を用いた方法を説明するための半導体基板の断面図である。It is sectional drawing of the semiconductor substrate for demonstrating the method of forming n + Ge layer which concerns on 2nd Embodiment, and using ion implantation. 図２７に続く工程での断面図である。FIG. 28 is a cross-sectional view at a step subsequent to FIG. 27. 図２８に続く工程での断面図である。FIG. 29 is a cross-sectional view in the process following FIG. 28. 図２９に続く工程での断面図である。FIG. 30 is a cross-sectional view at a step subsequent to FIG. 29. 図３０に続く工程での断面図である。FIG. 31 is a cross-sectional view in the process following FIG. 30. 第３の実施形態に係るｎ＋Ｇｅ層を形成する方法で、ＣＶＤを用いた方法を説明するための半導体基板の断面図である。It is sectional drawing of the semiconductor substrate for demonstrating the method using CVD by the method of forming n <+> Ge layer which concerns on 3rd Embodiment. 図３２に続く工程での断面図である。FIG. 33 is a cross-sectional view at a step subsequent to FIG. 32. 図３３に続く工程での断面図である。FIG. 34 is a cross-sectional view in the process following FIG. 図３４に続く工程での断面図である。FIG. 35 is a cross-sectional view at a step subsequent to FIG. 34. 本発明の第４の実施形態に係るＭＩＳ型トランジスタの断面図である。It is sectional drawing of the MIS type | mold transistor which concerns on the 4th Embodiment of this invention. 本発明の第５の実施形態に係るＣＭＩＳＦＥＴの断面図である。It is sectional drawing of CMISFET which concerns on the 5th Embodiment of this invention. 本発明の第６の実施形態に係るＦｉｎＭＩＳＦＥＴの斜視図である。It is a perspective view of FinMISFET which concerns on the 6th Embodiment of this invention. 第６の実施形態に係る素子領域を形成する方法を説明するための半導体基板の斜視図である。It is a perspective view of the semiconductor substrate for demonstrating the method to form the element area | region which concerns on 6th Embodiment. 図３９の次の工程での斜視図である。FIG. 40 is a perspective view at the next step of FIG. 39. 第７の実施形態において、Ｇｅ基板にＰが存在し、外方拡散する場合の熱処理前後の不純物濃度プロファイルを示す図である。In 7th Embodiment, P exists in Ge board | substrate and it is a figure which shows the impurity concentration profile before and behind heat processing in the case of carrying out outward diffusion. 図４１のＰの不純物プロファイルで、外方拡散がある場合と無い場合の拡散距離を比較した図である。It is the figure which compared the diffusion distance in the case where there is an outward diffusion, and there is no in the impurity profile of P of FIG. 図４１の不純物濃度プロファイルに対応する電子濃度プロファイルである。It is an electron concentration profile corresponding to the impurity concentration profile of FIG. 第８の実施形態において、ＰとＢが共存し外方拡散が無い場合における、熱処理前後の不純物濃度プロファイルを示す図である。In 8th Embodiment, when P and B coexist and there is no outward diffusion, it is a figure which shows the impurity concentration profile before and behind heat processing. Ｂが有る場合と無い場合で、いずれも外方拡散が無い場合のＰの拡散距離を比較した図である。It is the figure which compared the diffusion distance of P in the case where there is no B and the case where there is no outward diffusion. 図４５の不純物濃度プロファイルに対応する電子濃度プロファイルである。It is an electron concentration profile corresponding to the impurity concentration profile of FIG. 第９の実施形態において、ＰとＢが共存し外方拡散が有る場合における、熱処理前後の不純物濃度プロファイルを示す図である。In 9th Embodiment, when P and B coexist and there exists outward diffusion, it is a figure which shows the impurity concentration profile before and behind heat processing. Ｇｅ基板中にＢが存在し、外方拡散がある場合と無い場合のＰの拡散距離を比較した図である。It is the figure which compared the diffusion distance of P in case B exists in Ge board | substrate, and there are cases and there is no out diffusion. 図４７の不純物濃度プロファイルに対応する電子濃度プロファイルである。It is an electron concentration profile corresponding to the impurity concentration profile of FIG. 第１０の実施形態に係るｎ＋Ｇｅ層を形成する方法を説明するための半導体基板の断面図である。It is sectional drawing of the semiconductor substrate for demonstrating the method to form n <+> Ge layer which concerns on 10th Embodiment. 図５０に続く工程での断面図である。FIG. 50 is a cross-sectional view at a step subsequent to FIG. 50. 図５１に続く工程での断面図である。FIG. 52 is a cross-sectional view in a step subsequent to FIG. 51; 図５２に続く工程での断面図である。FIG. 52 is a cross-sectional view at a step subsequent to FIG. 52. 第１１の実施形態に係るｎ＋Ｇｅ層を形成する方法を説明するための半導体基板の断面図である。It is sectional drawing of the semiconductor substrate for demonstrating the method to form n <+> Ge layer which concerns on 11th Embodiment. 図５４に続く工程での断面図である。FIG. 56 is a cross-sectional view at a step subsequent to FIG. 54. 図５５に続く工程での断面図である。FIG. 56 is a cross-sectional view at a step subsequent to FIG. 55. 図５６に続く工程での断面図である。FIG. 56 is a cross-sectional view at a step subsequent to FIG. 56. 第１２の実施形態に係るｎ＋Ｇｅ層を形成する方法を説明するための半導体基板の断面図である。It is sectional drawing of the semiconductor substrate for demonstrating the method to form n <+> Ge layer which concerns on 12th Embodiment. 図５８に続く工程での断面図である。FIG. 58 is a cross-sectional view at a step subsequent to FIG. 58. 図５９に続く工程での断面図である。FIG. 60 is a cross-sectional view in the process following FIG. 59. 図６０に続く工程での断面図である。FIG. 61 is a cross-sectional view at a step subsequent to FIG. 60. 図６１に続く工程での断面図である。FIG. 61 is a cross-sectional view in a step subsequent to FIG. 61; Ｇｅ基板中にＰをイオン注入したままの状態での不純物濃度（ＳＩＭＳ）プロファイルである。It is an impurity concentration (SIMS) profile in a state in which P is ion-implanted into a Ge substrate. Ｇｅ基板中にＰをイオン注入して熱処理した場合の不純物濃度（ＳＩＭＳ）プロファイルである。It is an impurity concentration (SIMS) profile at the time of ion-implanting P into a Ge substrate and performing heat treatment. 図４２のＧｅ基板中のＢとＰの不純物濃度プロファイルとその際に形成される半導体の導電型のプロファイルを説明する模式図である。It is a schematic diagram explaining the impurity concentration profile of B and P in Ge board | substrate of FIG. 42, and the profile of the conductivity type of the semiconductor formed in that case. Ｇｅ基板中の高濃度のＢによってＰの拡散が抑制されることと、その際に形成される半導体の導電型のプロファイルを説明する模式図である。It is a schematic diagram explaining that the diffusion of P is suppressed by high concentration B in a Ge board | substrate, and the profile of the conductivity type of the semiconductor formed in that case.
　本発明の実施形態を説明する前に、本発明に至った経緯について説明する。前述したように、極浅かつ高電子濃度からなるｎ＋Ｇｅを形成するためには、熱処理時にｎ型不純物を拡散させないようにする技術が必要である。 Before describing the embodiments of the present invention, the background of the present invention will be described. As described above, in order to form n + Ge having an extremely shallow and high electron concentration, a technique for preventing the diffusion of n-type impurities during heat treatment is required.
　Ｇｅにおいてｎ型不純物の拡散のメカニズムは次のように説明される（例えば、 H. Bracht, Phys. Rev. B 75, 035210 (2007)参照）。Ｇｅ中でのｎ型不純物Ａの拡散は、格子置換位置(substitutional site)にある正イオンＡ＋ ｓと二価の負電荷を持つ空孔Ｖ２－が
　　　　　　　Ａ＋ ｓ＋Ｖ２－⇔（ＡＶ）－　…　（２）
の、化学平衡［質量作用の法則］によって表される反応によってペアになり、（ＡＶ）－（dopant-vacancy pair）の形を取って拡散する。つまり、Ａ＋ ｓによる直接の拡散はなく、（ＡＶ）－という形態(diffusion vehicle)を通して間接的に拡散する。Ａ＋ ｓによる拡散と見なしたとき、拡散方程式は、実効的な拡散係数Ｄｅｆｆを持つ下記の式（３）、（４）で表現される。
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000002
 The mechanism of diffusion of n-type impurities in Ge is described as follows (see, for example, H. Bracht, Phys. Rev. B 75, 035210 (2007)). In the diffusion of n-type impurity A in Ge, a positive ion A + s at a substitutional site (vacancy site) and a vacancy V 2 − having a divalent negative charge are A + s + V 2 − (AV) - ... (2)
The reaction is represented by the chemical equilibrium [the law of mass action], and is diffused in the form of (AV) - (dopant-vacancy pair). That is, no direct diffusion by A + s, (AV) - indirectly diffuses through form (Diffusion vehicle) that. When considered as diffusion by A + s , the diffusion equation is expressed by the following equations (3) and (4) having an effective diffusion coefficient D eff .
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000002
ここで、Ｃｓ ＋（ｘ，ｔ）は、格子置換位置にあるｎ型不純物の正イオンの濃度であり、xはｎ型不純物の座標（本明細書では基板表面からの深さと定義）、ｔは拡散時間、ｎ（ｘ，ｔ）は電子濃度、ｎｉ（ｘ，ｔ；Ｔ）は真性キャリア濃度（温度Ｔに依存）、Ｄ＊（ｎｉ）はｎｉに依存した係数である。このように、ｎ型不純物の実効拡散係数は、電子濃度ｎの自乗の依存性を持っている。これは、Ａ＋ ｓと（ＡＶ）－の電荷状態の差に由来している。Ｇｅ中のｎ型不純物は、このＤｅｆｆの電子濃度の自乗の依存性によって、特異な拡散現象を示す。Ｇｅ中にｎ型不純物しかない場合、不純物濃度が高くなるほど、それに伴って電子濃度も高くなると考えて良い。それゆえ、（４）式より、不純物濃度が高いときにはＤｅｆｆは大きくなり、不純物濃度が低くなるとＤｅｆｆは小さくなる。 Here, C s + (x, t) is the concentration of the positive ion of the n-type impurity at the lattice substitution position, x is the coordinate of the n-type impurity (herein defined as the depth from the substrate surface), t is a diffusion time, n (x, t) is an electron concentration, ni (x, t; T) is an intrinsic carrier concentration (depends on temperature T), and D * (ni) is a coefficient depending on ni. Thus, the effective diffusion coefficient of the n-type impurity has the dependence of the square of the electron concentration n. This is derived from the difference in charge state of A + s and (AV) − . The n-type impurity in Ge exhibits an unusual diffusion phenomenon due to the dependence of the electron concentration of D eff on the square. When only n-type impurities are present in Ge, it may be considered that the higher the impurity concentration, the higher the electron concentration. Therefore, (4) from the equation, D eff when high impurity concentration is increased, D eff when the impurity concentration is low is reduced.
　図６３は、燐（Ｐ）をＧｅにイオン注入して熱処理したときの不純物濃度プロファイルをＳＩＭＳによって分析したものである。Ｐのドーズ量は５×１０１５ｃｍ－２、加速エネルギーは３０ｋｅＶであり、窒素雰囲気で６００℃、３０分の熱処理を施している。比較のために、熱処理を加える前、つまりイオン注入しただけの場合のシミュレーションによる結果も示した。熱処理前は、ピーク濃度で略１０２１ｃｍ－３あり、濃度が１×１０１９ｃｍ－３である深さは約１００ｎｍである。 FIG. 63 shows the result of SIMS analysis of the impurity concentration profile when phosphorus (P) is ion-implanted into Ge and heat-treated. The dose amount of P is 5 × 10 15 cm −2 , the acceleration energy is 30 keV, and heat treatment is performed at 600 ° C. for 30 minutes in a nitrogen atmosphere. For comparison, simulation results before heat treatment, that is, in the case of only ion implantation are also shown. Before the heat treatment, the peak concentration is approximately 10 21 cm −3 and the depth is 1 × 10 19 cm −3 at a concentration of approximately 100 nm.
　一方で、熱処理後は、ピーク濃度で２×１０１９ｃｍ－３程度までに大きく減少し、また濃度が１×１０１９ｃｍ－３である深さは４００ｎｍを超えるほど拡散してしまう。ここで特徴的なのはその箱形というべきプロファイルの形状である。表面から４００ｎｍ程度までは緩やかに濃度は減少するが、それよりも深くなると急峻に濃度が減少する。これは、Ｄｅｆｆがｎ２に比例しているためである。つまり、濃度が高いとＤｅｆｆが大きいため拡散が速く、濃度が低くなるとＤｅｆｆが小さくなるため、特徴的な箱形プロファイルになると説明できる。 On the other hand, after the heat treatment, greatly reduced by 2 × 10 approximately 19 cm -3 at the peak concentration and the depth concentration of 1 × 10 19 cm -3 is diffuses more than the 400 nm. What is characteristic here is the shape of the profile which should be said box-like. The concentration gradually decreases from the surface to about 400 nm, but the concentration sharply decreases as it gets deeper than that. This is because D eff is proportional to n 2 . That is, if the concentration is high, the diffusion is fast because D eff is large, and since D eff is small if the concentration is low, it can be explained that the characteristic box-like profile is obtained.
　このように、Ｇｅ中のｎ型不純物の拡散が（ＡＶ）－という形態を通して拡散し、電子濃度の自乗ｎ２に依存する拡散係数を持つのならば、この負電荷を打ち消せば拡散が抑制できるかもしれない，と本発明者らは考えた。そこで、ｎ型不純物を補償するｐ型不純物としてボロン（Ｂ）を選び、Ｇｅ基板に導入して、Ｐの拡散が抑制できるかを確かめた。その結果が図６４である。Ｂを導入したＧｅにおけるＰの不純物プロファイルをＳＩＭＳ分析によって求めた。Ｇｅ基板にＢをドーズ量５×１０１５ｃｍ－２、加速エネルギー３０ｋｅＶで導入したあと、図６３と同じ条件でＰを導入して熱処理している。 Thus, diffusion of the n-type impurities in the Ge (AV) - diffuse through the form of if to have a diffusion coefficient dependent on the square n 2 of the electron density, diffusion suppressing if Uchikese this negative charge The present inventors thought that it might be possible. Therefore, boron (B) was selected as a p-type impurity to compensate for the n-type impurity and introduced into a Ge substrate to check whether the diffusion of P can be suppressed. The result is shown in FIG. The impurity profile of P in Ge introduced B was determined by SIMS analysis. After introducing B into a Ge substrate with a dose of 5 × 10 15 cm −2 and an acceleration energy of 30 keV, P is introduced and heat-treated under the same conditions as FIG.
　その結果によると、まず、Ｂのピーク濃度は約１×１０２１ｃｍ－３であり、またそのプロファイルから熱処理を加えても拡散していないことがわかる。従来までに、ＢＦ２をドーズ量４×１０１５ｃｍ－２、加速エネルギー２０ｋｅＶでＧｅにイオン注入し、６５０℃，１０秒の熱処理を施した場合でも、Ｂは全く拡散しない、という報告があり（C. O. Chui et al., Appl. Phys. Lett. 83, 3275 (2003)参照））、本発明での結果と矛盾がない。 According to the results, first, the peak concentration of B is about 1 × 10 21 cm −3 , and it is understood from the profile that the peak concentration is not diffused even when heat treatment is applied. It has been reported that B does not diffuse at all even when ion-implanting BF 2 into Ge at a dose of 4 × 10 15 cm −2 and acceleration energy of 20 keV and heat treatment at 650 ° C. for 10 seconds. (See, CO Chui et al., Appl. Phys. Lett. 83, 3275 (2003)), consistent with the results of the present invention.
　また、Ｐの濃度が１×１０１９ｃｍ－３である深さは約１００ｎｍであって、これは熱処理前のプロファイルと同じである。つまりＰは全く拡散していない。Ｂがない場合には、Ｐの濃度は２×１０１９ｃｍ－３まで低下してしまったが（図６３）、Ｂがある場合にはＰはピークで約７×１０２０ｃｍ－３という高濃度を維持している。 Also, the depth at which the concentration of P is 1 × 10 19 cm −3 is about 100 nm, which is the same as the profile before heat treatment. That is, P is not diffused at all. In the absence of B, the concentration of P decreased to 2 × 10 19 cm -3 (Fig. 63), but in the presence of B, P peaked at about 7 × 10 20 cm -3 at the peak. The concentration is maintained.
　こうして、Ｇｅにおけるｎ型不純物の拡散メカニズムに基づき、ｎ型不純物の拡散形態である（ＰＶ）－を打ち消すようにｐ型不純物を導入すれば、ｎ型不純物の拡散が完全に抑制できることを発見した。しかし、ＢによってＰの拡散は完全に抑えられるが、図６５からわかるように、基板の全体でＰよりもＢの濃度が高いため、ｐ＋Ｇｅが形成されている。Ｐの拡散が抑制できても、ｎ＋Ｇｅが形成されないのでは意味がない。 Thus, based on the diffusion mechanism of n-type impurity in Ge, a diffusion form of n-type impurity (PV) - By introducing a p-type impurity so as to cancel the diffusion of n-type impurities are found to be able to completely suppress . However, although the diffusion of P is completely suppressed by B, as can be seen from FIG. 65, p + Ge is formed because the concentration of B is higher than P in the entire substrate. Even if the diffusion of P can be suppressed, it does not make sense that n + Ge is not formed.
　Ｐの拡散を抑制しながらｎ＋Ｇｅを形成する方法としては、例えば、図６６のような方法が考えられる。ｐ型不純物としてＢを基板の奥に高濃度に導入し、ｎ型不純物としてＰを基板の表面付近に導入する。熱処理を加えると、Ｂは拡散しないが、Ｐは基板の奥に拡散し、Ｐの濃度に較べてＢの濃度が充分に高ければ、ＢによってＰの拡散が抑制される。Ｐの不純物濃度が高くできるので、電子濃度も高くでき、基板の表面にｎ＋Ｇｅが形成されることになる。しかし、この構造では、ｎ＋Ｇｅが形成されるかもしれないが、高濃度のＢが存在するためｐ＋Ｇｅも同時に形成されることになる。つまり、ｎ＋Ｇｅ／ｐ＋Ｇｅ構造ができてしまい、これではソース／ドレインには適用できない。 As a method of forming n + Ge while suppressing the diffusion of P, for example, a method as shown in FIG. 66 can be considered. B is introduced at a high concentration to the back of the substrate as a p-type impurity, and P is introduced near the surface of the substrate as an n-type impurity. When heat treatment is applied, B does not diffuse, but P diffuses to the back of the substrate, and if the concentration of B is sufficiently high compared to the concentration of P, B suppresses the diffusion of P. Since the impurity concentration of P can be increased, the electron concentration can also be increased, and n + Ge is formed on the surface of the substrate. However, in this structure, n + Ge may be formed, but p + Ge will be formed at the same time due to the presence of a high concentration of B. That is, an n + Ge / p + Ge structure is formed, which is not applicable to the source / drain.
　本発明者らは、上記発見に伴う問題を解決し、ｐ＋Ｇｅを存在させずに、極浅かつ高キャリア（電子）濃度であるｎ＋Ｇｅ構造を形成する方法を見出した。またそれによって形成された理想的なｎ＋Ｇｅ構造を見出すことができた。これを以下に実施形態として説明する。本発明の実施形態について図面を参照しながら説明するが、各実施形態を通して共通の構成には同一符号を付すものとし、重複する説明は省略する。また、各図の中には本発明の説明とその理解を促すための模式図があり、その形状や寸法、比などが実際の装置と異なる個所があっても、これらは以下の説明と公知の技術を参酌して適宜、設計変更することができる。 The present inventors have solved the problems associated with the above discovery and have found a method for forming an n + Ge structure which is an extremely shallow and high carrier (electron) concentration without the presence of p + Ge. It was also possible to find the ideal n + Ge structure formed thereby. This will be described below as an embodiment. Although the embodiments of the present invention will be described with reference to the drawings, the same reference numerals are given to the same components throughout the embodiments, and the redundant description will be omitted. Further, in each of the drawings, there is a schematic view for explaining the present invention and promoting its understanding, and even if there are places where its shape, size, ratio, etc. are different from the actual device, these will be described below. The design can be changed as appropriate in consideration of the technique of
　なお、本明細書において「Ｇｅを主成分とする」とは、Ｇｅの含有量が８５ａｔ．％以上であることをさす。例えば、Semicond. Sci. Technol. 12(1997)1515-1549には、Ｓｉの伝導帯の最小値はΔ点であり、Ｇｅの伝導帯の最小値はＬ点であり、ＳｉＧｅは組成比に依存して、ＳｉｘＧｅ１－ｘの場合、ｘ＜０．８５でΔとなり、ｘ＞０．８５でＬ点となることが報告されている。 In the present specification, "having Ge as a main component" means that the content of Ge is 85 at. It means that it is% or more. For example, in Semicond. Sci. Technol. 12 (1997) 1515-1549, the minimum value of the conduction band of Si is the Δ point, the minimum value of the conduction band of Ge is the L point, and SiGe depends on the composition ratio Then, in the case of Si x Ge 1 -x , it has been reported that Δ is obtained at x <0.85 and L point is obtained at x> 0.85.
（第１の実施形態）
　ここでは、本発明の第１の実施形態に係わる極浅かつ高電子濃度からなるｎ＋Ｇｅ層を有する半導体装置（基板）とその製造方法を説明する。図１Ａ，１Ｂは、Ｇｅ基板における不純物プロファイルを表す模式図である。 First Embodiment
Here, a semiconductor device (substrate) having an extremely shallow and high electron concentration n + Ge layer according to the first embodiment of the present invention and a method of manufacturing the same will be described. 1A and 1B are schematic views showing impurity profiles in a Ge substrate.
　図１Ａは熱処理前を示している。一定で低濃度のｐ型不純物を含む基板に、基板濃度に較べれば高濃度の、ｎ型不純物とｐ型不純物の二つを導入する。そのとき、ｐ型不純物は基板の内奥側に導入し、ｎ型不純物はそれよりも表面側に導入する。ここで、典型的な例として、ｎ型不純物はＰ、ｐ型不純物はＢを選んだ。このとき、Ｇｅ中の各不純物が電気的に活性化していれば、図に示すように、ｎ＋Ｇｅ／ｐ＋Ｇｅ／ｐ－Ｇｅ構造が形成される。尚、熱処理前にこのように不純物が電気的に活性化している必要は無い。各不純物の濃度は、図６３の場合と異なり、Ｐのピーク濃度の方が、Ｂのそれよりも充分に高くなっていることが特徴である。 FIG. 1A shows the state before heat treatment. An n-type impurity and a p-type impurity, which are higher in concentration than the substrate concentration, are introduced into a substrate containing a constant, low-concentration p-type impurity. At that time, the p-type impurity is introduced to the inner side of the substrate, and the n-type impurity is introduced to the surface side more than that. Here, as a typical example, n-type impurity was selected as P, and p-type impurity as B. At this time, if each impurity in Ge is electrically activated, an n + Ge / p + Ge / p - Ge structure is formed as shown in the figure. It is not necessary to electrically activate the impurities in this manner before the heat treatment. Unlike the case of FIG. 63, the concentration of each impurity is characterized in that the peak concentration of P is sufficiently higher than that of B.
　この構造に熱処理を加えると、前述したように、Ｇｅにおけるｎ型およびｐ型不純物の特性から、Ｐは拡散するが、Ｂは拡散しない。またＧｅ中におけるＰは、（ＰＶ）－という形態を通して間接的に拡散するため、プロファイルは箱形の、濃度が急峻に変化するものになる。そして、高濃度にＢが存在する領域をＰが拡散するとき、Ｂによって負電荷が打ち消されるため、（ＰＶ）－という形態での拡散が起こりにくくなり、Ｐの拡散が遅くなる。さらに熱処理を続けると、Ｐは図１Ｂのように、Ｂが高濃度に存在する領域全体に拡散する。Ｇｅ中でＢよりも常にＰの濃度を高くできるので、ｎ＋Ｇｅを形成できる。 When heat treatment is applied to this structure, as described above, P diffuses but B does not diffuse due to the characteristics of n-type and p-type impurities in Ge. P in the Ge also, (PV) - to indirectly diffused through that form, the profile of the box-shaped, concentration of which changes sharply. Then, when P diffuses in a region where B is present at a high concentration, the negative charge is canceled by B, so diffusion in the form of (PV) − becomes difficult to occur and diffusion of P becomes slow. When the heat treatment is further continued, P diffuses throughout the region where B is present at a high concentration as shown in FIG. 1B. Since the concentration of P can always be higher than B in Ge, n + Ge can be formed.
　つまり、最初はｐ型不純物を用いてｎ型不純物の拡散を抑制し、最終的にｎ型不純物をｐ型不純物よりも高くできるので、ｐ＋Ｇｅ領域を残さずに、浅くて高電子濃度からなるｎ＋Ｇｅ構造を形成できる。 That is, first, p-type impurities are used to suppress the diffusion of n-type impurities, and finally n-type impurities can be made higher than p-type impurities, so the p + Ge region is left shallow and shallow and high electron concentration N + Ge structure can be formed.
　次に、本発明によるｎ＋Ｇｅが定量的にどのように形成され、どのような構造になるかを説明する。前述したように、Ｇｅにおけるｎ型不純物の拡散は、（２）～（４）式の拡散方程式で表現される。ｐ型不純物も共存する場合は、それらに加えて次のことを考慮すれば良い。まず、ｐ型不純物は熱処理をしても拡散しないと仮定する。また、Ｇｅは電荷中性条件である（５）式をを満たすと仮定する。 Next, it will be explained how n + Ge according to the present invention is formed quantitatively and what kind of structure it takes. As described above, the diffusion of n-type impurities in Ge is expressed by the diffusion equations (2) to (4). When p-type impurities also coexist, the following may be taken into consideration in addition to them. First, it is assumed that p-type impurities do not diffuse even by heat treatment. Further, it is assumed that Ge satisfies the charge neutral condition (5).
　　　　　　　ｎ＋（ＮA－pA）＝ｐ＋（ＮD－ｎD）　　　　　 …　（５）
ここで、ｎは電子濃度、ｐはホール濃度、ＮAはｐ型不純物濃度、ＮDはｎ型不純物濃度、ｐAはアクセプターレベルに存在するホール密度、ｎDはドナーレベルに存在するドナー密度である。ｎ，ｐ，ｐA，ｎDは通常の平衡系の統計力学で表現できるとする。この（５）式を用いて、Ｇｅ基板の各座標、拡散の各時間におけるｎを求めながら、（３）式によって、Ｇｅにおけるｎ型不純物の拡散を計算した。ｎ型不純物と共存するｐ型不純物の影響は、（５）式から決まるｎを通して反映されている。 n + (N A- p A ) = p + (N D- n D ) (5)
Here, n is an electron concentration, p is a hole concentration, N A is a p-type impurity concentration, N D is an n-type impurity concentration, p A is a hole density at the acceptor level, and n D is a donor at the donor level It is a density. Let n, p, p A and n D be expressed by the statistical mechanics of a normal equilibrium system. The diffusion of n-type impurities in Ge was calculated by the equation (3) while obtaining the coordinates of the Ge substrate and n at each diffusion time using the equation (5). The influence of the p-type impurity coexisting with the n-type impurity is reflected through n determined from the equation (5).
＜ｎ＋Ｇｅ層にｎ型不純物だけが存在している場合＞
　図２は、本実施形態によるｎ+Ｇｅが形成される過程を計算した一例であり、不純物濃度と深さの関係である。計算するには拡散係数などが必要であり、それらは実験値とフィッティングして求めた。図２は、ｎ型不純物だけがＧｅに存在している場合である。ここで、ｎ型不純物の例としてＰを選んだ。Ｐの初期プロファイル（熱処理前のプロファイル）は、Ｇｅ基板表面から射影飛程（Projected Range）Ｒｐが５．０ｎｍ、標準偏差１．０ｎｍ、ドーズ量１×１０１５ｃｍ－２のガウス分布であると想定した。熱処理は短時間（１秒）のスパイクアニールを想定している。温度は７７３Ｋである。熱処理中の時間発展を十等分（０，０．１，０．２，…，１．０）にして、Ｐの不純物濃度プロファイルの経時変化を示した。 <When only n-type impurities exist in n + Ge layer>
FIG. 2 is an example of calculating the process of forming n + Ge according to the present embodiment, and shows the relationship between the impurity concentration and the depth. In order to calculate, the diffusion coefficient etc. are required, and they were found by fitting with the experimental values. FIG. 2 shows the case where only n-type impurities are present in Ge. Here, P was selected as an example of the n-type impurity. The initial profile of P (profile before heat treatment) is a Gaussian distribution with a Projected Range Rp of 5.0 nm, a standard deviation of 1.0 nm, and a dose of 1 × 10 15 cm −2 from the Ge substrate surface I assumed. The heat treatment assumes spike annealing for a short time (1 second). The temperature is 773K. The time evolution during heat treatment was made equal (0, 0.1, 0.2, ..., 1.0) to show the change with time of the impurity concentration profile of P.
　本例のようにＢが無い場合には、図２のプロファイルの経時変化からわかるように、最初に大きく拡散し、徐々にゆっくりになって拡散していく。熱処理前に濃度が１×１０１９ｃｍ－３の位置はＲｐから３．５ｎｍであるが、０．１秒後は１３．２ｎｍまで広がり、０．２秒後では１６．８ｎｍ、０．３秒後では１９．０ｎｍと広がり、１秒後では２７．２ｎｍまで拡散する。 When B is not present as in this example, as is apparent from the change with time of the profile in FIG. 2, the light first diffuses and then gradually spreads gradually. Before heat treatment, the concentration is 1 × 10 19 cm -3 from Rp to 3.5 nm, but after 0.1 sec, it spreads to 13.2 nm, and after 0.2 sec, 16.8 nm, 0.3 sec After that, it spreads to 19.0 nm, and diffuses to 27.2 nm after one second.
　図３は、図２と同じ条件のものであり、その電子濃度プロファイルを示したものである。図２と同様に、熱処理中の時間発展を十等分にして、Ｐの電子濃度プロファイルの変化を示した。図３を図２と較べるとわかるように、７×１０１７ｃｍ－３以上で不純物と電子濃度はほぼ一致している。これはＧｅ中にｎ型ドーパントであるＰだけが存在するからであり、表面から約３３ｎｍの深さまで電子だけからなるｎ＋Ｇｅになっている。 FIG. 3 shows the electron concentration profile under the same conditions as FIG. Similar to FIG. 2, the time evolution during the heat treatment was made sufficiently equal to show the change of the electron concentration profile of P. As can be seen by comparing FIG. 3 with FIG. 2, the impurity and electron concentrations almost coincide with each other at 7 × 10 17 cm −3 or more. This is because only P, which is an n-type dopant, is present in Ge, and is n + Ge consisting only of electrons up to a depth of about 33 nm from the surface.
　尚、ここでの電子濃度は、７７３Ｋという不純物が拡散する温度のときのものである。そのため、不純物濃度が電子濃度とほぼ同じ、つまりほぼ１００％イオン化していると考えている。一方で、室温では不純物が不完全イオン化を起こし、電子濃度が不純物濃度よりも低くなることがある。しかし、不純物が高濃度の場合には金属絶縁体転移により不純物の不完全イオン化はなく、つまり室温でも不純物濃度と電子濃度はほとんど同じと考えて良い。電子濃度が７×１０１７ｃｍ－３の一定領域は、真性キャリア濃度ｎiによるものであり、室温では基板濃度より低くなり、基板が通常の濃度のｐ型であれば、ホール濃度一定の領域が室温では現れる。 Here, the electron concentration is at a temperature at which the impurity of 773 K diffuses. Therefore, it is considered that the impurity concentration is approximately the same as the electron concentration, that is, approximately 100% ionized. On the other hand, at room temperature, the impurity may cause incomplete ionization, and the electron concentration may be lower than the impurity concentration. However, when the concentration of the impurity is high, there is no incomplete ionization of the impurity due to metal-insulator transition, that is, the impurity concentration and the electron concentration may be considered to be almost the same even at room temperature. The constant region with an electron concentration of 7 × 10 17 cm -3 is due to the intrinsic carrier concentration ni, which is lower than the substrate concentration at room temperature, and the region with a constant hole concentration is Appears at room temperature.
＜ｎ＋Ｇｅ層にｎ型不純物とp型不純物が同時に存在している場合＞
　図４は、ｎ型不純物と共にp型不純物も同時に存在している場合である。図２の場合に加えて、p型不純物がＧｅ基板全体に２．５×１０２０ｃｍ－３の高濃度で共存している。ここではp型不純物の例としてＢを選んだ。 <When n-type impurity and p-type impurity exist simultaneously in n + Ge layer>
FIG. 4 shows the case where a p-type impurity is also present simultaneously with the n-type impurity. In addition to the case of FIG. 2, p-type impurities coexist in the entire Ge substrate at a high concentration of 2.5 × 10 20 cm −3 . Here, B was selected as an example of the p-type impurity.
　ＢがＧｅ基板全体にある場合でも、Ｂが無い場合と同様に、最初は大きく拡散し、徐々にゆっくり拡散していく。しかしながら、Ｂがある場合には、Ｂが無い場合に較べて、その拡散速度は相対的にゆっくりである。熱処理前に濃度が１×１０１９ｃｍ－３の位置はＲｐら３．５ｎｍであり、０．１秒後は９．０ｎｍまで広がり、０．２秒後では１０．６ｎｍ、０．３秒後では１１．４ｎｍと広がり、１秒後では１４．２ｎｍまで拡散する。 Even when B is in the whole of the Ge substrate, it diffuses at first largely and gradually and gradually as in the case without B. However, when B is present, its diffusion rate is relatively slow compared to when B is absent. Before heat treatment, the position of the concentration is 1 × 10 19 cm -3 is 3.5 nm at Rp et al. And spreads to 9.0 nm after 0.1 sec, 10.6 nm after 0.2 sec, after 0.3 sec Spreads to 11.4 nm and diffuses to 14.2 nm after one second.
　図５は、Ｂ無しの場合（図２）と有りの場合（図４）のＰの拡散距離を比較したものである。濃度が１×１０１９ｃｍ－３の場合の、同じ拡散時間におけるそれぞれの拡散距離（Ｒｐを原点に取ったときの深さ）をプロットした。図から明らかなように、Ｂがあることによって拡散距離が短くなっており、それは距離が大きくなるほど、言い換えれば拡散時間が長くなるほど、その差は大きくなっていく。このように、Ｂがあることによって拡散が抑えられることがわかる。 FIG. 5 compares the diffusion distances of P without B (FIG. 2) and with P (FIG. 4). Each diffusion distance (depth when taking Rp as the origin) at the same diffusion time when the concentration is 1 × 10 19 cm −3 was plotted. As apparent from the figure, the presence of B shortens the diffusion distance, and the larger the distance, in other words, the longer the diffusion time, the larger the difference. Thus, it can be seen that the presence of B suppresses diffusion.
　図６は、図４と同じ条件のものであり、その電子濃度プロファイルを示したものである。ＢがＧｅ基板全体に２．５×１０２０ｃｍ－３という高濃度で存在しているため、熱処理前の状態でＰ濃度がＢ濃度より低い場所では、電子濃度は２．８×１０１５ｃｍ－３になる。（４）式からわかるように実効拡散係数は電子濃度の自乗に比例しているため、電子濃度が低いほど拡散が遅くなる。Ｂが無い場合には８．４×１０１７ｃｍ－３であるが、Ｂがある場合には２．８×１０１５ｃｍ－３であり、電子濃度が２桁以上低くなる。それゆえ、Ｂの存在によって実効拡散係数が小さくなり、拡散がゆっくりになる。 FIG. 6 shows the electron concentration profile under the same conditions as FIG. Since B is present at a high concentration of 2.5 × 10 20 cm -3 throughout the Ge substrate, the electron concentration is 2.8 × 10 15 cm at a place where the P concentration is lower than the B concentration before the heat treatment. It becomes -3 . As can be seen from equation (4), the effective diffusion coefficient is proportional to the square of the electron concentration, so the lower the electron concentration, the slower the diffusion. In the absence of B, it is 8.4 × 10 17 cm −3 , but in the presence of B, it is 2.8 × 10 15 cm −3 , and the electron concentration decreases by two digits or more. Therefore, the presence of B reduces the effective diffusion coefficient and makes diffusion slower.
　こうして、ＢがあることによってＰの拡散を抑えることができ、Ｂが無いときに較べて、浅くて高濃度のｎ＋Ｇｅが表面に形成されることになる。しかし、図４からわかるように、ＰよりＢの濃度が高い領域があるため、これはｎ＋Ｇｅ／ｐ＋Ｇｅである。ｐ＋Ｇｅにおけるホール濃度ｐは、図６と質量作用の法則ｎｐ＝ｎｉ２（ｎは電子濃度）の関係式から求められ、それは１．７５×１０２０［＝（７×１０１７）２／（２．８×１０１５）］ｃｍ－３という高濃度である。また、さらに、高濃度のＰが存在していてもＢによって補償されるため、Ｐの不純物濃度に較べて電子濃度が低くなっている。 Thus, the presence of B can suppress the diffusion of P, and a shallow and high concentration of n + Ge will be formed on the surface as compared to the absence of B. However, as can be seen from FIG. 4, this is n + Ge / p + Ge because there is a region where the concentration of B is higher than P. The hole concentration p in p + Ge is obtained from the relationship between FIG. 6 and the mass action law np = ni 2 (n is the electron concentration), which is 1.75 × 10 20 [= (7 × 10 17 ) 2 / It is a high concentration of (2.8 × 10 15 )] cm −3 . Furthermore, even if a high concentration of P is present, since it is compensated by B, the electron concentration is lower than the impurity concentration of P.
＜ｐ＋Ｇｅ層を作らずにｎ＋Ｇｅを形成する方法＞
　ｐ＋Ｇｅ層を作らず、また表面での電子濃度を下げずに浅くて電子が高濃度のｎ＋Ｇｅを形成するには、Ｂのプロファイルを調整すればよい。図７はＢのプロファイルを調整したものである。図３のように全体にＢを入れず、２．５×１０２０ｃｍ－３の一定濃度であるという条件は同じままに、表面から７．３ｎｍ～１８．９ｎｍまでの深さにだけＢが存在するようにした。Ｐのプロファイルは、図７からわかるように、図４のＰのプロファイルとほとんど差がない。また、このように一部にだけＢがある場合とＢが無い場合のＰの拡散距離を比較したものが図８であるが、図５とほぼ同じである。つまり、Ｂを基板全体に入れずに、一部だけに入れてもＰの拡散抑制の効果が同じくらいあるということを意味している。そして、一部だけにＢを入れるために、図４からわかるように、熱処理後に最終的に得られるＰのプロファイルは、Ｂよりも基板全体で濃度を高くすることができる。 <Method to form n + Ge without forming p + Ge layer>
The profile of B may be adjusted in order to form a high concentration n + Ge of electrons without forming ap + Ge layer and without reducing the electron concentration at the surface and forming a shallow electron. FIG. 7 is an adjustment of the profile of B. As shown in FIG. 3, B does not enter entirely, and the condition of constant concentration of 2.5 × 10 20 cm -3 is the same, B is only from the surface to a depth of 7.3 nm to 18.9 nm. It was made to exist. The profile of P is almost the same as the profile of P in FIG. 4, as can be seen from FIG. Moreover, although FIG. 8 compares the diffusion distance of P when there is B only in a part and there is no B in this way, it is almost the same as FIG. In other words, this means that even if only B is added to the entire substrate, and even if it is added to only a part, the effect of suppressing the diffusion of P is the same. Then, in order to put B only in part, the profile of P finally obtained after the heat treatment can be made higher in concentration in the whole substrate than B, as can be seen from FIG.
　図９は、図７と同じ条件のものであり、その電子濃度プロファイルを示したものである。図９以降の類似図面には、熱処理前と熱処理後の注記の記載を省略するが、図２と同様に、放物線状の曲線が熱処理前、テラス状の曲線が熱処理後を示す。図６とは異なり、基板の内奥側では真性キャリア濃度になっていて、Ｂが無い場合の図３と同じである。つまり、基板の内奥側にはｐ＋Ｇｅではなく、もともとのＧｅ基板の状態、例えば通常程度の不純物を含んだｐＧｅ基板になっていることがわかる。また、図６と較べて、表面側において電子濃度が高くなっている。これは表面にＢが存在しないため、電子濃度の減少、損失などが起こらず、したがって、電子濃度がＰの不純物濃度とほぼ同じ濃度になっているためである。ＰはＢによる拡散抑制効果により高い不純物濃度が維持されているので、Ｂが無い場合よりも高い電子濃度が実現されている。 FIG. 9 shows the electron concentration profile under the same conditions as FIG. Although the description of the notes before and after the heat treatment is omitted in the similar drawings after FIG. 9, the parabolic curve shows the heat treatment before and the terrace curve shows the heat treatment after the heat treatment as in FIG. Unlike FIG. 6, the inner side of the substrate has an intrinsic carrier concentration, which is the same as FIG. 3 when B is absent. That is, it can be seen that the inner side of the substrate is not the p + Ge, but the original Ge substrate state, for example, a pGe substrate containing impurities at a normal level. Also, compared to FIG. 6, the electron concentration is higher on the surface side. This is because there is no B on the surface, so there is no reduction or loss of the electron concentration, and hence the electron concentration is approximately the same as the impurity concentration of P. Since P has a high impurity concentration maintained by the diffusion suppressing effect of B, a higher electron concentration is realized than when B is absent.
　このように、Ｂを表面と基板の内奥側に入れず、最適な場所に最適な濃度で導入すれば、ＢによってＰの拡散を抑制し、Ｂがあってもｐ＋Ｇｅを残さず、また表面の電子濃度を低くすることなく、浅くて高濃度の電子からなるｎ＋Ｇｅ層を形成することができる。 In this way, if B is introduced at the optimum concentration to the surface and the inner side of the substrate, the diffusion of P is suppressed by B, and even if B is present, p + Ge is not left, In addition, it is possible to form an n + Ge layer composed of shallow and high concentration electrons without lowering the electron concentration on the surface.
＜ｎ型不純物を抑制するために必要なｐ型不純物の濃度＞
　つづいて、ｎ型不純物を抑制するためには、どのくらいの濃度のｐ型不純物が必要かを説明する。ここでもｎ型不純物としてＰ，ｐ型不純物としてＢを選んだ。Ｐの初期プロファイル（熱処理前のプロファイル）は、Ｇｅ基板表面からＲｐが５．０ｎｍ、標準偏差１．０ｎｍ、ドーズ量１×１０１４ｃｍ－２のガウス分布であると想定した。拡散温度は７７３Ｋである。Ｂの濃度を３通りに変化させた場合を示した。ＢはＧｅ基板表面からＰのＲｐの位置まで存在しない場合を想定した。 <P-type impurity concentration required to suppress n-type impurities>
Subsequently, in order to suppress the n-type impurity, it will be described how much concentration of the p-type impurity is required. Here too, P was selected as the n-type impurity and B was selected as the p-type impurity. The initial profile of P (profile before heat treatment) was assumed to be a Gaussian distribution with Rp of 5.0 nm, a standard deviation of 1.0 nm, and a dose of 1 × 10 14 cm −2 from the Ge substrate surface. The diffusion temperature is 773K. The case where the concentration of B was changed in three ways was shown. It is assumed that B does not exist from the surface of the Ge substrate to the position of Rp of P.
　まず、図１０はＢを５×１０１９ｃｍ－３の濃度で、Ｒｐ（５ｎｍ）から１０ｎｍまで入れた場合である。拡散時間は３秒とした。例えば、Ｐ濃度が１×１０１８ｃｍ－３の位置は、熱処理前には８．８ｎｍであったのが、熱処理後には１０．４ｎｍまで拡散しており、熱処理前後の差で１．６ｎｍだけ拡散している。 First, FIG. 10 shows the case where B is introduced from Rp (5 nm) to 10 nm at a concentration of 5 × 10 19 cm −3 . The diffusion time was 3 seconds. For example, the position of P concentration of 1 × 10 18 cm -3 was 8.8 nm before heat treatment, but diffused to 10.4 nm after heat treatment, and the difference between before and after heat treatment is only 1.6 nm. It is spreading.
　図１０の場合からＢだけを無くしたものが図１１である。Ｐ濃度が１×１０１８ｃｍ－３の位置は、熱処理前は同じ８．８ｎｍであり、熱処理後には１４．８ｎｍまで拡散している。拡散した距離は６．０ｎｍである。つまり、Ｂが無い場合には６．０ｎｍ拡散しているが、５×１０１９ｃｍ－３のＢがあることによって１．６ｎｍ拡散するだけで抑えられている。 It is FIG. 11 which eliminated only B from the case of FIG. The position of P concentration of 1 × 10 18 cm −3 is the same 8.8 nm before the heat treatment, and diffused to 14.8 nm after the heat treatment. The diffused distance is 6.0 nm. That is, when B is absent, the light is diffused by 6.0 nm, but when 5 × 10 19 cm -3 is present, the diffusion is suppressed only by 1.6 nm.
　このときの図１０，１１の不純物濃度プロファイルに対応する電子濃度プロファイルは、それぞれ、図１２，１３である。Ｂが無い場合（図１３）には、不純物濃度プロファイル（図１１）に対応して、電子濃度が１×１０１８ｃｍ－３の位置は１０．４ｎｍである。一方で、Ｂがある場合（図１２）には、不純物濃度プロファイル（図１０）に対応して、１４．８ｎｍまでｎ＋Ｇｅの領域が広がっている。また図からわかるように、拡散している途中はＢによって補償されるため、真性キャリア濃度より電子濃度が低く（ホール濃度が高く）、つまりｐ＋Ｇｅが形成されている。そのとき、電子濃度が低いのでゆっくり拡散し、最終的には電子濃度が真性キャリア濃度より低い領域が無くなり、つまりｐ＋Ｇｅ領域が無くて、極浅かつ高濃度の電子濃度からなるｎ＋Ｇｅだけが形成できている。 The electron concentration profiles corresponding to the impurity concentration profiles in FIGS. 10 and 11 at this time are shown in FIGS. 12 and 13, respectively. When B is not present (FIG. 13), the position at an electron concentration of 1 × 10 18 cm −3 is 10.4 nm, corresponding to the impurity concentration profile (FIG. 11). On the other hand, when B is present (FIG. 12), the n + Ge region is expanded to 14.8 nm corresponding to the impurity concentration profile (FIG. 10). As can be seen from the figure, since B is compensated during the diffusion, the electron concentration is lower than the intrinsic carrier concentration (the hole concentration is high), that is, p + Ge is formed. At that time, since the electron concentration is low, it diffuses slowly and finally there is no region where the electron concentration is lower than the intrinsic carrier concentration, that is, there is no p + Ge region, and n + Ge consisting of extremely shallow and high electron concentration Only can be formed.
　図１４は、図１０よりもＢ濃度を減らして、１×１０１９ｃｍ－３にした場合である。ＢはＲｐから２５．３ｎｍまで入れた。ここまでの内容から予想されるように、Ｂ濃度が低くなれば、Ｐが拡散する領域も広くなるため、Ｂを入れる領域も広くした方が良いからである。拡散時間は９５秒とした。例えば、Ｐ濃度が１×１０１８ｃｍ－３の位置は、熱処理前には８．８ｎｍであったのが、熱処理後には２５．４ｎｍまで拡散しており、熱処理前後の差で１７．０ｎｍだけ拡散している。 FIG. 14 shows the case where the B concentration is reduced to 1 × 10 19 cm −3 as compared with FIG. B was loaded from Rp to 25.3 nm. As expected from the above contents, the lower the B concentration, the wider the region to which P diffuses, so it is better to widen the region into which B is to be inserted. The diffusion time was 95 seconds. For example, the position of P concentration of 1 × 10 18 cm -3 was 8.8 nm before heat treatment, but diffused to 25.4 nm after heat treatment, and the difference between before and after heat treatment is only 17.0 nm. It is spreading.
　図１４の場合からＢだけを無くしたものが図１５である。Ｐ濃度が１×１０１８ｃｍ－３の位置は、熱処理前は同じ８．４ｎｍであり、熱処理後には３２．２ｎｍまで拡散している。拡散した距離は２３．２ｎｍである。つまり、Ｂが無い場合には２３．２ｎｍ拡散しているが、１×１０１９ｃｍ－３のＢがあることによって１７．０ｎｍ拡散するだけで抑えられている。 It is FIG. 15 which eliminated only B from the case of FIG. The position of P concentration of 1 × 10 18 cm −3 is the same 8.4 nm before the heat treatment, and diffused to 32.2 nm after the heat treatment. The diffused distance is 23.2 nm. That is, when B is not present, 23.2 nm is diffused, but because 1 × 10 19 cm −3 of B is present, it is suppressed only by 17.0 nm.
　このときの図１４，１５の不純物濃度プロファイルに対応する電子濃度プロファイルは、それぞれ、図１６，１７である。Ｂが無い場合（図１７）には、不純物濃度プロファイル（図１５）と対応して、電子濃度が１×１０１８ｃｍ－３の位置は３２．２ｎｍである。 The electron concentration profiles corresponding to the impurity concentration profiles in FIGS. 14 and 15 at this time are shown in FIGS. 16 and 17, respectively. When B is not present (FIG. 17), the position of the electron concentration of 1 × 10 18 cm −3 is 32.2 nm, corresponding to the impurity concentration profile (FIG. 15).
　一方で、Ｂがある場合（図１６）には、不純物濃度プロファイル（図１４）と対応して、２５．４ｎｍまでｎ＋Ｇｅの領域が広がっている。また図からわかるように、拡散している途中はＢによって補償されるため、真性キャリア濃度より電子濃度が低く（ホール濃度が高く）、つまりｐ＋Ｇｅが形成されている。そのとき、電子濃度が低いのでゆっくり拡散し、最終的には電子濃度が真性キャリア濃度より低い領域が無くなり、つまりｐ＋Ｇｅ領域が無くて、極浅かつ高濃度の電子濃度からなるｎ＋Ｇｅだけが形成できている。 On the other hand, when B is present (FIG. 16), the n + Ge region extends up to 25.4 nm, corresponding to the impurity concentration profile (FIG. 14). As can be seen from the figure, since B is compensated during the diffusion, the electron concentration is lower than the intrinsic carrier concentration (the hole concentration is high), that is, p + Ge is formed. At that time, since the electron concentration is low, it diffuses slowly and finally there is no region where the electron concentration is lower than the intrinsic carrier concentration, that is, there is no p + Ge region, and n + Ge consisting of extremely shallow and high electron concentration Only can be formed.
　図１８は、図１０，図１４よりもさらにＢ濃度を減らして、１×１０１８ｃｍ－３にした場合である。ＢはＲｐから３１．８ｎｍまで入れている。前述したように、Ｂ濃度が低くなれば、Ｐが拡散する領域も広くなるため、Ｂを入れる領域も広くした方が良いからである。拡散時間は１００秒とした。例えば、Ｐ濃度が１×１０１８ｃｍ－３の位置は、熱処理前には８．８ｎｍであったのが、熱処理後には３１．６ｎｍまで拡散しており、熱処理前後の差で２２．８ｎｍだけ拡散している。 FIG. 18 shows the case where the B concentration is further reduced to 1 × 10 18 cm −3 as compared with FIGS. 10 and 14. B is from Rp to 31.8 nm. As described above, since the lower the B concentration, the wider the region where P diffuses, it is better to widen the region where B is to be contained. The diffusion time was 100 seconds. For example, the position of P concentration of 1 × 10 18 cm -3 was 8.8 nm before heat treatment, but diffused to 31.6 nm after heat treatment, and the difference between before and after heat treatment is only 22.8 nm It is spreading.
　図１８の場合からＢだけを無くしたものが図１９である。Ｐ濃度が１×１０１８ｃｍ－３の位置は、熱処理前は同じ８．８ｎｍであり、熱処理後には３２．６ｎｍまで拡散している。拡散した距離は２３．８ｎｍである。つまり、Ｂが無い場合には２３．８ｎｍ拡散しているが、１×１０１８ｃｍ－３のＢがあることによって２２．８ｎｍ拡散するだけで抑えられている。 It is FIG. 19 which eliminated only B from the case of FIG. The position of P concentration of 1 × 10 18 cm −3 is the same 8.8 nm before the heat treatment, and diffused to 32.6 nm after the heat treatment. The diffused distance is 23.8 nm. That is, when B is not present, 23.8 nm is diffused, but because 1 × 10 18 cm -3 of B is present, it is suppressed only by 22.8 nm.
　このときの図１８，図１９の不純物濃度プロファイルに対応する電子濃度プロファイルは、それぞれ、図２０，図２１である。Ｂが無い場合（図２１）には、不純物濃度プロファイル（図１９）と対応して、電子濃度が１×１０１８ｃｍ－３の位置は３２．６ｎｍである。一方で、Ｂがある場合（図２０）には、不純物濃度プロファイル（図１８）と対応して、電子濃度が１×１０１８ｃｍ－３の位置は３１．６ｎｍである。また図からわかるように、拡散している途中はＢによって補償されるため、真性キャリア濃度ｎｉより電子濃度ｎが低く（ホール濃度ｐが高く）、つまりｐ＋Ｇｅが形成されている。そのとき、電子濃度が低いのでゆっくり拡散し、最終的には電子濃度が真性キャリア濃度より低い領域が無くなり、つまりｐ＋Ｇｅ領域が無くて、極浅かつ高濃度の電子濃度からなるｎ＋Ｇｅだけが形成できている。 The electron concentration profiles corresponding to the impurity concentration profiles in FIGS. 18 and 19 at this time are shown in FIGS. 20 and 21, respectively. When B is absent (FIG. 21), the position of the electron concentration of 1 × 10 18 cm −3 is 32.6 nm, corresponding to the impurity concentration profile (FIG. 19). On the other hand, when B is present (FIG. 20), the position of the electron concentration of 1 × 10 18 cm −3 is 31.6 nm, corresponding to the impurity concentration profile (FIG. 18). Also, as can be seen from the figure, since B is compensated during the diffusion, the electron concentration n is lower than the intrinsic carrier concentration ni (the hole concentration p is high), that is, p + Ge is formed. At that time, since the electron concentration is low, it diffuses slowly and finally there is no region where the electron concentration is lower than the intrinsic carrier concentration, that is, there is no p + Ge region, and n + Ge consisting of extremely shallow and high electron concentration Only can be formed.
　このように、Ｐの拡散距離を短くするには、Ｂ濃度が高いほど良い。Ｐの拡散を抑制してｎ＋Ｇｅを形成するＢ濃度の上限は、極限的には、熱処理前のＰの濃度Ｃｎ（ｘ，０）よりわずかに低くしておく（Ｃｎ（ｘ，０）＞Ｃｐ（ｘ，０））、あるいは、熱処理後に拡散してＢよりＰ濃度が高くなるようにする（Ｃｎ（ｘ，ｔ）＞Ｃｐ（ｘ，ｔ））。ここで、Ｃｎ（ｘ，ｔ），Ｃｐ（ｘ，ｔ）は、それぞれ、Ｐ，Ｂの深さｘ，拡散時間ｔにおける不純物濃度である。熱処理前には、拡散する方向であれば、ＰよりＢ濃度を高くしても構わない。また、Ｐの拡散を抑制する最低限のＢ濃度Ｃｐ（ｘ，０）は、拡散温度Ｔにおける真性キャリア濃度ｎｉ（ｘ，０；Ｔ）より高ければ効果がある（Ｃｐ（ｘ，０）＞ｎｉ（ｘ，０；Ｔ））。 Thus, to shorten the diffusion distance of P, the higher the B concentration, the better. The upper limit of the B concentration that suppresses the diffusion of P to form n + Ge is, in the extreme, slightly lower than the concentration Cn (x, 0) of P before heat treatment (Cn (x, 0) > Cp (x, 0)), or diffuse after heat treatment so that the P concentration becomes higher than B (Cn (x, t)> Cp (x, t)). Here, Cn (x, t) and Cp (x, t) are impurity concentrations at depth x and diffusion time t of P and B, respectively. Before the heat treatment, the B concentration may be higher than P as long as it is a diffusion direction. In addition, the minimum B concentration Cp (x, 0) for suppressing the diffusion of P is effective if it is higher than the intrinsic carrier concentration ni (x, 0; T) at the diffusion temperature T (Cp (x, 0)> ni (x, 0; T)).
　Ｐの拡散を抑制するためのＢのプロファイルとして、一定濃度の矩形領域を考えたが、これは前述したように、Ｇｅ中のｎ型不純物拡散メカニズムにより、ｎ型不純物のプロファイルが一定濃度の領域から急峻に濃度が減少する、いわば箱形プロファイルになるからである。より望ましくは、ｐ型不純物のプロファイルを、最終的に得たいｎ型不純物のプロファイルに近づけると、さらに浅くて高濃度の電子からなるｎ＋Ｇｅが形成できる。 As a profile of B for suppressing the diffusion of P, a rectangular area of constant concentration was considered, but as described above, the n-type impurity diffusion mechanism in Ge, an area of n-type impurity profile of constant concentration The density decreases sharply from the above, so to say, it becomes a box-shaped profile. More desirably, when the profile of the p-type impurity is made closer to the profile of the n-type impurity which is desired to be finally obtained, n + Ge can be formed which is shallower and has a high concentration of electrons.
　ここまでは、ＢによるＰの拡散抑制が最も適した時間の例を示してきた。ここでは、最適な時間を大きく超えた場合に、Ｐのプロファイルがどのようになるかを示す。図２２は、図１０と拡散時間だけが違う場合である。図１０では拡散時間が３秒であったが、図２２では１０秒である。図２２からわかるように、図１０よりＰの拡散が進んでいる。例えば、Ｐ濃度が１×１０１８ｃｍ－３の位置は、熱処理前には８．８ｎｍであったのが、熱処理後には１３．８ｎｍまで移動しており、熱処理前後の差で５．０ｎｍだけ拡散している。 So far, we have shown an example of the time when the diffusion suppression of P by B is most suitable. Here, it is shown how the profile of P becomes when the optimal time is greatly exceeded. FIG. 22 shows the case where only the diffusion time is different from FIG. The diffusion time was 3 seconds in FIG. 10, but 10 seconds in FIG. As can be seen from FIG. 22, the diffusion of P is advanced from FIG. For example, the position of P concentration of 1 × 10 18 cm -3 was 8.8 nm before heat treatment, but moved to 13.8 nm after heat treatment, and the difference between before and after heat treatment is 5.0 nm. It is spreading.
　図２２の場合からＢだけを無くしたものが図２３である。Ｐ濃度が１×１０１８ｃｍ－３の位置は、熱処理前は同じ８．４ｎｍであり、熱処理後には１８．９ｎｍまで拡散している。拡散した距離は１０．５ｎｍである。つまり、Ｂが無い場合には１０．５ｎｍ拡散してしまうが、１×１０１９ｃｍ－３のＢがあることによって５．０ｎｍ拡散するだけで抑えられている。ここで注目すべきは、図２２から明らかなように、ＰがＢのある領域を大きく超えて拡散しても、Ｂの濃度がＰの濃度を超えることはない、ということである。 It is FIG. 23 which eliminated only B from the case of FIG. The position of P concentration of 1 × 10 18 cm −3 is the same 8.4 nm before the heat treatment, and diffused to 18.9 nm after the heat treatment. The diffused distance is 10.5 nm. That is, when B is not present, 10.5 nm is diffused, but due to the presence of 1 × 10 19 cm -3 B, only 5.0 nm is suppressed. It should be noted here that, as apparent from FIG. 22, the concentration of B does not exceed the concentration of P even if P diffuses far beyond the region where B is present.
　図２２，２３の不純物濃度プロファイルに対応する電子濃度プロファイルは、それぞれ、図２４，２５である。Ｂが無い場合（図２５）には、不純物濃度プロファイル（図２３）と対応して、電子濃度が１×１０１８ｃｍ－３の位置は１８．９ｎｍである。一方で、Ｂがある場合（図２４）には、不純物濃度プロファイル（図２２）と対応して、１３．８ｎｍまでｎ＋Ｇｅの領域が広がっている。また図からわかるように、拡散している途中はＢによって補償されるため、真性キャリア濃度より電子濃度が低く（ホール濃度が高く）、つまりｐ＋Ｇｅが形成されている。そのとき、電子濃度が低いのでゆっくり拡散し、最終的には電子濃度が真性キャリア濃度より低い領域が無くなる。そしてこの場合にはＢが無い基板内奥側の領域にさらにＰは拡散していくが、この位置ではＰの濃度が低くなっているため、Ｐの拡散はゆっくりである。 The electron concentration profiles corresponding to the impurity concentration profiles of FIGS. 22 and 23 are FIGS. 24 and 25, respectively. When B is not present (FIG. 25), the position of the electron concentration of 1 × 10 18 cm −3 is 18.9 nm, corresponding to the impurity concentration profile (FIG. 23). On the other hand, when B is present (FIG. 24), the n + Ge region extends to 13.8 nm, corresponding to the impurity concentration profile (FIG. 22). As can be seen from the figure, since B is compensated during the diffusion, the electron concentration is lower than the intrinsic carrier concentration (the hole concentration is high), that is, p + Ge is formed. At that time, since the electron concentration is low, it diffuses slowly, and finally, there is no region where the electron concentration is lower than the intrinsic carrier concentration. In this case, P diffuses further into the region at the back of the substrate where there is no B, but at this position, the concentration of P is low, so the diffusion of P is slow.
　また、Ｂがある領域から無い領域に遷移する場所で、電子濃度の若干の低下が見られるが、それでも真性キャリア濃度よりも高く、室温では基板濃度よりも充分に電子濃度が高い。尚、これは急峻に高濃度からゼロに落ち込むようなＢのプロファイルを想定したからであり、現実には連続的に濃度は変化するため、電子濃度がこのように特異的に低くなることは無い。 In addition, although there is a slight decrease in the electron concentration at a place where B transitions from a region to a region, the electron concentration is still higher than the intrinsic carrier concentration and sufficiently higher than the substrate concentration at room temperature. This is because it assumed a profile of B that drops sharply from high concentration to zero, and in reality the concentration changes continuously, so the electron concentration does not fall specifically like this .
　このように、Ｐの拡散を抑制する最適な時間を大きく超えても、ｐ＋Ｇｅが形成されることはなく、Ｂ無しの場合に較べて充分に拡散抑制の効果もあり、極浅かつ高濃度の電子濃度からなるｎ＋Ｇｅだけが形成できる。 As described above, even if the optimum time for suppressing the diffusion of P is greatly exceeded, p + Ge is not formed, and the effect of suppressing the diffusion is sufficient compared to the case without B, and thus extremely shallow and high. Only n + Ge consisting of electron concentration of concentration can be formed.
＜ＰとＢが導入されたＧｅのキャリア濃度プロファイル＞
　図２６Ａ，２６Ｂは、ＰとＢの二つを導入して形成したＧｅのキャリア濃度プロファイルである。スプレディングレジスタンスプローブ（Spreading resistance probe）分析により求めた。Ｐのドーズ量は５×１０１５ｃｍ－２であり、窒素雰囲気で３０分の熱処理を施したものである。図２６Ａ、２６Ｂは、それぞれＢのドーズ量が２×１０１４、１×１０１５ｃｍ－２である。熱処理温度は、４００，５００，６００℃の３通りで行った。また、すべての条件において、Ｂが無い場合のキャリア濃度プロファイルも調べた。基板表面側に高濃度に存在するキャリアはすべて電子であり、また、基板の内奥側に存在する濃度一定領域は基板に含まれる不純物（Ｇａ）により生じたホールである。 <Carrier concentration profile of Ge introduced P and B>
26A and 26B show carrier concentration profiles of Ge formed by introducing two of P and B. FIG. It was determined by spreading resistance probe analysis. The dose amount of P is 5 × 10 15 cm −2 and is heat treated for 30 minutes in a nitrogen atmosphere. In FIGS. 26A and 26B, the dose amount of B is 2 × 10 14 and 1 × 10 15 cm −2 , respectively. The heat treatment temperature was three ways of 400, 500 and 600 ° C. In addition, under all conditions, the carrier concentration profile in the absence of B was also examined. The carriers present at high concentration on the substrate surface side are all electrons, and the constant concentration region present on the inner side of the substrate is holes generated by impurities (Ga) contained in the substrate.
　まず、図２６Ａ，２６Ｂから、４００，５００，６００℃と温度を高くするほど、電子が高濃度に存在する領域が基板の内奥側に広がっていくことがわかる。また、Ｂがある場合と無い場合を比較すると、Ｂがある方が拡散を抑えられている。その傾向は、Ｂのドーズ量に強く依存していて、Ｂのドーズ量が２×１０１４ｃｍ－２より１×１０１５ｃｍ－２の方が、各熱処理温度で拡散が抑制される。また、この高濃度領域はすべて電子であり、Ｂがあっても、ｐ＋Ｇｅの無いｎ＋Ｇｅが形成できている。 First, it is understood from FIGS. 26A and 26B that as the temperature is increased to 400, 500, and 600 ° C., the region in which the electron concentration is high spreads to the inner side of the substrate. Also, comparing B with and without B, diffusion is suppressed in the presence of B. The tendency strongly depends on the dose amount of B, and the diffusion amount is suppressed at each heat treatment temperature when the dose amount of B is 1 × 10 15 cm −2 from 2 × 10 14 cm −2 . Also, this high concentration region is all electrons, and even if there is B, n + Ge without p + Ge can be formed.
（第２の実施形態）
　第２の実施形態では、ｎ型不純物層の形成方法の実施形態を説明する。まず、ｐ型Ｇｅ基板１にＢをイオン注入する（図２７）。このとき、イオン注入の加速エネルギーを調整し、基板表面よりも内奥側に注入する。すると、ｐ型Ｇｅ基板１の表面より内奥側にＢの高濃度層２が形成される（図２８）。続いて、ｐ型Ｇｅ基板１にＰをイオン注入する（図２９）。加速エネルギーを調整し、Ｂの高濃度層２よりも表面側に注入する。ｐ型Ｇｅ基板１には表面側にＰの高濃度層３が形成され、それよりも基板奥側にＢの高濃度層４が形成される（図３０）。そして、この基板を熱処理すると、Ｐは拡散するがＢにより拡散が抑制され、最終的にはＰがＢよりも濃度が高くなるため、ｐ＋Ｇｅ領域が無くなり、浅くて高濃度の電子濃度からなるｎ＋Ｇｅ層が形成される（図３１）。このｎ＋Ｇｅ層には基板１に含まれるよりも多くのｐ型不純物が含まれている。 Second Embodiment
In the second embodiment, an embodiment of a method of forming an n-type impurity layer will be described. First, B is ion implanted into the p-type Ge substrate 1 (FIG. 27). At this time, the acceleration energy of ion implantation is adjusted, and implantation is performed on the inner side of the substrate surface. Then, the B high concentration layer 2 is formed on the inner side of the surface of the p-type Ge substrate 1 (FIG. 28). Subsequently, P is ion-implanted into the p-type Ge substrate 1 (FIG. 29). The acceleration energy is adjusted and injected on the surface side of the high concentration layer 2 of B. The high concentration layer 3 of P is formed on the surface side of the p-type Ge substrate 1, and the high concentration layer 4 of B is formed on the back side of the substrate (FIG. 30). Then, when this substrate is heat-treated, P diffuses but B suppresses diffusion, and finally P becomes higher in concentration than B, so the p + Ge region disappears, and the shallow and high concentration electron concentration An n + Ge layer is formed (FIG. 31). The n + Ge layer contains more p-type impurities than contained in the substrate 1.
（第３の実施形態）
　第３の実施形態では、ｎ型不純物拡散層の別の形成方法を示す。まず、ｐ型Ｇｅ基板１にＢをドープしたＧｅをＣＶＤによって堆積する（図３２）。すると、ｐ型Ｇｅ基板１表面にｐ＋Ｇｅ層６が形成される（図３３）。つづいてＰをドープしたＧｅをＣＶＤによって堆積する。ｐ＋Ｇｅ層６の上にｎ＋Ｇｅ層７が形成される（図３４）。このとき基板を加熱しながら堆積、あるいは堆積してから熱処理すると、前述の効果により浅くて高濃度の電子からなるｎ＋Ｇｅ層８が形成される（図３５）。このプロセスで、図３３のｐ＋Ｇｅ層６を形成せずに、図３４のｎ＋Ｇｅ層７を堆積すると、ｎ型不純物の拡散が速いため、ｐ型Ｇｅ基板１の内奥側に拡散してしまい、浅くて高濃度の電子からなるｎ＋Ｇｅ層８を形成できない。本プロセスのように、ｐ＋Ｇｅ層６を形成すれば、ＰをドープしたＧｅを堆積するときに、Ｐの基板奥側への拡散を防ぐことができる。 Third Embodiment
The third embodiment shows another method of forming an n-type impurity diffusion layer. First, Ge doped with B is deposited by CVD on the p-type Ge substrate 1 (FIG. 32). Then, ap + Ge layer 6 is formed on the surface of the p-type Ge substrate 1 (FIG. 33). Subsequently, P-doped Ge is deposited by CVD. An n + Ge layer 7 is formed on the p + Ge layer 6 (FIG. 34). At this time, when the substrate is heated or deposited and then heat-treated, an n + Ge layer 8 of shallow and high concentration electrons is formed by the above-described effect (FIG. 35). In this process, if the n + Ge layer 7 of FIG. 34 is deposited without forming the p + Ge layer 6 of FIG. It is impossible to form an n + Ge layer 8 consisting of shallow, high concentration electrons. If the p + Ge layer 6 is formed as in this process, diffusion of P to the back side of the substrate can be prevented when depositing P-doped Ge.
　以上第１～第３の実施形態によれば、ｐ型不純物の濃度および分布を制御することによって、極浅く、かつ高濃度キャリア密度を有するｎ型領域を形成することができる。 According to the first to third embodiments described above, by controlling the concentration and distribution of the p-type impurity, it is possible to form an n-type region which is extremely shallow and has a high carrier density.
（第４の実施形態）
　図３６は、上述のｎ＋Ｇｅ層を用いた半導体装置（ＭＩＳＦＥＴ）の模式断面図である。第４の実施形態の半導体装置は、基板の上に形成されたＧｅを主成分とするｐ型半導体層１０と、ｐ型半導体層１０の上に形成されたゲート絶縁層１２と、ゲート絶縁層１２の上に形成されたゲート電極１４と、ｐ型半導体１０のゲート絶縁層１２との境界領域をゲート長方向の両側から挟むようにｐ型半導体層１０の表面に選択的に形成された一対のｎ型不純物拡散領域（ソース・ドレイン領域）１８とを備えている。この半導体装置は、ｎ型不純物拡散領域１８の全部または一部に、ｎ型不純物を含有すると同時に、ｐ型半導体層１０に含有されるよりも高濃度のｐ型不純物を含有している。ｎ型不純物拡散領域の表面には、コンタクト電極１６が接合されている。 Fourth Embodiment
FIG. 36 is a schematic cross-sectional view of a semiconductor device (MISFET) using the n + Ge layer described above. The semiconductor device according to the fourth embodiment includes a p-type semiconductor layer 10 mainly composed of Ge formed on a substrate, a gate insulating layer 12 formed on the p-type semiconductor layer 10, and a gate insulating layer. A pair selectively formed on the surface of the p-type semiconductor layer 10 so as to sandwich the boundary region between the gate electrode 14 formed on the gate electrode 12 and the gate insulating layer 12 of the p-type semiconductor 10 from both sides in the gate length direction. And an n-type impurity diffusion region (source / drain region) 18 of FIG. This semiconductor device contains an n-type impurity in all or part of the n-type impurity diffusion region 18 and also contains a higher concentration of p-type impurity than contained in the p-type semiconductor layer 10. A contact electrode 16 is bonded to the surface of the n-type impurity diffusion region.
　ｐ型半導体層１０は、基板全体がＧｅ、あるいは少なくとも表面はＧｅを主成分とした基板の表層からなり、ｐ型不純物を含有している。また、ｐ型不純物はｎ型不純物領域全体にあっても良いが、電子濃度を高くしてコンタクト抵抗を低くするために、基板表面にはないことが望ましい。さらに、ｎ型不純物領域の周りに追加して、いわゆるＬＤＤやｎ型エクステンション、ハロー（halo）層を形成しても良い。 In the p-type semiconductor layer 10, the whole substrate is Ge, or at least the surface is a surface layer of the substrate mainly containing Ge, and contains a p-type impurity. Although the p-type impurity may be present in the entire n-type impurity region, it is desirable that the p-type impurity is not present on the substrate surface in order to increase the electron concentration to reduce the contact resistance. Furthermore, a so-called LDD, an n-type extension, or a halo layer may be formed around the n-type impurity region.
　本実施形態によれば、ｐ型不純物の濃度および分布を制御することによって、極浅く、かつ高濃度キャリア密度を有するｎ型ソース・ドレイン領域１８を形成することができる。この結果、微細Ｇｅチャネル半導体装置において、短チャネル効果を抑制するとともに寄生抵抗を少なくすることが可能となり、電流駆動力の高いＭＩＳＦＥＴを提供できる。 According to the present embodiment, by controlling the concentration and distribution of the p-type impurity, it is possible to form the n-type source / drain region 18 which is extremely shallow and has a high carrier density. As a result, in the fine Ge channel semiconductor device, it is possible to suppress the short channel effect and reduce the parasitic resistance, and it is possible to provide a MISFET with a high current driving capability.
（第５の実施形態）
　図３７は、上述のｎ＋Ｇｅ層およびｐ＋Ｇｅ層を用いたＣＭＩＳＦＥＴ（Complementary Metal Insulator Semiconductor Field Effect Transistor：相補型金属／酸化物／半導体型電界効果トランジスタ）の模式的断面図である。 Fifth Embodiment
FIG. 37 is a schematic cross-sectional view of a CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor) using the n + Ge layer and the p + Ge layer described above.
　より詳細には、図３７はＧｅチャネルを有するＣＭＩＳＦＥＴのゲート長方向の断面図を表す。基板１００の上部表面（主表面）に、Ｇｅからなるｐ型ウェル領域１０２及びｎ型ウェル領域１０４が、素子分離層１０６によって電気的に分離されて形成される。基板１００は、Ｇｅ基板や、Ｓｉ基板や、Ｓｉ基板上にＧｅ層を形成したものや、Ｓｉ基板上にＳｉＧｅ層の中間層を形成しさらにその上にＧｅ層を形成したものであってもよい。素子分離層１０６は、例えばＳｉＯ２によって形成される。ｐ型ウェル領域１０２には、ｎチャネルＭＩＳトランジスタが形成され、ｎ型ウェル領域１０４にはｐチャネルＭＩＳトランジスタが形成される。 More specifically, FIG. 37 shows a cross section in the gate length direction of a CMISFET having a Ge channel. In the upper surface (main surface) of the substrate 100, a p-type well region 102 and an n-type well region 104 made of Ge are electrically separated by an element isolation layer 106. The substrate 100 may be a Ge substrate, a Si substrate, a substrate on which a Ge layer is formed on a Si substrate, or a substrate on which an intermediate layer of a SiGe layer is formed on a Si substrate and a Ge layer is further formed thereon. Good. The element isolation layer 106 is formed of SiO 2 , for example. In the p-type well region 102, an n-channel MIS transistor is formed, and in the n-type well region 104, a p-channel MIS transistor is formed.
　ｎチャネルＭＩＳトランジスタの構成としては、ｐ型ウェル領域１０２内に、電流通路となる領域（チャネル領域）のゲート長両側に一対のｎ型エクステンション領域１０８が形成され、これらの外側に一対のｎ型ディープ領域１１０が形成される。ｐ型ウェル領域１０２の上部表面には、対向するｎ型エクステンション領域１０８、１０８のゲート長方向内側の端部にかかるようにしてチャネル領域上にゲート絶縁膜１１６が形成される。ゲート絶縁膜１１６の上部表面には、ゲート電極１１８が積層形成される。ゲート絶縁膜１１６及びゲート電極１１８の両側には、ゲート側壁１２４が形成される。 As the configuration of the n-channel MIS transistor, a pair of n-type extension regions 108 are formed in the p-type well region 102 on both sides of the gate length of the region (channel region) to be a current path. Deep regions 110 are formed. A gate insulating film 116 is formed on the channel region on the upper surface of the p-type well region 102 in such a manner that the gate insulating film 116 is applied to the inner end in the gate length direction of the opposing n-type extension regions 108. A gate electrode 118 is stacked on the upper surface of the gate insulating film 116. Gate sidewalls 124 are formed on both sides of the gate insulating film 116 and the gate electrode 118.
　ｎ型ディープ領域１１０は、ｎ型エクステンション領域１０８よりもｐ型ウェル領域１０２との接合深さが深くなるように構成される。ｎ型エクステンション領域１０８及びｎ型ディープ領域１１０は、ｎチャネルＭＩＳトランジスタのソース・ドレイン領域となる。 The n-type deep region 110 is configured such that the junction depth with the p-type well region 102 is deeper than the n-type extension region 108. The n-type extension region 108 and the n-type deep region 110 become source / drain regions of the n-channel MIS transistor.
　同様に、ｐチャネルＭＩＳトランジスタの構成としては、ｎ型ウェル領域１０４内に、電流通路となる領域（チャネル領域）のゲート長方向両側に一対のｐ型エクステンション領域１１２が形成され、これらの外側に一対のｐ型ディープ領域１１４が形成される。ｎ型ウェル領域１０４の上部表面には、一対のｐ型エクステンション領域１１２、１１２のゲート長方向内側の端部にかかるようにしてチャネル領域上にゲート絶縁膜１２０が形成される。ゲート絶縁膜１２０の上部表面には、ゲート電極１２２が積層形成される。ゲート絶縁膜１２０及びゲート電極１２２の両側には、ゲート側壁絶縁膜１２６が形成される。 Similarly, as a configuration of the p-channel MIS transistor, a pair of p-type extension regions 112 are formed on both sides in the gate length direction of a region (channel region) serving as a current path in the n-type well region 104. A pair of p-type deep regions 114 are formed. A gate insulating film 120 is formed on the channel region on the upper surface of the n-type well region 104 in such a manner that the gate insulating film 120 is applied to the inner end in the gate length direction of the pair of p-type extension regions 112. A gate electrode 122 is stacked on the upper surface of the gate insulating film 120. Gate sidewall insulating films 126 are formed on both sides of the gate insulating film 120 and the gate electrode 122.
　ｐ型ディープ領域１１４は、ｐ型エクステンション領域１１２よりもｎ型ウェル領域１０４との接合深さが深くなるように構成される。ｐ型エクステンション領域１１２及びｐ型ディープ領域１１４は、ｐチャネルＭＩＳトランジスタのソース・ドレイン領域となる。 The p-type deep region 114 is configured such that the junction depth with the n-type well region 104 is deeper than the p-type extension region 112. The p-type extension region 112 and the p-type deep region 114 become source / drain regions of the p-channel MIS transistor.
ｎチャネルＭＩＳトランジスタ及びｐチャネルＭＩＳトランジスタは、層間絶縁膜１３０によって覆われている。 The n-channel MIS transistor and the p-channel MIS transistor are covered by an interlayer insulating film 130.
　本実施形態において、ｎ型エクステンション領域１０８、ｎ型ディープ領域１１０のどちらか、あるいは両方は、前述の実施形態により形成されたものであり、ｐ型ドーパントを含んでいる。尚、このｐ型ドーパントは、ｐ型エクステンション領域１１２、ｐ型ディープ領域１１４に含まれているｐ型ドーパントと同じものにすることも可能である。 In the present embodiment, one or both of the n-type extension region 108 and the n-type deep region 110 are formed by the above-described embodiment and include a p-type dopant. The p-type dopant can also be the same as the p-type dopant contained in the p-type extension region 112 and the p-type deep region 114.
　次に、図１７を参照して上記のＣＭＩＳＦＥＴの製造方法について説明する。まず、基板１００の主表面上に素子分離層１０６を形成する。基板は、Ｇｅ基板や、Ｓｉ基板や、Ｓｉ基板の上にＧｅ層を形成したものや、Ｓｉ基板上にＳｉＧｅ層の中間層を挟みＧｅ層を形成したものであってよい。素子分離層１０６の形成方法は、局所酸化法や、ＳＴＩ（Shallow Trench Isolation）法であってもよく、素子分離層１０６の形状は、メサ型でもよい。素子分離層１０６を形成した後、ｐ型ウェル領域１０２及びｎ型ウェル領域１０４を形成する。ｐ型ウェル領域１０２及びｎ型ウェル領域１０４の形成には、Ｇｅ層に対する通常のイオン注入法を用いてもよいし、Ｇｅ層をエピタキシャル成長させた後にイオン注入を行ってもよい。 Next, a method of manufacturing the above-described CMISFET will be described with reference to FIG. First, the element isolation layer 106 is formed on the main surface of the substrate 100. The substrate may be a Ge substrate, a Si substrate, a substrate in which a Ge layer is formed on a Si substrate, or a substrate in which a Ge layer is formed on a Si substrate with an intermediate layer of a SiGe layer. The formation method of the element isolation layer 106 may be a local oxidation method or an STI (Shallow Trench Isolation) method, and the shape of the element isolation layer 106 may be a mesa. After the element isolation layer 106 is formed, the p-type well region 102 and the n-type well region 104 are formed. For the formation of the p-type well region 102 and the n-type well region 104, a conventional ion implantation method for the Ge layer may be used, or the ion implantation may be performed after the Ge layer is epitaxially grown.
　次に、ｐ型ウェル領域１０２及びｎ型ウェル領域１０４の上部表面にゲート絶縁膜１１６及び１２０を形成する。ゲート絶縁膜１１６及び１２０の形成方法については、例えば、Ｇｅ酸化物膜を熱酸化法で形成してもよく、Ｇｅ酸窒化膜をプラズマ酸窒化法で形成してもよく、Ｈｆ，Ｚｒ，Ｌａ，Ｙ，Ａｌなどから選ばれる金属元素を含む酸化物からなる高誘電率膜をＣＶＤ（Chemical Vapor Deposition：化学気相蒸着）法で堆積させてもよい。その後、既存の成膜技術を用いて、ゲート絶縁膜１１６及び１２０の上部表面にゲート電極１１８及び１２２となる単層または多層の導電膜を形成する。ここでは、一例として次の手法を用いる。ゲート電極１１８（ｎチャネルＭＩＳトランジスタ用）にタンタルカーバイドを、ゲート電極１２２（ｐチャネルＭＩＳトランジスタ用）にタングステンを、ＰＶＤ（Physical Vapor deposition：物理気相蒸着）により１０ｎｍ成膜する。その後、その上部表面にチタンナイトライドをＰＶＤにより１０ｎｍ成膜する。さらにその後、その上部表面に多結晶Ｓｉ層を減圧ＣＶＤ法により５０ｎｍ成膜する。 Next, gate insulating films 116 and 120 are formed on the upper surfaces of p type well region 102 and n type well region 104. As a method of forming the gate insulating films 116 and 120, for example, a Ge oxide film may be formed by a thermal oxidation method, or a Ge oxynitride film may be formed by a plasma oxynitridation method. Hf, Zr, La , Y, Al or the like may be deposited by a CVD (Chemical Vapor Deposition) method. Thereafter, a single layer or multilayer conductive film to be gate electrodes 118 and 122 is formed on the upper surfaces of the gate insulating films 116 and 120 using the existing film forming technology. Here, the following method is used as an example. Tantalum carbide is formed on the gate electrode 118 (for n-channel MIS transistor), and tungsten is formed on the gate electrode 122 (for p-channel MIS transistor) to a film thickness of 10 nm by physical vapor deposition (PVD). Thereafter, titanium nitride is deposited to a thickness of 10 nm on the upper surface by PVD. After that, a polycrystalline Si layer is deposited to a thickness of 50 nm on the upper surface by a low pressure CVD method.
　ゲート電極１１８（ｎチャネルＭＩＳトランジスタ用）には、タンタルシリサイド、窒化タンタルシリサイド、窒化チタンシリサイド、タングステンシリサイド、窒化タングステンシリサイド等を用いることができる。また、ゲート電極１２２（ｐチャネルＭＩＳトランジスタ用）には、ルテニウム、窒化チタン、窒化チタンアルミニウム、白金、白金イリジウム等を用いることができる。 For the gate electrode 118 (for n-channel MIS transistor), tantalum silicide, tantalum nitride silicide, titanium nitride silicide, tungsten silicide, tungsten nitride silicide, or the like can be used. Further, ruthenium, titanium nitride, titanium aluminum nitride, platinum, platinum iridium, or the like can be used for the gate electrode 122 (for p-channel MIS transistor).
　その後、フォトリソグラフィ技術によるパターニングを行い、異方性エッチングにより不要な膜を削除し、ゲート電極１１８及び１２２を形成する。その後、例えば、前述の実施形態による方法を用いて、側壁絶縁膜１２４、ｎ型エクステンション領域１０８、ｎ型ディープ領域１１０を形成する。 Thereafter, patterning by photolithography is performed, and an unnecessary film is removed by anisotropic etching to form gate electrodes 118 and 122. Thereafter, for example, the sidewall insulating film 124, the n-type extension region 108, and the n-type deep region 110 are formed by using the method according to the above-described embodiment.
　次に、自己整合ゲート方式により、ｐチャネルＭＩＳトランジスタのソース・ドレイン領域を形成する。ここで、「自己整合ゲート方法」とは、まずゲート積層を形成し、その後イオン注入等によってソース・ドレイン領域を形成する、という手法である。すなわち、ゲート電極１２２を傘として用いてボロン（Ｂ）のイオン注入を行い、ｐチャネル型ＭＩＳトランジスタのｐ型エクステンション領域１１２を形成する。その後、ゲート電極１２２とソース・ドレイン領域（ｐ型エクステンション領域１１２及びｐ型ディープ領域１１４）の間の絶縁のための側壁絶縁膜１２４を形成する。その後、ｐ型エクステンション領域１１２を作製した場合よりも大きな加速電圧によりボロン（Ｂ）のイオン注入を行い、ｐ型ディープ領域１１４を形成する。 Next, source / drain regions of the p-channel MIS transistor are formed by a self-aligned gate method. Here, the “self-aligned gate method” is a method in which a gate stack is first formed and then source / drain regions are formed by ion implantation or the like. That is, ion implantation of boron (B) is performed using the gate electrode 122 as an umbrella to form the p-type extension region 112 of the p-channel MIS transistor. Thereafter, a sidewall insulating film 124 for insulation between the gate electrode 122 and the source / drain regions (p-type extension region 112 and p-type deep region 114) is formed. Thereafter, boron (B) ions are implanted at an acceleration voltage higher than in the case where the p-type extension region 112 is formed, to form the p-type deep region 114.
　ソース・ドレイン領域（ｎ型エクステンション領域１０８、ｎ型ディープ領域１１０、ｐ型エクステンション領域１１２、及びｐ型ディープ領域１１４）の活性化プロセス温度としては、ゲート積層部（ゲート絶縁膜１１６、ゲート電極１１８、ゲート絶縁膜１２０、及びゲート電極１２２）及びソース・ドレイン領域のｎｐ接合部の特性を劣化させない温度が望ましく、例えば６００℃とすることができる。 The activation process temperature of the source / drain region (n-type extension region 108, n-type deep region 110, p-type extension region 112, and p-type deep region 114) is the gate laminate portion (gate insulating film 116, gate electrode 118). A temperature which does not degrade the characteristics of the gate insulating film 120 and the np junction of the gate electrode 122) and the source / drain region is desirable, for example, 600.degree.
　また、ソース・ドレイン領域の活性化処理方法としては、フラッシュランプアニール、レーザアニール等を用いることもできる。これらによれば、より短時間の処理で半導体中の不純物の活性化を実現できるため、ゲート電極１１８、１２２／ゲート絶縁膜１１６、１２０／半導体（ｐ型ウェル領域１０２、ｎ型ウェル領域１０４、ｎ型エクステンション領域１０８、ｎ型ディープ領域１１０、ｐ型エクステンション領域１１２、及びｐ型ディープ領域１１４）の構造を有する半導体装置の熱による劣化を低減することができる。 In addition, flash lamp annealing, laser annealing, or the like can also be used as a method for activating the source / drain regions. According to these, activation of the impurities in the semiconductor can be realized by processing in a shorter time, so the gate electrode 118, 122 / gate insulating film 116, 120 / semiconductor (p-type well region 102, n-type well region 104, Thermal degradation of a semiconductor device having a structure of n-type extension region 108, n-type deep region 110, p-type extension region 112, and p-type deep region 114) can be reduced.
　その後、減圧ＣＶＤにより層間絶縁膜１３０となるＳｉ酸化膜を堆積し、ＣＭＰ（Chemical Mechanical Planarization：化学機械平坦化）によりゲート電極１１８及び１２２の上端を露出させる。その後、スパッタ法等によりゲート電極１１８及び１２２の上面にニッケル層を５０ｎｍ成膜する。その後、５００℃の低温熱処理を行うことによって、ニッケルと多結晶Ｓｉとの界面領域からシリサイドが形成され、Ｎｉ２Ｓｉが形成される。ここで、本実施形態においては多結晶Ｓｉが全てシリサイドへと変換されているが、Ｎｉの膜厚をより薄くすることによって多結晶Ｓｉの一部だけをシリサイド化してもよい。その後、硫酸と過酸化水素水との混合溶液等を用いて未反応のＮｉを除去する。 Thereafter, a Si oxide film to be the interlayer insulating film 130 is deposited by low pressure CVD, and the upper ends of the gate electrodes 118 and 122 are exposed by CMP (Chemical Mechanical Planarization). Thereafter, a 50 nm thick nickel layer is formed on the upper surfaces of the gate electrodes 118 and 122 by sputtering or the like. Thereafter, by performing a low temperature heat treatment at 500 ° C., a silicide is formed from the interface region of nickel and polycrystalline Si, and Ni 2 Si is formed. Here, although all polycrystalline Si is converted to silicide in the present embodiment, only part of polycrystalline Si may be silicided by making the film thickness of Ni thinner. After that, unreacted Ni is removed using a mixed solution of sulfuric acid and hydrogen peroxide solution or the like.
　以上説明した製造方法により、図３７に表す構造のＣＭＯＳＦＥＴ半導体装置が作製される。ｐ型ドーパントの濃度および分布を制御することによって、極浅く、かつ高濃度キャリア密度を有するｎ型ソース・ドレイン領域（ｎ型エクステンション領域１０８及びｎ型ディープ領域１１０）を形成することができる。この結果、微細Ｇｅチャネル半導体装置において、短チャネル効果を抑制するとともに寄生抵抗を少なくすることが可能となり、電流駆動力が高くなる。 The CMOSFET semiconductor device having the structure shown in FIG. 37 is manufactured by the manufacturing method described above. By controlling the concentration and distribution of the p-type dopant, it is possible to form an n-type source / drain region (n-type extension region 108 and n-type deep region 110) which is extremely shallow and has a high carrier density. As a result, in the fine Ge channel semiconductor device, it is possible to suppress the short channel effect and reduce the parasitic resistance, and the current driving force becomes high.
（第６の実施形態）
　図３８は、第６の実施形態に係るＦｉｎＭＩＳＦＥＴの模式的斜視図である。本実施形態は、前述のｎ＋Ｇｅ／ｐＧｅ構造をＦｉｎＭＩＳＦＥＴに応用した例である。より詳細には、図３８において、２０８は支持基板、２０９は絶縁層、２１０はＧｅ層であり、２０８～２１０でＧＯＩ（Germanium on Insulator）基板２１１を形成している。ＧＯＩ層２１０を加工して線状（直方体状）の素子領域２０２が形成されている。素子領域２０２の中央部分には、ゲート絶縁膜２０３を介してゲート電極２０４が形成されている。ゲート電極２０４を挟む素子領域２０２の部分がソース・ドレイン領域２０５となる。 Sixth Embodiment
FIG. 38 is a schematic perspective view of FinMISFET according to the sixth embodiment. The present embodiment is an example in which the n + Ge / pGe structure described above is applied to FinMISFET. More specifically, in FIG. 38, 208 is a support substrate, 209 is an insulating layer, 210 is a Ge layer, and 208 to 210 form a GOI (Germanium on Insulator) substrate 211. The GOI layer 210 is processed to form a linear (rectangular) element region 202. A gate electrode 204 is formed in the central portion of the element region 202 with the gate insulating film 203 interposed therebetween. Portions of the element region 202 sandwiching the gate electrode 204 become source / drain regions 205.
　次に、本実施形態のＦｉｎＭＩＳＦＥＴの製造方法を説明する。まず図３９に示すように、ＧＯＩ層２１０に対し、例えばＢイオンを１００ｋｅＶ、２．０×１０１２ｃｍ－２で注入し、その後に、例えば５００℃、３０秒の熱工程を施す。続いて、例えばＲＩＥ法(反応性イオンエッチング法)等の異方性エッチングを施す事により、素子領域２０２以外の領域のＧＯＩ層２１０を除去し、素子領域２０２を形成する。 Next, a method of manufacturing the FinMISFET of this embodiment will be described. First, as shown in FIG. 39, with respect GOI layer 210, for example, by implanting B ions 100 keV, at 2.0 × 10 12 cm -2, followed by, for example 500 ° C., subjected to 30 seconds of heat treatment. Subsequently, by performing anisotropic etching such as RIE (reactive ion etching), the GOI layer 210 in the region other than the element region 202 is removed, and the element region 202 is formed.
　次に図３９に示すように、例えばＣＶＤ法（化学的気相成長法）等の方法を用いることにより、例えば厚さ５ｎｍのＨｆＯ２膜２１２を形成する。次に、図４０に示すように、ＨｆＯ２膜２１２の上に、例えばＣＶＤ法により、例えば厚さ１００ｎｍの、例えばタングステン等の高融点金属膜を堆積し、例えばＲＩＥ法等の異方性エッチングを施すことにより、高融点金属膜を加工してゲート電極２０４を形成する。続いて、例えばＲＩＥ法等の異方性エッチングを施すことにより、ＨｆＯ２膜２１２を加工して、ゲート絶縁膜２０３を形成する。 Next, as shown in FIG. 39, a HfO 2 film 212 with a thickness of 5 nm, for example, is formed by using a method such as CVD (chemical vapor deposition). Next, as shown in FIG. 40, on the HfO 2 film 212, a refractory metal film of, eg, 100 nm thickness, eg, tungsten is deposited by, eg, CVD method, and anisotropic etching, eg, RIE method, etc. The high melting point metal film is processed to form the gate electrode 204. Subsequently, the HfO 2 film 212 is processed by performing anisotropic etching such as RIE, for example, to form the gate insulating film 203.
　次に、第１の実施形態と同様に、例えば、Ｂを基板上方より全面に注入し、続いてＰを注入する。ＰとＢの注入の順序は逆でも良い。またこのとき、Ｐ注入の後にＲＩＥ法等によってゲート電極２０４，ゲート絶縁膜２１２をさらに細く加工してもよい。その後にＢを注入すれば、ＧＯＩ層２１０のチャネル側にＢだけを導入できる。そして熱工程によりｎ＋Ｇｅからなるソース・ドレイン領域５を形成すれば、ＭＯＳＦＥＴが形成される。このようにすれば、表面を高キャリア濃度のｎ＋Ｇｅにすることができ、またＰの拡散を抑制できるので、チャネル領域への横方向への拡散も抑制できる。以後は通常の層間絶縁膜形成工程、配線孔開孔工程、配線工程等を経て半導体装置が形成される。 Next, as in the first embodiment, for example, B is implanted over the entire surface of the substrate, and then P is implanted. The order of injection of P and B may be reversed. At this time, the gate electrode 204 and the gate insulating film 212 may be further thinned by RIE or the like after P implantation. After that, if B is injected, only B can be introduced on the channel side of the GOI layer 210. Then, a source / drain region 5 made of n + Ge is formed by a thermal process to form a MOSFET. In this way, the surface can be made of n + Ge having a high carrier concentration, and the diffusion of P can be suppressed, so that the lateral diffusion into the channel region can also be suppressed. Thereafter, the semiconductor device is formed through a normal interlayer insulating film forming process, a wiring hole forming process, a wiring process and the like.
　本実施形態によれば、ｎ＋Ｇｅからなるソース・ドレイン領域５を極浅かつ高キャリア濃度に形成することができ、高性能のＦｉｎＭＩＳＦＥＴを提供することができる。 According to this embodiment, the source / drain region 5 made of n + Ge can be formed to be extremely shallow and have a high carrier concentration, and a high performance Fin MISFET can be provided.
（第７の実施形態）
　第７の実施形態では、浅いｎ型拡散層を形成する別の方法について説明する。ここまでｎ型拡散層を浅くする方法として、ｐ型不純物（Ｂ）を基板内部に導入する方法を示した。ｐ型不純物によってｎ型不純物の基板奥側（内方）への拡散を抑制する。つまり、ｎ型不純物（Ｐ）の内方への拡散を抑えようとだけ考えた。そのとき、基板表面から雰囲気中への不純物の拡散（外方拡散）は全く起こらない状況を設定した。外方拡散が起こると不純物のドーズを損失することになり、表面を高キャリア濃度にする目的とは相反しているので、これを抑えようとすることは通常のプロセスでは当然のことである。しかしながら、内方への拡散を抑えようと考えたとき、むしろ積極的に外方拡散させた方がよいことが本発明での検討により明らかとなった。 Seventh Embodiment
In the seventh embodiment, another method of forming a shallow n-type diffusion layer will be described. As a method of making the n-type diffusion layer shallow so far, a method of introducing a p-type impurity (B) into the inside of the substrate has been shown. The p-type impurity suppresses the diffusion of the n-type impurity to the back side (inward) of the substrate. That is, it was thought only to suppress the inward diffusion of the n-type impurity (P). At that time, a situation was set in which diffusion (outward diffusion) of impurities from the substrate surface into the atmosphere did not occur at all. When out diffusion occurs, the dose of impurities is lost, which is contrary to the purpose of making the surface have a high carrier concentration, and it is natural for the ordinary process to try to suppress this. However, when it was intended to suppress the inward diffusion, it was clarified by the examination in the present invention that it is better to make the outward diffusion rather positive.
　図４１は、Ｇｅ中Ｐの不純物プロファイルであり、外方拡散を生じ、またその外方拡散の最大量が後述する何らかの方法によって制御された場合である。尚、表面に外方拡散を妨げるものが何もなく、真空へ外方拡散する場合が外方拡散量の上限と考える。図２とは外方拡散の有無が異なるだけで、その他はすべて同じ条件である。本発明において、外方拡散を表す物理量を、単位時間・単位面積当たりに基板最表面から外方へ放出される不純物の原子数と定義した。そのとき、（３）式は（６）式のように変更される。
Figure JPOXMLDOC01-appb-M000003
 FIG. 41 shows an impurity profile of P in Ge, in which out diffusion occurs, and the maximum amount of the out diffusion is controlled by some method described later. There is nothing to prevent the outward diffusion on the surface, and the case of outward diffusion to vacuum is considered to be the upper limit of the amount of outward diffusion. The conditions are the same as in FIG. 2 except for the presence or absence of outward diffusion. In the present invention, the physical quantity representing the outward diffusion is defined as the number of atoms of impurities released outward from the outermost surface of the substrate per unit time and unit area. At that time, equation (3) is changed as equation (6).
Figure JPOXMLDOC01-appb-M000003
ここで、
Figure JPOXMLDOC01-appb-M000004
 here,
Figure JPOXMLDOC01-appb-M000004
と定義した。Ｊ（ｃｍ－２ｓ－１）は、外方拡散の最大量を決めるものであり、表面の濃度が高い場合には、表面でＪだけが外方拡散し、表面濃度が低い場合には、Ｊよりも少ない量が外方拡散する。 It was defined as J (cm -2 s -1 ) determines the maximum amount of out diffusion, and when the surface concentration is high, only J diffuses out at the surface, and when the surface concentration is low, An amount smaller than J diffuses out.
　図４１では、Ｊ＝１×１０１５ｃｍ－２ｓ－１である。これからわかるように、外方拡散がない場合（図１）と同様に、最初は大きく拡散し、徐々にゆっくりになりながら拡散していく。しかし、外方拡散がある場合には、その拡散速度は、無い場合に較べて相対的にゆっくりである。熱処理前に濃度が１×１０１９ｃｍ－３の位置はＲｐから３．５ｎｍであり、０．１秒後は１２．７ｎｍまで広がり、０．２秒後では１５．１ｎｍ、０．３秒後では１６．６ｎｍと広がり、１秒後では２１．６ｎｍまで拡散する。 In FIG. 41, J = 1 × 10 15 cm −2 s −1 . As can be seen from this, as in the case of no outward diffusion (FIG. 1), the light diffuses initially at a large rate and gradually diffuses gradually. However, if there is outward diffusion, the rate of diffusion is relatively slow compared to when it is not. Before heat treatment, the concentration is 1 × 10 19 cm -3 from Rp to 3.5 nm, and after 0.1 seconds it spreads to 12.7 nm, after 0.2 seconds 15.1 nm, after 0.3 seconds Spreads to 16.6 nm and diffuses to 21.6 nm after one second.
　外方拡散がある場合には、無い場合に較べて、表面側の濃度が減少していくことが特徴的である。最表面において存在する不純物が表面の外側に抜けていくからである。この場合の外方拡散Ｊは、１×１０１５ｃｍ－２ｓ－１である。最初は最表面と基板奥での不純物濃度が高いため、Ｊと同じ量の不純物が抜けていく。そのため、最初は表面での不純物濃度の減少が速い。しかし、時間が経過するに従って、不純物の内方への拡散も進み、最表面と基板奥での不純物濃度が低下する。すると、最表面ではＪよりも少ない量しか外方拡散できなくなるため、最表面での濃度の減少する速度も遅くなる。つまり、外方拡散は、内方への拡散の影響も受けている。内方への拡散が少なければ外方拡散は多くなり、反対に内方への拡散が多ければ外方への拡散は少なくなる。 It is characteristic that when there is outward diffusion, the concentration on the surface side decreases as compared with the case where there is no outward diffusion. This is because impurities present at the outermost surface escape to the outside of the surface. The outward diffusion J in this case is 1 × 10 15 cm −2 s −1 . Since the impurity concentration at the outermost surface and the back of the substrate is high at first, the same amount of impurity as J is eliminated. Therefore, the reduction of the impurity concentration on the surface is fast at first. However, as time passes, the inward diffusion of the impurity also proceeds, and the impurity concentration at the outermost surface and the back of the substrate decreases. Then, at the outermost surface, only an amount smaller than J can be diffused outward, so the rate of decrease of the concentration at the outermost surface also becomes slower. In other words, outward diffusion is also affected by inward diffusion. The less the inward diffusion, the more the outward diffusion, and the more the inward diffusion, the less the outward diffusion.
　図４２は、外方拡散無しの場合（図２）と有りの場合（図４１）のＰの拡散距離を比較したものである。濃度が１×１０１９ｃｍ－３の場合の、同じ拡散時間におけるそれぞれの内方拡散距離（Ｒｐを原点に取ったときの深さ）をプロットした。図から明らかなように、外方拡散を起こすことによって内方への拡散距離が短くなっており、それは距離が大きくなるほど、言い換えれば拡散時間が長くなるほど、その差は大きくなっていく。このように、外方拡散をあえて起こすことによって、外方拡散を抑えた場合に較べて、内方拡散が抑えられることがわかる。 FIG. 42 compares the diffusion distances of P in the case of no outward diffusion (FIG. 2) and in the case of presence (FIG. 41). Respective inward diffusion distances (depths with Rp taken as the origin) at the same diffusion time when the concentration is 1 × 10 19 cm −3 were plotted. As apparent from the figure, the inward diffusion distance is shortened by causing the outward diffusion, and the difference becomes larger as the distance becomes longer, that is, as the diffusion time becomes longer. As described above, it can be understood that inward diffusion can be suppressed by intentionally causing outward diffusion as compared with the case where outward diffusion is suppressed.
　図４３は、図４１と同じ条件のものであり、その電子濃度プロファイルを示したものである。図３と同様に、この場合にはｎ型ドーパントしかないため、電子濃度は、７７３Ｋにおける真性キャリア濃度ｎｉ以上（＞７×１０１７ｃｍ－３）で不純物濃度と一致している。このように、表面から２６．６ｎｍがｎ＋Ｇｅとなっており、外方拡散無しの場合に較べて、浅いｎ＋Ｇｅ層が形成できることがわかる。 FIG. 43 shows the electron concentration profile under the same conditions as FIG. As in FIG. 3, since there is only n-type dopant in this case, the electron concentration is in agreement with the impurity concentration at the intrinsic carrier concentration ni or more at 773 K (> 7 × 10 17 cm −3) . Thus, it is understood that 26.6 nm from the surface is n + Ge, and a shallow n + Ge layer can be formed as compared with the case without out diffusion.
（第８の実施形態）
　この外方拡散による内方拡散抑制の効果は、本発明のｐ型不純物によってｎ型不純物の拡散を抑制する効果と一緒に用いれば、単なる組み合わせ以上の効果があり、さらに効果的である。ここでは、Ｇｅ基板にｎ型不純物と共にｐ型不純物も同時に存在して、外方拡散がある場合と無い場合を比較した場合に、ｎ型不純物の拡散にどのような違いが現れるかを示す。 Eighth Embodiment
The effect of the inward diffusion suppression by the outward diffusion is more effective if it is used together with the effect of suppressing the diffusion of the n-type impurity by the p-type impurity of the present invention, and the effect is more than a mere combination. Here, a p-type impurity is simultaneously present in the Ge substrate together with the n-type impurity, and it is shown what kind of difference appears in the diffusion of the n-type impurity when comparing the case of the out diffusion and the case of the out diffusion.
　図４４は、ｎ型不純物Ｐとｐ型不純物Ｂが共存している場合で、外方拡散がない場合である。図２の場合に加えて、ＢがＧｅ基板の表面から７．５～１７．５ｎｍまでの深さに存在している。ここでは、ＰがＢの分布している領域を大きく超えて拡散する場合を示した。前述したように、ｎ型不純物の拡散が、ｐ型不純物が分布している領域を超えてしまっても、ｐ型不純物が無い場合に較べれば、内方への拡散が極めて効果的に抑制できる。 FIG. 44 shows the case where the n-type impurity P and the p-type impurity B coexist and there is no out diffusion. In addition to the case of FIG. 2, B is present at a depth of 7.5 to 17.5 nm from the surface of the Ge substrate. Here, the case is shown where P diffuses far beyond the region where B is distributed. As described above, even if the diffusion of the n-type impurity exceeds the region where the p-type impurity is distributed, the inward diffusion can be extremely effectively suppressed as compared with the case where the p-type impurity is not present. .
　図４５は、Ｂ無しの場合（図２）と有りの場合（図４４）のＰの拡散距離を比較したものであり、どちらも外方拡散が無い場合である。濃度が１×１０１９ｃｍ－３の場合の、同じ拡散時間におけるそれぞれの拡散距離（Ｒｐを原点に取ったときの深さ）をプロットした。図から明らかなように、ＰがＢの分布している領域を大きく超えても、Ｂが無い場合に較べて拡散距離が短くなっている。 FIG. 45 is a comparison of the diffusion distance of P in the case without B (FIG. 2) and in the case with (FIG. 44), both of which are cases where there is no outward diffusion. Each diffusion distance (depth when taking Rp as the origin) at the same diffusion time when the concentration is 1 × 10 19 cm −3 was plotted. As apparent from the figure, even if P greatly exceeds the area where B is distributed, the diffusion distance is shorter than when B is not present.
　図４６は、図４４と同じ条件のものであり、その電子濃度プロファイルを示したものである。前述したものと同様に、全体がｎ＋Ｇｅになっていることがわかる。 FIG. 46 shows the electron concentration profile under the same conditions as FIG. It turns out that the whole becomes n <+> Ge similarly to what was mentioned above.
（第９の実施形態）
　Ｇｅ基板中にＢが存在し、さらに外方拡散がある場合の不純物プロファイルを示したものが図４７である。外方拡散量Ｊは１×１０１５ｃｍ－２ｓ－１である。これからわかるように、拡散の振る舞いは、外方拡散がない場合（図１）やＢが内在する場合（図４４）と大きく異なっている。この場合には、外方と内方への拡散が同時に起こる。内方へ拡散するＰはＢが存在する領域で拡散速度が遅くなる。外方拡散がない場合には、表面からＰが外に抜けられないので、いわば内方へ跳ね返されることになる。そのため、図４４の場合にはＢの存在する領域を多くのＰが通り抜け、基板の内方へ拡散した。 Ninth Embodiment
FIG. 47 shows the impurity profile when B is present in the Ge substrate and further outward diffusion is present. The outward diffusion amount J is 1 × 10 15 cm −2 s −1 . As can be understood from this, the diffusion behavior is largely different from the case where there is no outward diffusion (FIG. 1) or the case where B is inherent (FIG. 44). In this case, outward and inward diffusion occur simultaneously. The inward diffusion of P slows down in the region where B is present. If there is no outward diffusion, P can not escape from the surface, so it will be repelled in an inward manner. Therefore, in the case of FIG. 44, a large amount of P passes through the region where B exists and diffuses inward of the substrate.
　一方、図４７の場合には、ＰはＢの存在する領域をゆっくり拡散すると同時に、表面に向かい、表面から外側に抜け出すことができる。つまり、基板奥へ拡散しすぎないように表面から外方拡散させることにより、Ｂによる拡散抑制の効果を利用して内方への拡散を抑制することができる。熱処理前に濃度が１×１０１９ｃｍ－３の位置はＲｐから３．５ｎｍであり、０．１秒後は８．９ｎｍまで広がり、０．２秒後では１０．３ｎｍ、０．３秒後では１１．０ｎｍと広がり、１秒後では１２．２ｎｍまで拡散する。 On the other hand, in the case of FIG. 47, P can diffuse toward the surface at the same time as it diffuses slowly in the region where B exists, and can escape outward from the surface. That is, by diffusing outward from the surface so as not to diffuse too far into the substrate, it is possible to suppress the inward diffusion by using the diffusion suppression effect of B. Before heat treatment, the concentration is 1 × 10 19 cm -3 from Rp to 3.5 nm, and after 0.1 seconds it spreads to 8.9 nm, after 0.2 seconds 10.3 nm, after 0.3 seconds Spreads to 11.0 nm, and diffuses to 12.2 nm after one second.
　図４８は、Ｇｅ基板中にＢが存在し、さらに外方拡散無しの場合（図４４）と有りの場合（図４７）のＰの拡散距離を比較したものである。濃度が１×１０１９ｃｍ－３の場合の、同じ拡散時間におけるそれぞれの内方拡散距離（Ｒｐを原点に取ったときの深さ）をプロットした。図から明らかなように、外方拡散を起こすことによって内方への拡散距離が短くなっており、それは距離が大きくなるほど、言い換えれば拡散時間が長くなるほど、その差は大きくなっていく。このように、外方拡散をあえて起こすことによって、外方拡散を抑えた場合に較べて、内方拡散が抑えられることがわかる。 FIG. 48 compares the diffusion distances of P in the case where B exists in the Ge substrate and there is no outward diffusion (FIG. 44) and in the case where it is present (FIG. 47). Respective inward diffusion distances (depths with Rp taken as the origin) at the same diffusion time when the concentration is 1 × 10 19 cm −3 were plotted. As apparent from the figure, the inward diffusion distance is shortened by causing the outward diffusion, and the difference becomes larger as the distance becomes longer, that is, as the diffusion time becomes longer. As described above, it can be understood that inward diffusion can be suppressed by intentionally causing outward diffusion as compared with the case where outward diffusion is suppressed.
　図４９は、図４７と同じ条件のものであり、その電子濃度プロファイルを示したものである。ＢがＧｅ基板の表面から７．５～１７．５ｎｍの範囲に、２．５×１０２０ｃｍ－３という高濃度で存在しているため、熱処理前の状態でＰ濃度がＢ濃度より低い場所では、電子濃度は２．８×１０１５ｃｍ－３になる。（４）式からわかるように実効拡散係数は電子濃度の自乗に比例しているため、電子濃度が低いほど拡散が遅くなる。またこの場合には、外方へ向かう方が電子濃度が高いため拡散が速い。図４６の場合とは異なり、外方拡散があるため、Ｂのある領域を大幅に超えることがない。 FIG. 49 shows the electron concentration profile under the same conditions as FIG. Since B is present at a high concentration of 2.5 × 10 20 cm -3 in the range of 7.5 to 17.5 nm from the surface of the Ge substrate, a place where the P concentration is lower than the B concentration before the heat treatment Then, the electron concentration is 2.8 × 10 15 cm −3 . As can be seen from equation (4), the effective diffusion coefficient is proportional to the square of the electron concentration, so the lower the electron concentration, the slower the diffusion. In this case, the diffusion is faster because the electron concentration is higher when going outward. Unlike the case of FIG. 46, since there is outward diffusion, it does not significantly exceed the region where B is present.
　外方拡散するとドーズを損失することになるが、それ以上に５００℃以上の熱処理をしても内部への拡散が抑えられる利点の方が遙かに大きい。ｎ型不純物を導入したあとは、不純物の電気的活性化をさせなければならないので、高温での熱処理が必要になる。高温での熱処理を行うと拡散が速くなり、ｎ＋Ｇｅ層が深くなる。制御して外方拡散を起こせば、高温の熱処理を行っても、内方への拡散が遅くなるため、浅いｎ＋Ｇｅ層が形成できる。 When it diffuses out, it loses the dose, but the advantage is that the inward diffusion is suppressed even if the heat treatment is performed at 500 ° C. or more. After the n-type impurity is introduced, it is necessary to electrically activate the impurity, so heat treatment at a high temperature is required. Heat treatment at high temperatures results in faster diffusion and deeper n + Ge layers. If controlled outward diffusion is performed, a shallow n + Ge layer can be formed because the inward diffusion is delayed even if a high temperature heat treatment is performed.
（第１０の実施形態）
　ここでは、ｎ型不純物層の形成方法の実施形態を図５０～５３を参照して説明する。まず、ｐ型Ｇｅ基板１の表面を、例えば、ＨＦやＨＣｌなどのハロゲン酸により前処理する。そして、通常はイオン注入前に形成する保護膜などは形成せず、表面に何も形成しない状態でｐ型Ｇｅ基板１にＰをイオン注入する（図５０）。すると、ｐ型Ｇｅ基板１の表面付近にＰの高濃度層３が形成される（図５１）。続いて、この基板を熱処理すると、Ｐの内方への拡散と外方への拡散が起きる（図５２）。本発明の効果により、イオン注入したドーズよりは低くなるが、浅くて高濃度のｎ＋Ｇｅ層が形成される（図５３）。ここでは、表面の前処理などを行い、表面に何も形成していない状態にしてからイオン注入し、外方拡散を起こす例を示した。表面に保護膜などがある状態でイオン注入し、その後に表面の前処理などを行い、表面に何も形成していない状態にして、外方拡散を起こしても良い。 Tenth Embodiment
Here, an embodiment of a method of forming an n-type impurity layer will be described with reference to FIGS. First, the surface of the p-type Ge substrate 1 is pretreated, for example, with a halogen acid such as HF or HCl. Then, normally, a protective film or the like formed before ion implantation is not formed, and P is ion implanted into the p-type Ge substrate 1 in a state where nothing is formed on the surface (FIG. 50). Then, a high concentration layer 3 of P is formed in the vicinity of the surface of the p-type Ge substrate 1 (FIG. 51). Subsequently, when the substrate is heat-treated, inward diffusion and outward diffusion of P occur (FIG. 52). By the effect of the present invention, a shallow and high concentration n + Ge layer is formed although it is lower than the ion implanted dose (FIG. 53). Here, an example is shown in which the surface is pretreated and nothing is formed on the surface and then ion implantation is performed to cause outward diffusion. Ions may be implanted in a state in which a protective film or the like is present on the surface, and then pretreatment of the surface may be performed to cause outward diffusion while nothing is formed on the surface.
（第１１の実施形態）
　続いて、ｎ型不純物層の他の形成方法の実施形態を図５４～５７を参照して説明する。まず、ｐ型Ｇｅ基板１の表面にＰイオン注入する（図５４）。このとき、表面に保護膜があってもなくても構わない。続いて、Ｇｅ表面にＳｉＯｘ薄膜２０をＣＶＤなどの方法により堆積する。なお、イオン注入する前に形成しても構わない。そして、ｐ型Ｇｅ基板にＰをイオン注入する（図５５）。続いて、この基板を熱処理すると、Ｐの内方への拡散と外方への拡散が起きる（図５６）。このとき、Ｇｅ基板表面にはＳｉＯｘ薄膜があるため、ＳｉＯｘ薄膜が無い場合と較べて外方拡散量を少なくすることができる。またその膜厚を調整することにより外方拡散量も制御できる。その膜厚は、０～３ｎｍの範囲であることが望ましい。熱処理後、ＨＦ処理などのハロゲン酸前処理によりＳｉＯｘをＧｅ基板表面から除去する（図５７）。 Eleventh Embodiment
Subsequently, another embodiment of the method for forming the n-type impurity layer will be described with reference to FIGS. 54 to 57. First, P ions are implanted into the surface of the p-type Ge substrate 1 (FIG. 54). At this time, the protective film may or may not be present on the surface. Subsequently, a SiOx thin film 20 is deposited on the Ge surface by a method such as CVD. It may be formed before ion implantation. Then, P is ion-implanted into the p-type Ge substrate (FIG. 55). Subsequently, when the substrate is heat-treated, inward diffusion and outward diffusion of P occur (FIG. 56). At this time, since the SiOx thin film is present on the surface of the Ge substrate, the amount of outward diffusion can be reduced as compared with the case where the SiOx thin film is not present. Further, the amount of outward diffusion can also be controlled by adjusting the film thickness. The film thickness is desirably in the range of 0 to 3 nm. After the heat treatment, SiOx is removed from the surface of the Ge substrate by halogen acid pretreatment such as HF treatment (FIG. 57).
　こうして、浅くて高濃度の電子濃度からなるｎ＋Ｇｅ層７が形成できる。尚、ここではＳｉＯｘを通してすべてが外方拡散する例について示したが、ＳｉＯｘ中やＳｉＯｘ／Ｇｅ界面に一部、あるいはすべてＰをトラップさせても良い。ＳｉＯｘが、例えばポーラスである場合、Ｐは膜の中により取り込むことができる。ＳｉＯxが除去しきれずに、基板表面付近にＳｉやＯが残っていても問題ない。コンタクトのメタルがＧｅ基板表面の電荷中性準位（charge neutrality level）にピニング（pinning）される影響が低くなるため、むしろＳｉやＯは残った方がよい。 Thus, an n + Ge layer 7 can be formed which is shallow and has a high concentration of electrons. Here, although an example in which all out-diffuse through SiOx is shown, a part or all of P may be trapped in the SiOx or the SiOx / Ge interface. If SiOx is, for example, porous, P can be incorporated into the membrane. There is no problem if Si or O remains near the substrate surface without removing SiOx. It is preferable that Si and O be left since the influence of the metal of the contact being pinned to the charge neutrality level of the Ge substrate surface is reduced.
　以上、ＳｉＯx薄膜を用いて説明したが、これに代えて、ＧｅＯｘ薄膜を用いてもよい。ＧｅＯｘ薄膜の場合、Ｐをイオン注入した後に、Ｇｅ基板表面に、ＧｅＯｘ薄膜２２を堆積、あるいは酸素雰囲気で成膜する。ＧｅはＧｅＯの形態で脱離する性質があるが、高圧の酸素雰囲気では脱離が抑えられるので、ＧｅＯｘの成膜や膜厚の維持が可能である。 As mentioned above, although explained using a SiOx thin film, it may replace with this and may use a GeOx thin film. In the case of the GeOx thin film, after ion implantation of P, the GeOx thin film 22 is deposited on the surface of the Ge substrate or formed in an oxygen atmosphere. Ge has the property of being desorbed in the form of GeO, but since desorption is suppressed in a high pressure oxygen atmosphere, deposition of GeO x and maintenance of film thickness are possible.
　続いて、この基板を熱処理すると、Ｐの内方への拡散と外方への拡散が起きる。このとき、ＳｉＯｘ薄膜の場合と同じように、Ｇｅ基板表面にはＧｅＯｘ薄膜があるため、ＧｅＯｘ薄膜が無い場合と較べて外方拡散量を少なくすることができる。またその膜厚を調整することにより外方拡散量も制御できる。その膜厚は、０～３ｎｍの範囲であることが望ましい。 Subsequently, when the substrate is heat treated, inward diffusion and outward diffusion of P occur. At this time, as in the case of the SiOx thin film, since the GeOx thin film is present on the surface of the Ge substrate, the amount of out-diffusion can be reduced as compared with the case where the GeOx thin film is absent. Further, the amount of outward diffusion can also be controlled by adjusting the film thickness. The film thickness is desirably in the range of 0 to 3 nm.
　熱処理後、ＨＦ処理などのハロゲン酸前処理によりＧｅＯｘをＧｅ基板表面から除去する。あるいは、酸素雰囲気からそれ以外の雰囲気で、例えば窒素雰囲気や真空中で熱処理して、ＧｅＯｘ層を脱離させる。こうして、浅くて高濃度の電子濃度からなるｎ＋Ｇｅ層が形成できる。 After the heat treatment, GeOx is removed from the surface of the Ge substrate by halogen acid pretreatment such as HF treatment. Alternatively, the GeOx layer is released by heat treatment from an oxygen atmosphere to another atmosphere, for example, in a nitrogen atmosphere or vacuum. Thus, an n + Ge layer having a shallow and high electron concentration can be formed.
　なお、ここではＧｅＯｘを通してすべてが外方拡散する例について示したが、ＧｅＯｘ中やＧｅＯｘ／Ｇｅ界面に一部、あるいはすべてＰをトラップさせても良い。ＧｅＯｘが、例えばポーラスである場合、Ｐは膜の中により取り込むことができる。また、Ｇｅ表面をプラズマ酸化すれば、ＧｅＯｘが形成されると同時に、Ｇｅ基板の表面付近に空孔が形成される。拡散係数は空孔の数が増えると大きくなるため、外方拡散が促進される。さらに表面が負に帯電していれば、拡散メカニズムにより、負に帯電した空孔が多く増えるため、外方拡散が促進される。 Note that although an example in which all out-diffuse through GeOx is shown here, a part or all of P may be trapped in the GeOx or GeOx / Ge interface. When GeOx is, for example, porous, P can be incorporated into the membrane. In addition, when the Ge surface is plasma oxidized, GeOx is formed, and at the same time, vacancies are formed in the vicinity of the surface of the Ge substrate. Since the diffusion coefficient increases as the number of holes increases, outward diffusion is promoted. Furthermore, if the surface is negatively charged, the diffusion mechanism promotes the outward diffusion because the number of negatively charged holes increases.
　外方拡散を抑制する膜は、熱処理中常に存在する必要がない。例えば、それらの膜は、熱処理の最初は存在していなくて途中で形成しても良いし、熱処理の最初に存在していて途中で無くしても良い。例えば、ＧｅＯｘの場合、常に熱処理中にＧｅＯｘ層が表面に存在したが、そうでなくても良い。熱処理の最初の段階では、酸素の圧力を、例えば７０気圧の高圧雰囲気で行う。すると、ＧｅＯｘ層の脱離が起こらず、成長させることもできる。そして、熱処理の途中で圧力を下げ、例えば、酸素やそれ以外の雰囲気で常圧あるいは真空にするとＧｅＯの脱離が起きるので、ＧｅＯｘ層の除去が可能になる。あるいは、熱処理の最初の段階では、酸素やそれ以外の雰囲気で常圧あるいは真空にすると、表面に何もない状態にすることができる。そして、酸素の圧力が、例えば７０気圧の高圧の雰囲気で熱処理を行う。すると、ＧｅＯｘ層の脱離が起こらないので、表面にＧｅＯｘ層を形成することができる。 The membrane that suppresses the outward diffusion need not always be present during the heat treatment. For example, those films may not be present at the beginning of the heat treatment and may be formed on the way, or may be present at the beginning of the heat treatment and eliminated on the way. For example, in the case of GeOx, a GeOx layer is always present on the surface during heat treatment, but this may not be the case. In the first stage of the heat treatment, the pressure of oxygen is performed in a high pressure atmosphere of, for example, 70 atm. Then, desorption of the GeOx layer does not occur, and growth can also be performed. Then, the pressure is lowered in the middle of the heat treatment, for example, when atmospheric pressure or vacuum is applied under oxygen or other atmosphere, desorption of GeO occurs, so that the GeOx layer can be removed. Alternatively, in the first stage of the heat treatment, the surface can be made empty by applying atmospheric pressure or vacuum in oxygen or other atmosphere. Then, the heat treatment is performed in an atmosphere at a high pressure of, for example, 70 atm under the pressure of oxygen. Then, since desorption of the GeOx layer does not occur, a GeOx layer can be formed on the surface.
　以上、ＳｉＯｘとＧｅＯｘについての例を示したが、外方拡散の効果があれば他の膜でも良い。例えば、ＳｉＯＮやＳｉＧｅＯ，ＧｅＯＮ，ＨｆＯｘ，ＬａＯｘ，ＡｌＯｘ，ＴｉＯｘ，ＴａＯｘ，ＺｒＯｘなどの薄膜の絶縁体でも良いし、Ｓｉ，ＳｉＧｅなどの半導体薄膜でも良い。これらがｎ＋Ｇｅ基板表面付近に残っていても良い。なお、上記膜の構成元素の構成比は、ｘを用いて表示していない場合においても任意である。 Although the examples of SiOx and GeOx have been described above, other films may be used as long as the effect of out diffusion is obtained. For example, a thin film insulator such as SiON, SiGeO, GeON, HfOx, LaOx, AlOx, TiOx, TaOx, or ZrOx may be used, or a semiconductor thin film such as Si or SiGe may be used. These may be left near the n + Ge substrate surface. Note that the composition ratio of the constituent elements of the film is optional even in the case where it is not displayed using x.
（第１２の実施形態）
　続いて、ｎ型不純物層の他の形成方法の実施形態を図５８～６２を参照して説明する。まず、ｐ型Ｇｅ基板１の表面にＰをイオン注入する（図５８）。そして、Ｇｅ基板表面に、Ｎｉ薄膜２４を堆積する（図５９）。尚、Ｎｉ薄膜を形成してからＰをイオン注入しても良い。続いて、この基板を熱処理すると、Ｐの内方への拡散と外方への拡散が起きる（図６０）。 Twelfth Embodiment
Subsequently, another embodiment of the method for forming the n-type impurity layer will be described with reference to FIGS. First, P is ion implanted into the surface of the p-type Ge substrate 1 (FIG. 58). Then, a Ni thin film 24 is deposited on the surface of the Ge substrate (FIG. 59). Alternatively, P may be ion-implanted after the Ni thin film is formed. Subsequently, heat treatment of this substrate causes inward diffusion and outward diffusion of P (FIG. 60).
　このとき、Ｇｅ基板１の表面にはＮｉ薄膜があるため、ＮｉＧｅ層２６が形成されると共に、Ｎｉ薄膜が無い場合と較べて外方拡散量を少なくすることができる。またその膜厚を調整することにより外方拡散量も制御できる。薄い方がよいため、熱処理前のＮｉ層２４の厚さＴＮｉは、０＜ＴＮｉ＜５ｎｍ、形成されたＮｉＧｅ層２６の厚さＴＮｉＧｅは０＜ＴＮｉＧｅ＜１０ｎｍの範囲を満たすことが望ましい（図６１）。熱処理後、未反応のＮｉを例えばＨＣｌなどで除去する（図６２）。 At this time, since the Ni thin film is present on the surface of the Ge substrate 1, the NiGe layer 26 is formed, and the amount of outward diffusion can be reduced as compared with the case where the Ni thin film is not present. Further, the amount of outward diffusion can also be controlled by adjusting the film thickness. Since it is better to be thinner, the thickness T Ni of the Ni layer 24 before heat treatment should satisfy the range of 0 <T Ni <5 nm, and the thickness T NiGe of the formed NiGe layer 26 satisfy the range of 0 <T NiGe <10 nm Desirable (FIG. 61). After the heat treatment, unreacted Ni is removed with, for example, HCl (FIG. 62).
　こうして、浅くて濃度の電子濃度からなるｎ＋Ｇｅ層が形成できる。尚、ＮｉＧｅが存在する領域にＰが存在していても良い。また、Ｎｉについての実施例を示したが、Ｇｅと低温で反応し、低い抵抗率を持てばよい。そのような材料として、１５０～３６０℃で反応し、２２～１２９μΩｃｍの低抵抗な相を持つＦｅ，Ｃｏ，Ｐｄ，Ｐｔ，Ｃｕなどがある（S. Gaudet et al., International SiGe Technology and Devices Meeting, 18 (2006); J. Appl. Phys. 100, 034306 (2006).参照)。これらの一つ以上を用いても良い。 Thus, an n + Ge layer can be formed which is shallow and has a concentration of electrons. P may be present in the region where NiGe exists. Also, although an example of Ni is shown, it may react with Ge at low temperature and have a low resistivity. Such materials include Fe, Co, Pd, Pt, Cu, etc. which react at 150 to 360 ° C. and have a low resistance phase of 22 to 129 μΩ cm (S. Gaudet et al., International SiGe Technology and Devices Meeting , 18 (2006); J. Appl. Phys. 100, 034306 (2006). One or more of these may be used.
　なお実施形態を通じ、ｎ型不純物としてＰを例に取ったが、他のものでも良く、例えば、Ａｓ，Ｓｂ，Ｂｉなどの一つ以上であっても良い。ｐ型不純物も同様であり、他のものでも良く、例えば、Ｂ，Ａｌ，Ｇａ，Ｉｎなどの一つ以上であっても良い。また本発明ではＢが拡散しない温度７７３Ｋを想定したが、Ｐよりも拡散が遅ければＢが拡散する高い温度でも効果があるし、もちろん低い温度でも効果があり、温度には制限がない。不純物を導入する方法として、ＣＶＤ、イオン注入の例を示したが、その他の方法でも構わない。 Although P is taken as an example of the n-type impurity throughout the embodiment, other elements may be used, for example, one or more of As, Sb, Bi and the like. The p-type impurity is also the same, and may be another one, for example, one or more of B, Al, Ga, In and the like. In the present invention, a temperature 773 K at which B does not diffuse is assumed. However, if the diffusion is slower than P, it is effective even at a high temperature at which B diffuses, and of course it is effective even at a low temperature, and the temperature is not limited. Although examples of CVD and ion implantation have been shown as methods of introducing impurities, other methods may be used.
　基板としてＧｅ主成分とするｐ型半導体を例に取り説明したが、ｎ型半導体でもよく、あるいは化合物半導体などの他の半導体でも構わない。その半導体にとってｎ型不純物となるものが、本発明で説明したＧｅにおけるｎ型不純物の拡散メカニズムと同様に、空孔とペアになり、それが電荷を帯びているのならば、その電荷を打ち消すｐ型不純物を本発明と同様に用いれば、本発明と同様の効果があり、ｎ型不純物の拡散が抑制され、極浅かつ高キャリア濃度のｎ型不純物領域が形成できる。 Although a p-type semiconductor mainly composed of Ge has been described as an example of the substrate, it may be an n-type semiconductor or another semiconductor such as a compound semiconductor. What becomes an n-type impurity for the semiconductor is paired with a vacancy and, if it is charged, cancels the charge, similarly to the diffusion mechanism of the n-type impurity in Ge described in the present invention If p-type impurities are used in the same manner as in the present invention, the same effects as in the present invention can be obtained, diffusion of n-type impurities can be suppressed, and extremely shallow n-type impurity regions with high carrier concentration can be formed.
　また半導体として、Ｇｅ主成分とする半導体を例に取り示したが、化合物半導体でも構わない。化合物半導体としては、例えば、ＩＩＩ－Ｖ族半導体があり、ＧａＡｓ、ＩｎＰ，ＩｎＳｂ，ＧａＮ，ＩｎＧａＡｓなどがある。ＧａＡｓにおいてｐ型ドーパントは、例えばＺｎ、ｎ型ドーパントは、例えばＳｉが用いられる。ＧａＡｓ中でのＺｎの拡散は、次の化学平衡で表されるキックアウト（kick-out）メカニズムによって説明される（例えば、H. Bracht et al., Physica B, 308, 831 (2001)参照）。 Further, as a semiconductor, a semiconductor containing Ge as a main component is exemplified, but a compound semiconductor may be used. Examples of compound semiconductors include III-V semiconductors, such as GaAs, InP, InSb, GaN, and InGaAs. In GaAs, for example, Zn is used as a p-type dopant, and Si is used as an n-type dopant. The diffusion of Zn in GaAs is explained by the kick-out mechanism represented by the following chemical equilibrium (see, for example, H. Bracht et al., Physica B, 308, 831 (2001)) .
　　　 Ｚｎ＋ ｉ　⇔　Ｚｎ－ Ｇａ＋Ｉ２＋ Ｇａ　　　（７）
　ここで、Ｚｎ＋ ｉ  は格子間 (interstitial)のＺｎ、Ｚｎ－ ＧａはＧａのサイトを占めるＺｎ、Ｉ２＋ Ｇａはセルフインタースティシャル（self-interstitial）のＧａである。Ｚｎ＋ ｉは格子間を拡散し、Ｇａが格子間にキックアウトされて（Ｉ２＋ Ｇａ）、Ｇａのサイトが空いたところにＺｎが入り込む（Ｚｎ－ Ｇａ）。Ｚｎが１０２０ｃｍ－３を超える高濃度では、キンクアンドテイル（kink-and-tail）メカニズムに従うという報告もあるが、いずれにしても、ｐ型ドーパントとして働くＺｎの拡散を防ぐためには、電荷を補償、つまり打ち消すように、ｎ型ドーパントとして働くＳｉを導入してやればよい。Ｚｎの拡散係数は大きいので、拡散係数の小さいＳｉと組み合わせれば、本発明の効果によって、最初はＺｎの拡散をＳｉによって抑え、最終的には浅くて高キャリア濃度のｐ＋ＧａＡｓが形成できる。 Zn + i Zn Zn − Ga + I 2 + Ga (7)
Where Zn + i   Is an interstitial Zn, Zn - Ga is a Zn occupying Ga site, and I 2 + Ga is a self-interstitial Ga. Zn + i is diffused between the lattice, Ga is kick out between the lattice (I 2+ Ga), Zn enters into the place vacated the site of Ga (Zn - Ga). At high concentrations of Zn> 10 20 cm -3 it has been reported that the kink-and-tail mechanism is followed, but in any case, to prevent the diffusion of Zn acting as a p-type dopant, In order to compensate, that is, cancel, Si acting as an n-type dopant may be introduced. Since the diffusion coefficient of Zn is large, when combined with Si having a small diffusion coefficient, the effect of the present invention can initially suppress the diffusion of Zn by Si and finally form shallow and high carrier concentration p + GaAs .
　また、ｐ型不純物層はＧｅ基板の内奥側に形成した場合を述べたが、ｐ型半導体基板の表面側にｐ型不純物層を形成して、熱処理の際におけるｎ型不純物の外方拡散、すなわち表面から外側への拡散を抑制するバリア層としても用いることができる。このとき、ｐ型不純物層は、ｐ型不純物を含むＧｅでも良いし、Ｓｉでもよく、あるいはＳｉＯ２などでも構わない。熱処理後、ｐ型不純物層は除去しても良い。 Although the p-type impurity layer is formed on the inner side of the Ge substrate, the p-type impurity layer is formed on the surface side of the p-type semiconductor substrate, and the outward diffusion of the n-type impurity occurs during heat treatment. That is, it can also be used as a barrier layer which suppresses the diffusion from the surface to the outside. At this time, the p-type impurity layer may be Ge containing p-type impurities, may be Si, or may be SiO 2 or the like. After the heat treatment, the p-type impurity layer may be removed.
　さらにｐ型不純物層は、ｎ型不純物の基板内奥側への拡散抑制だけでなく、チャネルのある横方向への拡散を抑えるように形成しても良い。その場合には、ｎ型不純物拡散層のチャネル側にｐ型不純物が含まれることになる。また素子分離の方向へｎ型不純物が抜けて不純物濃度が低下するのを防ぐようにｐ型不純物を用いても良い。その場合には、ｎ型不純物拡散層は、素子分離側にｐ型不純物を含む構造になる。このようにｐ型不純物は、ｎ型不純物の拡散を防ぐ方向に形成し、拡散を抑制した後、ｎ型不純物に補償させて、ｎ＋Ｇｅだけが形成されるように用いることができる。 Furthermore, the p-type impurity layer may be formed not only to suppress the diffusion of the n-type impurity to the deep side in the substrate but also to suppress the diffusion in the lateral direction with the channel. In that case, the p-type impurity is contained on the channel side of the n-type impurity diffusion layer. In addition, a p-type impurity may be used to prevent the n-type impurity from escaping in the direction of element isolation to reduce the impurity concentration. In that case, the n-type impurity diffusion layer has a structure including the p-type impurity on the element isolation side. As described above, the p-type impurity can be formed in the direction to prevent the diffusion of the n-type impurity, and after suppressing the diffusion, can be used to compensate for the n-type impurity to form only n + Ge.
　また、今までの説明を、ｎとｐとを反対に置き換え、正負の符号を逆に取れば、ｎ＋層形成に限らず、ｐ＋層形成にも適用できる。ｎ型不純物がｐ型不純物よりも拡散が速ければ、ｐ型不純物はｎ型不純物の拡散抑制に利用できるし、反対にｐ型不純物がｎ型不純物よりも拡散が速ければ、ｎ型不純物はｐ型不純物の拡散抑制に利用できるからである。つまり、拡散の遅い不純物を利用して、拡散の速い不純物の拡散を抑制することで、拡散の速い不純物からなる浅くて高キャリア濃度の不純物拡散層の形成が可能になる。 Further, if n and p are replaced with each other and the positive and negative signs are reversed, the above description can be applied not only to the formation of n + layer but also to the formation of p + layer. If the n-type impurity diffuses faster than the p-type impurity, the p-type impurity can be used to suppress the diffusion of the n-type impurity. Conversely, if the p-type impurity diffuses faster than the n-type impurity, the n-type impurity It is because it can be utilized for the diffusion suppression of the type impurity. That is, by suppressing the diffusion of the fast diffusion impurity using the slow diffusion impurity, it is possible to form a shallow, high carrier concentration impurity diffusion layer made of the fast diffusion impurity.
　以上、具体例を参照しつつ本発明の実施形態について説明した。しかし、本発明はこれらの具体例に限定されるものではない。すなわち、これら具体例に、当業者が適宜設計変更を加えたものも、本発明の特徴を備えている限り、本発明の範囲に包含される。例えば、前述した各具体例が備える各要素およびその配置、材料、条件、形状、サイズなどは、例示したものに限定されるわけではなく適宜変更することができる。 The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. That is, those to which those skilled in the art appropriately modify the design of these specific examples are also included in the scope of the present invention as long as they have the features of the present invention. For example, each element included in each specific example described above and its arrangement, material, conditions, shape, size, and the like are not limited to those illustrated, and can be appropriately changed.
　また、前述した実施形態は、技術的に可能な限りにおいて組み合わせることができ、これらを組み合わせたものも本発明の特徴を含む限り本発明の範囲に包含される。 Also, the embodiments described above can be combined as far as technically possible, and combinations of these are included in the scope of the present invention as long as they include the features of the present invention.
１…ｐ型Ｇｅ基板、２…高濃度のＢが存在するＧｅ層、３…高濃度のＰが存在するＧｅ層
４…高濃度のＰとＢが共存するＧｅ層、５…ｐ型不純物を含むｎ＋Ｇｅ層、６…ｐ＋Ｇｅ層、
７…ｎ＋Ｇｅ層、８…ｐ型不純物を含むｎ＋Ｇｅ層、１０…ｐ型半導体層、１２…ゲート絶縁層、１４…ゲート電極、１６…コンタクト電極、１８…ｎ型不純物拡散領域、２０…ＳｉＯｘ薄膜、２２…ＧｅＯｘ薄膜、２４…Ｎｉ層、２６…ＮｉＧｅ層、１００…基板、１０２…ｐ型ウェル領域、１０４…ｎ型ウェル領域、１０６…素子分離層、１０８…ｎ型エクステンション領域、１１０…ｎ型ディープ領域、１１２…ｐ型エクステンション領域、１１４…ｐ型ディープ領域、１１６…ゲート絶縁膜、１１８…ゲート電極、１２０…ゲート絶縁膜、１２２…ゲート電極、１２４、１２６…ゲート側壁絶縁膜、１３０…層間絶縁膜、２０２…素子（半導体）領域、２０３…ゲート絶縁膜、２０４…ゲート電極、２０５…ソース・ドレイン領域、２０８…支持基板、２０９…埋め込み絶縁層、２１０…Ｇｅ層、２１１…ＧＯＩ基板、２１２…ＨｆＯ２膜 DESCRIPTION OF SYMBOLS 1 ... p-type Ge board | substrate, 2 ... Ge layer in which B of high concentration exists, 3 ... Ge layer in which P of high concentration exists 4 ... Ge layer in which P and B of high concentration coexist, 5 ... p-type impurity N + Ge layer, 6 ... p + Ge layer, including
7 n + Ge layer, 8 n + Ge layer containing p-type impurity, 10 p-type semiconductor layer, 12 gate insulating layer, 14 gate electrode, 16 contact electrode, 18 n-type impurity diffusion region DESCRIPTION OF SYMBOLS 20 ... SiOx thin film, 22 ... GeOx thin film, 24 ... Ni layer, 26 ... NiGe layer, 100 ... board | substrate, 102 ... p-type well area, 104 ... n-type well area, 106 ... element separation layer, 108 ... n-type extension area 110 ... n-type deep region, 112 ... p-type extension region, 114 ... p-type deep region, 116 ... gate insulating film, 118 ... gate electrode, 120 ... gate insulating film, 122 ... gate electrode, 124, 126 ... gate sidewall Insulating film 130: interlayer insulating film 202: element (semiconductor) region 203: gate insulating film 204: gate electrode 205: source / drain region , 208: supporting substrate, 209: embedded insulating layer, 210: Ge layer, 211: GOI substrate, 212: HfO 2 film

Claims (10)

  1. 　ｎ型とｐ型のうちの一方の導電型の半導体基板と、
    　前記半導体基板表面に選択的に設けられ、他方の導電型の一対の不純物拡散領域と、
    　前記一対の不純物拡散領域により挟まれた前記半導体基板上に設けられたゲート絶縁層と、
    　前記ゲート絶縁層の上に設けられたゲート電極と、
    を備え、前記不純物拡散領域の少なくとも一部は、前記一方の導電型を有し、かつ前記基板の不純物濃度より高い不純物濃度を有していることを特徴とする半導体装置。     a semiconductor substrate of one of n-type and p-type conductivity type;
    A pair of impurity diffusion regions of the other conductivity type selectively provided on the surface of the semiconductor substrate;
    A gate insulating layer provided on the semiconductor substrate sandwiched between the pair of impurity diffusion regions;
    A gate electrode provided on the gate insulating layer;
    And at least a part of the impurity diffusion region has the one conductivity type and has an impurity concentration higher than the impurity concentration of the substrate.
  2. 　前記半導体基板はＧｅを主成分とするｐ型半導体からなる半導体層を前記表面に有し、前記一対の不純物拡散領域は前記半導体層に設けられたｎ型不純物拡散領域であり、前記ｎ型不純物拡散領域の少なくとも一部は、前記ｐ型半導体のｐ型不純物濃度よりも高いｐ型不純物濃度を有していることを特徴とする請求項１に記載の半導体装置。 The semiconductor substrate has a semiconductor layer made of a p-type semiconductor mainly composed of Ge on the surface, and the pair of impurity diffusion regions are n-type impurity diffusion regions provided in the semiconductor layer, and the n-type impurity The semiconductor device according to claim 1, wherein at least a part of the diffusion region has a p-type impurity concentration higher than the p-type impurity concentration of the p-type semiconductor.
  3. 　前記ｎ型不純物拡散領域に含有される前記ｐ型不純物濃度は、前記ｎ型拡散領域の表面側よりも内奥側において高いことを特徴とする請求項２に記載の半導体装置。 3. The semiconductor device according to claim 2, wherein the concentration of the p-type impurity contained in the n-type impurity diffusion region is higher on the inner side than on the surface side of the n-type diffusion region.
  4. 　Ｇｅを主成分とする半導体層の表面に、高濃度の不純物拡散領域を形成する方法であって、
    　前記半導体層の表面に、ｎ型不純物およびｐ型不純物を導入する工程と、
    　前記ｎ型不純物とｐ型不純物を導入後、熱処理して、前記半導体層内にｎ型不純物拡散領域を形成する工程と、
    を含むことを特徴とする半導体装置の製造方法。     A method of forming a high concentration impurity diffusion region on the surface of a semiconductor layer containing Ge as a main component,
    Introducing an n-type impurity and a p-type impurity to the surface of the semiconductor layer;
    Heat treatment after introducing the n-type impurity and the p-type impurity to form an n-type impurity diffusion region in the semiconductor layer;
    A method of manufacturing a semiconductor device, comprising:
  5. 　前記ｎ型不純物およびｐ型不純物を導入する工程において、前記ｎ型不純物は、前記ｐ型不純物に比して、前記半導体層の表面側に形成することを特徴とする請求項４に記載の半導体装置の製造方法。 5. The semiconductor according to claim 4, wherein, in the step of introducing the n-type impurity and the p-type impurity, the n-type impurity is formed on the surface side of the semiconductor layer as compared to the p-type impurity. Device manufacturing method.
  6. 　前記ｎ型不純物およびｐ型不純物を導入する工程において、前記ｎ型不純物を導入した後に、前記ｐ型不純物を導入することを特徴とする請求項４に記載の半導体装置の製造方法。 5. The method of manufacturing a semiconductor device according to claim 4, wherein in the step of introducing the n-type impurity and the p-type impurity, the p-type impurity is introduced after the n-type impurity is introduced.
  7. 　前記ｎ型不純物拡散領域に含有される前記ｐ型不純物は、前記熱処理の温度における真性キャリア濃度よりも高いことを特徴とする請求項４に記載の半導体装置の製造方法。 5. The method for manufacturing a semiconductor device according to claim 4, wherein the p-type impurity contained in the n-type impurity diffusion region is higher than the intrinsic carrier concentration at the temperature of the heat treatment.
  8. 　前記半導体層はｐ型不純物を含有し、前記ｎ型不純物拡散領域の少なくとも一部は、前記半導体層のｐ型不純物濃度よりも高いｐ型不純物濃度を有することを特徴とする請求項４に記載の半導体装置の製造方法。 5. The semiconductor device according to claim 4, wherein the semiconductor layer contains a p-type impurity, and at least a part of the n-type impurity diffusion region has a p-type impurity concentration higher than the p-type impurity concentration of the semiconductor layer. Semiconductor device manufacturing method.
  9. 　前記熱処理において、前記ｎ型不純物が前記半導体層の外方に拡散することを特徴とする請求項４に記載の半導体装置の製造方法。 5. The method of manufacturing a semiconductor device according to claim 4, wherein in the heat treatment, the n-type impurity is diffused outward of the semiconductor layer.
  10. 　前記熱処理時に、前記半導体層の表面にＳｉ，ＳｉＧｅおよびＧｅの何れかから選ばれた半導体、ＧｅＯ，ＳｉＯ，ＳｉＯＮ，ＳｉＧｅＯ，ＧｅＯＮ，ＨｆＯｘ，ＬａＯｘ，ＡｌＯｘ，ＴｉＯｘ，ＴａＯｘおよびＺｒＯｘの何れかから選ばれた絶縁体、Ｎｉ，Ｆｅ，Ｃｏ，Ｐｄ，ＰｔおよびＣｕの何れかから選ばれた導電体のいずれかの薄膜が形成されていることを特徴とする請求項４に記載の半導体装置の製造方法。 At the time of the heat treatment, the surface of the semiconductor layer is selected from any of Si, SiGe and Ge, GeO, SiO, SiON, SiGeO, GeON, HfOx, LaOx, AlOx, TiOx, TaOx and ZrOx. 5. A semiconductor device according to claim 4, wherein a thin film of any one of a conductive material selected from any of an insulating material, Ni, Fe, Co, Pd, Pt and Cu is formed. Method.
PCT/JP2009/067423 2009-03-09 2009-10-06 Semiconductor device and method for manufacturing same WO2010103687A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009055267A JP2012099510A (en) 2009-03-09 2009-03-09 Semiconductor device and method of manufacturing the same
JP2009-055267 2009-03-09

Publications (1)

Publication Number Publication Date
WO2010103687A1 true WO2010103687A1 (en) 2010-09-16

Family

ID=42727988

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2009/067423 WO2010103687A1 (en) 2009-03-09 2009-10-06 Semiconductor device and method for manufacturing same

Country Status (2)

Country Link
JP (1) JP2012099510A (en)
WO (1) WO2010103687A1 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01166521A (en) * 1987-12-23 1989-06-30 Hitachi Ltd Compound semiconductor device
JPH0499037A (en) * 1990-08-06 1992-03-31 Fujitsu Ltd Manufacture of semiconductor device
JP2004289154A (en) * 2003-03-21 2004-10-14 Texas Instruments Inc Complementary implant for narrowing junction for ultra-shallow junction
JP2005347731A (en) * 2004-05-07 2005-12-15 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method therefor
JP2007335606A (en) * 2006-06-14 2007-12-27 Fujitsu Ltd Semiconductor device and manufacturing method thereof
JP2008041988A (en) * 2006-08-08 2008-02-21 Hiroshima Univ Germanium semiconductor device manufacturing method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01166521A (en) * 1987-12-23 1989-06-30 Hitachi Ltd Compound semiconductor device
JPH0499037A (en) * 1990-08-06 1992-03-31 Fujitsu Ltd Manufacture of semiconductor device
JP2004289154A (en) * 2003-03-21 2004-10-14 Texas Instruments Inc Complementary implant for narrowing junction for ultra-shallow junction
JP2005347731A (en) * 2004-05-07 2005-12-15 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method therefor
JP2007335606A (en) * 2006-06-14 2007-12-27 Fujitsu Ltd Semiconductor device and manufacturing method thereof
JP2008041988A (en) * 2006-08-08 2008-02-21 Hiroshima Univ Germanium semiconductor device manufacturing method

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
A.CHRONEOS ET AL.: "Enginnering the free vacancy and active donor concentrations in phosphorus and arsenic double donor-doped germanium", JOUNAL OF APPLIED PHYSICS, vol. 104, 2008, pages 113724-1 - 113724-4 *
S.CHAKRAVARTHI ET AL.: "Dopant diffusion modeling for heteroepitaxial SiGe/Si Devices", J. VAC. SCI. TECHNOL. B, vol. 24, no. 2, 2006, pages 608 - 612, XP012091369, DOI: doi:10.1116/1.2170095 *

Also Published As

Publication number Publication date
JP2012099510A (en) 2012-05-24

Similar Documents

Publication Publication Date Title
US7888747B2 (en) Semiconductor device and method of fabricating the same
US5972783A (en) Method for fabricating a semiconductor device having a nitrogen diffusion layer
CN102931222B (en) Semiconductor device and method for manufacturing the same
TWI321832B (en) Semiconductor device, and method for manufacturing the same
US6436747B1 (en) Method of fabricating semiconductor device
US6806534B2 (en) Damascene method for improved MOS transistor
JP3616514B2 (en) Semiconductor integrated circuit and manufacturing method thereof
US7985985B2 (en) Semiconductor device and method of fabricating the same
US6743704B2 (en) Method of manufacturing a semiconductor device
CA2660885A1 (en) Silicon-on-insulator (soi) junction field effect transistor and method of manufacture
WO2006007394A2 (en) Strained tri-channel layer for semiconductor-based electronic devices
US8362522B2 (en) Semiconductor device and method for manufacturing the same
US6734109B2 (en) Method of building a CMOS structure on thin SOI with source/drain electrodes formed by in situ doped selective amorphous silicon
US8816448B2 (en) Semiconductor device and manufacturing method thereof
US6432802B1 (en) Method for fabricating semiconductor device
US5296387A (en) Method of providing lower contact resistance in MOS transistor structures
JP4299866B2 (en) Manufacturing method of semiconductor device
KR101028982B1 (en) Semiconductor device and method for manufacturing the same
WO2006053338A2 (en) System and method for improved dopant profiles in cmos transistors
JP2009182109A (en) Semiconductor device
WO2010103687A1 (en) Semiconductor device and method for manufacturing same
WO2009084376A1 (en) Semiconductor device and process for producing the semiconductor device
JP3946910B2 (en) Manufacturing method of semiconductor device
KR100336572B1 (en) Method for forming semiconductor device with gate electrode using poly silicon-germanium
JP2000349039A (en) Manufacture of semiconductor device having shallow diffusion layer

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09841512

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09841512

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP