JP2012074427A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a shortage of bonding strength between columnar electrodes and solder terminals, and degradation in reliability without using an underfill material.SOLUTION: A semiconductor device comprises: a semiconductor substrate; a plurality of wiring lines provided on the semiconductor substrate; a plurality of solder terminals each connected to the plurality of wiring lines; and a resin layer covering at least portions of the plurality of wiring lines. An overcoat film, which covers at least around the solder terminals, is coated on the resin layer. The height of the overcoat film between the adjacent solder terminals is lower than that of the solder terminals.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  A so-called WLP (Wafer Level Package) in which a plurality of columnar electrodes are provided on a semiconductor substrate, a sealing resin is provided around the columnar electrodes, and solder terminals are provided on the columnar electrodes exposed without being covered with the sealing resin. ) Is known. By the way, if the periphery of the columnar electrode is simply covered with the sealing resin, there is a concern that the bonding strength between the solder terminal and the columnar electrode is insufficient. Further, there has been a problem that the reliability of the environmental test is impaired due to moisture absorption of the sealing resin itself and moisture absorption from the joint interface between the columnar electrode and the sealing resin. In recent years, when a semiconductor device is mounted on a circuit board, a technique for preventing the above-described problem has been developed by filling and curing a liquid underfill material between the semiconductor device and the circuit board ( For example, see Patent Document 1).

JP 2005-347362 A

By the way, in the semiconductor device as well as other electronic devices, it is desired to suppress the manufacturing cost. However, as described above, the use of the underfill material contributes to the increase in the manufacturing cost. .
An object of the present invention is to suppress insufficient bonding strength between a columnar electrode and a solder terminal and a decrease in reliability without using an underfill material.

In order to solve the above problems, according to one aspect of the present invention,
A semiconductor substrate;
A plurality of wirings provided on the semiconductor substrate;
A plurality of solder terminals respectively connected on the plurality of wirings;
A resin layer covering at least a part of the plurality of wirings,
An overcoat film covering at least the periphery of the solder terminal is coated on the resin layer, and the height of the overcoat film between the adjacent solder terminals is lower than the height of the solder terminal. A semiconductor device is provided.

In the semiconductor device, preferably
A columnar electrode is provided between the wiring and the solder terminal,
The wiring and the solder terminal are connected by the columnar electrode,
The overcoat film covers the entire solder terminal.
In the semiconductor device, preferably
A wiring board having a wiring pattern connected to the solder terminal and disposed opposite to the semiconductor substrate is provided.

According to another aspect of the invention,
The solder terminal on the resin layer of the semiconductor substrate, comprising: a plurality of wirings; a plurality of solder terminals respectively connected on the plurality of wirings; and a resin layer covering at least a part of the plurality of wirings. Overcoat film is formed to cover the periphery of
A method of manufacturing a semiconductor device is provided, wherein a height of the overcoat film between the adjacent solder terminals is lower than a height of the solder terminals.

Preferably in the manufacturing method of the semiconductor device,
A columnar electrode is formed under the solder terminal on the semiconductor substrate,
The overcoat film covers the entire solder terminal.
Preferably, in the method of manufacturing a semiconductor device, a wiring board having a wiring pattern is disposed opposite to the semiconductor substrate so that the wiring pattern and the solder terminal are connected.

  According to the present invention, lack of bonding strength between the columnar electrode and the solder terminal and a decrease in reliability can be suppressed without using an underfill material.

It is sectional drawing which shows the semiconductor device which concerns on embodiment of this invention. It is explanatory drawing for demonstrating the manufacturing method of the semiconductor device of this embodiment. It is explanatory drawing for demonstrating the manufacturing method of the semiconductor device of this embodiment. It is explanatory drawing for demonstrating the manufacturing method of the semiconductor device of this embodiment. It is explanatory drawing for demonstrating the manufacturing method of the semiconductor device of this embodiment. It is explanatory drawing for demonstrating the manufacturing method of the semiconductor device of this embodiment. It is explanatory drawing for demonstrating the manufacturing method of the semiconductor device of this embodiment. It is explanatory drawing for demonstrating the manufacturing method of the semiconductor device of this embodiment. It is explanatory drawing for demonstrating the manufacturing method of the semiconductor device of this embodiment. It is explanatory drawing for demonstrating the manufacturing method of the semiconductor device of this embodiment. It is explanatory drawing for demonstrating the manufacturing method of the semiconductor device of this embodiment. It is explanatory drawing for demonstrating the manufacturing method of the semiconductor device of this embodiment. It is explanatory drawing for demonstrating the manufacturing method of the semiconductor device of this embodiment. It is explanatory drawing for demonstrating the manufacturing method of the semiconductor device of this embodiment. FIG. 7 is a cross-sectional view showing a modification of the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view showing a modification of the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view showing a modification of the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view showing a modification of the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view showing a modification of the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view showing a modification of the semiconductor device of FIG. 1.

  The best mode for carrying out the present invention will be described below with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples.

  FIG. 1 is a cross-sectional view showing a semiconductor device 1 according to an embodiment of the present invention. The semiconductor device 1 includes a semiconductor substrate 11 made of silicon or the like, a plurality of connection pads 12 made of a conductive material such as metal, an insulating film 13 made of an insulating material such as silicon oxide or silicon nitride, and a protective film 14. , Wiring 15, columnar electrode 21, sealing resin 22, solder terminal 23, overcoat film 24, and the like.

On the surface of the semiconductor substrate 11, electronic circuits, connection pads 12, wirings for connecting these, and the like are formed.
The connection pad 12 is connected to the wiring on the semiconductor substrate 11. The insulating film 13 is formed on the surface of the semiconductor substrate 11 and covers electronic circuits and wirings.
The insulating film 13 is provided with an opening 13a for exposing the connection pad 12. As shown in FIGS. 1 and 2, the opening 13 a is smaller than the connection pad 12.

  A columnar electrode 21 is disposed on a part of the upper surface of the insulating film 13 via a protective film 14 and a wiring 15.

  A protective film 14 is formed on the upper surface of the insulating film 13. The protective film 14 can be made of a high-functional plastic material such as polyimide or polybenzoxazole (PBO), a plastic material such as epoxy, phenol, or silicon, or a composite material thereof.

  The protective film 14 is provided with an opening 14 a that exposes the connection pad 12. If the protective film 14 is a photosensitive resin, the openings 14a can be collectively formed on the semiconductor substrate 11 by coating, exposing, developing, and curing. The opening 14a can be formed by a laser, for example. As shown in FIG. 1, the opening 14a of the protective film 14 is smaller than the opening 13a of the insulating film 13, and the connection pad 12 and the protective film 14 are in close contact with each other at the outer periphery of the opening 14a.

  A wiring 15 is formed on a part of the upper surface of the protective film 14 and on the connection pad 12 exposed from the opening 14a. The wiring 15 is a lower layer, and includes an electroplating seed layer 16 serving as a nucleus for electrolytic plating of the upper layer, and an upper wiring layer 19 having a conductive material such as copper. The electroplating seed layer 16 is made of, for example, Ti, Ta, TiW or the like as an adhesion layer that enhances adhesion with the protective film 14, and TiN, TaN, or the like as a diffusion prevention layer. It is preferable to stack Cu or the like with a thickness of about 600 nm by sputtering or the like. A part of the seed layer 16 for electrolytic plating is connected to the connection pad 12 through the openings 13a and 14a. The wiring 15 is a wiring for electrically connecting the wiring of the electronic circuit provided on the semiconductor substrate 11 to the columnar electrode 21.

  A wiring layer 19 made of a conductive material such as copper is formed on the upper surface of the electroplating seed layer 16. The wiring layer 19 is thicker than the electroplating seed layer 16 and preferably has a thickness of, for example, 1 μm to 5 μm.

  The wiring 15, which is a laminate of the electroplating seed layer 16 and the wiring layer 19, connects the corresponding one or more connection pads 12 and the one or more columnar electrodes 21. The wirings 15 are arranged so as to be electrically insulated from other adjacent wirings 15.

  The end of the wiring 15 opposite to the connection pad 12 is a land. A columnar electrode 21 made of a conductive material such as copper is formed on the top surface of the land. The height of the columnar electrode 21 is about 10 to 70 μm, and is about 15 to 75 μm together with the thickness of the wiring 15. The side surface of the columnar electrode 21 is protected by a sealing resin 22 as a resin layer. A solder terminal 23 is provided on the top of the columnar electrode 21.

  An upper portion of the wiring 15 and the protective film 14 is filled with a sealing resin 22 except for a portion where the columnar electrode 21 is provided. The sealing resin 22 is made of, for example, a composite (composite material) of a thermosetting resin such as a thermosetting polyimide, an epoxy resin, or a phenol resin and a filler such as silica. However, a thermosetting resin containing no filler may be used.

  An overcoat film 24 made of an insulating resin is coated on the sealing resin 22 so as to cover the periphery of the solder terminal 23. Therefore, the top of the solder terminal 23 is exposed from the overcoat film 24. The overcoat film 24 is coated so as to have a shape that is recessed between adjacent columnar electrodes 21.

  Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS. Here, FIGS. 2 to 14 are cross-sectional views showing the semiconductor substrate 11 before dicing during manufacture.

First, as shown in FIG. 2, a connection pad 12 and an insulating film 13 are formed on a semiconductor substrate (semiconductor wafer) 11 before dicing. Next, as shown in FIG. 3, an electroplating seed layer 16 that covers the entire surface of the protective film 14 and the connection pads 12 is formed by a vapor deposition method such as sputtering.
Next, as shown in FIG. 4, a wiring resist 17 is formed except for a region where the wiring layer 19 is formed on the seed layer 16 for electrolytic plating.

Next, as shown in FIG. 5, a wiring layer 19 is deposited by electrolytic plating using the electrolytic plating seed layer 16 as a cathode in a portion where the wiring resist 17 is not formed.
Thereafter, as shown in FIG. 6, the wiring resist 17 is removed.

  Next, as shown in FIG. 7, after a dry film is laminated on the top surface of the seed layer 16 for electrolytic plating and the wiring layer 19 on the semiconductor substrate 11, an opening 20a having a predetermined cross-sectional shape is formed on the dry film. The resist 20 for the columnar electrode 21 is formed by patterning the dry film so that a large number are formed. The columnar electrode 21 is formed in the opening 20 a formed in the resist 20.

Next, as shown in FIG. 8, columnar electrodes 21 are deposited in the openings 20a of the resist 20 by electrolytic plating using the seed layer 16 for electrolytic plating as a cathode.
Next, as shown in FIG. 9, the resist 20 is removed.

Next, as shown in FIG. 10, the electroplating seed layer 16 in the region where the wiring layer 19 and the columnar electrode 21 are not formed is removed by soft etching, and the wiring layer 19 and the electroplating seed layer below the wiring layer 19 are removed. A wiring 15 which is a laminate with 16 is formed.
At this time, the surfaces of the wiring layer 19 and the columnar electrode 21 are also etched to the same extent as the thickness of the electroplating seed layer 16, but the wiring layer 19 and the columnar electrode 21 are compared with the electroplating seed layer 16. Since it is thick enough, it has no effect.

  Next, a disconnection of the wiring 15, the presence of foreign matter on the protective film 14 and the columnar electrode 21, and a wiring defect are confirmed by an appearance inspection. Next, by treating the surface of the protective film 14 with oxygen plasma, an impure layer on the surface is removed, a clean surface is exposed, and surface insulation is ensured.

  Next, as shown in FIG. 11, a sealing resin 22 that covers the top of the columnar electrode 21 is filled on the semiconductor substrate (semiconductor wafer) 11 by a printing method.

Next, as shown in FIG. 12, the upper surface of the columnar electrode 21 and the upper surface of the columnar electrode 21 are ground substantially simultaneously by grinding the sealing resin 22 from the upper surface with a grinder. Form. As a result, even if the columnar electrodes 21 are formed at nonuniform heights during electrolytic plating, they can be made substantially the same height. A region of the sealing resin 22 where the columnar electrode 21 is disposed becomes an opening 22a.
Next, the back surface of the semiconductor substrate (semiconductor wafer) 11 is ground and thinned.
Next, surface treatment is performed by light-etching the upper surface of the columnar electrode 21, and solder terminals 23 are provided as shown in FIG.
Thereafter, as shown in FIG. 14, an overcoat film 24 is coated on the upper portion of the sealing resin 22. At this time, the overcoat film 24 is coated so as to cover the periphery of the solder terminal 23 and to expose the top of the solder terminal 23. Furthermore, between the adjacent columnar electrodes 21, the overcoat film 24 is coated so as to be recessed. That is, the height of the overcoat film 24 between the adjacent solder terminals 23 is lower than the height of the solder terminals 23.
The semiconductor device 1 shown in FIG. 1 is completed by dicing after the overcoat film 24 is cured.

As described above, according to this embodiment, since the insulating overcoat film 24 covering the periphery of the solder terminal 23 is coated on the sealing resin 22, the solder terminal 23 and the columnar shape are covered by the overcoat film 24. The bonding strength with the electrode 21 can be increased. Further, since the overcoat film 24 is coated, moisture absorption of the sealing resin 22 itself and moisture absorption from the bonding interface between the solder terminal 23 and the columnar electrode 21 can be prevented. It can also be increased. As described above, it is possible to suppress insufficient bonding strength between the columnar electrode 21 and the solder terminal 23 and a decrease in reliability without using an underfill material.
Further, since the overcoat film 24 is coated, it is possible to suppress the flow of solder when the semiconductor device 1 is mounted on the mounting substrate, and it is also possible to prevent a short circuit between the melted solder terminals 23. is there. If short-circuiting between the solder terminals 23 is prevented in this way, board mounting with a fine pitch arrangement becomes possible.
Further, since the short circuit of the solder terminal 23 is prevented, the size of the solder terminal 23 itself can be increased. Thereby, the joint strength with the columnar electrode 21 and the joint strength with the mounting substrate can be improved, and various mechanical strength tests and environmental reliability tests can be further improved.
And since the diameter of the columnar electrode 21 can also be enlarged with the enlargement of the solder terminal 23, heat dissipation can also be improved. The malfunction of the semiconductor device 1 can be suppressed by improving the heat dissipation.

  In addition, since the overcoat film 24 is recessed between the solder terminals 23 of the adjacent columnar electrodes 21, the stress applied to the solder terminals 23 can be relaxed and the strength can be further increased as compared with the case of being flat. .

Note that the present invention is not limited to the above embodiment, and can be modified as appropriate.
For example, as in the semiconductor device 1A shown in FIG. 15, the overcoat film 24a may cover the entire solder terminal 23. If the overcoat film 24 a covers the entire solder terminal 23, the coating operation can be simplified as compared with the case where the overcoat film 24 is coated so as to expose the solder terminal 23. When the semiconductor device 1A is mounted on the mounting substrate, the overcoat film 24a is melted together with the solder terminals 23 by reflow heating. That is, since the solder terminal 23 is exposed from the overcoat film 24a at the time of mounting, mounting on the substrate becomes possible.
As shown in FIG. 16, the solder terminal 23 may be exposed by polishing the top portion of the overcoat film 24a and the solder terminal 23 before mounting. In this case, the height of the solder terminal 23 can be made uniform, and thinning at the time of mounting becomes possible.

  Further, in the above embodiment, the case where the overcoat film 24 is recessed between the solder terminals 23 of the adjacent columnar electrodes 21 has been described as an example. However, the overcoat as in the semiconductor device 11B shown in FIG. The film 24b may be flat. In this case, as indicated by the dotted line portion T shown in FIG. 17, the overcoat film 24b is flatly coated on the sealing resin 22 so as to cover the entire solder terminal 23, and after the overcoat film 24b is cured, the overcoat film 24b is coated. And the solder terminal 23 is polished. At the time of polishing, as shown in FIG. 18, it is preferable to adjust the polishing amount so that the height is in accordance with the specifications of the semiconductor device 1B.

Then, the semiconductor device 1B may further include a wiring substrate 40 disposed to face the semiconductor substrate 11 as shown in FIG. The wiring board 40 is provided with a wiring pattern 41 connected to the solder terminal 23. When the wiring substrate 40 is disposed opposite to the semiconductor substrate 11 so that the wiring pattern 41 and the solder terminal 23 are connected, the back surface of the semiconductor substrate 11 and the front surface of the wiring substrate 40 are flush with each other. Although FIG. 19 shows an example embedded in the wiring board 40, surface mounting may be used. Thus, if it is mounted on the wiring board 40, it can be repaired because it is a solder connection.
As in the semiconductor device 1C shown in FIG. 20, the solder terminal 23 is formed directly on the wiring 15, and the portion other than the solder terminal 23 forming portion is covered with a resin layer 42 such as polyimide resin or epoxy resin, and the columnar electrode 21 is covered. The structure which does not form may be sufficient.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 11 Semiconductor substrate 12 Connection pad 13 Insulating film 13a Opening 14 Protective film 14a Opening 15 Wiring 16 Seed layer for electroplating 21 Columnar electrode 22 Sealing resin (resin layer)
22a Opening 23 Solder terminal 24 Overcoat film 40 Wiring board 41 Wiring pattern 42 Resin layer

Claims (6)

A semiconductor substrate;
A plurality of wirings provided on the semiconductor substrate;
A plurality of solder terminals respectively connected on the plurality of wirings;
A resin layer covering at least a part of the plurality of wirings,
An overcoat film covering at least the periphery of the solder terminal is coated on the resin layer, and the height of the overcoat film between the adjacent solder terminals is lower than the height of the solder terminal. Semiconductor device. The semiconductor device according to claim 1,
A columnar electrode is provided between the wiring and the solder terminal,
The wiring and the solder terminal are connected by the columnar electrode,
The semiconductor device according to claim 1, wherein the overcoat film covers the entire solder terminal. The semiconductor device according to claim 1 or 2,
A semiconductor device comprising: a wiring board having a wiring pattern connected to the solder terminal and disposed opposite to the semiconductor substrate. The solder terminal on the resin layer of the semiconductor substrate, comprising: a plurality of wirings; a plurality of solder terminals respectively connected on the plurality of wirings; and a resin layer covering at least a part of the plurality of wirings. Overcoat film is formed to cover the periphery of
A method of manufacturing a semiconductor device, wherein a height of the overcoat film between adjacent solder terminals is lower than a height of the solder terminals. In the manufacturing method of the semiconductor device according to claim 4,
A columnar electrode is formed under the solder terminal on the semiconductor substrate,
The method of manufacturing a semiconductor device, wherein the overcoat film covers the entire solder terminal. In the manufacturing method of the semiconductor device according to claim 4 or 5,
A method of manufacturing a semiconductor device, comprising: arranging a wiring substrate having a wiring pattern opposite to the semiconductor substrate so that the wiring pattern and the solder terminal are connected.

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