JP5587702B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  Some semiconductor devices have a structure as shown in FIG. The electrode pad 112 of the semiconductor wafer 111 is provided, and an insulating layer 114 is provided on the surface covered with the protective insulating film 113 opening the electrode pad 112, and the insulating layer 114 corresponds to the central portion of the electrode pad 112. An opening 114a is provided in the portion. An electroplating seed layer 116 is provided on the surface of the insulating layer 114 and in the opening 114 a, and a wiring layer 119 is provided on the electroplating seed layer 116 to form a wiring 115. One end of the wiring 115 is connected to the electrode pad 112.

  A columnar electrode 121 is provided on the other end portion of the wiring 115, and the periphery of the columnar electrode 121 and the wiring 115 and the insulating layer 114 are sealed with a sealing layer 122. The top of the columnar electrode 121 is exposed from the sealing layer 122, and a solder terminal 123 is provided on the top of the columnar electrode 121. The semiconductor device 101 is connected to a circuit board (not shown) via a solder terminal 123 (see, for example, Patent Document 1).

JP 2008-218731 A

  By the way, in a semiconductor device, there may be a non-connection pad which is not used as a connection pad among a plurality of electrode pads. Here, the wiring connected to the connection pad has to be designed so as to bypass the non-connection pad so as not to leak current with the non-connection pad, and the layout of the wiring is limited.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, which have a high degree of freedom in wiring layout design and can prevent current leakage.

In order to solve the above problems, according to the first aspect of the present invention,
A semiconductor substrate;
A plurality of electrode pads made of a conductive material provided on one surface of the semiconductor substrate;
A protective insulating film made of an insulating material provided on one surface of the semiconductor substrate;
An insulating layer provided on the upper surface of the protective insulating film;
Wiring provided on the upper surface of the insulating layer;
An external connection electrode connected to the wiring,
The electrode pad is at least partially exposed by an opening provided in the protective insulating film and the insulating layer, and is covered with the first electrode pad connected to the wiring through the opening and at least the insulating layer. A second electrode pad that is not exposed,
The protective insulating film is provided with an opening at a position corresponding to the second electrode pad,
The insulating layer is formed by laminating a plurality of insulating films at least between the second electrode pad and the wiring, and a part of the wiring overlaps the second electrode pad through the plurality of insulating films. A semiconductor device is provided which is provided at a position.

According to a second aspect of the invention,
A protective insulating film and an insulating layer having an opening exposing at least a part of the first electrode pad are formed on one surface of the semiconductor substrate on which the first electrode pad and the second electrode pad are provided. And covering the second electrode pad with at least the insulating layer;
Forming a wiring connected to the first electrode pad through the opening on the upper surface of the insulating layer;
Forming an external connection electrode connected to the wiring,
An opening is provided at a position corresponding to the second electrode pad in the protective insulating film,
The insulating layer is formed by laminating the plurality of insulating films at a position corresponding to at least the second electrode pad, so that one of the wirings overlaps with the second electrode pad via the plurality of insulating films. A method for manufacturing a semiconductor device is provided.

  According to the present invention, it is possible to increase density and prevent current leakage.

1 is a plan view showing a semiconductor device 1 according to a first embodiment of the present invention. It is II-II arrow sectional drawing of FIG. 10 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device 1. FIG. 10 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device 1. FIG. 10 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device 1. FIG. 10 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device 1. FIG. 10 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device 1. FIG. 10 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device 1. FIG. 10 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device 1. FIG. 10 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device 1. FIG. 10 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device 1. FIG. 10 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device 1. FIG. 10 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device 1. FIG. 10 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device 1. FIG. 10 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device 1. FIG. FIG. 3 is an enlarged cross-sectional view in the vicinity of a non-connected pad 12nc of the semiconductor device 1. 1 is a cross-sectional view of a conventional semiconductor device 101. FIG.

  FIG. 1 is a plan view showing a semiconductor device 1 according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along arrow II-II in FIG. The semiconductor device 1 includes a semiconductor device wafer 10, a first insulating film 14A, a second insulating film 14B, a wiring 15, a columnar electrode 21, a sealing layer 22, a solder terminal 23, and the like.

The semiconductor device wafer 10 includes a semiconductor substrate 11 made of a semiconductor such as silicon, a plurality of electrode pads 12 made of a conductive material such as metal, a protective insulating film 13 made of an insulating material such as silicon oxide or silicon nitride, Is provided.
An electronic circuit is provided on the surface or inside of the semiconductor substrate 11.
The electrode pad 12 is connected to at least one of the electronic circuit of the semiconductor substrate 11 or the wiring connected to the electronic circuit of the semiconductor substrate 11, the electronic circuit of the semiconductor substrate 11, and the electronic circuit of the semiconductor substrate 11. A non-connected pad 12nc that is not connected to any of the connected wirings.
The protective insulating film 13 is formed on the surface of the semiconductor substrate 11 and covers electronic circuits and wirings.
The protective insulating film 13 is provided with an opening 13a that exposes the connection pad 12c of the electrode pad 12. The protective insulating film 13 covers the non-connecting pad 12nc. As shown in FIGS. 1 and 2, since the opening 13 a is smaller than the connection pad 12 c of the electrode pad 12, the periphery of the connection pad 12 c is covered with the protective insulating film 13.

On the upper surface of the protective insulating film 13, an insulating layer 14 including a first insulating film 14A and a second insulating film 14B is provided in this order.
The first insulating film 14A and the second insulating film 14B are made of a high-functional plastic material such as polyimide or polybenzoxazole (PBO), a plastic material such as epoxy, phenol, or silicon, or a composite material thereof. Can be used.

The first insulating film 14A is provided with an opening 14a that exposes the connection pad 12c. If the first insulating film 14 </ b> A is a photosensitive resin, the openings 14 a can be collectively formed on the semiconductor device wafer 10 by coating, exposing, developing, and main curing. The opening 14a can be formed by, for example, irradiating the first insulating film 14A at a position corresponding to the connection pad 12c with, for example, laser light after coating the first insulating film 14A on the entire surface. As shown in FIGS. 1 and 2, the opening 14a is smaller than the opening 13a of the protective insulating film 13, and the connection pad 12c and the first insulating film 14A are in close contact with each other on the outer peripheral side of the opening 14a.
Note that the opening 14a is not formed on the non-connecting pad 12nc, and the first insulating film 14A is also formed on the non-connecting pad 12nc via the protective insulating film 13.

  A second insulating film 14B is formed on the upper surface of the first insulating film 14A. The same material may be used for the first insulating film 14A and the second insulating film 14B, or different materials may be used.

The second insulating film 14B is provided with an opening 14b exposing the connection pad 12c at the same position as the opening 14a. The opening 14b can be formed in the same manner as the opening 14a.
Note that the opening 14b is not formed on the non-connecting pad 12nc, and the second insulating film 14B is also formed on the first insulating film 14A above the non-connecting pad 12nc.

  A wiring 15 is formed on the upper part of the connection pad 12c exposed from the openings 13a, 14a, and 14b and on a part of the upper surface of the second insulating film 14B. The wiring 15 is a lower layer, and includes an electroplating seed layer 16 serving as a nucleus for electrolytic plating of the upper layer, and an upper wiring layer 19 having a conductive material such as copper. The seed layer 16 for electrolytic plating is, for example, Ti, Ta, TiW or the like as an adhesion layer for improving the adhesion with the second insulating film 14B, and a diffusion prevention layer such as TiN or TaN as a thickness of about 200 nm. As the conductive layer, Cu or the like is preferably stacked with a thickness of about 600 nm by a sputtering method or the like. A portion of the electroplating seed layer 16 is connected to the connection pad 12c through the openings 13a, 14a, and 14b. The wiring 15 is a wiring for conducting an electronic circuit provided on the silicon substrate 11 to the columnar electrode 21.

  A wiring layer 19 made of a conductive material such as copper is formed on the upper surface of the electroplating seed layer 16. The wiring layer 19 is thicker than the electroplating seed layer 16 and preferably has a thickness of, for example, 1 μm to 5 μm.

The wiring 15, which is a laminate of the electroplating seed layer 16 and the wiring layer 19, connects the corresponding one or more connection pads 12 c and the one or more columnar electrodes 21. The wirings 15 are arranged so as to be electrically insulated from other adjacent wirings 15.
In order to increase the degree of integration, as shown in FIGS. 1 and 2, a part of the wiring 15 connected to the connection pad 12c is arranged at a position overlapping the non-connection pad 12nc. The non-connecting pad 12nc and the wiring 15 thereabove are insulated by a first insulating film 14A and a second insulating film 14B provided therebetween.

  The end portion of the wiring 15 opposite to the end portion connected to the connection pad 12c forms a land on the first insulating film 14A and the second insulating film 14B. A columnar electrode 21 made of a conductive material such as copper is formed on the top surface of the land. The diameter of the columnar electrode 21 is 50 to 500 μm. The height of the columnar electrode 21 is about 45 to 99 μm, and is about 50 to 100 μm together with the thickness of the wiring 15. The side surface of the columnar electrode 21 is protected by the sealing layer 22. A solder terminal 23 is provided on the top of the columnar electrode 21.

  The upper part of the wiring 15 and the second insulating film 14 </ b> B is filled with a sealing layer 22 except for a portion where the columnar electrode 21 is provided. The sealing layer 22 includes, for example, a composite (composite material) of a thermosetting resin such as a thermosetting polyimide, an epoxy resin, or a phenol resin and a filler such as silica. However, a thermosetting resin containing no filler may be used.

  Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS. Here, FIGS. 3 to 16 are cross-sectional views showing the semiconductor substrate 11 in the course of manufacture.

  First, as shown in FIG. 3, a photosensitive resin, which is a material for the first insulating film 14A, is applied to the surface of the semiconductor device wafer 10 before the dicing, which includes the electrode pads 12 and the protective insulating film 13 on the semiconductor substrate 11. Then, the first insulating film 14A is formed by exposure and development. At this time, an opening 14a is provided in the first insulating film 14A on the connection pad 12c. Next, as shown in FIG. 4, a photosensitive resin as a material for the second insulating film 14B is applied, and exposed and developed to form the second insulating film 14B. At this time, an opening 14b is provided in the second insulating film 14B on the connection pad 12c.

Next, as shown in FIG. 5, an electroplating seed layer 16 that covers the entire surface of the second insulating film 14B and the electrode pad 12 is formed by a vapor deposition method such as sputtering.
Next, as shown in FIG. 6, a wiring resist 17 is formed except for a region where the wiring layer 19 is formed on the seed layer 16 for electrolytic plating.

Next, as shown in FIG. 7, a wiring layer 19 is deposited on the portion where the wiring resist 17 is not formed by electrolytic plating using the electrolytic plating seed layer 16 as a cathode.
Thereafter, as shown in FIG. 8, the wiring resist 17 is removed.

  Next, as shown in FIG. 9, a dry film is attached to the upper surfaces of the electroplating seed layer 16 and the wiring layer 19 and patterned to form a resist 20 for the columnar electrode 21. Note that the resist 20 is provided with a plurality of openings 20 a in portions where the plurality of columnar electrodes 21 are formed.

Next, as shown in FIG. 10, columnar electrodes 21 are deposited in the openings 20a of the resist 20 by electrolytic plating using the seed layer 16 for electrolytic plating as a cathode.
Next, as shown in FIG. 11, the resist 20 is removed.

Next, as shown in FIG. 12, the wiring layer 19 and the electroplating seed layer 16 in the region where the columnar electrode 21 is not formed are removed by soft etching, and the wiring layer 19 and the electroplating seed layer below the wiring layer 19 are removed. A wiring 15 which is a laminate with 16 is formed.
At this time, the surfaces of the wiring layer 19 and the columnar electrode 21 are also etched to the same extent as the thickness of the electroplating seed layer 16, but the wiring layer 19 and the columnar electrode 21 are compared with the electroplating seed layer 16. Since it is thick enough, it has no effect.

  Next, the presence or absence of foreign matter on the semiconductor device wafer 10 is confirmed by visual inspection. Next, the surface of the second insulating film 14B is treated with oxygen plasma to remove foreign matters such as carbides on the surface.

  Next, as shown in FIG. 13, the sealing layer 22 that covers the columnar electrode 21 is formed on the semiconductor device wafer 10 by filling a resin that becomes the sealing layer 22 by a printing method.

Next, as shown in FIG. 14, the upper surface of the columnar electrode 21 and the sealing layer 22 are formed substantially flush by cutting the upper portion of the columnar electrode 21 while cutting the sealing layer 22 from the upper surface with a grinder. To do. As a result, even if the columnar electrodes 21 are formed at nonuniform heights during electrolytic plating, they can be made substantially the same height.
Next, a surface treatment is performed by light etching the upper surface of the columnar electrode 21, and a solder terminal 23 is provided as shown in FIG. Thereafter, the semiconductor device 1 shown in FIGS. 1 and 2 is completed by dicing.

  By the way, there may be a case where a minute pinhole is generated in the protective insulating film 13, the first insulating film 14A, and the second insulating film 14B. FIG. 16 shows a state in which minute pinholes 13b are formed in the protective insulating film 13 for some reason, and minute pinholes 14c and 14d are generated in the first insulating film 14A and the second insulating film 14B. It is an expanded sectional view near 12nc. As shown in FIG. 16, since the positions of the pinhole 13b and the pinholes 14c and 14d are stochastically shifted, the insulation between the wiring 15 (connection pad 12c) and the non-connection pad 12nc is maintained. Further, even if pinholes are formed in one or two layers of the protective insulating film 13, the first insulating film 14A, and the second insulating film 14B, insulation is maintained unless pinholes are formed in the remaining two or one layer. Be drunk.

  If the insulating film is a single layer, the electroplating seed layer 16 and the wiring layer 19 are formed in the pinhole, so that the wiring 15 (connection pad 12c) may be electrically connected to the non-connection pad 12nc. is there.

  On the other hand, in the present embodiment, since the first insulating film 14A and the second insulating film 14B are laminated, the protective insulating film 13, the first insulating film 14A, and the second insulating film 14B are assumed to be minute. Even if the pinholes 13b, 14c, and 14d are formed, it is considered that the pinholes 13b, 14c, and 14d are hardly formed at the same position. Further, even if the pinhole 14c is formed in the first insulating film 14A, as shown in FIG. 16, the pinhole 14c is filled with the second insulating film 14B formed later. Even if the pinhole 14d is formed in the second insulating film 14B and the seed layer 16 for electrolytic plating is formed in the pinhole 14d, the wiring 15 does not conduct with the non-connected pad 12nc because of the first insulating film 14A. . For this reason, the non-connecting pad 12nc and the wiring 15 can be stacked with the insulating layer 14 interposed therebetween, and the density of the wiring 15 can be increased.

In the above embodiment, the second insulating film 14B is formed on the entire upper surface of the first insulating film 14A. However, the present invention is not limited to this. For example, the second insulating film 14B may be partially formed only at a position overlapping the non-connecting pad 12nc. Alternatively, the first insulating film 14A may be partially formed only on the non-connecting pad 12nc, and the second insulating film 14B may be formed on the first insulating film 14A and the protective insulating film 13.
In the above embodiment, the insulating layer 14 is two layers, but may be a multilayer of three or more layers.
In the above embodiment, the opening 13a is provided in the protective insulating film 13 only at a position corresponding to the connection pad 12c. However, the opening 13a may be provided in both the connection pad 12c and the non-connection pad 12nc. Even in such a structure, the insulating property of the non-connecting pad 12 nc can be maintained by providing the plurality of insulating films 14 between the wiring 15.

DESCRIPTION OF SYMBOLS 1,101 Semiconductor device 10 Semiconductor device wafer 11, 111 Semiconductor substrate 12, 112 Electrode pad 13, 113 Protective insulating film 14, 114 Insulating layer 14A, 14B Insulating film 13a, 14a, 14b, 20a, 114a Opening 14c, 14d Pinhole 15, 115 Wiring 16, 116 Electroplating seed layer 17 Wiring resist 19, 119 Wiring layer 21, 121 Columnar electrode (external connection electrode)
22, 122 Sealing layer 23, 123 Solder terminal

Claims (4)

A semiconductor substrate;
A plurality of electrode pads made of a conductive material provided on one surface of the semiconductor substrate;
A protective insulating film made of an insulating material provided on one surface of the semiconductor substrate;
An insulating layer provided on the upper surface of the protective insulating film;
Wiring provided on the upper surface of the insulating layer;
An external connection electrode connected to the wiring,
The electrode pad is at least partially exposed by an opening provided in the protective insulating film and the insulating layer, and is covered with the first electrode pad connected to the wiring through the opening and at least the insulating layer. A second electrode pad that is not exposed,
The protective insulating film is provided with an opening at a position corresponding to the second electrode pad,
The insulating layer is formed by laminating a plurality of insulating films at least between the second electrode pad and the wiring, and a part of the wiring overlaps the second electrode pad through the plurality of insulating films. A semiconductor device provided at a position.   2. The semiconductor device according to claim 1, wherein the plurality of insulating films are made of a plastic material of polyimide or polybenzoxazole, an epoxy-based, phenol-based, or silicon-based plastic material, or a composite material thereof. A protective insulating film and an insulating layer having an opening exposing at least a part of the first electrode pad are formed on one surface of the semiconductor substrate on which the first electrode pad and the second electrode pad are provided. And covering the second electrode pad with at least the insulating layer;
Forming a wiring connected to the first electrode pad through the opening on the upper surface of the insulating layer;
Forming an external connection electrode connected to the wiring,
An opening is provided at a position corresponding to the second electrode pad in the protective insulating film,
The insulating layer is formed by laminating the plurality of insulating films at a position corresponding to at least the second electrode pad, so that one of the wirings overlaps with the second electrode pad via the plurality of insulating films. A method for manufacturing a semiconductor device, characterized in that a part is provided. Said plurality of insulating films, plastic material a polyimide or polybenzoxazole, or epoxy, phenolic, plastic material silicon, or according to claim 3, characterized in that formed using these composite materials A method for manufacturing a semiconductor device.

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