JP2012066136A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine that prevents false recognition of a winning state of game balls.SOLUTION: The game machine includes: a random number generating circuit GNR for storing on-information in a first storage part 60 when the level of a winning switch signal SG is significantly changed, and storing a counter counted value at the time in second storage parts 45 and 46; and an input port INP for receiving the winning switch signal SG. The game machine also includes: a first means for determining input data in the input port INP and storing the on-information in a third storage part EDG if the level of the winning switch signal SG is significantly changed; a second means for acquiring and temporarily storing the counter counted value stored in the second storage parts 45 and 46 on condition that the on-information is stored in the first storage part 60 after the first means is actuated; and a third means for executing a lottery process based on the temporarily stored counter counted value on condition that the on-information is stored in the third storage part EDG after the second means is actuated.

Description

  The present invention relates to a gaming machine such as a ball ball game machine or a slot machine that generates a big hit state by a lottery process caused by a game operation, and more particularly to a game machine that does not execute a lottery process due to a malfunction.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7-7-7, a big hit state is established, and the big winning opening is repeatedly opened to generate a profit state advantageous to the player.

  However, in actuality, whether or not the big hit state is determined in advance by the big hit lottery process executed at the time of winning the game ball, and the symbol display unit performs a symbol variation operation exclusively to enliven the player Yes. In the jackpot lottery process, for example, the output value of a random number generation circuit configured in hardware is used as a random number value for jackpot determination, and is compared with the jackpot winning value to determine whether or not the jackpot state.

  By the way, since the jackpot winning value is found when the game machine is acquired and the program is analyzed, a high security level is required for the random number generation circuit. Therefore, it is preferable to incorporate a random number generation circuit inside the one-chip microcomputer, and the applicant has separately proposed the circuit configuration (Patent Document 1).

  This random number generation circuit is configured to include a latch circuit (register) that stores the winning state when the detection switch SW provided at the symbol start port detects the passage of the game ball. In the present invention, the winning state of the game ball is grasped by interrupting the CPU by the output of the latch circuit or by periodically checking the output level of the latch circuit by the CPU.

Japanese Patent Application No. 2008-180326

  However, in the above invention, since the latch circuit that stores the winning state of the game ball operates at the edge of the switch signal, it cannot be said that there is no possibility that the latch circuit malfunctions due to the influence of noise or the like. If such a malfunction occurs, the big hit lottery process is executed even though it is not in the winning state, and an unreasonable big hit state may occur. There are also concerns about illegal acts aimed at unreasonable big hits.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a gaming machine that does not erroneously recognize a winning state of a game ball.

In order to achieve the above object, the present invention executes a lottery process based on a detection signal indicating the occurrence of a predetermined gaming operation, and determines whether or not to generate a gaming state advantageous to the player When the level of the detection signal changes significantly, the ON information is stored in the first storage unit and the counter count value at that time is stored in the second storage unit, and the detection signal is received. And a first means for storing ON information in the third storage section when the input signal of the input port is determined and the level of the detection signal changes significantly, and the first means functions. Then, on condition that the ON information is stored in the first storage unit, the second means that acquires and temporarily stores the counter count value stored in the second storage part functions. After that, ON information is stored in the third storage unit Preparative to the condition, it is configured to include a third means for executing the lottery processing based on the counter values stored temporarily a. The present invention is preferably applied to a ball game machine and a slot machine.

  The third means functions to store invalid data in the area where the counter count value is temporarily stored, while the lottery process does not cause a gaming state advantageous to the player depending on the invalid data. It is preferable to configure. Specifically, it is optimal that the lottery process is not executed depending on invalid data.

  The present invention is preferably configured to include a main process that is started when power is turned on, and a timer interrupt process that is periodically executed by interrupting the main process. The timer interrupt processing is realized.

  In addition, it is preferable that the detection signal is supplied to the random number generation circuit and the input port via a switching element that is in an ON state except when a predetermined game operation occurs. The output of the switching element is preferably supplied to a circuit board on which the random number generation circuit and the input port are mounted via a wiring cable and a connection connector. Here, it is optimal in terms of security that the output of the switching element is separately supplied to the circuit board through different wiring cables and connection connectors.

The first means should preferably acquire the input data a plurality of times in succession and determine the level change of the detection signal on the condition that the same data is acquired. Other effects can be eliminated. In addition, the first means performs an AND operation by logically inverting either one of the data acquired by the previous timer interrupt process and the current input data when determining the input data, so that the level of the detection signal is It is effective to automatically detect that has changed. The ON information stored in the first storage unit should be maintained as it is until the second means acquires the counter count value from the second storage unit. If such a configuration is adopted, the malfunction is eliminated. Effective above.

  The random number generation circuit includes a counter that is cyclically updated in response to a count clock, and a detection storage circuit that acquires and holds the counter in synchronization with an edge of the count clock when the detection signal is received. A latch circuit that acquires and holds the output data of the counter as the random number value in synchronization with an edge of the detection signal received from the detection storage circuit on condition that the control signal is at a permission level; and the latch circuit And a control circuit that changes the control signal from a permission level to a prohibition level after obtaining the random number value.

  In the present invention, after the latch circuit acquires the output data of the counter, the control circuit changes the control signal from the permission level to the prohibition level. Therefore, even if the detection signal vibrates, the counter output data is repeatedly acquired. There is no fear of being done. It is preferable that when the CPU acquires the random number value held by the latch circuit, the control circuit returns the control signal of the prohibited level to the permitted level. By adopting such a configuration, it is possible to eliminate the overwriting of the detection signal only by the CPU quickly acquiring the output data of the counter.

Preferably, the counter updates the counter value in synchronization with the first edge of the count clock, while the detection storage circuit holds the detection signal in synchronization with the second edge of the count clock. . In this case, the counter value acquired by the latch circuit is a stable value after the update is reliably completed.

  The counting clock is preferably generated by dividing the basic clock by two. In this case, since the duty ratio of the counting clock is 50%, the operation of the latch circuit is further stabilized.

  The present invention includes a logic gate that receives the detection signal output from the detection memory circuit and the control signal output from the control circuit, and the output of the logic gate is supplied to the latch circuit. Is preferred. Preferably, the control circuit is constituted by a flip-flop that receives the output signal of the logic gate by inverting the logic and stores a fixed value in synchronization with an edge of the output signal. The fixed value is typically at the H level, and the flip-flop is preferably a D-type flip-flop.

  The control circuit is preferably provided with a clear terminal for forcibly resetting its output value. The clear terminal is preferably activated when the CPU acquires the output data of the counter held by the latch circuit. The clear terminal of the logic circuit is preferably activated at the time of power reset together with the clear terminal of the counter and the detection memory circuit.

  The output data of the latch circuit is effectively acquired by the CPU via a buffer circuit having three states. The three states are an H level state, an L level state, and an open state (Hi impedance state).

According to the above-described present invention, since the contents of the first storage unit and the third storage unit are checked for duplication, the winning state of the game ball is virtually not misidentified.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated in detail the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a circuit block diagram which shows the principal part of the one-chip microcomputer of a main control part. It is a circuit block diagram which shows a random number generation circuit. It is a time chart which shows operation | movement of a random number generation circuit. It is a flowchart explaining the system reset process of a main control part. It is a flowchart explaining the timer interruption process of a main control part. It is a flowchart explaining the principal part of a timer interruption process in detail. It is a circuit diagram explaining another Example.

  Examples of the present invention will be described in detail below. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side rather than from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. An upper plate 8 for storing game balls for launch is mounted on the front plate 7, and a lower plate 9 for storing game balls overflowing from or extracted from the upper plate 8 and a launch handle 10 are mounted at the bottom of the front frame 3. And are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, the game board 5 is provided with a guide rail 13 formed of a metal outer rail and an inner rail in an annular shape, and a liquid crystal color display DISP is provided at the approximate center of the game area 5a inside. Has been placed. In addition, at a suitable place in the game area 5a, a symbol start opening 15, a big winning opening 16, a plurality of normal winning openings 17 (four on the right and left of the large winning opening 16), and a gate 18 serving as a passing opening are arranged. Yes. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The liquid crystal display DISP is a device that variably displays a specific symbol related to a big hit state and displays a background image and various characters in an animated manner. This liquid crystal display DISP has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. And, in the special symbol display parts Da to Dc, a reach effect is executed that expects a big hit state to be invited, or in the special symbol display parts Da to Dc and the surroundings, a notice effect that informs the result of the success / failure is executed. Is done.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time, and the lottery extracted at the time when the game ball passes through the gate 18 is extracted. The stop symbol determined by the random number for use is displayed and stopped.

For example, the symbol start port 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws 15a. When the stop symbol after fluctuation of the normal symbol display unit 19 displays a winning symbol, it is opened and closed. The claw 15a is opened only for a predetermined time or until a predetermined number of game balls are detected.

  When a game ball wins the symbol start port 15, the display symbols of the special symbol display portions Da to Dc change for a predetermined time and are determined based on the lottery result corresponding to the winning timing of the game ball to the symbol start port 15. Stop at the stop symbol. In addition, in special symbol display parts Da-Dc and its circumference, a notice effect may be performed between a series of symbol effects.

  The big winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward, but when the stop symbol after the symbol change of the special symbol display portions Da to Dc is a big hit symbol such as “777”, the “big hit game” Is started, and the opening / closing plate 16a is opened.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol of the special symbols, a privilege that the game after the end of the special game is in a high probability state is given.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. A dashed line in the figure mainly indicates a DC voltage line.

As shown in the figure, this pachinko machine GM is provided with a power supply board 20 that receives AC 24V and outputs various DC voltages, system reset signals (power reset signals) SYS, and the like, and a main control board 21 that plays a central role in game control operations. And an effect control board 22 that executes a lamp effect and a sound effect based on the control command CMD received from the main control board 21, and a liquid crystal that drives the liquid crystal display DISP based on the control command CMD ′ received from the effect control board 22. The control board 23, the payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21 and paying out the game ball, and the game ball is fired in response to the player's operation. The launch control board 25 is mainly configured.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. Further, the control command CMD ′ output from the effect control board 22 is transmitted to the liquid crystal control board 23 via the effect interface board 27, and the control command CMD ″ output from the main control board 21 is set to the main board relay board 28. Is transmitted to the payout control board 24 via.

  The main control board 21, the effect control board 22, the liquid crystal control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Accordingly, the circuits mounted on the control boards 21 to 24 and the operations realized by the circuits are collectively referred to as a function. In this specification, the main control unit 21, the effect control unit 22, and the liquid crystal control unit 23 are used. , And the payout control unit 24. All or part of the effect control unit 22, the liquid crystal control unit 23, and the payout control unit 24 is a sub-control unit.

  By the way, the pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and the new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, and a frame relay board 32, and these circuit boards are Each is fixed in place on the front frame 3. On the other hand, on the back of the game board 5, a main control board 21, an effect control board 22, and a liquid crystal control board 23 are fixed together with a liquid crystal display DISP and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 28 through the connection connector C2, and is connected to the power supply relay board 30 through the connection connector C3. The main board relay board 28 outputs the system reset signal SYS, the RAM clear signal DEL, the voltage drop signal, the backup power supplies BAK, DC12V, and DC32V received from the power board 20 to the main controller 21 as they are. Similarly, the power supply relay board 30 also outputs the system reset signal SYS received from the power supply board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The production interface board 27 outputs the received system reset signal SYS to the production control unit 22 and the liquid crystal control unit 23 as they are.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and the system reset signal SYS, the RAM clear signal DEL, the voltage drop signal, the backup power supply, which are received by the main control unit 21. BAK is received directly along with other power supply voltages.

  Here, the system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V is turned on to the power supply board 20, and the one-chip microcomputers of the respective control units 21 to 24 by this power supply reset signal. The other IC elements are reset in power supply.

RAM clear signal DEL received from power supply board 20 by main control unit 21 and payout control unit 24
Is a signal that determines whether or not to initialize all areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24, and is a value corresponding to the ON / OFF state of the initialization switch SW operated by the staff have.

  The voltage drop signal received from the power supply board 20 by the main control unit 21 and the payout control unit 24 is a signal indicating that the AC power supply 24V has started to drop. By receiving this voltage drop signal, each control unit 21, In 24, a necessary termination process is started prior to a power failure or business termination. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 25 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  On the other hand, the effect control unit 22 and the liquid crystal control unit 23 are not provided with the power supply backup function described above. However, as described above, the system reset signal SYS is commonly supplied to the effect control unit 22 and the liquid crystal control unit 23 via the power relay board 30 and the effect interface board 27, and other controls are performed. The power supply reset operation is realized at a timing substantially synchronized with the units 21 and 24.

  As illustrated, the main control unit 21 transmits a control command CMD "to the payout control unit 25 via the main board relay board 28, while the payout control unit 25 receives a prize ball indicating a payout operation of the game ball. A count signal and a status signal CON relating to an abnormality in the payout operation are received, and the status signal CON includes, for example, a replenishment out signal, a payout shortage error signal, and a lower plate full signal.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 29. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The switch signal includes a winning switch signal SG transmitted from the symbol start port 15 to the main control unit 21.

  FIG. 4 illustrates a part of the internal configuration of the one-chip microcomputer 21 </ b> A of the main control unit 21. Here, the portion that receives the winning switch signal SG from the detection switch SW of the symbol start port 15 via the game board relay board 29 is mainly shown.

As illustrated, the one-chip microcomputer 21A includes a CPU equivalent to Z80CPU (Zilog), a counter timer circuit CTC equivalent to Z80CTC (counter timer circuit), RO
An M and RAM memory circuit, a watchdog timer WDT, a random number generation circuit GNR, and an input port INP are mainly incorporated.

  The winning switch signal SG from the symbol start port 15 is supplied to the random number generation circuit GNR of the one-chip microcomputer 21A and the input port INP via the buffer circuit BUF arranged on the game board relay board 29. Yes. Here, the winning switch signal SG is supplied to the input port INP through the external wiring of the one-chip microcomputer 21A. However, from the viewpoint of crime prevention, the winning switch signal SG is supplied to the input port INP through the internal wiring of the one-chip microcomputer 21A. Preferably it is supplied.

In any case, not only the symbol start port 15 but also a switch signal from the prize winning port 16 and the detection switch of the gate 18 is supplied to the input port INP. For convenience of explanation, in this embodiment, it is assumed that a total of 8-bit switch signals including an error detection switch are supplied to the input port INP.

  As shown in the figure, the buffer circuit BUF has an open collector type output section, and the input side is pulled up to 12V and the output side is pulled up to 5V. When the game ball passes through the symbol start port 15 and enters a winning state, the buffer circuit BUF outputs a winning switch signal SG as a positive logic ON signal. That is, in this embodiment, the output transistor Tr of the buffer circuit BUF is normally in an ON state and is configured to be in an OFF state when a game ball is won.

  Therefore, for example, even if an illegal player removes the connector CN and supplies the power supply voltage 5V to the signal line of the winning switch signal SG, the winning switch signal SG in the ON state cannot be generated. Conversely, when the output transistor of the buffer circuit BUF is normally in an OFF state and is turned ON when a game ball is won, the connector CN is disconnected and the signal line of the winning switch signal SG is connected to the ground. As a result, the winning switch signal SG in the ON state can be generated, which may cause a security problem.

  The random number generation circuit GNR detects that the winning switch signal SG is in an ON state and holds a detection content, a counter that is updated at high speed in response to the counting clock Φ, and the winning switch signal is ON. And a random value register for holding the counter value at the moment when the state is reached.

  FIG. 5 is a circuit diagram specifically showing the random number generation circuit GNR. As illustrated, the random number generation circuit GNR includes a first flip-flop 41 that receives a clock pulse having a frequency f at a clock terminal CK, a second flip-flop 42 that receives a Q-bar output of the first flip-flop at a clock terminal CK, Two counters 43 and 44 that receive a Q output of one flip-flop and execute a counting operation; first and second latch circuits 45 and 46 that receive the outputs of the first and second counters 43 and 44, respectively; First and second buffer circuits 47 and 48 disposed between the two latch circuits 45 and 46 and the CPU data bus, and a winning storage circuit HIT for storing the ON state of the winning switch signal SG as a winning detection signal DET And it is composed around. The clock pulse is supplied from the outside of the one-chip microcomputer 21A or is supplied from the counter timer circuit CTC built in the one-chip microcomputer 21A.

  The winning memory circuit HIT is mainly composed of a third flip-flop 60, first and second AND gates 61 and 62, a NOT gate 63, and a third buffer circuit 64.

  In this embodiment, the third flip-flop 60 and the third buffer circuit 64 of the winning memory circuit HIT realize a latch register that stores the ON state (winning detection signal DET) of the winning switch signal SG. The first and second latch circuits 45 and 46 and the first and second buffer circuits 47 and 47 constitute a random value register as a whole.

  The first to third flip-flops 41, 42, and 60 are all formed of D-type flip-flops. When a signal supplied to the clock terminal CK rises, data at the D input terminal at that time is stored. And output to the Q output terminal. When an L level signal is supplied to the clear terminal CLR, the Q output is forcibly set to the L level, while the Q bar output is set to the H level.

  Since the power reset signal SYS output from the power supply board 20 is directly supplied to the clear terminals CLR of the first and second flip-flops 41 and 42, the Q output terminal is automatically set to the L level when the power is turned on. It becomes.

  The first flip-flop 41 has its Q-bar output fed back to its D input terminal. Therefore, the first flip-flop 41 functions as a divide-by-2 circuit for the clock pulse with the frequency f, and the clock pulse with the frequency f / 2 is output from the Q output terminal with a duty ratio of 50%. In this embodiment, this clock pulse becomes the count clock Φ supplied to the first counter 43. It should be noted that the logically inverted count clock Φbar is output from the Q bar output terminal of the first flip-flop 41.

  The second flip-flop 42 receives the winning switch signal SG at the D input terminal. The clock terminal CK receives a logically inverted count clock Φbar. Therefore, the winning switch signal SG is stored and output to the Q output terminal at the timing when the counting clock Φ bar rises. This output signal (latch signal) LT is supplied to the winning memory circuit HIT.

  The two counters 43 and 44 are binary counters having 8-bit output terminals Q0 to Q7. The first counter 43 receives the count clock Φ output from the first flip-flop 41 at the clock terminal CK, and the second counter 44 receives the Q7 output of the first counter at the clock terminal CK and executes the count operation. is doing. Therefore, the two counters 43 and 44 output any numerical value of 0000H to FFFFH updated in synchronization with the rising edge of the count clock Φ. Here, H means a hexadecimal number.

  Since the power reset signal SYS output from the power supply board 20 is directly supplied to the clear terminals CLR of the counters 43 and 44, the outputs of the counters 43 and 44 are automatically reset to 0000H when the power is turned on. The

  The first and second latch circuits 45 and 46 are configured to be equivalent to, for example, 74825, and include eight D-type flip-flops. When a signal supplied to the clock terminal CK of the latch circuits 45 and 46 rises, each 8-bit data supplied from the counters 43 and 44 at that time is stored and output as a random value RND. As illustrated, the output of the first AND gate 61 is supplied to the clock terminal CK.

The first and second buffer circuits 47 and 48 are general-purpose bus buffers equivalent to 74244 or the like. When the L level chip select signals CS1 and CS2 are received from the OE (output enable) terminal from the CPU, the latch circuit 45 is provided. , 46 received from each 8-bit data (random value RN
D) is output. As shown, the chip select signal CS2 is supplied to the input terminal of the second AND gate 62 together with the OE terminal of the buffer circuit 48. The buffer circuits 47 and 48 are tristate buffers, and when the OE terminal is at the H level, the output terminal is in the HiZ state.

  The Q output of the second flip-flop 42 and the Q-bar output of the third flip-flop 60 are supplied to the input terminal of the first AND gate 61 constituting the winning memory circuit HIT. The Q output of the second flip-flop 42 is a latch signal LT, and the Q-bar output of the third flip-flop 60 is a control signal CTL. Note that the latch signal LT and the control signal CTL are pulled up to the H level.

The output of the first AND gate 61 is supplied to the clock terminal CK of the first and second latch circuits 45 and 46, and is also supplied to the clock terminal CK of the third flip-flop 60 via the NOT gate 63. Yes. When a signal received at its clock terminal CK rises, the latch circuits 45 and 46 and the third flip-flop 60 perform a latch operation for storing data supplied to each input terminal therein. Therefore, the latch circuits 45 and 46 execute the latch operation at the rising timing of the output signal of the first AND gate 61, while the third flip-flop 60 executes the latch operation at the falling timing of the output signal of the first AND gate 61. To do. However, since the inverted latch signal LT bar is supplied to the clock terminal CK of the third flip-flop 60 via the NOT gate 63, the third flip-flop 60 is slightly delayed from the latch operation of the latch circuits 45 and 46. Latch operation.

  An H level voltage Vcc is fixedly supplied to the D input terminal of the third flip-flop 60. The Q output of the third flip-flop 60 is supplied to the buffer circuit 64. The Q output of the third flip-flop 60 means the winning detection signal DET.

  The buffer circuit 64 has a circuit configuration equivalent to that of a bus buffer such as 74244. When the L-level chip select signal CS3 is received from the CPU at the OE terminal, the 1-bit data (winning detection) received from the third flip-flop 60 is received. Signal DET). Note that the buffer circuit 64 is also a three-state buffer.

  A chip select signal CS2 and a power reset signal SYS are supplied to the input terminal of the second AND gate 62. The output of the second AND gate 62 is supplied to the clear terminal CLR of the third flip-flop 60. Therefore, when either or both of the chip select signal CS2 and the power reset signal SYS become L level, the Q output of the third flip-flop 60 becomes L level and the Q bar output becomes H level.

  However, the power reset signal SYS is constantly at the H level after the game machine has started to operate normally, and the chip select signal CS2 is H except for the data read timing at which the data in the buffer circuit 48 is acquired by the CPU. Is a level. Accordingly, the Q-bar output (control signal CTL) of the third flip-flop 60 is maintained at the H level even after the third flip-flop 60 is cleared to the H level when the power is turned on.

  In such an initial state, when the winning switch signal SG is turned on, the Q bar output of the third flip-flop 60 changes to L level at the timing when the latch signal LT falls, and until the data read timing of the buffer circuit 48, Maintain that state. On the other hand, after the Q bar output (control signal CTL) of the third flip-flop 60 returns to the H level at the data read timing of the buffer circuit 48, the H level is maintained.

  FIG. 6 is a time chart showing waveforms of respective parts of the random number generation circuit GNR. As shown in FIGS. 6A and 6B, the count values of the counters 43 and 44 are continuously updated in synchronization with the rise of the count clock Φ. The first counter 43 generates the lower 8 bits of the random value RND, and the second counter 44 generates the upper 8 bits of the random value RND.

  When the game ball passes through the symbol start port 15 during the counter value updating operation, the winning switch signal SG falls to the L level after rising to the H level (ON state). The winning switch signal SG is supplied to the main controller 21 via the buffer circuit BUF (see FIG. 4).

  Since the winning switch signal SG is supplied to the D input terminal of the second flip-flop 42, the winning switch signal SG is stored in the second flip-flop 42 at the timing when the counting clock Φ bar rises, It is output to the Q output terminal. This output signal is supplied as a latch signal LT to the winning memory circuit HIT (see FIGS. 6C to 6E).

In this embodiment, the winning switch signal SG is not used as a latch signal as it is, but the winning switch signal SG is shaped by the count clock Φ bar to be the latch signal LT. Therefore, even if ringing occurs at the rise or fall of the winning switch signal SG, such a vibration component is automatically absorbed by the counting clock Φ bar.

  The latch signal LT output from the second flip-flop 42 is supplied to the clock terminals CK of the two latch circuits 45 and 46 via the input terminal of the first AND gate 61. Therefore, if the control signal CTL supplied to the first AND gate 61 is at the H level, the output data of the counters 43 and 44 is acquired as the random value RND by the latch circuits 45 and 46 at the rising timing of the latch signal. . As shown in FIG. 6 (h), since the control signal CTL is at the H level at the normal timing, the random number value RND is acquired by the latch circuits 45 and 46 corresponding to the winning switch signal SG. .

  However, in this embodiment, the latch circuits 45 and 46 are operated at the rising timing of the count clock Φ bar, rather than operating the latch circuits 45 and 46 at an arbitrary timing when the winning switch signal SG is generated. The count clock Φ bar has a duty ratio of 50%, and its rising timing coincides with the falling timing of the counting clock Φ. Since the counters 43 and 44 are updated at the rising timing of the counting clock Φ, according to the configuration of the present embodiment, the counter 43 is accurately delayed by 1/2 cycle from the update timing of the counters 43 and 44. , 44 stable output data is latched.

  On the other hand, if the latch circuit is operated at random timing, or if the counter update timing and the latch operation timing are not sufficiently separated, an unreasonable counter value during the update may be acquired. There is sex.

  By the way, the latch signal LT is logically inverted at the NOT gate 63 and supplied to the clock terminal CK of the third flip-flop 60 (see FIG. 6F). Therefore, the Q output of the third flip-flop 60 becomes H level at the falling timing of the latch signal LT. This H level can be recognized by the CPU via the buffer circuit 64 as well as the winning detection signal DET indicating that the winning switch signal SG is turned on.

  When the winning detection signal DET becomes H level, the Q bar output of the third flip-flop 60 becomes L level. The Q-bar output of the third flip-flop 60 is supplied to the first AND gate 61 as the control signal CTL. However, since the control signal CTL becomes L level, the latch signal LT is changed to H level again after that. Even if it rises, the latch circuits 45 and 46 do not latch. Therefore, for example, even if ringing occurs at the fall of the winning switch signal SG, the circuit is not affected.

  As will be described later, the CPU acquires data in the buffer 64 every 2 mS and determines whether or not the winning detection signal is at the H level. When the winning detection signal becomes H level, the CPU accesses the buffer 47 and the buffer 48 in this order, and the random number values (16-bit length) latched in the latch circuits 45 and 46 every 8 bits. To get to. That is, the chip select signals CS1 and CS2 are set to the L level in this order only by this data read timing.

  When the chip select signal CS2 becomes L level, the output of the second AND gate 62 changes to L level, so that the Q bar output of the third flip-flop 60 changes from L level to H level, and the control signal CTL becomes H level. Return to level. Therefore, thereafter, the latch signal LT is generated corresponding to the winning switch signal SG, and a new counter value (random number value) is latched in the latch circuits 45 and 46.

As described above, in the random number generation circuit GNR of the embodiment, once the counter values (random number value RND) of the counters 43 and 44 are latched by the latch circuits 45 and 46, the CPU
As long as the random number value RND is not obtained via 7, 48, for example, even if the winning switch signal SG changes, the winning detection signal DET is not generated. Therefore, even if ringing occurs in the winning switch signal SG or the latch signal LT, there is no possibility that the winning detection signal DET is generated twice.

  As described above, in the present embodiment, the winning circuit is not permitted until the random number value RND is acquired by the CPU after the random number value RND is latched by the latch circuits 45 and 46. Therefore, there is a possibility that a problem may occur when the game balls win continuously. However, the CPU checks the winning detection signal DET every 2 mS. If the winning detection signal DET is ON, the CPU immediately acquires the random value RND via the buffers 47 and 48. There is no risk of harm. That is, it is not possible for a game ball to win continuously at a time interval of about 2 mS if the moving speed of the game ball is taken into consideration.

  Further, when the random number value RND is acquired, the winning detection signal DET automatically returns to the OFF level, so that an erroneous determination does not occur in the next check process.

  Next, an outline of a program of the main control unit 21 that controls the game operation in an integrated manner will be described. 7 to 9 are flowcharts showing a control program of the main control unit 21. The control program of the main control unit 21 includes a system reset process (FIG. 7) that is activated based on restoration or input of the power supply voltage, and a maskable timer interrupt process (FIG. 8 (FIG. 8 ( a)).

  Hereinafter, the system reset processing program (main processing) will be described with reference to FIG. The main process is started when the initialization switch SW is turned off and the power is turned on, such as when recovering from a power failure, and when the game hall is opened, the initialization switch SW is turned on. There is a case where the power source is turned on by being operated. Note that, due to the runaway control program, the watchdog timer WDT may be activated and the CPU may be forcibly reset.

  In any case, the Z80 CPU first sets itself to the interrupt disabled state (ST1) and sets to the interrupt mode 2 (ST2). Further, the value of the stack pointer SP in the CPU is initialized to the final address of the stack area (ST3), and the values of internal registers including each part of the one-chip microcomputer are initialized (ST4).

  Subsequently, the RAM clear signal DEL is acquired from the input port (ST5). The RAM clear signal DEL is a signal for determining whether or not to initialize all areas of the built-in RAM of the one-chip microcomputer 21A, and has a value corresponding to the ON / OFF state of the initialization switch SW operated by the staff. Have.

  Next, the level of the RAM clear signal is determined (ST6). If it is assumed that the RAM clear signal is in the ON state, the entire area of the built-in RAM is cleared to zero (ST10). Therefore, the value of the backup flag BFL set in the process of step ST37 in FIG. 8B becomes zero together with other checksum values.

Next, a power-on command for notifying that the RAM area has been cleared to zero is output (ST11), and the CTC that outputs the interrupt signal INT for starting the timer interrupt operation (FIG. 8A) is initialized ( ST12). Then, with the CPU set to the interrupt disabled state (ST13), update processing is executed for various counters (ST14), and then the CPU is returned to the interrupt enabled state and the process returns to step ST13. Note that the counter updated in step ST14 includes an out symbol counter, but this out symbol counter is
This is a counter for determining what kind of out-of-game is produced when the result of the big win lottery processing in the special symbol processing (ST27) in FIG.

  Returning to the determination process in step ST6, the RAM clear signal is in the OFF state when the CPU is forcibly reset by the watchdog timer WDT or when the CPU is restored from the power failure state. In such a case, the content of the backup flag BFL is determined following the determination in step ST6 (ST7). The backup flag BFL is data indicating that the operation of the power supply monitoring process of FIG. 8B has been executed. In this embodiment, the backup flag BFL is set to 5AH in the process of step ST37 when the power is turned off. It is cleared to zero in the process of step ST33 after the power is restored.

  When the power is turned on or when recovering from a power failure, the content of the backup flag BFL is 5AH. However, if the program goes into a runaway state for some reason and a CPU reset operation is caused by the watchdog timer, the backup flag BFL = 00H. Therefore, when BFL ≠ 5AH (normally BFL = 00H), the process proceeds from step ST7 to step ST10 to return the operation of the gaming machine to the initial state.

  On the other hand, if the backup flag BFL = 5AH, a checksum operation for calculating a checksum value is executed (ST8). Here, the checksum operation is an 8-bit addition operation for the work area of the built-in RAM. When the checksum value is calculated, the calculation result is compared with the stored value at the SUM address in the RAM (ST9).

  In the SUM address, the checksum value by the same checksum calculation is stored in the power supply monitoring process (FIG. 8B) executed when the voltage drops (ST38). The stored calculation results are maintained by a backup power source together with other data in the built-in RAM. Therefore, the two should be matched by the determination in step ST9.

  However, if the checksum calculation (ST38) cannot be executed when the power is turned off, or if it can be executed, the data in the work area will be damaged until the checksum calculation (ST8) of the main process is executed. In such a case, the determination result in step ST9 is inconsistent. If data corruption is detected due to a discrepancy between the determination results, the process proceeds to step ST10, RAM clear processing is executed, and the operation of the gaming machine is returned to the initial state. On the other hand, if it is determined in step ST9 that the checksum value obtained by the checksum calculation (ST8) matches the stored value at the SUM address, the process proceeds to step ST12.

  Next, a timer interrupt processing program (FIG. 8A) that is started every 2 mS while interrupting the main processing described above will be described. When the timer interrupt occurs, the power supply monitoring process is immediately executed without saving the CPU register (ST20). This is because the timing at which the timer interrupt process is started is fixed immediately after step ST15.

  In the power supply monitoring process (ST20), the level of the voltage drop signal supplied from the power supply board 20 is determined. The specific processing content will be described later. When the power monitoring process (ST20) ends, the value of the winning counter RG used in the lottery operation in the normal symbol process (ST26) is updated (ST21). Note that the random value RND for jackpot determination used in the lottery operation in the special symbol process (ST27) is generated by the random number generation circuit GNR in FIG. 5, and is not updated in the process of step ST21.

When the winning random number update process (ST21) ends, a timer subtraction process is performed for the timer that manages the time of each gaming operation (ST22). The timer to be subtracted here is mainly used for managing the opening time of the electric tulip and the special winning opening and other game effect times.

  Subsequently, ON / OFF signals of various switches including the winning detection switch of the symbol start opening 15 and the big winning opening 16 are inputted, and the ON / OFF signal level and its rising state are stored in the work area (ST23). . FIG. 9A is a flowchart showing the switch input process (ST23) in detail.

  First, 8-bit data is continuously input twice from the input port INP (FIG. 4) of the one-chip microcomputer 21A (ST50 to ST51). Then, this process (ST50 to ST51) is repeated until the same data is continuously acquired (ST52). Therefore, even if ringing occurs in various switch signals including the winning switch signal SG, the input data is correctly acquired at the stage where the vibration has subsided.

  In this way, when the same data is continuously acquired, the input data is stored in the B register of the CPU (ST53). As described above, in this embodiment, since all the 8-bit data is significant data, mask processing or the like is unnecessary.

  Next, the data of the LVL address storing the ON / OFF state of the switch signal (8 bits) at the time of the previous interrupt processing is acquired in the A register of the CPU and the bit is inverted (ST54). Then, the switch signal acquired this time and an AND operation are executed and stored in the A register of the CPU (ST55). As a result, the previous acquired data (address LVL) and the current acquired data (B register) are compared, and the bit changed from “0” to “1” in the 8-bit data of the A register. Only becomes “1”. A bit that is “1” indicates that the switch signal corresponding to the bit has risen.

  Therefore, the value of the B register of the CPU is newly stored in the LVL address, and the value of the A register is stored in the EDG address (ST56). Therefore, thereafter, only by referring to the EDG address, the switch signal rising from the L level to the H level can be grasped at the time of the current interrupt processing.

  When the switch input process (ST23) as described above is completed, an error management process is performed (ST24). The error management process includes a determination as to whether an abnormality has occurred inside the device, such as whether or not the supply of game balls has stopped or the game balls are clogged.

  Next, after executing the management process based on the prize ball counting signal received from the payout control unit 24 (ST25), the normal symbol process is performed (ST26). The normal symbol processing means determination as to whether or not to operate an ordinary electric accessory such as an electric tulip. Specifically, when it is determined that the game ball has passed through the gate based on the switch input result in step ST23, the winning counter RG updated in the random number updating process (ST21) is compared with the winning winning value. Done. If the comparison result is a winning state, the operation mode is changed to the winning operation mode. In addition, if it is a hit, processing for the operation of a normal electric accessory such as an electric tulip is performed.

Subsequently, special symbol processing is performed (ST27). The special symbol process is a determination as to whether or not a special electric accessory such as the special prize opening 16 is operated, and the main part thereof is as shown in FIG. 9B. First, it is determined whether or not the third flip-flop 60 of the random number generation circuit GNR holds an H level winning detection signal DET (latch flag). Specifically, 8-bit data is acquired from the third buffer circuit 64 (ST60), and the bit corresponding to the latch flag is determined (ST61). When it is determined that the winning detection state is established, a 16-bit random number value RND is acquired every 8 bits from the buffers 47 and 48 of the random number generation circuit GNR and stored in the TEMP address and the TEMP + 1 address ( ST62). Note that at the stage when the upper 8 bits of the random number value RND are acquired, the winning detection signal DET returns to the L level, and the control signal CTL returns to the H level (see FIG. 6).

  Next, the data of the EDG address is determined to determine whether or not the bit corresponding to the winning switch signal SG is “1” (ST63). As described above, in the switch input process, data of the input port INP is acquired (ST50 to ST51), and whether or not the winning switch signal SG rises is stored in the EDG address (ST56). Therefore, when it is determined that the winning switch signal SG has not risen according to the stored contents of the EDG address, the big hit lottery process (ST66) is skipped.

  On the other hand, if it is determined that the winning switch signal SG rises according to the stored contents of the EDG address, 16-bit data below the TEMP address is copied to the LOT address and the LOT + 1 address (ST64). Then, invalid data for the big hit lottery is stored at the TEMP address and the TEMP + 1 address. Here, the invalid data is data in which the big hit lottery process is skipped even if it is used as a random value for the big hit lottery. For simplicity, the invalid data may be lost data that does not become a big hit state even if it is used for the big hit lottery as a random value.

  Next, the big hit lottery process is executed using the 16-bit data stored after the LOT address as the random number value RND (ST66). Although not shown in the drawing, if the lottery result is a winning state, the operation mode is changed to a big hit operation mode. In addition, if it is a big hit, processing for the operation of special electric accessories such as a big prize opening is performed.

  After such special symbol processing (ST27), the lighting operation of the LEDs managed by the main control unit 21 is advanced (ST28), and the solenoid drive processing for realizing the opening / closing operation of the electric tulip, the big prize opening, etc. is executed. Later (ST29), the CPU is returned to the interrupt permission state EI and the timer interrupt is finished (ST30). As a result, the process returns from the interrupt process routine to the infinite loop process (FIG. 7) of the main process, and the process of step ST17 is executed.

  As described above, in this embodiment, the winning switch signal SG is double checked, and even if the winning detection signal DET is garbled due to noise or the like, an unreasonable big hit state occurs. There is nothing. Even if the data input process (ST50 to ST51) repeated twice does not eliminate the adverse effects such as ringing, an unreasonable big hit state does not occur. Hereinafter, these points will be confirmed based on FIG.

  In the normal case, No. 1 in FIG. 1 or No. As shown in FIG. 4, the H / L level (ON / OFF state) of the winning detection signal DET acquired in the process of step ST60 correctly matches the contents of the EDG address stored in the process of step ST56. Therefore, at such a normal time, for example, when the winning detection signal DET (latch flag) is ON, the random value RND is acquired below the TEMP address (ST62), and after the random value RND is copied below the LOT address (ST64). ), The jackpot lottery process is executed based on the random number value RND copied below the LOT address (ST66).

  Further, when the winning detection signal DET (latch flag) is OFF at the normal time, the process of step ST62 is skipped, and then the big win lottery process is skipped by the determination of step ST63.

Next, No. 9 in FIG. Consider 2 abnormal situations. In this case, the winning detection signal DET
Is determined to be in the OFF state, the process of step ST62 is skipped. Therefore, the data below the TEMP address remains invalid data, and no significant data is stored.

  Thereafter, in the determination of step ST63, since the corresponding bit is in the ON state, the processes of steps ST64 to ST66 are executed. However, since invalid data is stored below the TEMP address, invalid data copied below the LOT address is used for the big hit lottery process (ST66), and the big hit lottery is performed due to the invalidity of the random number value RND. Processing is skipped. Therefore, No. 1 in FIG. No adverse effect occurs at the time of 2 abnormalities.

  Subsequently, No. 9 in FIG. Consider 3 abnormal times. In this case, since it is erroneously determined that the winning detection signal DET is in the ON state, the random value RND is stored in the TEMP address (ST62). However, in the determination of step ST63, since it is determined that the winning switch signal SG has not risen, the big hit lottery process (ST66) is not executed, and no adverse effects occur. After that, normally No. If the state 4 occurs, the data below the TEMP address is updated at that stage, and the big hit lottery process (ST66) is executed based on the data.

  By the way, since there is a time lag between the execution timing of the switch input process (ST23) and the execution timing of the special symbol process (ST27), the winning switch signal SG is in the OFF state during the switch input process (ST23). In addition, at the time of special symbol processing (ST27), the winning switch signal SG may be turned on. However, in this embodiment, since the determination result of the switch processing (ST23) that has been executed first is determined after the determination of the latch flag (winning detection signal DET) (see ST61 and ST63), there is no problem. Absent.

  That is, in this case, since the latch flag (winning detection signal DET) to be determined after the switch input process (ST23) is in the ON state at the first timer interruption, the random number value is passed through the path from ST61 to ST62. RND is stored in the TEMP address. However, since the winning switch signal is still in the OFF state during the switch input process, the timer interrupt process ends through the process of step ST63. At the time of this timer interruption, the latch flag (winning detection signal DET) returns to the OFF state at the timing when the random number value RND is acquired below the TEMP address (ST62) (see FIG. 6 (g)).

  Therefore, at the next timer interruption, the process of step ST62 is skipped through the route of ST60 → ST61 → ST63. Thereafter, the random number value RND stored below the TEMP address at the previous timer interruption is copied below the LOT address, and the big hit lottery process is executed based on the random value RND (ST66). For this reason, the time difference between the execution timing of the switch input process (ST23) and the execution timing of the special symbol process (ST27) does not cause any adverse effect.

  Next, the power supply monitoring process (ST20) shown in FIG. In the power supply monitoring process (ST20), first, a voltage drop signal supplied from the power supply board 20 is acquired through an input port (not shown) (ST31), and it is determined whether it is an abnormal level (ST32). If it is not an abnormal level, the abnormal number counter and the backup flag BFL are cleared to zero and the process is terminated (ST33).

On the other hand, if the voltage drop signal is at an abnormal level, the abnormal number counter is incremented (+1) (ST34), and it is determined whether the counting result exceeds the upper limit value MAX (ST35). This is because the data acquired from the input port may be garbled due to the influence of noise or the like, and the abnormal level is continuously set for a predetermined number of times (for example, upper limit MAX = 2). In the case of maintaining, it is determined that the AC power source is actually shut off.

  As described above, in this embodiment, the subsequent backup processing is not started immediately even when the power is turned off, and the operation start timing is delayed by MAX × 2 mS. However, (1) The power supply drop signal is not a drop in the DC power supply voltage, but a drop in the AC DC voltage is detected. (2) The DC power supply voltage is maintained for a while after the AC power supply is shut off by a large capacity capacitor. (3) The power supply monitoring process is repeated at a high speed (every 2 ms), and (4) the backup process is extremely simple and finishes quickly, so there is virtually no adverse effect.

  By the way, as a result of the determination in step ST35, if the count value of the abnormal number counter coincides with the upper limit value MAX, the abnormal number counter is cleared to zero (ST36), and then 5AH is set to the backup flag BFL (ST37). Next, the same calculation as in step ST7 of the main routine is executed for the same work area (work area), and the calculation result is stored (ST38). The operation to be executed is typically an 8-bit addition operation.

  Thereafter, the one-chip microcomputer 21A is set in a RAM access prohibited state (ST39), and output data of all output ports is cleared (ST40). As a result, unreasonable data is prevented from being transmitted to the payout control unit 24 that starts the same type of power supply monitoring process later than the main control unit 21. When the above backup processing is completed, the generation of the interrupt signal INT is prohibited by the setting processing for CTC, and the DC power supply voltage is lowered while repeating the infinite loop processing (ST41). At this timing, the CPU is originally in an interrupt disabled state (see ST30). However, in this embodiment, an interrupt signal from the CTC is used to eliminate as much as possible the possibility of malfunction due to a drop in power supply voltage. INT output is also prohibited.

  Although the embodiments of the present invention have been specifically described above, the specific description content is not intended to limit the present invention, and various modifications can be made. For example, in the description of the embodiment, a configuration in which the value of the latch flag is checked by the timer interrupt process (flag sense method) is adopted, but a configuration in which the winning detection signal DET is directly supplied to the interrupt terminal of the CPU may be employed.

  In order to increase the security level, it is preferable to provide two transmission paths between the game board relay board 29 and the main control board 21 and transmit the same winning switch signal through different paths.

  FIG. 10 shows this configuration, and the game board receives the winning switch signal SG supplied to the random number generation circuit GNR and the winning switch signal SG supplied to the input port INP through different connectors CN1 and CN2. It is received from the relay board 29. Therefore, for example, even if the connector CN1 is removed and an illegal board is attached between the game board relay board 29 and the connector CN1, the illegal big hit lottery process cannot be executed.

  In the case of the illustrated example, in order to generate an illegal winning switch signal SG, it is necessary to turn on / off the switch circuit S1 by remote operation, for example, after cutting the original signal line. Even if nothing is done, the winning switch signal SG supplied to the input port INP cannot be turned ON. Even if the switch circuit S2 is provided on the upstream side of the disconnection point and is turned ON / OFF in synchronization with the switch circuit S1, the illegal action will not succeed because the transistor of the buffer circuit BUF is ON. . In this regard, if the transistor of the buffer circuit BUF is steadily turned off, illegal actions cannot be effectively excluded (see FIG. 10B).

GM gaming machine RND counter count value SG detection signal 60 first storage unit 45, 46 second storage unit GNR random number generation circuit INP input port EDG third storage unit

In order to achieve the above object, the present invention executes a lottery process based on a detection signal indicating the occurrence of a predetermined gaming operation, and determines whether or not to generate a gaming state advantageous to the player When the level of the detection signal changes significantly, the ON information is stored in the first storage unit and the counter count value at that time is stored in the second storage unit, and the detection signal is received. And a first means for storing ON information in the third storage unit when the input signal of the input port is determined and the level of the detection signal changes significantly, and the first means has functioned. Then, on condition that the ON information is stored in the first storage unit, the second unit that acquires and temporarily stores the counter count value stored in the second storage unit functions. After that, ON information is stored in the third storage unit. On condition Rukoto, is configured to have a third means for executing the lottery processing based on the counter values stored temporarily, said random number generating circuit and said input port, ON is steadily While the L level detection signal is steadily received via the switching element that maintains the operation, the switching element is turned OFF to receive the H level detection signal when a predetermined gaming operation occurs. It is configured. The present invention is preferably applied to a ball game machine and a slot machine.

Claims (10)

A gaming machine that executes a lottery process due to a detection signal indicating the occurrence of a predetermined gaming action and determines whether or not to generate a gaming state advantageous to the player,
When the level of the detection signal changes significantly, ON information is stored in the first storage unit, and a random number generation circuit that stores the counter count value at that time in the second storage unit, and an input port that receives the detection signal Provided,
A first means for storing ON information in a third storage unit when the input data of the input port is determined and the level of the detection signal is significantly changed;
A second means for acquiring and temporarily storing the counter count value stored in the second storage section on the condition that ON information is stored in the first storage section after the first means functions;
And a third means for executing the lottery process based on the counter count value temporarily stored on the condition that ON information is stored in the third storage unit after the second means functions. A gaming machine characterized by being configured. The third means functions to store invalid data in an area where the counter count value is temporarily stored,
The gaming machine according to claim 1, wherein the lottery process is configured so that a gaming state advantageous to a player does not occur depending on the invalid data. A main process that is started when the power is turned on, and a timer interrupt process that is periodically executed by interrupting the main process,
The gaming machine according to claim 1 or 2, wherein the first to third means are realized in the timer interrupt processing.   The gaming machine according to any one of claims 1 to 3, wherein the detection signal is supplied to the random number generation circuit and the input port via a switching element that is in an ON state except when a predetermined gaming operation occurs.   The gaming machine according to claim 4, wherein an output of the switching element is supplied to a circuit board on which the random number generation circuit and the input port are mounted via a wiring cable and a connection connector.   The gaming machine according to claim 5, wherein the output of the switching element is separately supplied to the circuit board through different wiring cables and connection connectors. The gaming machine according to any one of claims 1 to 6, wherein the first means determines the level change of the detection signal on the condition that the input data is continuously acquired a plurality of times and the same data is acquired. . The first means changes the level of the detection signal by logically inverting either one of the data acquired by the previous timer interrupt process and the current input data when determining the input data. The gaming machine according to claim 3, which automatically detects the occurrence.   9. The gaming machine according to claim 1, wherein the ON information stored in the first storage unit is maintained as it is until the second means acquires the counter count value from the second storage unit. The random number generation circuit includes:
A counter that is cyclically updated in response to a counting clock;
Upon receipt of the detection signal, a detection memory circuit that acquires and holds it in synchronization with the edge of the counting clock;
A latch circuit that acquires and holds the output data of the counter as the random number value in synchronization with an edge of the detection signal received from the detection storage circuit on condition that the control signal is at a permission level;
The gaming machine according to claim 1, further comprising: a control circuit that changes the control signal from a permission level to a prohibition level after the latch circuit acquires the random number value.