JP2017060855A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of changing security operation in response to an operation state and uniformizing hardware design of a memory circuit.SOLUTION: A main control section includes: forbiddance setup means that sets a start address and an ending address at discretionary timing to set an access forbiddance area of RAM; access control means CTL capable of controlling an access to the RAM access forbiddance area into a permission state or a forbiddance state; first abnormality reset means 51 that, in a state where the access is controlled into the forbiddance state by the access control means, detects the access to the RAM forbiddance area to forcibly reset CPU; second abnormality reset means 50 for detecting that an area other than an RAM use area is accessed to forcibly reset the CPU; and write control means capable of uniformly controlling data write operation to the RAM into the forbiddance state or the permission state.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a gaming machine that generates a big hit state by a lottery process caused by a gaming operation, and more particularly to a gaming machine that can realize a desired security operation without hindering an original performance control operation.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passing of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display time is changed in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7-7-7, a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a game state is determined by a jackpot lottery executed on the condition that a game ball has won at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing.

JP 2005-304632 A

  By the way, since the winning value of the big win lottery can be determined by analyzing the control program of the gaming machine, for example, there is a concern about an illegal act of trying to execute an illegal program that can arbitrarily generate a winning state.

  Thus, various countermeasures have been conventionally proposed (for example, Patent Document 1), but a configuration that can appropriately change the security operation in accordance with the operation state of the gaming machine is not known. Also, there is no known effective method that can unify the hardware design of the memory circuit for a plurality of types of gaming machines.

  The present invention has been made in view of the above-described problems, and can change the security operation in accordance with the operating state of the gaming machine, so that the hardware design of the memory circuit can be defined for a plurality of types of gaming machines. An object is to provide a gaming machine that can be unified.

  In order to achieve the above-described object, the present invention executes main lottery processing based on a detection signal indicating the occurrence of a predetermined game action, and determines whether or not to generate a game state advantageous to the player. The main control unit includes a ROM that stores a control program and data in a nonvolatile manner, a RAM that stores work data in a volatile manner, and a CPU that operates based on the control program in the ROM. And a one-chip microcomputer having a built-in configuration, setting a start address and an end address at an arbitrary timing to set a RAM access prohibited area, and access to the access prohibited area Access control means capable of controlling the access state to a permitted state or a prohibited state, and a prohibited area of the RAM in a state where access is controlled to the prohibited state by the access control means First abnormal reset means for forcibly resetting the CPU upon detection of access, second abnormal reset means for forcibly resetting the CPU upon detection of access outside the ROM use area, and RAM And a write control means capable of uniformly controlling the data write operation in a prohibited state or a permitted state.

  The prohibition setting means of the present invention can set the RAM access prohibition area at an arbitrary timing, and the access control means of the present invention can control access to the access prohibition area to a permitted state or a prohibited state. The degree of freedom in design and control operations is high, and as a result, game control can be optimized.

  Specifically, for multiple types of gaming machines, a RAM area that is not used or prohibited can be set for each model, so the RAM memory capacity can be standardized and the hardware design of the memory circuit can be simplified. it can. In addition, regardless of the type of gaming machine, the access prohibited area can be changed during the game operation, or the access to the access prohibited area can be changed to the prohibited / permitted state, so that the control operation can be simplified. .

  For example, when the same data is written in a series of RAM areas, there are a large number of access-prohibited areas discretely existing on the way only by temporarily changing the access to the access-prohibited area to a permitted state. However, regardless of the type of gaming machine, it can be processed at once with a simple program. In this type of gaming machine, since the storage capacity of the ROM is limited, such simple processing is extremely effective in saving the storage area of the ROM.

  The access control means should preferably control access to the access prohibited area of the RAM to a permitted state or a prohibited state in a state where the second abnormality reset means functions. When such a configuration is adopted, access to the non-use area of the ROM is monitored regardless of the access permission to the access prohibition area, so that the security level is not particularly lowered.

  The write control means should preferably control the data write operation uniformly in a prohibited state while permitting the data read operation from the RAM. By adopting such a configuration, it is possible to continue a limited control operation while preventing destruction of the RAM.

  The main control unit is configured to include backup means for maintaining the stored contents of the RAM even after the power is shut off. When the power is shut off, after the predetermined data is stored in the RAM, the data write operation is uniformly performed by the write control means. It is preferable that access is prohibited and access to the access prohibited area is permitted by the access control means. If such a configuration is adopted, even if the CPU is in a runaway state due to a drop in the power supply voltage, the CPU is not reset and the stored contents of the RAM are not rewritten, so the stored contents of the RAM are destroyed. It will not be done.

  In addition, the main control unit has a backup unit that maintains the stored contents of the RAM even after the power is turned off. When the power is turned on, after the initial setting process of each part of the one-chip microcomputer is completed, the write control unit writes the data. It is preferable that the operation is uniformly permitted, and access to the access prohibited area is permitted by the access control means. By adopting such a configuration, for example, even when a jump-on access prohibited area or a non-use area is provided in the RAM, for example, the entire area can be cleared at once.

  Preferably, the one-chip microcomputer is provided with a minimum value register capable of storing the start address of the prohibited RAM area and a maximum value register capable of storing the end address of the prohibited RAM area. An appropriate address value is set in the minimum value register and the maximum value register.

  The write control means preferably includes a logic circuit that controls a predetermined signal transmitted through the control bus among the address bus output from the CPU to the RAM and the control bus. Note that the gaming machine of the present invention is typically a bullet ball game machine or a revolving game machine.

  As described above, according to the present invention, noise countermeasures and illegal countermeasures can be changed according to the operating state of the gaming machine, and the hardware design of the memory circuit can be standardized for a plurality of types of gaming machines.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a circuit diagram which shows the internal circuit of a one-chip microcomputer. It is a block diagram which shows the internal structure of an abnormal reset circuit. It is a time chart which shows memory access operation of CPU. It is a flowchart explaining the main process of a main control part. It is a flowchart explaining the timer interruption process of a main control part.

  Examples of the present invention will be described in detail below. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side rather than from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. An upper plate 8 for storing game balls for launch is mounted on the front plate 7, and a lower plate 9 for storing game balls overflowing from or extracted from the upper plate 8 and a launch handle 10 are mounted at the bottom of the front frame 3. And are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, the game board 5 is provided with a guide rail 13 formed of a metal outer rail and an inner rail in an annular shape, and a liquid crystal color display DISP is provided at the approximate center of the game area 5a inside. Is arranged. In addition, at a suitable place in the game area 5a, a symbol start opening 15, a big winning opening 16, a plurality of normal winning openings 17 (four on the right and left of the large winning opening 16), and a gate 18 serving as a passing opening are arranged. Yes. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The liquid crystal display DISP is a device that variably displays a specific symbol related to a big hit state and displays a background image and various characters in an animated manner. This liquid crystal display DISP has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. And, in the special symbol display parts Da to Dc, a reach effect is executed that expects a big hit state to be invited, or in the special symbol display parts Da to Dc and the surroundings, a notice effect that informs the result of the success / failure is executed. Is done.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time, and the lottery extracted at the time when the game ball passes through the gate 18 is extracted. The stop symbol determined by the random number for use is displayed and stopped.

  For example, the symbol start opening 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws 15a. When the stop symbol after the fluctuation of the normal symbol display unit 19 displays a winning symbol, the symbol start port 15 is opened and closed. The claw 15a is opened only for a predetermined time or until a predetermined number of game balls are detected.

  When a game ball wins the symbol start port 15, the display symbols of the special symbol display portions Da to Dc change for a predetermined time and are determined based on the lottery result corresponding to the winning timing of the game ball to the symbol start port 15. Stop at the stop symbol. In addition, in special symbol display parts Da-Dc and its circumference, a notice effect may be performed between a series of symbol effects.

  The big winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward, but when the stop symbol after the symbol change of the special symbol display portions Da to Dc is a big hit symbol such as “777”, the “big hit game” Is started, and the opening / closing plate 16a is opened.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol of the special symbols, a privilege that the game after the end of the special game is in a high probability state is given.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. A dashed line in the figure mainly indicates a DC voltage line.

  As shown in the figure, this pachinko machine GM is provided with a power supply board 20 that receives AC 24V and outputs various DC voltages, system reset signals (power reset signals) SYS, and the like, and a main control board 21 that plays a central role in game control operations. And an effect control board 22 that executes a lamp effect and a sound effect based on the control command CMD received from the main control board 21, and a liquid crystal that drives the liquid crystal display DISP based on the control command CMD ′ received from the effect control board 22. The control board 23, the payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21 and paying out the game ball, and the game ball is fired in response to the player's operation. The launch control board 25 is mainly configured.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. Further, the control command CMD ′ output from the effect control board 22 is transmitted to the liquid crystal control board 23 via the effect interface board 27, and the control command CMD ″ output from the main control board 21 is set to the main board relay board 28. Is transmitted to the payout control board 24 via.

  The main control board 21, the effect control board 22, the liquid crystal control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Accordingly, the circuits mounted on the control boards 21 to 24 and the operations realized by the circuits are collectively referred to as a function. In this specification, the main control unit 21, the effect control unit 22, and the liquid crystal control unit 23 are used. , And the payout control unit 24. All or part of the effect control unit 22, the liquid crystal control unit 23, and the payout control unit 24 is a sub-control unit.

  By the way, the pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and the new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, and a frame relay board 32, and these circuit boards are Each is fixed in place on the front frame 3. On the other hand, on the back of the game board 5, a main control board 21, an effect control board 22, and a liquid crystal control board 23 are fixed together with a liquid crystal display DISP and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 28 through the connection connector C2, and is connected to the power supply relay board 30 through the connection connector C3. The main board relay board 28 outputs the system reset signal SYS, the RAM clear signal DEL, the voltage drop signal, the backup power supplies BAK, DC12V, and DC32V received from the power board 20 to the main controller 21 as they are. Similarly, the power supply relay board 30 also outputs the system reset signal SYS received from the power supply board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The production interface board 27 outputs the received system reset signal SYS to the production control unit 22 and the liquid crystal control unit 23 as they are.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and the system reset signal SYS, the RAM clear signal DEL, the voltage drop signal, the backup power supply, which are received by the main control unit 21. BAK is received directly along with other power supply voltages.

  Here, the system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V is turned on to the power supply board 20, and the one-chip microcomputers of the respective control units 21 to 24 by this power supply reset signal. The other IC elements are reset in power supply.

  The RAM clear signal DEL received from the power supply board 20 by the main control unit 21 and the payout control unit 24 is a signal that determines whether or not to initialize all areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. Therefore, it has a value corresponding to the ON / OFF state of the initialization switch SW operated by the attendant.

  The voltage drop signal received from the power supply board 20 by the main control unit 21 and the payout control unit 24 is a signal indicating that the AC power supply 24V has started to drop. By receiving this voltage drop signal, each control unit 21, In 24, a necessary termination process is started prior to a power failure or business termination. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 25 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  On the other hand, the effect control unit 22 and the liquid crystal control unit 23 are not provided with the power supply backup function described above. However, as described above, the system reset signal SYS is commonly supplied to the effect control unit 22 and the liquid crystal control unit 23 via the power relay board 30 and the effect interface board 27, and other controls are performed. The power supply reset operation is realized at a timing substantially synchronized with the units 21 and 24.

  As illustrated, the main control unit 21 transmits a control command CMD "to the payout control unit 25 via the main board relay board 28, while the payout control unit 25 receives a prize ball indicating a payout operation of the game ball. A count signal and a status signal CON relating to an abnormality in the payout operation are received, and the status signal CON includes, for example, a replenishment out signal, a payout shortage error signal, and a lower plate full signal.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 29. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The switch signal includes a winning switch signal SG transmitted from the symbol start port 15 to the main control unit 21.

  FIG. 4 illustrates a part of the internal configuration of the one-chip microcomputer 21 </ b> A of the main control unit 21. Here, a portion including a winning switch signal SG received from the detection switch of the symbol start port 15 via the game board relay board 29 is shown.

  As illustrated, the one-chip microcomputer 21A includes a CPU equivalent to Z80CPU (Zilog), a counter timer circuit CTC equivalent to Z80CTC (counter timer circuit), a ROM and RAM memory circuit, a watchdog timer WDT, and a random number generator. A circuit GNR, an abnormal reset circuit ABN that detects illegal access (illegal memory access) of a memory or an IO port and forcibly resets the CPU, and an input port INP are incorporated.

  The winning switch signal SG from the symbol start port 15 is supplied to the random number generation circuit GNR of the one-chip microcomputer 21A and the input port INP via the buffer circuit BUF arranged on the game board relay board 29. Yes. The input port INP is supplied not only with the symbol start port 15 but also with a switch signal from the big winning port 16 and the detection switch of the gate 18.

  The buffer circuit BUF has an open collector type output section, and the input side is pulled up to 12V and the output side is pulled up to 5V. When the game ball passes through the symbol start port 15 and enters a winning state, the buffer circuit BUF outputs a winning switch signal SG as a positive logic ON signal.

  The random number generation circuit GNR detects that the winning switch signal SG is in an ON state and holds a detection content, a counter that is updated at high speed in response to the counting clock Φ, and the winning switch signal is ON. And a random value register that holds a counter value at the moment when the state is reached as a random value.

  When the CPU grasps that the winning switch signal SG is in the ON state based on the input data from the input port INP, the CPU obtains a random value from the random value register of the random number generation circuit GNR, and uses this as the winning value. The lottery process (special symbol process ST27 in FIG. 8) is executed.

  The abnormal reset circuit ABN includes a plurality of maximum value registers MAX and minimum value registers MIN, and each register is written with an address value and port number required by the CPU prior to the start of the game control operation. It is configured to be. Although not particularly limited, in this embodiment, the address value and the port number are written in the two's complement (negative number) format in the minimum value register MIN.

  The abnormal reset circuit ABN is connected to the CPU address bus, control bus, and data bus. If the address value output to the address bus is in an abnormal state (illegal memory access), the CPU reset is performed. A reset signal is output to the terminal RESET. Note that a reset signal is also supplied to the reset terminal RESET of the CPU from the watchdog timer WDT that has detected an abnormality.

  FIG. 5 is a circuit block diagram showing a circuit configuration of the abnormal reset circuit ABN. As shown in the figure, the abnormal reset circuit ABN includes a ROM unauthorized access detection unit 50 that detects unauthorized access to the ROM, a RAM unauthorized access detection unit 51 that detects unauthorized access to the RAM, and an IO unauthorized detection that detects unauthorized access to the IO port. And an access detection unit 52. The three detection units 50 to 52 have similar circuit configurations, and all the detection units are configured to output an L level abnormality signal ER when an unauthorized access is detected.

  The abnormal signal ER output from each of the detection units 50 to 52 is supplied to the NAND gate G4, and the output thereof is supplied to the NAND gate G5. A reset control signal CTL output from the CPU is supplied to the NAND gate G5. Therefore, if any abnormal signal ER becomes L level while the reset control signal CTL is at H level, an L level reset signal is supplied to the reset terminal RESET of the CPU, and the CPU is forcibly reset. .

  The unauthorized access detection units 50 and 51 include a 16-bit minimum value register MIN that stores and holds the minimum address value START in 2's complement format, and a 16-bit maximum value register MAX that stores and holds the maximum address value END. A 16-bit latch circuit LT for obtaining address data DATA of the address bus, two adders ADD1 for performing a 16-bit addition operation, a complement operation unit CMP for performing a two's complement operation, And an output gate GT for receiving an overflow signal CY output from the adder ADD1.

  Here, the minimum value register MIN, the maximum value register MAX, and the latch circuit LT are configured to be reset by a power reset signal when the power is turned on. Therefore, the contents of each register are 0000H unless the CPU sets a numerical value in each register MIN, MAX. Similarly, the latch circuit LT maintains the stored value (0000H) immediately after the power is turned on unless the address value of the address bus is acquired.

  The complement calculation unit CMP is a circuit that converts input data into a two's complement format and inverts the sign of the numerical value. More specifically, after logically inverting (NOT operation) the output data DATA of the latch circuit LT, an operation of adding 1 to this is executed. As a result, the output of FFFFH-DATA + 1 is obtained with a 16-bit length for the acquired data DATA from the address bus. The hexadecimal number FFFFH is 65535 in decimal number.

  The adder ADD is configured by combining one half adder (Half adder) and 15 full adders (Full adder), the addition result of 16 bits length, and 1 bit overflow from the most significant digit A circuit that outputs a signal CY.

  As illustrated, the output gate GT of the ROM unauthorized access detection unit 50 is configured by an AND gate (negative logic OR gate), and the output gate GT of the RAM unauthorized access detection unit 51 is configured by a NAND gate.

  The ROM unauthorized access detection unit 50 is provided with an OR gate G1 that receives the MREQ bar signal and the M1 bar signal output from the CPU, and the output of the OR gate G1 is supplied to the latch circuit LT as a latch signal. Therefore, in the ROM unauthorized access detection unit 50, the address data DATA of the address bus is acquired by the latch circuit LT at the timing when both the M1 bar signal and the MREQ signal bar become L level.

  As described above, since the ROM unauthorized access detection unit 50 latches the address data DATA at the timing when both the M1 bar signal and the MREQ signal bar become L level, each instruction stored in the ROM is stored in the operation code unit. The validity of the address storing the following operand part cannot be determined. For example, in the case of a 3-byte instruction such as LDA, (NN), the validity of the address value of the memory storing the operand part (address NN) is not determined. However, in an instruction having a length of a plurality of bytes, it is virtually impossible to store only the opcode part in the valid area and to store the continuous operand part in the illegal area.

  Subsequently, the RAM unauthorized access detection unit 51 will be described. As shown in the figure, the RAM unauthorized access detection unit 51 includes a NOT gate G2 that logically negates the MREQ bar signal output from the CPU, and a NAND gate G3 that receives the RFSH bar signal and the output signal of the NOT gate G2. The output of G3 is supplied to the latch circuit LT as a latch pulse. Therefore, the RAM unauthorized access detection unit 51 acquires the address data DATA of the address bus in the latch circuit LT in synchronization with the falling edge of the MREQ signal bar on condition that the RFSH bar signal is at the H level.

  The IO unauthorized access detection unit 52 has a configuration similar to that of the RAM unauthorized access detection unit 51, and includes an 8-bit minimum value register MIN that stores and holds the minimum port number START in two's complement format, and the maximum port number. An 8-bit length maximum value register MAX for storing and holding END, an 8-bit length latch circuit LT for acquiring lower 8-bit data of the address bus, and two addition units ADD that perform an 8-bit length addition operation; A complement calculation unit CMP that performs a two's complement calculation and a NAND gate GT that receives an overflow signal CY output from two addition units ADD are configured.

  In each circuit configuration described above, the minimum value register MIN and the maximum value register MAX store address values and port numbers that specify ROM use areas and RAM or IO port use prohibition areas.

  For example, the minimum value register MIN of the ROM unauthorized access detection unit 50 stores a start address START in which ROM data (control program and control data) is stored, and the maximum value register MAX stores ROM data. The end address END is stored. Therefore, if a ROM address other than the valid storage area (STAR to END) is accessed in the operation code fetch cycle, it is determined that the access is illegal.

  On the other hand, the RAM start address START for which use is prohibited is stored in the minimum value register MIN of the RAM unauthorized access detection unit 51, and the RAM end address END for which use is prohibited is stored in the maximum value register MAX. It is like that. Similarly, the start port number START of the IO port prohibited to be used is stored in the minimum value register MIN of the IO port unauthorized access detection unit 52, and the end port of the IO port prohibited to be used is stored in the maximum value register. The number END is stored. Therefore, in the RAM unauthorized access detection unit 51 and the IO port unauthorized access detection unit 52, when an address or port number in the prohibited range (STAR to END) is accessed, this is unauthorized access. As described above, the minimum value register MIN stores the start address and the start port number in a two's complement format.

  FIG. 6 is a time chart showing the operation contents of the Z80 CPU, and shows an operation code fetch cycle (a), a memory read / write cycle (b), and an IO read / write cycle (c).

  In the operation code fetch cycle (FIG. 6A), the ROM address storing the operation code of the control program is output from the CPU program counter in synchronization with the M1 bar signal, and then the MREQ bar signal falls.

  As shown in FIG. 5, the ROM unauthorized access detection unit 50 is provided with an OR gate G1 that receives the M1 bar signal and the MREQ bar signal. Therefore, the address value DATA of the address bus is acquired by the latch circuit LT at the falling edge of the MREQ bar signal (see FIG. 6A). After that, the MREQ bar signal also falls at the timing when the refresh address is output. At this timing, the M1 bar signal is at the H level, so that the latch circuit LT of the ROM unauthorized access detection unit 50 is not affected.

  In the memory read / write cycle (FIG. 6B), a memory read / write operation based on the execution of the control program is executed in synchronization with the MREQ bar signal. As shown in FIG. 5, since the NOT gate G2 and the NAND gate G3 are arranged in the RAM unauthorized access detector 51, the memory address value of the access destination output from the program counter in the memory read / write cycle is MREQ. Acquired by the latch circuit LT at the falling edge of the bar signal. Note that the MREQ bar signal also falls at the timing when the refresh address is output, but at this timing, the RFSH bar signal is at the L level, so that the latch circuit LT of the RAM unauthorized access detection unit 51 is not affected. The RAM unauthorized access detection unit 51 also determines an address value in the operation code fetch cycle, but does not cause any problem because it only determines whether or not it is in a use-prohibited range (START to END).

  In the IO read / write cycle (FIG. 6C), the IO port access operation is executed in synchronization with the IORQ bar signal based on the execution of the IN instruction and OUT instruction of the control program. Corresponding to this operation, the IO unauthorized access detector 52 is provided with a NOT gate G2 and a NAND gate G3, so that the 8-bit long port number of the access destination is a latch circuit at the falling edge of the IOREQ bar signal. Acquired by LT.

  As described above, in this embodiment, the 16-bit address value output in the opcode fetch cycle is acquired by the latch circuit LT of the ROM unauthorized access detection unit 50 and output in the memory read / write cycle. Is acquired by the latch circuit LT of the RAM unauthorized access detection unit 51. Further, the lower 8-bit address value output in the IO read / write cycle is acquired by the latch circuit LT of the IO unauthorized access detection unit 52.

  The address value DATA acquired by the latch circuit LT is calculated in the addition unit of the unauthorized access detection units 50 to 52. First, the operation of the ROM unauthorized access detection unit 50 will be described from the addition operation of the start address value stored in the minimum value register MIN.

  When the addition unit ADD1 on the left side adds 16 bits to the two's complement start address (FFFFH-START + 1) stored in the minimum value register MIN and the ROM address value DATA acquired from the address bus, When DATA> = START, overflow occurs from the most significant bit (CY = 1), and when DATA <START, overflow does not occur (CY = 0).

  Here, since the start address START is the start address where the control program is stored, if DATA <START (CY = 0) in which overflow does not occur (CY = 0), it means that the address is an illegal access to an originally nonexistent address. Become.

  Next, the operation of the right addition unit ADD1 will be described. For the end address END stored in the maximum value register MAX, the ROM address value DATA obtained from the address bus is subjected to a 2's complement operation and then added to the end address END in the other adder ADD1. Therefore, from the relationship of FFFFH−DATA + 1 + END, when END> = DATA, overflow occurs from the most significant bit (CY = 1), and when END <DATA, overflow does not occur (CY = 0).

  Here, since the end address END is the last address where the control program is stored, if END <DATA (CY = 0) where no overflow occurs (CY = 0), it means that it is an illegal access to an address that does not exist originally. Become.

  Since the overflow signal CY output from the two adders ADD1 is supplied to the AND gate (negative logic OR gate) GT in this way, when one of the overflow signals CY becomes CY = 0 In (illegal memory access), the abnormal signal ER becomes L level.

  Subsequently, the operation of the RAM unauthorized access detection unit 51 is confirmed. When the addition unit ADD1 on the left side adds 16 bits of the start address (FFFFH-START + 1) in 2's complement format stored in the minimum value register MIN and the address value DATA acquired from the address bus, DATA> When = START, an overflow occurs from the most significant bit (CY = 1), and when DATA <START, no overflow occurs (CY = 0).

  In the RAM unauthorized access detection unit 51, since the start address START is the start address of the RAM that is prohibited from being used, if DATA> = START (CY = 1) in which overflow occurs, unauthorized access to the prohibited address area is performed. There is a possibility.

  For the right adder ADD1, the operation of the RAM unauthorized access detector 51 is the same as that of the ROM unauthorized access detector 50. After the address value DATA obtained from the address bus is complemented by 2, the operation is terminated. It is added to the address END. Therefore, from the relationship of FFFFH−DATA + 1 + END, when END> = DATA, overflow occurs from the most significant bit (CY = 1), and when END <DATA, overflow does not occur (CY = 0).

  Here, since the end address END is the final address of the RAM whose use is prohibited, if END> = DATA (CY = 1) in which overflow occurs, there is a possibility that it is an illegal access to an address that does not originally exist. is there.

  Since the overflow signal CY output from the two adders ADD1 is supplied to the NAND gate GT in this way, when both of the two overflow signals CY are CY = 1, that is, when DATA> = START. If END> = DATA, the RAM area in the prohibited range (START to END) is illegally accessed, and the abnormal signal ER, which is the output of the NAND gate GT, is output. L level.

  The operation of the IO unauthorized access detection unit 52 is the same as that of the RAM unauthorized access detection unit 51 described above except that each operation is 8 bits long. In other words, if DATA> = START and END> = DATA with respect to the start number START and end number END of the port number prohibited to be used, the abnormal signal ER is assumed to be unauthorized access. L level.

  Next, the gaming operation of the main control unit 21 executed by the CPU shown in FIG. 4 will be described. FIGS. 7 to 8 are flowcharts showing a control program of the main control unit 21, which is started at a system reset process (FIG. 7) that is started based on the restoration or turn-on of the power supply voltage and every predetermined time (2 mS). And maskable timer interrupt processing (FIG. 8A).

  Hereinafter, the system reset processing program (main processing) will be described with reference to FIG. The main process is started when the initialization switch SW is turned off and the power is turned on, such as when recovering from a power failure, and when the game hall is opened, the initialization switch SW is turned on. There is a case where the power source is turned on by being operated. The abnormal reset circuit ABN and the watchdog timer WDT may be activated to forcibly reset the CPU.

  In any case, the Z80 CPU first initializes the value of the stack pointer SP in the CPU corresponding to the final address of the stack area (ST1).

  Next, the values of various registers including the register of the abnormal reset circuit ABN of the one-chip microcomputer are initialized (ST2). Specifically, the ROM use start address START and the use end address END of the main control unit are stored in the minimum value register MIN and the maximum value register MAX of the ROM unauthorized access detection unit 50. Since each address value is 16 bits long, it is stored every 8 bits in synchronization with the chip select signals CS1 to CS4.

  In addition, the start address START and the end address END of the RAM area that is prohibited from being used in the RAM of the main control unit are stored in the minimum value register MIN and the maximum value register MAX of the RAM unauthorized access detection unit 51. Similarly, the start port number START and the end port number END of the IO port whose use is prohibited are stored in the minimum value register MIN and the maximum value register MAX of the IO unauthorized access detection unit 52.

  Note that the initial setting process may be omitted for the above-described minimum value register MIN and maximum value register MAX when the RAM or IO port is not provided with a prohibited area. The minimum value register MIN and the maximum value register MAX are reset when the power is turned on. Therefore, the overflow signal CY is always CY = 0 in the addition operation of DATA + 0 with respect to the acquired data DATA from the address bus. This is because the abnormal signal ER is always maintained at the H level.

  Therefore, by utilizing such an operation, the use prohibition area is temporarily changed to a usable state by temporarily storing zero data in the minimum value register MIN and the maximum value register MAX during the game control operation. You can also Conversely, the minimum value register MIN and the maximum value register MAX are turned on to start the game control operation, and necessary address values are stored in the respective registers at appropriate timings to generate temporary use prohibition areas. You can also If it is desired to return the temporary use-prohibited area to the use-permitted state, zero data may be stored in each register.

  In any case, when the initial setting process in step ST2 is completed, the abnormal signal ER is output from the RAM unauthorized access detector 51 or the unauthorized access detector 52 of the IO port by setting the reset control signal CTL to the L level. The prohibited state is set (ST3).

  As shown in FIG. 5, the abnormal signal ER from the RAM unauthorized access detector 51 and the IO port unauthorized access detector 52 is supplied to the NAND gate G5 via the NAND gate G4. The reset control signal CTL is supplied to the input terminal of the NAND gate G5.

  Therefore, after the reset control signal CTL is set to the L level by the process of step ST3, the output of the NAND gate G5 is always at the H level, so that the RAM unauthorized access detecting unit 51 and the IO port unauthorized access detecting unit 52 The abnormal signal ER is blocked by the NAND gate G5 and is not supplied to the reset terminal of the CPU. However, since the abnormal signal ER from the ROM unauthorized access detection unit 50 does not pass through the NAND gate G5, the CPU is forcibly reset at the time of unauthorized access.

  In the present embodiment, the process of step ST3 is provided in order to clear all the RAM areas at once in the RAM clear process (ST10), although the use prohibited areas (START to END) are provided in the RAM. In addition, by performing the clear process including the use-prohibited area, no trouble is caused even when the use-prohibited area of the RAM is temporarily used.

  When the processing in step ST3 as described above is completed, the write inhibit signal INH is changed from the L level to the H level, and the RAM is set in a writable state (ST4). As shown in FIG. 4, in this embodiment, the WR bar signal (see FIG. 6) output from the control bus of the CPU is supplied to the RAM via the NAND gate GT0. Since the write inhibit signal INH is supplied to the NAND gate GT0, the write operation (Write) to the RAM is permitted by setting the write inhibit signal INH to the H level by the process of step ST4. . In this embodiment, the read operation (Read) from the RAM is always permitted regardless of the level of the write inhibit signal INH.

  When the processing in step ST4 as described above is completed, a RAM clear signal DEL is acquired from the input port (ST5). The RAM clear signal DEL is a signal for determining whether or not to initialize all areas of the built-in RAM of the one-chip microcomputer 21A, and has a value corresponding to the ON / OFF state of the initialization switch SW operated by the staff. Have.

  Next, the level of the RAM clear signal is determined (ST6). If it is assumed that the RAM clear signal is in the ON state, the entire area of the built-in RAM is cleared to zero (ST10). Therefore, the value of the backup flag BFL set in the process of step ST37 in FIG. 8B becomes zero together with other checksum values. Since the RAM clear process (ST10) is executed in a state where the reset control signal CTL is set to the L level, there is no possibility that the CPU is forcibly reset even if the use prohibited area is accessed.

  Next, after outputting a power-on command for notifying that the RAM area is cleared to zero (ST11), the reset control signal CTL initialized to the L level is returned to the H level, thereby detecting the unauthorized access to the RAM. The abnormal signal ER from the unit 51 or the unauthorized access detection unit 52 of the IO port is set to an output enabled state (ST12). As a result, thereafter, when the RAM area or the IO port that is prohibited from being used is accessed, the CPU is forcibly reset based on the abnormal signal ER that has transitioned to the L level.

  Subsequently, the CTC that outputs the interrupt signal INT for starting the timer interrupt operation (FIG. 8A) is initialized (ST13). Then, with the CPU set to the interrupt disabled state (ST14), update processing is executed for various counters (ST15), and then the CPU is returned to the interrupt enabled state and the process returns to step ST14. Note that the counter updated in step ST14 includes an out symbol counter, but this out symbol counter is out of the result of the big hit lottery process in the special symbol processing (ST27) of FIG. 8A. It is a counter for deciding what kind of out-of-game to produce when it becomes a state.

  Returning to the determination process in step ST6, the RAM clear signal is in the OFF state when the CPU is forcibly reset by the watchdog timer WDT or the like or when the CPU recovers from the power failure state. In such a case, the content of the backup flag BFL is determined following the determination in step ST6 (ST7). The backup flag BFL is data indicating that the operation of the power supply monitoring process of FIG. 8B has been executed. In this embodiment, the backup flag BFL is set to 5AH in the process of step ST37 when the power is turned off. It is cleared to zero in the process of step ST33 after the power is restored.

  When the power is turned on or when recovering from a power failure, the content of the backup flag BFL is 5AH. However, if the program goes into a runaway state for some reason and a CPU reset operation is caused by the watchdog timer, the backup flag BFL = 00H. Therefore, when BFL ≠ 5AH (normally BFL = 00H), the process proceeds from step ST7 to step ST10 to return the operation of the gaming machine to the initial state.

  On the other hand, if the backup flag BFL = 5AH, a checksum operation for calculating a checksum value is executed (ST8). Here, the checksum operation is an 8-bit addition operation for the work area of the built-in RAM. When the checksum value is calculated, the calculation result is compared with the stored value at the SUM address in the RAM (ST9).

  In the SUM address, the checksum value by the same checksum calculation is stored in the power supply monitoring process (FIG. 8B) executed when the voltage drops (ST38). The stored calculation results are maintained by a backup power source together with other data in the built-in RAM. Therefore, the two should be matched by the determination in step ST9.

  However, if the checksum calculation (ST38) cannot be executed when the power is turned off, or if it can be executed, the data in the work area will be damaged until the checksum calculation (ST8) of the main process is executed. In such a case, the determination result in step ST9 is inconsistent. If data corruption is detected due to a discrepancy between the determination results, the process proceeds to step ST10, RAM clear processing is executed, and the operation of the gaming machine is returned to the initial state. On the other hand, if it is determined in step ST9 that the checksum value obtained by the checksum calculation (ST8) matches the stored value at the SUM address, the process proceeds to step ST12.

  Next, a timer interrupt processing program (FIG. 8A) that is started every 2 mS while interrupting the main processing described above will be described. When the timer interrupt occurs, the power supply monitoring process is immediately executed without saving the CPU register (ST20). This is because the timing at which the timer interrupt process is started is fixed immediately after step ST16.

  In the power supply monitoring process (ST20), the level of the voltage drop signal supplied from the power supply board 20 is determined. The specific processing content will be described later. When the power monitoring process (ST20) ends, the value of the winning counter RG used in the lottery operation in the normal symbol process (ST26) is updated (ST21). Note that the random value RND for jackpot determination used in the lottery operation in the special symbol process (ST27) is generated by the random number generation circuit GNR in FIG. 5, and is not updated in the process of step ST21.

  When the winning random number update process (ST21) ends, a timer subtraction process is performed for the timer that manages the time of each gaming operation (ST22). The timer to be subtracted here is mainly used for managing the opening time of the electric tulip and the special winning opening and other game effect times.

  Subsequently, ON / OFF signals of various switches including the winning detection switch of the symbol start opening 15 and the big winning opening 16 are inputted, and the ON / OFF signal level and its rising state are stored in the work area (ST23). . Subsequently, an error management process is performed (ST24). The error management process includes a determination as to whether an abnormality has occurred inside the device, such as whether or not the supply of game balls has stopped or the game balls are clogged.

  Next, after executing the management process based on the prize ball counting signal received from the payout control unit 24 (ST25), the normal symbol process is performed (ST26). The normal symbol processing means determination as to whether or not to operate an ordinary electric accessory such as an electric tulip. Specifically, when it is determined that the game ball has passed through the gate based on the switch input result in step ST23, the winning counter RG updated in the random number updating process (ST21) is compared with the winning winning value. Done. If the comparison result is a winning state, the operation mode is changed to the winning operation mode. In addition, if it is a hit, processing for the operation of a normal electric accessory such as an electric tulip is performed.

  Subsequently, special symbol processing is performed (ST27). The special symbol process is a determination as to whether or not to operate a special electric accessory such as the special winning opening 16. Specifically, when it is determined that the winning switch signal SG has risen, the big hit lottery process is executed using the random number value RND stored in the random number register of the random number generation circuit GNR. Although not shown in the drawing, if the lottery result is a winning state, the operation mode is changed to a big hit operation mode. In addition, if it is a big hit, processing for the operation of special electric accessories such as a big prize opening is performed.

  After such special symbol processing (ST27), the lighting operation of the LEDs managed by the main control unit 21 is advanced (ST28), and the solenoid drive processing for realizing the opening / closing operation of the electric tulip, the big prize opening, etc. is executed. Later (ST29), the CPU is returned to the interrupt permission state EI and the timer interrupt is finished (ST30). As a result, the process returns from the interrupt process routine to the infinite loop process (FIG. 7) of the main process, and the process of step ST15 is executed.

  Next, the power supply monitoring process (ST20) shown in FIG. 8B will be described. In the power supply monitoring process (ST20), first, a voltage drop signal supplied from the power supply board 20 is acquired through an input port (not shown) (ST31), and it is determined whether it is an abnormal level (ST32). If it is not an abnormal level, the abnormal number counter and the backup flag BFL are cleared to zero and the process is terminated (ST33).

  On the other hand, if the voltage drop signal is at an abnormal level, the abnormal number counter is incremented (+1) (ST34), and it is determined whether the counting result exceeds the upper limit value MAX (ST35). This is because the data acquired from the input port may be garbled due to the influence of noise or the like, and the abnormal level is continuously set for a predetermined number of times (for example, upper limit MAX = 2). In the case of maintaining, it is determined that the AC power source is actually shut off.

  As described above, in this embodiment, the subsequent backup processing is not started immediately even when the power is turned off, and the operation start timing is delayed by MAX × 2 mS. However, (1) The power supply drop signal is not a drop in the DC power supply voltage, but a drop in the AC DC voltage is detected. (2) The DC power supply voltage is maintained for a while after the AC power supply is shut off by a large-capacitance capacitor. (3) The power supply monitoring process is repeated at a high speed (every 2 ms), and (4) the backup process is extremely simple and finishes quickly, so there is virtually no adverse effect.

  By the way, as a result of the determination in step ST35, if the count value of the abnormal number counter coincides with the upper limit value MAX, the abnormal number counter is cleared to zero (ST36), and then 5AH is set to the backup flag BFL (ST37). Next, the same calculation as in step ST7 of the main routine is executed for the same work area (work area), and the calculation result is stored (ST38). The operation to be executed is typically an 8-bit addition operation.

  After that, the write inhibit signal INH is set to the L level to set the write to the RAM in a prohibited state, and the reset control signal CTL is set to the L level (ST39). Then, the output data of all output ports is cleared (ST40). As a result, unreasonable data is prevented from being transmitted to the payout control unit 24 that starts the same type of power supply monitoring process later than the main control unit 21.

  Here, the reset control signal CTL is set to the L level to prevent the CPU reset due to the unauthorized access of the RAM or the unauthorized access of the IO port, which may cause an abnormal operation as the power supply voltage decreases. This is to prevent this. That is, even if the write inhibit signal INH is set to the L level, only the write to the memory (Write) is prohibited and the read from the memory is possible. Therefore, if the reset control signal CTL is set to H If the level is maintained, a CPU reset may occur due to a read operation of an illegal address in the RAM as the power supply voltage drops. In this case, the RAM may be abnormally rewritten by the processing after step ST4. Because it becomes.

  When the above backup process is completed, the generation of the interrupt signal INT is prohibited by the setting process for the CTC, and the DC power supply voltage is lowered while repeating the infinite loop process (ST41). At this timing, the CPU is originally in an interrupt disabled state (see ST30). However, in this embodiment, an interrupt signal from the CTC is used to eliminate as much as possible the possibility of malfunction due to a drop in power supply voltage. INT output is also prohibited.

  Although the embodiments of the present invention have been specifically described above, the specific description content is not intended to limit the present invention, and various modifications can be made. For example, in this embodiment, in order to simplify the hardware configuration, the start address converted into the two's complement format is stored in the minimum value register MIN. However, in order to reduce the processing of the CPU, the minimum value register Of course, the complement calculation unit CMP may be arranged in the preceding stage.

  Further, the abnormal reset circuit ABN of the embodiment is provided with the IO port unauthorized access unit 52, but this may be omitted. In particular, when the port design is performed using the memory mapped IO method instead of the port mapped IO method, the RAM port unauthorized access unit 51 is sufficient.

  In the embodiment, the configuration in which one each of the minimum value register MIN and the maximum value register MAX is arranged in each of the unauthorized access units 50 to 52 has been described. However, the registers MIN and MAX are appropriately increased as necessary. .

ST2 Prohibition setting means CTL access control means 51 First abnormality reset means 50 Second abnormality reset means INH Write control means GM gaming machine 21 Main control unit

In order to achieve the above-described object, the present invention executes main lottery processing based on a detection signal indicating the occurrence of a predetermined game action, and determines whether or not to generate a game state advantageous to the player. The main control unit includes a ROM that stores a control program and data in a nonvolatile manner, a RAM that stores work data in a volatile manner, and a CPU that operates based on the control program in the ROM. And a one-chip microcomputer with built-in, and a prohibition setting means for setting a RAM access prohibition area by setting a start address and an end address, and permitting access to the RAM access prohibition area state or an access control means capable of controlling the disabled state, Accession the forbidden region of the RAM in a state in which the access by the access control means is controlled to prohibit state An abnormal reset means for forcibly resetting the CPU by detecting that it has been accessed, and a write control means capable of uniformly controlling the data write operation to the RAM to a prohibited state or a permitted state, The write control means uniformly controls the data write operation to the prohibited state while permitting the data read operation from the RAM .

The prohibition setting means can set the access prohibition area of the RAM , and the access control means can control the access to the access prohibition area to the permission state or the prohibition state. As a result, game control can be optimized.

In addition, the write control means uniformly controls the data write operation in a state in which the data read operation from the RAM is permitted. Therefore, the write control unit performs the limited constant control operation while preventing the RAM from being destroyed. Can continue.

As described above, according to the present invention, in correspondence with the operation state of the gaming machine can change the illegal measures, it is also possible to standardize the hardware design of the memory circuit for a plurality of models of the gaming machine.

Claims (8)

A gaming machine having a main control unit that executes a lottery process due to a detection signal indicating the occurrence of a predetermined gaming operation and determines whether or not to generate a gaming state advantageous to the player,
The main control unit has a one-chip microcomputer including a ROM that stores a control program and data in a nonvolatile manner, a RAM that stores work data in a volatile manner, and a CPU that operates based on the control program in the ROM. And configured as
A prohibition setting means for setting a start address and an end address at an arbitrary timing and setting a RAM access prohibition area;
Access control means capable of controlling access to the access prohibited area to a permitted state or a prohibited state;
First anomaly reset means for forcibly resetting the CPU upon detecting access to the prohibited area of the RAM in a state where the access is controlled to be prohibited by the access control means;
A second abnormal reset means for forcibly resetting the CPU by detecting that an area other than the ROM use area is accessed;
Write control means capable of uniformly controlling the data writing operation to the RAM to a prohibited state or a permitted state;
A gaming machine characterized by having a structure.   The gaming machine according to claim 1, wherein the access control means controls the access to the access prohibited area of the RAM to a permitted state or a prohibited state in a state where the second abnormality reset means functions.   The gaming machine according to claim 1 or 2, wherein the write control means controls the data write operation uniformly to a prohibited state while permitting the data read operation from the RAM. The main control unit is configured to have backup means for maintaining the stored contents of the RAM even after the power is shut off,
The data write operation is uniformly prohibited by the write control means after predetermined data is stored in the RAM when the power is shut off, and access to the access prohibited area is permitted by the access control means. 4. The gaming machine according to any one of 3. The main control unit is configured to have backup means for maintaining the stored contents of the RAM even after the power is shut off,
When the power is turned on, after the initial setting process of each part of the one-chip microcomputer is completed, the data write operation is uniformly permitted by the write control means, and the access to the access prohibited area is permitted by the access control means. The gaming machine according to any one of claims 1 to 4.   6. The gaming machine according to claim 5, wherein the data stored in the RAM is erased in a state where the data write operation is uniformly permitted and access to the access prohibited area is permitted. The one-chip microcomputer is provided with a minimum value register capable of storing the start address of the prohibited RAM area and a maximum value register capable of storing the end address of the prohibited RAM area,
The gaming machine according to claim 1, wherein the CPU is configured to set appropriate address values in the minimum value register and the maximum value register.   The write control means comprises a logic circuit for controlling a predetermined signal transmitted by the control bus among the address bus output from the CPU to the RAM and the control bus. The gaming machine described in 1.