JP2012054341A - Semiconductor substrate and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a normally-off semiconductor device that has a high threshold voltage and a low leakage current.SOLUTION: The semiconductor device comprises a semiconductor element having a high electron mobility transistor (HEMT) structure including a ground layer (buffer layer) 3 of a III-nitride containing at least Al provided on a substrate 2, and a semiconductor group provided on the ground layer 3 and layered with a first semiconductor layer (channel layer) 4 of a III-nitride containing at least Al, preferably of GaN, and a second semiconductor layer (electron supply layer) 6 of a III-nitride containing at least Al, preferably of AlxGa1-xN where X≥0.2. The semiconductor device further comprises an insulating film 7 of a mixed crystal of Al2O3-SiO2 formed on the semiconductor element and a gate electrode 9 formed on the insulating film 7.

Description

  The present invention relates to a semiconductor substrate using group III nitride and a semiconductor device using the same, specifically, MIS (Metal-Insulater-Semiconductor) or MOS (Metal-Oxide-Semiconductor) The present invention relates to a (oxide-semiconductor) type HEMT (High Electron Mobility Transistor) element.

  III-nitride semiconductors such as GaN have high band gap, high breakdown electric field strength, and high melting point, so they are expected as high-power, high-frequency, and high-temperature semiconductor device materials to replace GaAs-based materials. As a device that makes use of such physical properties, HEMT elements and the like have been researched and developed. For example, a heterostructure type HEMT device in which GaN is formed as a so-called channel layer on a substrate such as sapphire or SiC, and further AlGaN or AlN is formed thereon as a so-called electron supply layer has been studied and developed.

  In the HEMT device as described above, due to the difference in lattice constant (of the a axis) between the channel layer and the electron supply layer, a channel effect is generated due to a piezo effect (piezoelectric effect) and a spontaneous polarization effect that generate an electric field from the surface to the substrate. A two-dimensional electron gas is generated on the surface of the layer. In AlGaN, the higher the Al concentration, the larger the lattice constant difference, so that the piezo effect and the spontaneous polarization effect also increase.

  Since this HEMT device has a high carrier concentration (sheet carrier concentration) on the surface of the channel layer, it has been intensively researched and developed as a high-current transistor. In particular, a group III nitride semiconductor has a larger band gap than silicon, has a high breakdown voltage, and can operate at a high temperature. Therefore, it is promising as a power device that can replace silicon power devices such as power MOS and IGBT.

 However, this HEMT device is normally a normally-on device due to its high carrier concentration. That is, only a device in which a current flows between the source and the drain without applying a voltage to the gate can be formed. In actual applications, a normally-off device is desired in which a current does not flow between the source and the drain when no voltage is applied to the gate, particularly in a power device or the like, from the viewpoint of safety.

 In fact, silicon power devices, power MOSs, and IGBTs that are in practical use are normally off devices. For this reason, even in the group III nitride semiconductor, it is desired to realize a normally-off device such as a MIS (MOS) type HEMT device.

Various attempts have also been made to realize a normally-off device in a nitride-based MIS (MOS) type HEMT device. The main ones are:
(1) Method using a recess gate structure (see Patent Document 1, Non-Patent Documents 1 to 4)
(2) A method of suppressing the piezoelectric effect (piezoelectric effect) and the spontaneous polarization effect by reducing the Al concentration of a semiconductor layer made of group III nitride containing Al. (3) A semiconductor layer made of group III nitride containing fluorine ions for Al. To suppress the spontaneous polarization effect by injecting into a non-patent document 5-11
(4) Method for reducing the thickness of the second semiconductor layer (electron supply layer) made of Group III nitride containing Al as much as possible (see Patent Document 2 and Non-Patent Documents 12 to 15)
(5) A method of reducing the spontaneous polarization of the second semiconductor layer (electron supply layer) made of a group III nitride containing Al grown on a nonpolar or antipolar substrate as the substrate (non-patented) (Refer to References 16 and 17)
(6) Method of growing a layer made of p-type group III nitride on a second semiconductor layer (electron supply layer) made of group III nitride containing Al to form a junction type HEMT (Patent Document 3) -5, see non-patent documents 18-20)
(7) Conduction of the second semiconductor layer (electron supply layer) by providing a semiconductor layer having a smaller band gap on the second semiconductor layer (electron supply layer) made of Group III nitride containing Al. There is a method of lifting a belt (see Non-Patent Document 21).

  However, although either method is normally off, a large threshold voltage cannot be obtained.

  (8) On the other hand, a method using a MIS (MOS) structure in which an oxide film or an insulator film is deposited on a second semiconductor layer (electron supply layer) made of a group III nitride containing Al (Patent Document 6) -8 and non-patent documents 22 to 33), these films are deposited by sputtering, plasma CVD, laser ablation, atomic layer epitaxy, or the like, or a nitride layer formed on the surface is later formed by ozone or plasma radicals. Various methods have already been tried, such as participation, but generally the threshold voltage is small, and even if a large threshold voltage is obtained, there are many interface states, and a semiconductor device that operates normally could not.

  Further, an invention has been made in which an amorphous AlOnNy film is used as an insulator film (see Patent Document 9). However, since an amorphous film is used, a semiconductor device having many interface states and operating normally is used. could not. Further, although an invention has been made in which an Al2O3 film is laminated on an AlN film as an insulator film (see Patent Document 10), since a mixed crystal is not used as in the present invention, a semiconductor layer and an insulator film are used. Therefore, the present invention is completely different from the present invention.

JP 2008-198789 A JP 2007-250950 A JP 2007-66979 A JP 2006-339561 A JP 2007-19309 A JP 2003-332356 A JP 2006-210518 A JP 2007-250950 A JP 2005-183597 A JP 2006-32552 A

S. Maroldt et al., Jpn. J. Appl. Physics, 48 (2009) 04C-83. M. Kuraguchi et al., Phys.stat.sol. (A), 204 (2007), 2010. T. Oka et al., IEEE Electron Device Lett., 29 (2008), 668. W. Saito et al., IEEE Trans. Electron Devices, 53 (2006), 356. W. Chen et al., Appl. Phys. Lett., 92 (2008), 253501. Y. Cai et al., IEEE Electron Device Lett., 26 (2005), 435. Y. Cai et al., IEEE Trans. Electron Devices, 53 (2006), 2207. D. Song et al., IEEE Electron Device Lett., 28 (2007), 189. T. Paiacios et al., IEEE Electron Device Lett., 27 (2006), 428. C.S.Suh et al., IEEE IDEM Tech. Digest, # 35.3 (2006). A. Basu et al., Int. Conf. Compound Semiconductor MANTECH Tech Digest (2008), pp. 253. T.J.Anderson et al., IEEE Electron Device Lett., 30 (2009), 1251. C. Ostermaier et al., IEEE Electron Device Lett., 30 (2009), 1030. Y. Ohmaki et al., Jpn. J. Appl. Phys., 45 (2006), L1168. A. Endoh et al., Jpn. J. Appl. Phys., 43 (2004), 2255. T. Fujiwara et al., Appl. Phys. Express, 2 (2009), 011001. M. Kuroda et al., J. Appl. Phys., 102 (2007), 093703. T. Fujii et al., 46 (2007), 115. Y. Uemoto et al., IEDM09 (2009), 165. Y. Uemoto et al., IEEE Trans. Electron Devices, 54 (2007), 3393. T. Mizutani et al., IEEE Electron Device Lett., 28 (2007), 549. Y. Niiyama et al, 47 (2008), 5409, 7128. M. Tajima et al, Jpn. J. Appl. Phys., 48 (2009) 020203. C.F.Lo et al., J. Vac. Sci. Technol. B, 8 (2010), 52. S. Sugiura et al., Solid State Electronics, 54 (2010) 79. M. Kuroda et al. IEEE Trans. Electron Devices, 57 (2010) 368. H. Kambayashi et al., IEEE Electron Device Lett., 28 (2007), 1077. K. Matocha et al., IEEE Electron Device Lett., 52 (2005), 6. S.C.Binari et al., Proc. Electrochem. Soc., Vol.95-21.pp.136. R. Therrien et al., Microchem. Eng., 48 (1999), 303. F. Ren et al., Solid-State Electron. 43 (1999), 1817. P. Chen et al., Proc. Mater. Res. Soc., 622 (2000), T.2.9.1. K.-W. Lee et al., Electron Lett., 38 (2002), 829.

  The present invention has been made in view of the above points, and uses an Al2O3-SiO2 mixed crystal as an insulating film, increases the threshold voltage, reduces the interface state, and is normally off and normally. It is an object of the present invention to obtain a semiconductor element that operates.

  In principle, the normally-off device method described in (1) to (7) above cannot provide a high threshold voltage. On the other hand, the MOS type or MIS type structure described in (8) is capable of a high threshold voltage normally-off device, but in reality, it can be practically used regardless of many studies. A normally-off device with a threshold voltage has not been realized. As a result of diligent investigation on the reason, the present inventors have reached the following conclusion.

  In the conventional MOS type or MIS type structure, the MOS layer or MIS type device cannot be operated because the insulating layer does not physically match the underlying semiconductor layer and has many interface levels. It was. The present inventors, unlike conventional insulating layers, consist of a mixed crystal of Al2O3-SiO2 as an insulating layer material that is physicochemically matched with the semiconductor layer under the insulating layer and reduces unnecessary interface states. We focused on insulating film materials.

  The present invention has been made on the basis of the above investigation. In the invention according to claim 1, the substrate, the underlayer as a buffer layer formed on the substrate, and the base layer are formed. A semiconductor substrate comprising a semiconductor layer group, wherein the semiconductor layer group includes a first semiconductor layer as a channel layer formed of a single layer or multiple layers made of a group III nitride, and the first semiconductor A second semiconductor layer as an electron supply layer composed of a single layer or multiple layers made of a group III nitride having a larger band gap than the layer, and is laminated in this order from the base layer side, and the semiconductor layer An insulating film made of a mixed crystal of Al2O3-SiO2 is formed on the group.

  According to a second aspect of the present invention, in the semiconductor substrate according to the first aspect, in order to increase a current flowing through the first semiconductor layer, an impurity is contained in a single layer or multiple layers constituting the second semiconductor layer. Is added.

  According to a third aspect of the present invention, in the semiconductor substrate according to the first or second aspect, the semiconductor layer group is between the second semiconductor layer and the insulating film made of the mixed crystal of Al2O3-SiO2. In order to control the position of the conductor, it has a third semiconductor layer as a conduction band edge adjusting layer composed of a single layer or multiple layers made of group III nitride.

  According to a fourth aspect of the present invention, a source electrode and a gate electrode are formed on the semiconductor substrate according to any one of the first to third aspects, and the gate electrode is formed on the insulating film made of the mixed crystal of Al2O3-SiO2. A semiconductor device in which is formed.

It is a schematic diagram which shows the structure of the MOS type HEMT element formed using the semiconductor laminated structure. It is a schematic diagram which shows the structure of the MOS type HEMT element which concerns on a modification. It is a schematic diagram which shows the structure of the MOS type HEMT element which concerns on a modification.

  FIG. 1 is a conceptual diagram showing a configuration of a MOS type HEMT element formed using the semiconductor multilayer structure 1 according to the present embodiment. For convenience of illustration, the ratio of the thickness of each layer in FIG. 1 does not reflect the actual ratio.

  The semiconductor multilayer structure 1 includes a base layer (buffer layer) 3, a first semiconductor layer (channel layer) 4, and a second semiconductor layer (electron supply layer) 6 on a predetermined substrate 2. Hereinafter, the first semiconductor layer (channel layer) 4 and the second semiconductor layer (electron supply layer) 6 may be simply referred to as a semiconductor layer or a semiconductor layer group. Further, as shown below, the semiconductor multilayer structure 1 is formed by epitaxially growing these semiconductor layer groups on the substrate 2 and is used for subsequent element formation in the same manner as the substrate. This is sometimes referred to as an epitaxial substrate.

  The MOS HEMT device is formed by forming a source electrode 8, a gate electrode 9, and a drain electrode 10 on the semiconductor multilayer structure 1.

  The substrate 2 is appropriately selected according to the composition and structure of the underlying layer (buffer layer) 3 and the semiconductor layer formed thereon and the formation method of each layer. For example, as the substrate 2, sapphire, silicon carbide, silicon, germanium, oxide (ZnO, LiAlO2, LiGaO2, MgAl2O4, (LaSr) (AlTa) O3, NdGaO3, MgO, etc.), Si-Ge alloy, III-V group Compounds (GaAs, AlN, GaN, AlGaN, AlInN), borides (such as ZrB2), and the like can be used. There is no particular limitation on the thickness of the substrate 2, but a thickness of several hundred μm to several mm is preferable for convenience of handling.

  The underlayer (buffer layer) 3 is formed from a single layer or multiple layers made of various Group III nitrides depending on the composition and structure of the semiconductor layer formed thereon or the formation method of each layer. The underlayer (buffer layer) 3 is preferably formed to a thickness of 0.5 μm or more and 5 μm or less, and preferably has a structure with as little strain and dislocation density as possible.

  In addition, such an underlayer (buffer layer) 3 can be formed by a known film formation method such as MOCVD method or MBE method. By appropriately adjusting the film forming conditions, the dislocation density is 1 × 10 11 / cm 2 or less, preferably 5 × 10 10 / cm 2 or less, more preferably 1 × 10 10 / cm 2 or less. It is formed as it is.

  The first semiconductor layer (channel layer) 4 is preferably formed of a high-resistance group III nitride. More preferably, it is formed of GaN (i-GaN) that does not contain impurities that cause a reduction in resistance. FIG. 1 illustrates the case where the first semiconductor layer (channel layer) 4 is formed of i-GaN. The first semiconductor layer (channel layer) 4 is also formed by a known film formation method such as MOCVD method or MBE method. By being formed on the base layer (buffer layer) 3 having high crystallinity as described above, the first semiconductor layer (channel layer) 4 also has good crystal quality.

  In addition, near the upper surface of the first semiconductor layer (channel layer) 4, electrons serving as carriers are supplied from the second semiconductor layer (electron supply layer) 6, thereby generating a high-concentration two-dimensional electron gas. A two-dimensional electron gas region 5 is formed. For this reason, the first semiconductor layer (channel layer) 4 needs to be thick enough to secure the two-dimensional electron gas region 5, but if the thickness is too large, cracks are likely to occur. The thickness is preferably about several μm.

  The second semiconductor layer (electron supply layer) 6 is formed of a group III nitride containing at least Al. Preferably, in the group III nitride having a composition of AlxGa1-xN, the band gap of the second semiconductor layer (electron supply layer) 6 is larger than the band gap of the first semiconductor layer (channel layer) 4. Formed. The second semiconductor layer (electron supply layer) 6 is formed to have a thickness of 5 nm to 60 nm as a whole. The second semiconductor layer (electron supply layer) 6 has a point of forming the two-dimensional electron gas region 5 and a point of device operation (that is, main gate voltage application). This is preferable from the viewpoint of current controllability.

  The second semiconductor layer (electron supply layer) 6 is formed by a known film forming method such as MOCVD method or MBE method. The piezo effect increases as the second semiconductor layer (electron supply layer) 6 is formed of a group III nitride having a large value of x, that is, an Al-rich group III nitride. The sheet carrier concentration is improved. Preferably, the second semiconductor layer (electron supply layer) 6 is formed of a group III nitride in a range satisfying x ≧ 0.2. However, if x is large, cracks are likely to occur, so it is necessary to select growth conditions that do not cause cracks. Further, a two-dimensional electron gas is generated by generating a semiconductor layer having a band gap larger than that of the second semiconductor layer (electron supply layer) 6 between the two-dimensional electron gas region 5 and the second semiconductor layer (electron supply layer) 6. The mobility of electrons in the region 5 can also be increased.

  The insulating film 7 made of a mixed crystal of Al2O3-SiO2 formed on the surface of the second semiconductor layer (electron supply layer) 6 is formed by sputtering, plasma CVD, vapor deposition, laser ablation, ALE (atomic layer epitaxy), ALD (atomic atoms). Various thin film growth methods such as layer deposition method, MOCVD (metal organic vapor phase epitaxy), MBE (molecular beam epitaxy), etc. can be used. As for the composition ratio of the Al 2 O 3 —SiO 2 mixed crystal, the composition ratio is determined so as to physicochemically match the surface of the second semiconductor layer 6. Specifically, the composition is determined from the viewpoint of lattice constant, coefficient of thermal expansion, interface state density, and the like.

  For the purpose of oxidizing Al when the insulating film 7 made of a mixed crystal of Al 2 O 3 —SiO 2 is formed on the surface of the second semiconductor layer (electron supply layer) 6 by various thin film growth methods as described above. An oxygen partial pressure in the hydrogen gas is installed by controlling the water vapor pressure in the hydrogen gas by installing a device for controlling the water vapor pressure by heating or cooling water in the middle of the pipe for flowing hydrogen gas to the thin film growth apparatus. If the control is precisely controlled, an insulating film 7 made of a mixed crystal of high-quality Al2O3-SiO2 that is more effectively physicochemically matched with the surface of the second semiconductor layer (electron supply layer) 6 can be formed.

  The source electrode 8 and the drain electrode 10 are formed on the surface of the second semiconductor layer (electron supply layer) 6 by, for example, ohmic contact with Ti / Au / Ni / Au. The source electrode 8 and the drain electrode 10 may be formed after a predetermined contact process is performed on the electrode forming portion on the surface of the second semiconductor layer (electron supply layer) 6. The gate electrode 9 is formed on the surface of the insulating film 7 made of a mixed crystal of Al2O3-SiO2 by, for example, Schottky junction with Pd / Ti / Au.

  In the MOS HEMT device having such a configuration, an electric field is generated from the surface to the substrate due to the lattice constant difference between the first semiconductor layer (channel layer) 4 and the second semiconductor layer (electron supply layer) 6. The two-dimensional electron gas layer 5 is generated on the surface of the first semiconductor layer (channel layer) 4 by the piezoelectric effect and the spontaneous polarization effect.

  Normally, since the sheet carrier concentration by this two-dimensional electron gas region is large, a normally-on MOS type HEMT device is produced. In order to make such a MOS type HEMT device normally-on, in order to reduce the sheet carrier concentration in the two-dimensional electron gas region, as described above, (1) a method using a recessed gate structure, (2) Al A method of suppressing the piezoelectric effect (piezoelectric effect) and the spontaneous polarization effect by reducing the Al concentration of the semiconductor layer made of group III nitride containing silicon, and (3) injecting fluorine ions into the semiconductor layer made of group III nitride containing Al. (4) a method of reducing the thickness of the second semiconductor layer (electron supply layer) 6 made of a group III nitride containing Al as much as possible, and (5) nonpolar and antipolarity on the substrate. A method of reducing the spontaneous polarization of the second semiconductor layer (electron supply layer) 6 made of a group III nitride containing Al grown on the substrate has been tried. 2D electronic gas Since the sheet carrier concentration by the layer is reduced, the feature of the MOS type HEMT device that allows a large current to flow is suppressed, and the threshold voltage is small even if normally-off is possible. is doing.

  Further, in order to take advantage of the characteristics of the MOS type HEMT device that allows a large current to flow and to increase the threshold voltage, (6) a second semiconductor layer made of a group III nitride containing Al (electron supply layer) ) A method of growing a layer made of p-type group III nitride on 6 to form a junction type HEMT, (7) Second semiconductor layer (electron supply layer) 6 made of group III nitride containing Al On the other hand, a method of raising the conduction band of the second semiconductor layer (electron supply layer) 6 by providing a semiconductor layer having a band gap smaller than that has been tried, but the threshold voltage is not sufficiently high. Further, there is a disadvantage that the leakage current of the gate is large.

  In contrast, (8) a method using a MIS (MOS) structure in which an oxide film or an insulator film is deposited on a second semiconductor layer (electron supply layer) 6 made of a group III nitride containing Al. Is a method similar to a silicon MOS device, and most promising, but the MIS (MOS) structure insulating film 7 that has been tried so far is Si3N4, SiO2, SiO2, Gd2O3, polysilicon, etc. Even if the threshold voltage was large, the interface state density was large, and a good semiconductor device could not be manufactured.

  Further, since the MOS type HEMT device according to the present embodiment uses the insulating film 7 made of a mixed crystal of Al 2 O 3 —SiO 2, a film that is physicochemically matched with the surface of the semiconductor multilayer structure 1 is formed. Therefore, a MOS type HEMT element having a high threshold voltage and a small leakage current has been realized, and such a semiconductor device far exceeds the value easily conceived from the conventionally disclosed technology. In the present embodiment, the insulating film 7 made of a mixed crystal of Al 2 O 3 —SiO 2 formed on the surface of the second semiconductor layer (electron supply layer) 6 is combined with the second semiconductor layer (electron supply layer) 6 and physical chemistry. It can be inferred that a normally-off element that can operate at a large threshold voltage could be realized by reducing the electrically active interface state because the composition can be controlled so as to match.

  As described above, in the MOS type HEMT device according to the present embodiment, a group III nitride, preferably a base layer (buffer layer) 3 made of a group III nitride is provided on a substrate 2. And a first semiconductor layer 4 made of GaN and a group III nitride containing at least Al, preferably AlxGa1-xN, and a second semiconductor layer (electron supply layer) 6 where x ≧ 0.2. And a second semiconductor layer (electron supply layer) 4 and an Al2O3- layer by forming an insulating film 7 made of a mixed crystal of Al2O3-SiO2 on the semiconductor layer group so as to match the physicochemical as much as possible. A normally-off element that can operate at a large threshold voltage (at least +1 V or more, preferably +3 V or more) by reducing the electrically active interface state between the insulating films 7 made of a mixed crystal of SiO 2. There has been realized.

<Modification>
The structure of the MOS type HEMT element is not limited to the above-described embodiment, and various structures can be adopted. 2 and 3 are diagrams showing an example of a MOS type HEMT device having a structure different from the above, which is manufactured by using the semiconductor multilayer structure 1 according to the present embodiment.

  In FIG. 2, the sheet carrier concentration in the two-dimensional electron gas region 5 can be increased by adding an impurity to one or more of the single layer or multiple layers constituting the second semiconductor layer (electron supply layer) 6. Therefore, a MOS type HEMT device in which more current flows can be obtained. In addition, since the sheet carrier concentration in the two-dimensional electron gas region 5 can be increased by the impurity concentration without depending on spontaneous polarization or piezo polarization, even if the thickness of the second semiconductor layer (electron supply layer) 6 is thin, the current can be supplied. A flowing MOS type HEMT device is formed. At this time, since the second semiconductor layer (electron supply layer) 6 can be made thinner, a normally-off MOS type HEMT device can be more easily formed, so that a MOS type HEMT device having a larger threshold voltage can be obtained. . As an impurity to be added, Si may be doped as an n-type dopant, and other elements in place of Si may be either a single layer or multiple layers constituting the second semiconductor layer (electron supply layer). One or more doped embodiments may be used.

  FIG. 3 shows the position of the conductor on the second semiconductor layer (electron supply layer) 6 and between the second semiconductor layer (electron supply layer) 6 and the insulating film 7 made of a mixed crystal of Al 2 O 3 —SiO 2. 2 shows a MOS type HEMT structure having a third semiconductor layer (conduction band edge adjusting layer) 11 composed of a single layer or multiple layers made of group III nitride. Since the third semiconductor layer (conduction band edge adjusting layer) 11 has a large band gap, it has a function of adjusting the height of the conduction band edge of the second semiconductor layer (electron supply layer) 6. The threshold voltage of marily off can be increased.

  Also in the structure shown in FIG. 3, a mixed crystal made of Al 2 O 3 and SiO 2 is used as the insulating film 7 and is physicochemically matched with the semiconductor layer under the insulating film 7 (the third semiconductor layer 11 in this example). Thus, a normally-off element that can operate with a large threshold voltage can be realized as in the above-described embodiment.

  Further, the semiconductor layer under the source electrode and the drain electrode may be either the second semiconductor layer (electron supply layer) 6 or the third semiconductor layer (conduction band edge adjusting layer) 11. For example, the portion may be etched by reactive ion etching (RIE) to expose a part of the portion, and the source electrode 8 and the drain electrode 10 may be formed.

  Further, the semiconductor layer under the source electrode and the drain electrode may be either the second semiconductor layer (electron supply layer) 6 or the third semiconductor layer (conduction band edge adjusting layer) 11. The part is etched by, for example, reactive ion etching (RIE), and a part thereof is exposed. Then, Si doped GaN is provided as a contact layer by selective regrowth, and a source electrode and a drain electrode are formed thereon. It may be configured as described above.

  Further, the semiconductor layer under the source electrode and the drain electrode may be the second semiconductor layer (electron supply layer) 6 or the third semiconductor layer (conduction band edge adjusting layer) 11. A tapered groove may be provided up to a part of the semiconductor layer (electron supply layer) 6, and the gate electrode 9 may be provided on the bottom surface.

  Also in the MOS type HEMT device having the above-described structure, an electrically active interface state is formed between the second semiconductor layer 4 and the insulating film 7 made of a mixed crystal of Al2O3-SiO2, similarly to the above-described embodiment. By reducing the position, a normally-off element that can operate with a large threshold voltage is realized.

  The present invention is not limited to the above-described various embodiments and modifications thereof, and may be configured by appropriately combining them.

  In this example, the semiconductor multilayer structure 1 according to the above-described embodiment and a MOS type HEMT device using the same were manufactured. First, a C-plane sapphire single crystal having a diameter of 2 inches and a thickness of 600 μm was used and placed in a reaction vessel of a predetermined MOCVD apparatus. In the MOCVD apparatus, at least H2, N2, TMG (trimethylgallium), TMA (trimethylaluminum), NH3, and silane gas can be supplied into the reaction tube as a reaction gas or a carrier gas. The substrate 29 was heated to 1210 ° C. while flowing hydrogen as a carrier gas at a flow rate of 3.5 m / sec and the pressure in the reaction tube was maintained at 25 Torr, and then held for 10 minutes to perform thermal cleaning of the substrate 29. .

  Thereafter, while maintaining the substrate temperature at 1210 ° C., TMA and its carrier gas, hydrogen, are supplied, and NH 3 and its carrier gas, hydrogen, are supplied, thereby forming an underlayer (buffer layer) 3 as An AlN layer having a thickness of 1.5 μm was grown. At that time, the respective flow rates were controlled so that the supply molar ratio of TMA and NH3 was TMA: NH3 = 1: 400. The half width of the X-ray rocking curve for the (002) plane of the base layer (buffer layer) 3 thus obtained was 70 seconds, and the dislocation density was 3 × 10 13 / cm 2.

  Subsequently, after the temperature was set to 1110 ° C. and the pressure was set to 750 Torr, TMG and NH 3 were supplied at a supply molar ratio of TMG: NH 3 = 1: 1800 to form the first semiconductor layer (channel layer) 4. A GaN layer having a thickness of 2.5 μm was formed. At this time, the supply amounts of TMG and NH3 were set so that the film formation rate was about 3.5 μm / hr.

  After the formation of the GaN layer as the first semiconductor layer (channel layer) 4, the temperature is set to 1090 ° C., and the supply molar ratio of TMA, TMG, and NH 3 becomes TMA: TMG: NH 3 = 0.15: 0.6: 1800. Thus, a second semiconductor layer (electron supply layer) 6 having a composition of Al 0.25 Ga 0.75 N was formed. Thus, the semiconductor multilayer structure 1 was obtained.

  A mixed crystal film of Al 2 O 3 and SiO 2 was formed on the surface of the semiconductor multilayer structure 1 thus obtained. In a vacuum deposition apparatus having an H2 supply pipe, Al and Si were deposited by electron beam deposition. During this deposition, the semiconductor layer substrate is heated, and a small amount of water vapor is mixed in the H2 supply pipe so that the oxygen partial pressure is based on thermodynamic calculation so that Al and Si are oxidized. The insulating film 7 of mixed crystal of Al2O3 and SiO2 was formed by supplying H2 whose oxygen partial pressure was precisely controlled. In addition, when depositing Al and Si, the deposition may be performed by a resistance heating method.

  Further, after etching and patterning the surface of the semiconductor multilayer structure 1 with the mixed crystal insulating film 7 of Al 2 O 3 —SiO 2 by RIE or the like, Ti / Au / Ni / Au is formed at a predetermined position on the surface of the semiconductor multilayer structure 1. The source electrode 8 and the drain electrode 10 to be formed were formed by ohmic junction, and the gate electrode 9 made of Pd / Ti / Au was formed by Schottky junction to obtain a MOS type HEMT device.

With respect to the MOS HEMT device thus obtained, a transconductance at room temperature of 200 mS / mm was obtained when the current density was 970 mA / mm, the threshold voltage was 7.7 V, and the gate length was 2 μm.
(Comparative example)
As this comparative example, a MOS type HEMT device having the same semiconductor multilayer structure as that of the MOS type HEMT device according to the example was manufactured except that Al 2 O 3 and SiO 2 which are usually used as the insulating film 7 were grown by sputtering.

  The MOS type HEMT devices thus obtained each had a transconductance at room temperature of 120 mS / mm when the current density was 380 mA / mm, the threshold voltage was 1.3 V, and the gate length was 2 μm. That is, it can be seen that the MOS type HEMT device in this comparative example has inferior device characteristics than the example.

  From the above examples and comparative examples, it can be seen that the MOS type HEMT device according to the present embodiment has a remarkably superior characteristic than that of a stable, low interface state and high threshold voltage. .

According to the above-described embodiment and examples, the following method for manufacturing a semiconductor device can be obtained. That is,
Forming a base layer as a buffer layer on the substrate;
A first semiconductor layer as a channel layer composed of a single layer or multiple layers made of group III nitride and a group III nitride having a band gap larger than that of the first semiconductor layer are formed on the base layer. A step of stacking a second semiconductor layer as an electron supply layer composed of a single layer or multiple layers to form a semiconductor layer group;
Forming an insulating film made of a mixed crystal of Al2O3-SiO2 on the semiconductor layer group;
Forming a source electrode and a drain electrode on the semiconductor layer group, and forming a gate electrode on the insulating film.

  In this manufacturing method, in order to oxidize Al and Si in order to create an Al2O3-SiO2 insulating layer, an apparatus for controlling water vapor pressure by heating or cooling water in the middle of a pipe through which hydrogen gas flows to a thin film growth apparatus Therefore, by controlling the water vapor pressure in the hydrogen gas, the oxygen partial pressure in the hydrogen gas is controlled precisely to oxidize Al and Si, so that an insulating film with a good crystal quality is formed. A semiconductor device that can be deposited on the semiconductor layer group above the formation layer, has a small leakage current, a low interface state, and has good device characteristics is realized.

DESCRIPTION OF SYMBOLS 1 Semiconductor laminated structure 2 Substrate 3 Underlayer (buffer layer)
4 First semiconductor layer (channel layer)
5 Two-dimensional electron gas region 6 Second semiconductor layer (electron supply layer)
7 Al2O3-SiO2 insulating layer 8 Drain electrode 9 Gate electrode 10 Source electrode 11 Third semiconductor layer (conduction band edge adjusting layer)

Claims (4)

A substrate,
An underlayer as a buffer layer formed on the substrate;
A semiconductor substrate comprising a semiconductor layer group formed on the underlayer,
The semiconductor layer group is
A first semiconductor layer as a channel layer composed of a single layer or multiple layers made of group III nitride;
A second semiconductor layer as an electron supply layer composed of a single layer or multiple layers made of a group III nitride having a band gap larger than that of the first semiconductor layer;
Is laminated in this order from the base layer side,
An insulating film made of a mixed crystal of Al2O3-SiO2 is formed on the semiconductor layer group.   The semiconductor substrate according to claim 1, wherein an impurity is added to a single layer or multiple layers constituting the second semiconductor layer in order to increase a current flowing through the first semiconductor layer. Semiconductor substrate.   3. The semiconductor substrate according to claim 1, wherein the semiconductor layer group controls a position of a conductor between the second semiconductor layer and the insulating film made of the mixed crystal of Al 2 O 3 —SiO 2. A semiconductor substrate comprising a third semiconductor layer as a conduction band edge adjusting layer composed of a single layer or multiple layers made of group III nitride.   A source electrode and a gate electrode are formed on the semiconductor substrate according to claim 1, and the gate electrode is formed on the insulating film made of the mixed crystal of Al 2 O 3 —SiO 2. Semiconductor device.