JP2012009501A - Semiconductor substrate manufacturing method and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element of a high electron mobility transistor (HEMT) structure or of a metal insulator semiconductor (MIS) (metal oxide semiconductor (MOS)) HEMT structure excellent in device features.SOLUTION: A semiconductor laminated structure comprises a group of semiconductor layers each including a ground layer (buffer layer) 3 provided on a substrate 2 with a group III nitride including at least Al, a first semiconductor layer (channel layer) 4 provided on the ground layer 3 with a group III nitride, favorably GaN, and a second semiconductor layer (electron supply layer) 6 provided on the semiconductor layer 4 with a group III nitride including at least Al, favorably AlxGa1-xN where x≥0.2. The buffer layer 3 and the first semiconductor layer 4 are formed by a metal-organic chemical vapor deposition (MOCVD) method, and the second semiconductor layer 6 is formed by a molecular beam epitaxy (MBE) method.

Description

  The present invention relates to a semiconductor substrate using a group III nitride and a method of manufacturing a semiconductor device using the same, and in particular, a MIS (Metal-Insulater-Semiconductor) type HEMT (High Electron Mobility Transistor). The present invention relates to a method for manufacturing a mobility transistor device.

  III-nitride semiconductors such as GaN have high band gap, high breakdown electric field strength, and high melting point, so they are expected as high-power, high-frequency, and high-temperature semiconductor device materials to replace GaAs-based materials. As a device that makes use of such physical properties, HEMT elements and the like have been researched and developed. For example, a heterostructure type HEMT device in which GaN is formed as a so-called channel layer on a substrate such as sapphire or SiC, and further AlGaN or AlN is formed thereon as a so-called electron supply layer has been studied and developed.

  In the HEMT device as described above, due to the difference in lattice constant (of the a axis) between the channel layer and the electron supply layer, a channel effect is generated due to a piezo effect (piezoelectric effect) and a spontaneous polarization effect that generate an electric field from the surface to the substrate. A two-dimensional electron gas is generated on the surface of the layer. In AlGaN, the higher the Al concentration, the larger the lattice constant difference, so that the piezo effect and the spontaneous polarization effect also increase.

  Since this HEMT device has a high carrier concentration (sheet carrier concentration) on the surface of the channel layer, it has been intensively researched and developed as a high-current transistor. In particular, a group III nitride semiconductor has a larger band gap than silicon, has a high breakdown voltage, and can operate at a high temperature. Therefore, it is promising as a power device that can replace silicon power devices such as power MOS and IGBT.

  However, this HEMT device is normally a normally-on device due to its high carrier concentration. That is, only a device in which a current flows between the source and the drain without applying a voltage to the gate can be formed. In actual applications, a normally-off device is desired in which a current does not flow between the source and the drain when no voltage is applied to the gate, particularly in a power device or the like, from the viewpoint of safety.

  In fact, silicon power devices, power MOSs, and IGBTs that are in practical use are normally off devices. For this reason, even in the group III nitride semiconductor, it is desired to realize a normally-off device such as a MIS (MOS) type HEMT device.

Various attempts have also been made to realize a normally-off device in a nitride-based MIS (MOS) type HEMT device. The main ones are:
(1) Method using a recess gate structure (see Patent Document 1, Non-Patent Documents 1 to 4)
(2) A method of suppressing the piezoelectric effect (piezoelectric effect) and the spontaneous polarization effect by reducing the Al concentration of a semiconductor layer made of group III nitride containing Al. (3) A semiconductor layer made of group III nitride containing fluorine ions for Al. To suppress the spontaneous polarization effect by injecting into a non-patent document 5-11
(4) Method for reducing the thickness of the second semiconductor layer (electron supply layer) made of Group III nitride containing Al as much as possible (see Patent Document 2 and Non-Patent Documents 12 to 15)
(5) A method of reducing the spontaneous polarization of the second semiconductor layer (electron supply layer) made of a group III nitride containing Al grown on a nonpolar or antipolar substrate as the substrate (non-patented) (Refer to References 16 and 17)
(6) Method of growing a layer made of p-type group III nitride on a second semiconductor layer (electron supply layer) made of group III nitride containing Al to form a junction type HEMT (Patent Document 3) -5, see non-patent documents 18-20)
(7) Conduction of the second semiconductor layer (electron supply layer) by providing a semiconductor layer having a smaller band gap on the second semiconductor layer (electron supply layer) made of Group III nitride containing Al. There is a method of lifting a belt (see Non-Patent Document 21).

  However, although either method is normally off, a large threshold voltage cannot be obtained.

  (8) On the other hand, a method using a MIS (MOS) structure in which an oxide film or an insulator film is deposited on a second semiconductor layer (electron supply layer) made of a group III nitride containing Al (Patent Document 6) -8 and non-patent documents 22 to 33), these films are deposited by sputtering, plasma CVD, laser ablation, atomic layer epitaxy, or the like, or a nitride layer formed on the surface is later formed by ozone or plasma radicals. Various methods have already been tried, such as participation, but generally the threshold voltage is small, and even if a large threshold voltage is obtained, there are many interface states, and a semiconductor device that operates normally could not.

  Further, an invention has been made in which an amorphous AlOnNy film is used as an insulator film (see Patent Document 9). However, since an amorphous film is used, a semiconductor device having many interface states and operating normally is used. could not.

  Further, as an insulator film, an invention of laminating an Al2O3 film on an AlN film has been made (see Patent Document 10), but since a mixed crystal of AlN and Al2O3 is not used as in the present invention, the semiconductor layer and Since physicochemical consistency with the insulating film cannot be obtained, the present invention is completely different from the present invention.

JP 2008-198789 A JP 2007-250950 A JP 2007-66979 A JP 2006-339561 A JP 2007-19309 A JP 2003-332356 A JP 2006-210518 A JP 2007-250950 A JP 2005-183597 A JP 2006-32552 A

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  The conventional semiconductor laminated structure of HEMT structure or MIS (MOS) type HEMT structure has been formed by MOCVD method (metal organic chemical vapor deposition method) or MBE method (molecular beam epixy method). The MOCVD method has a high growth rate, but has a drawback that impurities such as carbon and hydrogen are likely to enter. On the other hand, although the MBE method has a slow growth rate, it has the advantages of good growth film purity and good controllability in thin film formation.

  The present invention takes advantage of the characteristics of the above two methods to mainly use the MOCVD method as in the prior art when forming the HEMT structure or the MIS (MOS) type HEMT structure semiconductor laminated structure, and particularly the semiconductor layer. It is a first object of the present invention to obtain a semiconductor device having a performance that has not been obtained so far by using the MBE method for the layer important in the characteristics of the above.

  It is a second object of the present invention to increase the threshold voltage and reduce the interface state so that a normally-off and normally operating semiconductor element can be obtained.

  According to the first aspect of the present invention, in order to achieve the first object, a substrate, a base layer as a buffer layer formed on the substrate, and a semiconductor layer group formed on the base layer The semiconductor layer group includes a first semiconductor layer as a channel layer composed of a single layer or multiple layers made of a group III nitride, and a group III having a larger band gap than the first semiconductor layer. A method of manufacturing a semiconductor substrate, wherein a second semiconductor layer as an electron supply layer composed of a single layer or multiple layers of nitride is laminated in this order from the base layer side, wherein the buffer layer And the first semiconductor layer are formed by MOCVD, and the second semiconductor layer is formed by MBE.

  According to a second aspect of the present invention, in order to achieve the first object, in the semiconductor substrate manufacturing method according to the first aspect, an insulating film containing an oxide is formed on the semiconductor layer group. In the step of forming the insulating film containing the oxide, water vapor is mixed in hydrogen gas when the elemental element or the compound of the element constituting the oxide is deposited on the second semiconductor layer. Thus, the elemental element or elemental compound is oxidized.

  According to a third aspect of the present invention, in the method for manufacturing a semiconductor substrate according to the second aspect, when water is mixed in hydrogen gas, water is heated or cooled when the elemental element or elemental compound is oxidized. Thus, the water vapor pressure is controlled to control the oxygen partial pressure when the elemental element or the elemental compound is oxidized.

  According to a fourth aspect of the present invention, in the method for manufacturing a semiconductor substrate according to the first aspect, an insulating film containing an oxide is formed on the semiconductor layer group, and the insulating film containing the oxide is MBE. It is formed by the method.

  According to a fifth aspect of the present invention, in the semiconductor substrate manufacturing method according to any one of the first to fourth aspects, a conductor is provided between the second semiconductor layer and the insulating film containing the oxide. Forming a third semiconductor layer as a conduction band edge adjusting layer composed of a single layer or multiple layers made of a group III nitride to control the position of the third semiconductor, and in this step, the third semiconductor The layer is formed by the MBE method.

  According to a sixth aspect of the present invention, in the method for manufacturing a semiconductor substrate according to any one of the first to fifth aspects, the second semiconductor layer is formed in order to increase a current flowing through the first semiconductor layer. An impurity is added to a single layer or multiple layers constituting the layer.

  According to a seventh aspect of the invention, there is provided a semiconductor device manufacturing method in which a source electrode, a gate electrode, and a gate electrode are formed on the semiconductor substrate according to any one of the first to sixth aspects.

1 is a schematic diagram showing a configuration of a HEMT element formed using a semiconductor multilayer structure 1. FIG. It is a schematic diagram which shows the structure of the HEMT element which concerns on a modification. It is a schematic diagram which shows the structure of the HEMT element which concerns on a modification. 1 is a schematic diagram showing a configuration of a MIS (MOS) type HEMT element formed using a semiconductor multilayer structure 1; It is a schematic diagram which shows the structure of the MIS (MOS) type | mold HEMT element which concerns on a modification. It is a schematic diagram which shows the structure of the MIS (MOS) type | mold HEMT element which concerns on a modification. It is a schematic diagram of a method for forming an insulating film containing an oxide by controlling the water vapor pressure and precisely controlling the oxygen partial pressure. FIG. 10 is a schematic diagram illustrating a method for forming an insulating film containing an oxide by precisely controlling an oxygen partial pressure by controlling a water vapor pressure according to a modification.

  FIG. 1 is a conceptual diagram showing a configuration of a HEMT element formed using the semiconductor multilayer structure 1 according to the present embodiment. For convenience of illustration, the ratio of the thickness of each layer in FIG. 1 does not reflect the actual ratio.

  The semiconductor multilayer structure 1 includes a base layer (buffer layer) 3, a first semiconductor layer (channel layer) 4, and a second semiconductor layer (electron supply layer) 6 on a predetermined substrate 2. Hereinafter, the first semiconductor layer (channel layer) 4 and the second semiconductor layer (electron supply layer) 6 may be simply referred to as a semiconductor layer or a semiconductor layer group. Further, as shown below, the semiconductor multilayer structure 1 is formed by epitaxially growing these semiconductor layer groups on the substrate 2 and is used for subsequent element formation in the same manner as the substrate. This is sometimes referred to as an epitaxial substrate.

  The HEMT element is formed by forming a gate electrode 7, a source electrode 8, and a drain electrode 9 on the semiconductor multilayer structure 1.

  The substrate 2 is appropriately selected according to the composition and structure of the underlying layer (buffer layer) 3 and the semiconductor layer formed thereon and the formation method of each layer. For example, as the substrate 2, sapphire, silicon carbide, silicon, germanium, oxide (ZnO, LiAlO2, LiGaO2, MgAl2O4, (LaSr) (AlTa) O3, NdGaO3, MgO, etc.), Si-Ge alloy, III-V group Compounds (GaAs, AlN, GaN, AlGaN, AlInN), borides (such as ZrB2), and the like can be used. There is no particular limitation on the thickness of the substrate 2, but a thickness of several hundred μm to several mm is preferable for convenience of handling.

  The underlayer (buffer layer) 3 is formed from a single layer or multiple layers made of various Group III nitrides depending on the composition and structure of the semiconductor layer formed thereon or the formation method of each layer. The underlayer (buffer layer) 3 is preferably formed to a thickness of 0.5 μm or more and 5 μm or less, and preferably has a structure with as little strain and dislocation density as possible.

  Further, such a base layer (buffer layer) 3 is formed by MOCVD. If the base layer is made thick using the MOCVD method with a high growth rate, the first semiconductor layer (channel layer) 4 can also be made thick, so that a device with a high breakdown voltage can be obtained. By appropriately adjusting the film forming conditions, the dislocation density is 1 × 10 11 / cm 2 or less, preferably 5 × 10 10 / cm 2 or less, more preferably 1 × 10 10 / cm 2 or less. It is formed as it is.

  The first semiconductor layer (channel layer) 4 is preferably formed of a high-resistance group III nitride. More preferably, it is formed of GaN (i-GaN) that does not contain impurities that cause a reduction in resistance. FIG. 1 illustrates the case where the first semiconductor layer (channel layer) 4 is formed of i-GaN. The first semiconductor layer (channel layer) 4 is also formed by the MOCVD method. When the MOCVD method having a high growth rate is used, the first semiconductor layer (channel layer) 4 can be made thick, so that a device with a high breakdown voltage can be obtained.

  In addition, near the upper surface of the first semiconductor layer (channel layer) 4, electrons serving as carriers are supplied from the second semiconductor layer (electron supply layer) 6, thereby generating a high-concentration two-dimensional electron gas. A two-dimensional electron gas region 5 is formed. For this reason, the first semiconductor layer (channel layer) 4 has a higher breakdown voltage as the thickness is larger. On the other hand, if the thickness is too large, cracks are likely to occur, so that the thickness is about 1 to 10 μm. It is preferable to be formed.

  The second semiconductor layer (electron supply layer) 6 is formed of a group III nitride containing at least Al. Preferably, in the group III nitride having a composition of AlxGa1-xN, the band gap of the second semiconductor layer (electron supply layer) 6 is larger than the band gap of the first semiconductor layer (channel layer) 4. Formed. The second semiconductor layer (electron supply layer) 6 is supplied near the upper surface of the first semiconductor layer (channel layer) 4 from the second semiconductor layer (electron supply layer) 6 by spontaneous polarization as the thickness thereof increases. Since the number of electrons increases, a two-dimensional electron gas having a high electron concentration is formed in the two-dimensional electron gas region 5. Therefore, the second semiconductor layer (electron supply layer) 6 has a thickness of 20 nm to 60 nm as a whole, depending on the structure of the device manufactured from the point of device operation (that is, controllability of the main current with respect to gate voltage application). Formed in thickness.

  The second semiconductor layer (electron supply layer) 6 is formed by the MBE method. Since it is preferable to make this film highly pure, it is preferable to produce this film using the MBE method. The piezo effect increases as the second semiconductor layer (electron supply layer) 6 is formed of a group III nitride having a large value of x, that is, an Al-rich group III nitride. The sheet carrier concentration is improved. Preferably, the second semiconductor layer 6 is formed of a group III nitride in a range satisfying x ≧ 0.2. However, if x is large, cracks are likely to occur, so it is necessary to select growth conditions that do not cause cracks. Further, a two-dimensional electron gas is generated by generating a semiconductor layer having a band gap larger than that of the second semiconductor layer (electron supply layer) 6 between the two-dimensional electron gas region 5 and the second semiconductor layer (electron supply layer) 6. The mobility of electrons in the region 5 can also be increased.

  In the case of the HEMT structure, the gate electrode 7 is formed on the surface of the second semiconductor layer (electron supply layer) 6 by, for example, Pd / Ti / Au by Schottky junction. The source electrode 8 and the drain electrode 9 are formed on the surface of the second semiconductor layer (electron supply layer) 6 by, for example, ohmic contact with Ti / Au / Ni / Au. The source electrode 8 and the drain electrode 9 may be formed after a predetermined contact process is performed on the electrode formation portion on the surface of the second semiconductor layer (electron supply layer) 6.

  In the HEMT device having such a configuration, an electric field is generated from the surface to the substrate due to a lattice constant difference between the first semiconductor layer (channel layer) 4 and the second semiconductor layer (electron supply layer) 6. The two-dimensional electron gas region 5 is generated on the surface of the first semiconductor layer (channel layer) 4 due to the piezo effect and the spontaneous polarization effect.

  Note that the structure of the HEMT element is not limited to the above-described embodiment, and various structures can be employed. 2 and 3 are diagrams showing an example of a HEMT element having a structure different from the above, which is manufactured using the semiconductor multilayer structure 1 according to the present embodiment.

  In FIG. 2, the sheet carrier concentration in the two-dimensional electron gas region 5 can be increased by adding an impurity to one or more of the single layer or multiple layers constituting the second semiconductor layer (electron supply layer) 6. Therefore, a HEMT element in which more current flows can be obtained. In addition, since the sheet carrier concentration in the two-dimensional electron gas region 5 can be increased by the impurity concentration without depending on spontaneous polarization or piezo polarization, even if the thickness of the second semiconductor layer (electron supply layer) 6 is thin, the current can be supplied. A flowing HEMT element is produced. At this time, since the second semiconductor layer (electron supply layer) 6 can be made thinner, a normally-off HEMT element can be more easily formed, so that a HEMT element having a larger threshold voltage can be obtained. As an impurity to be added, Si may be doped as an n-type dopant, and other elements in place of Si may be a single layer or multiple layers constituting the second semiconductor layer (electron supply layer) 6. Any one or more of them may be doped.

  FIG. 3 shows a group III nitride on the second semiconductor layer (electron supply layer) 6 to control the position of the conductor between the second semiconductor layer (electron supply layer) 6 and the gate electrode. 1 shows a HEMT structure having a third semiconductor layer (conduction band edge adjusting layer) 11 composed of a single layer or multiple layers made of Since the third semiconductor layer (conduction band edge adjusting layer) 11 has a large band gap, it has a function of adjusting the height of the conduction band edge of the second semiconductor layer (electron supply layer) 6. The threshold voltage of marily off can be increased.

  Further, in the case of the MIS (MOS) type HEMT device, in the above-described embodiment, an insulating film is provided on the uppermost semiconductor layer, and the structure shown in FIGS. 4 to 6 is employed. In the MIS (MOS) type HEMT device of FIG. 4, a base (buffer) layer 3 made of a group III nitride is provided on a substrate 2 and then a first semiconductor layer made of a group III nitride, preferably GaN. 4 and a group III nitride containing at least Al, preferably AlxGa1-xN, and a second semiconductor layer (electron supply layer) 6 having x ≧ 0.2 is formed, and a semiconductor layer group is formed. Further, by forming the higher-purity insulating film 10 by the MBE method, by reducing the electrically active interface state between the second semiconductor layer (electron supply layer) 6 and the insulating film 10, A normally-off element that can operate with a large threshold voltage is realized.

  FIG. 5 shows that the sheet carrier concentration in the two-dimensional electron gas region 5 can be increased by adding an impurity to one or more of the single layer or multiple layers constituting the second semiconductor layer (electron supply layer) 6. Therefore, an MIS (MOS) type HEMT device in which more current flows can be obtained. In addition, since the sheet carrier concentration in the two-dimensional electron gas region 5 can be increased by the impurity concentration without depending on spontaneous polarization or piezo polarization, even if the thickness of the second semiconductor layer (electron supply layer) 6 is thin, the current can be supplied. A flowing MIS (MOS) type HEMT device can be formed. At this time, since the second semiconductor layer (electron supply layer) 6 can be made thinner, a normally-off MIS (MOS) type HEMT device can be more easily formed. ) Type HEMT device. As an impurity to be added, Si may be doped as an n-type dopant, and other elements in place of Si may be a single layer or multiple layers constituting the second semiconductor layer (electron supply layer) 6. Any one or more of them may be doped.

  FIG. 6 shows a group III nitride on the second semiconductor layer (electron supply layer) 6 to control the position of the conductor between the second semiconductor layer (electron supply layer) 6 and the insulating film 10. 1 shows a MIS (MOS) type HEMT structure having a third semiconductor layer (conduction band edge adjusting layer) 11 composed of a single layer or multiple layers made of a material. Since the third semiconductor layer (conduction band edge adjusting layer) 11 has a large band gap, it has a function of adjusting the height of the conduction band edge of the second semiconductor layer (electron supply layer) 6. The threshold voltage of marily off can be increased.

  The semiconductor laminated structure 1 described above is usually grown by MOCVD. Since the MOCVD method has a high growth rate, a thick film can be formed for the buffer layer and the first semiconductor layer (channel layer) 4, which is advantageous in increasing the breakdown voltage and decreasing the dislocation density. However, the purity of the second semiconductor layer (electron supply layer) 6 and the third semiconductor layer (conduction band edge adjusting layer) 11 that determine the sheet carrier concentration in the two-dimensional electron gas region is higher than that using the MOCVD method. It is advantageous to use an MBE method that can produce a high semiconductor layer.

  In general, since the sheet carrier concentration by the two-dimensional electron gas region 5 is large, a normally-on HEMT element or MIS (MOS) type HEMT element is produced. In order to make such a HEMT device or a MIS (MOS) type HEMT device normally off, in order to reduce the sheet carrier concentration in the two-dimensional electron gas region, as described above, (1) a recess gate structure (2) A method of suppressing the piezoelectric effect (piezoelectric effect) and the spontaneous polarization effect by reducing the Al concentration of the semiconductor layer made of group III nitride containing Al, and (3) Group III nitride containing fluorine ions with Al. (4) A method of reducing the thickness of the second semiconductor layer (electron supply layer) 6 made of a group III nitride containing Al as much as possible, and (5) a substrate. For example, a method of reducing the spontaneous polarization of the second semiconductor layer (electron supply layer) 6 made of a group III nitride containing Al grown on the substrate using a non-polar and anti-polar substrate has been tried. The In either method, the sheet carrier concentration due to the two-dimensional electron gas layer is reduced, so that the feature of the HEMT device that allows a large current to flow is suppressed. Has the disadvantage of being small.

  In order to increase the threshold voltage by making use of the feature of the HEMT device that allows a large current to flow, (6) the second semiconductor layer (electron supply layer) 6 made of group III nitride containing Al is used. A method of growing a p-type group III nitride layer to form a junction type HEMT; (7) on a second semiconductor layer (electron supply layer) 6 made of group-III nitride containing Al; An attempt has been made to provide a semiconductor layer having a smaller band gap and raise the conduction band of the second semiconductor layer (electron supply layer) 6 to form a HEMT, but the threshold voltage is sufficiently high. In addition, the gate leakage current is large.

  Further, (8) a method using a MIS (MOS) structure in which an oxide film or an insulator film is deposited on a second semiconductor layer (electron supply layer) 6 made of a group III nitride containing Al includes silicon. The MIS (MOS) structure insulating film that has been tried so far is Si3N4, SiO2, Ga2O3, Gd2O3, polysilicon, etc., and even if the threshold voltage is large, the interface has been tried. A semiconductor device having a high level density was not able to be manufactured.

  In the HEMT device according to the present embodiment, since the second semiconductor layer (electron supply layer) 6 that determines the sheet carrier concentration in the two-dimensional electron gas region uses an MBE method that can form a semiconductor layer with high purity, In addition to higher sheet carrier concentration due to the two-dimensional electron gas region, the third semiconductor layer (conduction band edge adjusting layer) 11 is also formed with a flatter layer, so that a HEMT device with better performance is realized. Such a semiconductor device far exceeds the value easily conceived from the conventionally disclosed technology. In the present embodiment, since the second semiconductor layer (electron supply layer) 6 and the third semiconductor layer (conduction band edge adjusting layer) 11 are formed by the MBE method, more electrons are two-dimensional electrons. It is assumed that a HEMT element that is supplied to the gas region, flows a larger current, and can operate at a higher frequency can be realized.

  Further, in the MIS (MOS) type HEMT device according to the present embodiment, since the insulating film 10 is manufactured by the MBE method, the purity of the insulating film 10 is improved, and a flatter insulating film can be formed. MIS (MOS) type HEMT device with a low threshold voltage and a small leakage current is realized, and such a semiconductor device far exceeds the value easily conceived from the technology disclosed heretofore. It is. In the present embodiment, for the second semiconductor layer (electron supply layer) 6 and the insulating film 10 that determine the sheet carrier concentration by the two-dimensional electron gas region 5, the MBE method that can form a semiconductor layer and an insulating film with high purity is used. As a result, the sheet carrier concentration in the two-dimensional electron gas region is higher, and the composition can be controlled so that the insulating film is physically and chemically aligned with the second semiconductor layer (electron supply layer). It is presumed that a normally-off element capable of operating with a large threshold voltage could be realized by reducing the active interface state.

  As described above, in the HEMT device according to the present embodiment, a base layer (buffer layer) 3 made of a group III nitride is provided on a substrate 2 and then a group III nitride, preferably GaN. The first semiconductor layer 4 made of is formed by MOCVD. Further, a group III nitride containing at least Al, preferably AlxGa1-xN and x ≧ 0.2, the second semiconductor layer (electron supply layer) 6 and the third semiconductor layer (conduction band edge adjusting layer) 11. Since the MBE method is used to form the oxide film, the oxide film and the insulator film can be made with higher purity, and the third semiconductor layer (conduction band edge adjusting layer) 11 can be made flat, so that the film can be formed at higher speed and higher frequency. An operable HEMT element or the like is realized.

  In the MIS (MOS) type HEMT device according to the present embodiment, a base layer (buffer layer) 3 made of a group III nitride is provided on the substrate 2 and then a group III nitride, preferably GaN. The first semiconductor layer 4 is formed by MOCVD. Further, it is formed in the case of a group III nitride containing at least Al, preferably a second semiconductor layer (electron supply layer) 6 or MIS (MOS) type HEMT structure in which AlxGa1-xN and x ≧ 0.2. Since the MBE method is used to form the insulating film 10, the insulating film is formed so as to have a higher purity and physicochemical alignment with the second semiconductor layer (electron supply layer) 6 as much as possible. By reducing the electrically active interface state between the second semiconductor layer (electron supply layer) 6 and the insulating film 10, it is possible to operate with a large threshold voltage (at least +1 V or more, preferably +3 V or more). A normally-off element is realized.

<Modification>
In the various embodiments described above, the semiconductor layer under the source electrode and the drain electrode is the third semiconductor layer (conduction band edge adjusting layer) 11 even if it is the second semiconductor layer (electron supply layer) 6. Even in such a case, the source electrode 8 and the drain electrode 9 may be formed after a part thereof is etched by, for example, reactive ion etching (RIE) to expose a part thereof.

  The semiconductor layer below the source electrode and the drain electrode may be a part of the second semiconductor layer (electron supply layer) 6 or the third semiconductor layer (conduction band edge adjusting layer) 11. For example, reactive ion etching (RIE) is used to expose a portion thereof, and then a GaN doped with Si is provided as a contact layer by selective regrowth, and a source electrode and a drain electrode are formed thereon. It may be configured.

  The semiconductor layer below the source electrode and the drain electrode is the second semiconductor layer (electron supply layer) 6 or the third semiconductor layer (conduction band edge adjusting layer) 11. A tapered groove may be provided up to a part of the semiconductor layer (electron supply layer) 6 and the gate electrode 7 may be provided on the bottom surface.

  Further, the insulating film 10 may be formed as follows in addition to the MBE method. That is, the apparatus shown in FIGS. 7 and 8 is used to heat or cool water in the middle of a pipe through which hydrogen gas flows to the insulating film growth apparatus for the purpose of oxidizing the elements constituting the oxide or the compound of the elements. An insulating film 10 containing an oxide is formed by precisely controlling the oxygen partial pressure in the hydrogen gas by installing a device for controlling the pressure and thereby controlling the water vapor pressure in the hydrogen gas.

  Specifically, in the apparatus shown in FIG. 7, the element A compound gas and element B are supplied from the element A compound gas inlet 114, the element B compound gas inlet 116, and the element X compound gas inlet 120 to the insulating film growth apparatus 112. Compound gas and element X compound gas are introduced, and hydrogen gas is introduced from the hydrogen gas inlet 107. Further, gas is discharged from the gas exhaust port 118. Further, a steam generator 104 is connected to a pipe through which hydrogen gas is introduced via a valve 111, and water (pure water) 105 in the steam generator 104 is heated by a steam pressure adjusting heater and cooling device 6. The water vapor pressure is controlled by heating or cooling. This water vapor pressure is measured by the dew point measuring device 110 through the valve 109. In the insulating film growth apparatus 112, a growth apparatus heater 101 and a susceptor 102 are provided, and a substrate 103 with a semiconductor layer is placed thereon.

  In the apparatus shown in FIG. 7, first, the valve 108 is closed, the valves 109, 111, 113, 118 are opened, the inside of the apparatus 112 is evacuated, the valve 113 is closed, and the water vapor pressure is adjusted to a predetermined pressure. Next, the valves 108 and 113 are opened to allow hydrogen gas to flow from the inlet 107, and the valves 115, 117 and 121 are opened to introduce a gas for forming an element constituting the oxide or a compound of the element. At that time, by controlling the water vapor pressure in the hydrogen gas, the oxygen partial pressure in the hydrogen gas is precisely controlled to form the insulating film 10 containing oxide. The composition ratio of the oxide of the insulating film 10 containing an oxide is determined so as to be physicochemically matched with the surface of the second semiconductor layer (electron supply layer) 6. Specifically, the composition is determined from the viewpoint of lattice constant, coefficient of thermal expansion, interface state density, and the like.

  For example, when forming the insulating film 10 of Al 2 O 3, the substrate 103 of the above-mentioned semiconductor multilayer structure 1 is installed, and TMA (compound of elements constituting the oxide) is supplied while hydrogen gas is allowed to flow from the inlet 107 as a carry gas. It flows from the inlet 114. At this time, in order to precisely control the water vapor pressure in the hydrogen gas, a vessel filled with ultrapure water is connected in the middle of the hydrogen gas pipe, and the water vapor pressure is adjusted by heating or cooling the temperature of the vessel. The water vapor pressure is precisely measured using a dew point meter 110. At this time, the Al2O3 insulating film 10 is formed by adjusting the water vapor pressure so that the oxygen partial pressure based on thermodynamic calculation is obtained so that TMA is oxidized. The oxygen partial pressure can be easily calculated as PO2 = K2 / PH2O2 based on the reaction H2O = H2 + 1 / 2O2. Here, K is an equilibrium constant of the reaction of H2O = H2 + 1 / 2O2.

  In the apparatus shown in FIG. 8, the element A 123 and the element B 126 are evaporated from the element A evaporation cell 122 and the element B evaporation cell 125 using the element A heater 124 and the element B heater 127, respectively. Other than this, the apparatus is the same as that shown in FIG. In the apparatus shown in FIG. 8, similarly to the apparatus shown in FIG. 7, by controlling the water vapor pressure in the hydrogen gas, the oxygen partial pressure in the hydrogen gas is precisely controlled to form the insulating film 10 containing oxide. To do.

  For example, when forming the insulating film 10 made of a mixed crystal of Al 2 O 3 -Ga 2 O 3, the substrate 103 having the above-described semiconductor stacked structure 1 is placed, and a vacuum state is applied to mix Al and Ga (elements constituting an oxide) Knudsen cell 122. And evaporate from 125. At this time, in order to precisely control the water vapor pressure in the hydrogen gas while flowing the hydrogen gas from the inlet 107, a container containing ultrapure water is connected in the middle of the hydrogen gas pipe, and the temperature of the container is heated or The water vapor pressure is adjusted by cooling. The water vapor pressure is precisely measured using a dew point meter 10. At this time, the Al2O3-Ga2O3 insulating film 34 is formed by adjusting the water vapor pressure so that the oxygen partial pressure based on thermodynamic calculation is obtained so that the evaporated Al and Ga are oxidized.

  In this way, for the purpose of oxidizing the element constituting the oxide or the compound of the element, the thin film growth apparatus has a device for controlling the water vapor pressure by heating or cooling water in the middle of a pipe through which hydrogen gas flows. By controlling the water vapor pressure in the hydrogen gas, the oxygen partial pressure in the hydrogen gas is precisely controlled to oxidize the elements constituting the oxide or the compound of the elements, so that an insulating film with good crystal quality Can be deposited on the semiconductor layer group above the base layer, a leakage current is small, an interface state is small, and a semiconductor device having good device characteristics is realized.

(Example 1)
In this example, the semiconductor multilayer structure 1 according to the above-described embodiment and a MOS type HEMT device using the same were manufactured. First, a C-plane sapphire single crystal having a diameter of 2 inches and a thickness of 600 μm was used and placed in a reaction vessel of a predetermined MOCVD apparatus. In the MOCVD apparatus, at least H2, N2, TMG (trimethylgallium), TMA (trimethylaluminum), NH3, and silane gas can be supplied into the reaction tube as a reaction gas or carrier gas. The substrate 29 was heated to 1210 ° C. while flowing hydrogen as a carrier gas at a flow rate of 3.5 m / sec and the pressure in the reaction tube was maintained at 25 Torr, and then held for 10 minutes to perform thermal cleaning of the substrate 29. .

  Thereafter, while maintaining the substrate temperature at 1210 ° C., TMA and its carrier gas, hydrogen, are supplied, and NH 3 and its carrier gas, hydrogen, are supplied, thereby forming an underlayer (buffer layer) 3 as 1 A 5 μm thick AlN layer was grown. At that time, the respective flow rates were controlled so that the supply molar ratio of TMA and NH3 was TMA: NH3 = 1: 400. The half width of the X-ray rocking curve for the (002) plane of the base layer (buffer layer) 3 thus obtained was 70 seconds, and the dislocation density was 3 × 10 13 / cm 2.

  Subsequently, after the temperature was set to 1110 ° C. and the pressure was set to 750 Torr, TMG and NH 3 were supplied at a supply molar ratio of TMG: NH 3 = 1: 1800 to obtain a thickness as the first semiconductor layer (channel layer). A GaN layer having a thickness of 2.5 μm was formed. At this time, the supply amounts of TMG and NH3 were set so that the film formation rate was about 3.5 μm / hr.

  After the formation of the GaN layer as the first semiconductor layer (channel layer), a composition of Al 0.25 Ga 0.75 N is set to 800 ° C. using an MBE apparatus having an Al, Ga, In Knudsen cell and a nitrogen radical source source. The 2nd semiconductor layer (electron supply layer) 6 which has was formed. Thus, the semiconductor multilayer structure 1 was obtained.

  Further, a gate electrode 7 made of Pd / Ti / Au is formed at a predetermined position on the surface of the semiconductor multilayer structure 1 by a Schottky junction, and a source electrode 8 and a drain electrode 9 made of Ti / Au / Ni / Au are formed. It formed by ohmic junction and the HEMT element was obtained.

With respect to the HEMT device thus obtained, a transconductance at room temperature of 170 mS / mm was obtained when the current density was 780 mA / mm and the gate length was 2 μm.
(Comparative Example 1)
As this comparative example, a semiconductor laminated structure having the same structure as that of Example 1 was produced by MOCVD. When forming the second semiconductor layer 6 having a composition of Al0.25Ga0.75N, the temperature is set to 1090 ° C., and the supply molar ratio of TMA, TMG, and NH3 is TMA: TMG: NH3 = 0.15: 0.6: A second semiconductor layer (electron supply layer) 6 having a composition of Al 0.25 Ga 0.75 N was formed by supplying 1800.

  Further, a gate electrode 7 made of Pd / Ti / Au is formed at a predetermined position on the surface of the semiconductor multilayer structure 1 by a Schottky junction, and a source electrode 8 and a drain electrode 9 made of Ti / Au / Ni / Au are formed. It formed by ohmic junction and the HEMT element was obtained.

With respect to the HEMT device thus obtained, the transconductance at room temperature when the current density was 420 mA / mm and the gate length was 2 μm was 140 mS / mm.
(Example 2)
In the same manner as in Example 1, the base layer (buffer layer) 3 and the first semiconductor layer (channel layer) 4 were formed by MOCVD, and the second semiconductor layer 6 was formed by MBE. The second semiconductor layer (electron supply layer) 6 composed of an Al0.2In0.8N layer of about 10 nm is formed at 800 ° C. using an MBE apparatus having an Al, Ga, In Knudsen cell and a nitrogen radical source source. did. Thus, the semiconductor multilayer structure 1 was obtained.

  Further, a gate electrode 7 made of Pd / Ti / Au is formed at a predetermined position on the surface of the semiconductor multilayer structure 1 by a Schottky junction, and a source electrode 8 and a drain electrode 9 made of Ti / Au / Ni / Au are formed. An MIS type HEMT device was obtained by forming an ohmic junction.

With respect to the MIS HEMT device thus obtained, a transconductance at room temperature of 190 mS / mm was obtained when the current density was 820 mA / mm and the gate length was 2 μm.
(Comparative Example 2)
As this comparative example, a semiconductor laminated structure having the same structure as that of Example 1 was produced by MOCVD. When forming the second semiconductor layer 6 having a composition of Al0.2In0.8N, the temperature is set to 1090 ° C., and the supply molar ratio of TMA, TMI, and NH3 is TMA: TMI: NH3 = 0.25: 0.75: The second semiconductor layer (electron supply layer) 6 having a composition of Al0.2In0.8N was formed by supplying 1800.

  Further, a gate electrode 7 made of Pd / Ti / Au is formed at a predetermined position on the surface of the semiconductor multilayer structure 1 by a Schottky junction, and a source electrode 8 and a drain electrode 9 made of Ti / Au / Ni / Au are formed. It formed by ohmic junction and the HEMT element was obtained.

With respect to the HEMT device thus obtained, a transconductance at room temperature of 160 mS / mm was obtained when the current density was 560 mA / mm and the gate length was 2 μm.
(Example 3)
As in Example 1, a base layer (buffer layer) 3 and a first semiconductor layer (channel layer) 4 were formed by MOCVD, and then, as in Example 2, Al, Ga, In Knudsen cell and nitrogen The second semiconductor layer (electron supply layer) 6 composed of an Al0.2In0.8N layer of about 10 nm was formed at 800 ° C. using an MBE apparatus having a radical source of Thus, the semiconductor multilayer structure 1 was obtained.

  An insulating film made of an oxide film of Al 2 O 3 was formed on the surface of the semiconductor multilayer structure 1 thus obtained by the MBE method. Al was supplied from the Knudsen cell, and oxygen supplied oxygen gas into the MBE apparatus to form an Al2O3 insulating film.

  Further, a gate electrode 7 made of Pd / Ti / Au is formed at a predetermined position on the surface of the semiconductor multilayer structure 1 by a Schottky junction, and a source electrode 8 and a drain electrode 9 made of Ti / Au / Ni / Au are formed. It formed by ohmic junction and the HEMT element was obtained.

For the HEMT device thus obtained, a transconductance at room temperature of 160 mS / mm was obtained when the current density was 760 mA / mm, the threshold voltage was 6.0 V, and the gate length was 2 μm.
(Comparative Example 3)
As this comparative example, a semiconductor laminated structure having the same structure as that of Comparative Example 2 was produced by MOCVD under the same conditions as in Comparative Example 2. The Al 2 O 3 insulating film was formed by sputtering.

  Further, a gate electrode 7 made of Pd / Ti / Au is formed at a predetermined position on the surface of the semiconductor multilayer structure 1 by a Schottky junction, and a source electrode 8 and a drain electrode 9 made of Ti / Au / Ni / Au are formed. An ohmic junction was formed to obtain a MOS type HEMT device.

  For the HEMT device thus obtained, a transconductance at room temperature of 30 mS / mm was obtained when the current density was 340 mA / mm, the threshold voltage was −0.5 V, and the gate length was 2 μm.

  From the above examples and comparative examples, the HEMT device and the MIS (MOS) type HEMT device according to the present embodiment have characteristics that are stable, have low interface states, and are significantly superior to those having a large threshold voltage. You can see that

DESCRIPTION OF SYMBOLS 1 Semiconductor laminated structure 2 Substrate 3 Underlayer (buffer layer)
4 First semiconductor layer (channel layer)
5 Two-dimensional electron gas region 6 Second semiconductor layer (electron supply layer)
7 Gate electrode 8 Drain electrode 9 Source electrode 10 Insulating film 11 Third semiconductor layer (conduction band edge adjusting layer)
DESCRIPTION OF SYMBOLS 101 Growth apparatus heater 102 Susceptor 103 Substrate with a semiconductor layer 104 Water vapor generating apparatus 105 Pure water 106 Water vapor pressure adjusting heater and cooling apparatus 107 Hydrogen gas inlet 108 Valve 1
109 Valve 2
110 Dew point measuring device 111 Valve 3
112 Insulating film growth device 113 Valve 4
114 Element A compound gas inlet 115 Valve 5
116 Element B Compound Gas Inlet 117 Valve 6
118 Valve 7
119 Gas exhaust port 120 Element X compound gas inlet port 121 Valve 8
122 Element A evaporation cell 123 Element A
124 Element A heater 125 Element B evaporation cell 126 Element B heater 127 Element B evaporation cell

Claims (7)

A substrate,
An underlayer as a buffer layer formed on the substrate;
A semiconductor layer group formed on the base layer,
The semiconductor layer group is
A first semiconductor layer as a channel layer composed of a single layer or multiple layers made of group III nitride;
A second semiconductor layer as an electron supply layer composed of a single layer or multiple layers made of a group III nitride having a band gap larger than that of the first semiconductor layer;
Is a manufacturing method of a semiconductor substrate laminated in this order from the base layer side,
A method of manufacturing a semiconductor substrate, wherein the buffer layer and the first semiconductor layer are formed by an MOCVD method, and the second semiconductor layer is formed by an MBE method. In the manufacturing method of the semiconductor substrate of Claim 1,
An insulating film containing an oxide is formed on the semiconductor layer group,
In the step of forming the insulating film containing the oxide,
When the elemental element or elemental compound constituting the oxide is deposited on the second semiconductor layer, the elemental element or elemental compound is oxidized by mixing water vapor into the hydrogen gas. A method for manufacturing a semiconductor substrate.   In the method of manufacturing a semiconductor substrate according to claim 2, when water vapor is mixed in hydrogen gas to oxidize a single element or an element compound, water vapor pressure is controlled by heating or cooling water, A method for producing a semiconductor substrate, comprising controlling an oxygen partial pressure when oxidizing a single element or a compound of an element. In the manufacturing method of the semiconductor substrate of Claim 1,
An insulating film containing an oxide is formed on the semiconductor layer group,
An insulating film containing the oxide is formed by an MBE method.   5. The method of manufacturing a semiconductor substrate according to claim 1, wherein a group III is used to control a position of a conductor between the second semiconductor layer and the insulating film containing the oxide. Forming a third semiconductor layer as a conduction band edge adjusting layer composed of a single layer or multiple layers made of nitride, and in this step, forming the third semiconductor layer by the MBE method. A method of manufacturing a semiconductor substrate.   6. The method of manufacturing a semiconductor substrate according to claim 1, wherein a single layer or multiple layers constituting the second semiconductor layer are formed in order to increase a current flowing through the first semiconductor layer. A method of manufacturing a semiconductor substrate, comprising adding an impurity. A method of manufacturing a semiconductor device, comprising forming a source electrode, a gate electrode, and a gate electrode on the semiconductor substrate according to claim 1.