JP2012009965A - Oscillation circuit operation state detecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oscillation circuit operation state detecting circuit for detecting an operation state of an oscillation circuit in a short time.SOLUTION: Between a power supply terminal of VDD and a power supply terminal of VSS, transistors MP1 and MN1 having a node N1 as a common connection point are connected in series and transistors MP2 and MN2 having a node N2 as a common connection point are connected in series. A capacity C1 is connected between the nodes N1 and N2. An input side of an NOR1 is connected to the nodes N1 and N2. A power source I1 is connected to the transistors MP1 and MN1 in series, and a power source I2 is connected to the transistors MP2 and MN2 in series. An OFF-resistance of the transistors MN1 and MN2 is made to be lower than that of the transistors MP1 and MP2. The oscillation circuit operation state detecting circuit turns on the transistors MN1 and MN2 and turns off the transistors MP2 and MN1 when an oscillation clock signal of an oscillation circuit is at a first logic level, and vice versa at a second logic level.

Description

  The present invention relates to an oscillation circuit operation state detection circuit that detects an oscillation state of an oscillation circuit.

  As a clock signal source for electronic equipment, an oscillation circuit using a crystal resonator is generally used. As long as a stable clock signal is not generated in the oscillation circuit, the electronic device cannot be operated normally. Therefore, as described in Patent Document 1, an additional circuit for monitoring the oscillation state is used in addition to the oscillation circuit. ing. In a small electronic device using a battery as a power source such as a portable terminal, power consumption is reduced by performing an intermittent operation in which the power is turned on only when necessary. In the intermittent operation, the power supply is frequently turned on / off, so the startup time from when the power supply is turned on to when the device can be used stably is required to be as short as possible.

  By the way, in most electronic devices, it is the clock signal source that needs to be activated first when the power is turned on. For this purpose, various oscillation circuits composed of ceramic resonators and crystal resonators are used according to the required accuracy. It is done. However, in any oscillation circuit, a stable oscillation output cannot be obtained immediately after the power is turned on. Therefore, it is necessary to keep the electronic device in a standby state until a stable oscillation output is obtained (oscillation start time). There is. Generally, a standby state of an electronic device is created by a delay reset circuit, a method of counting a certain number of generated clock signals, or the like.

JP-A-2-32413

  In this case, the standby state is always the worst case because the operation must be compensated for even if the oscillation start-up time fluctuates due to environmental conditions such as variations in elements constituting the oscillation circuit, ambient temperature, and power supply voltage. Set to time. For this reason, even under conditions where the oscillation startup time is relatively short, it is necessary to be in a standby state until the set time, and power that does not contribute to operation is consumed in the standby state.

  An object of the present invention is to provide an oscillation circuit operation state detection circuit that solves the above-mentioned problems.

In order to achieve the above object, according to a first aspect of the present invention, the first transistor is on the high potential power terminal side and the second transistor is between the high potential power terminal and the low potential power terminal. A third transistor is connected between the first and second transistors connected in series with the first node as a common connection point so as to be on the terminal side, and between the high potential power supply terminal and the low potential power supply terminal. The third and fourth transistors connected in series with a second node as a common connection point so as to be on the high potential power supply terminal side and the fourth transistor on the low potential power supply terminal side; A capacitor connected between a node and the second node, a gate circuit to which the potentials of the first node and the second node are input, and the first and second transistors connected in series 1 current source and a second current source connected in series to the third and fourth transistors, and the OFF resistances of the second and fourth transistors are the same as those of the first and third transistors. When the gate circuit is set to a value smaller than the OFF resistance, and a logical sum circuit or a logical sum negation circuit is used for the gate circuit, and the oscillation clock signal of the oscillation circuit is the first logic, the first and fourth transistors are The second and third transistors are turned off and the second and third transistors are turned off, and the first and fourth transistors are turned off and the second and third transistors are turned on in the second logic. Features.
According to the second aspect of the present invention, the first transistor is on the high potential power terminal side and the second transistor is on the low potential power terminal side between the high potential power terminal and the low potential power terminal. A third transistor on the high-potential power supply terminal side between the first and second transistors connected in series with one node as a common connection point, and between the high-potential power supply terminal and the low-potential power supply terminal The third and fourth transistors connected in series with the second node as a common connection point so that the four transistors are on the low potential power supply terminal side, the first node, and the second node; A capacitor connected between the gate, a gate circuit to which the potentials of the first node and the second node are input, a first current source connected in series to the first and second transistors, 3rd And a second current source connected in series to the fourth transistor, and the OFF resistances of the first and third transistors are set to be smaller than the OFF resistances of the second and fourth transistors. When the gate circuit uses an AND circuit or an AND circuit and the oscillation clock signal of the oscillation circuit is the first logic, the first and fourth transistors are turned on and the second and third transistors are turned on. In the second logic, the first and fourth transistors are turned off and the second and third transistors are turned on.

  According to the oscillation circuit operation state detection circuit of the present invention, since the activation of the oscillation circuit is detected by being operated by the actually generated clock signal, the waiting time until a stable clock signal is generated at the time of activation of the electronic device is reduced. It can be shortened to the minimum necessary, and low power consumption of electronic devices can be realized. Further, since the operation state of the oscillation circuit is not detected immediately when the clock signal is stopped, the operation stop of the oscillation circuit can also be detected.

1 is a circuit diagram of an oscillation circuit operation state detection circuit according to a first embodiment of the present invention. It is a circuit diagram of the oscillation circuit operation state detection circuit of the 2nd Example of this invention. FIG. 6 is a circuit diagram of an oscillation circuit operation state detection circuit according to a third embodiment of the present invention. FIG. 5 is an operation waveform diagram of the oscillation circuit operation state detection circuit of FIGS.

<First embodiment>
FIG. 1 shows an oscillation circuit operation state detection circuit 10 according to the first embodiment of the present invention. The oscillation circuit operating state detection circuit 10 includes a PMOS transistor MP1 and an NMOS transistor MN1 connected in series between a power supply terminal having a potential VDD and a power supply terminal (grounding terminal) having a potential VSS, with the node N1 as a common connection point, and a potential VDD. A PMOS transistor MP2 and an NMOS transistor MN2 connected in series between the power supply terminal and the power supply terminal of the potential VSS with the node N2 as a common connection point, a capacitor C1 connected between the nodes N1 and N2, and the nodes N1 and N2 An OR circuit NOR1 to which a potential is input, a current source I1 connected in series to the transistors MP1 and MN1, and a current source I2 connected in series to the transistors MP2 and MN2 are provided.

  The gates of the transistors MP1 and MN1 are connected to the non-inverting input terminal IN, and the gates of the transistors MP2 and MN2 are connected to the inverting input terminal INB. An oscillation clock signal of an oscillation circuit (not shown) is input to the non-inverting input terminal IN, and an inverted signal of the oscillation clock signal of the oscillation circuit is input to the inverting input terminal INB. The logical OR circuit NOR1 outputs a high level when both of the two input signals do not exceed the input threshold voltage, and the output becomes a low level when one or both of the input signals exceed the input threshold voltage. OUT is an output terminal OUT that outputs the detection result of the operating state of the oscillation circuit. The OFF resistances of the transistors MN1 and MN2 on the potential VSS side are set to be smaller than the OFF resistances of the transistors MP1 and MP2 on the potential VDD side.

  At time t0 in FIG. 4, when the oscillation circuit is stopped and a high level signal is input to the non-inverting input terminal IN and a low level signal is input to the inverting input terminal INB, the transistors MN1 and MP2 are in the ON state. The transistors MP1 and MN2 are turned off. At this time, a charge is charged from the current source I2 to the capacitor C1 via the transistor MP2 to increase the potential of the node N2, and the node N1 is discharged to the potential C1 via the transistor MN1 to become the potential VSS. Therefore, since the potential of the node N2 exceeds the input threshold voltage of the logical sum negation circuit NOR1, the output terminal OUT is at a low level.

  On the other hand, when the oscillation circuit is stopped and a low level signal is input to the non-inverting input terminal IN and a high level signal is input to the inverting input terminal INB, the ON / OFF state of each transistor is reversed. Charge is charged from the current source I1 to the capacitor C1 via the transistor MP1 and the potential of the node N1 rises, and the node N2 is discharged via the transistor MN2 to discharge the charge of the capacitor C1 to the potential VSS. Therefore, since the potential of the node N1 exceeds the input threshold voltage of the logical sum negation circuit NOR1, the output terminal OUT is similarly at a low level.

  As described above, when the oscillation circuit is stopped, the output terminal OUT of the oscillation circuit operation state detection circuit 10 is always at the low level regardless of the stop state.

  Next, at time t1 in FIG. 4, the oscillation circuit starts oscillating, and logic clock signals that are inverted to each other are input to the non-inverting input terminal IN and the inverting input terminal INB. At this time, the ON / OFF states of the MOS transistors are alternately switched, and charging / discharging of the capacitor C1 described at time t0 is repeated in the cycle of the clock signal.

  Since the OFF resistances of the transistors MN1 and MN2 are set to be smaller than the OFF resistances of the transistors MP1 and MP2, when the capacitor C1 is alternately charged and discharged, the nodes N1 and N1 due to the accumulated charges in the capacitor C1 are used. As the OFF resistance of the transistors MN1 and MN2 is smaller, the average potential of N2 is as close as possible to the potential VSS and does not exceed the input threshold voltage of the logical sum negation circuit NOR1, and the oscillation circuit operation state detection circuit The ten output terminals OUT are at a high level. The current values of the current sources I1 and I2 are preferably the same, but there may be some differences.

  Note that the potentials of the nodes N1 and N2 are not necessarily close to the potential VSS, and the charge / discharge time constant may be determined so as to be lower than the input threshold voltage of the logical sum negation circuit NOR1. Further, instead of the logical sum negation circuit NOR1, a logical circuit OR may be used.

  Next, at time t2 in FIG. 4, the oscillation circuit stops again, and the non-inverting input terminal IN and the inverting input terminal INB become high-level or low-level signals. At this time, similarly to the time t0, the potential of one of the nodes N1 and N2 rises and exceeds the input dark value voltage of the logical sum negation circuit NOR1, so that the output terminal OUT of the oscillation circuit operation state detection circuit 10 is at the low level. Thus, it can be detected that the oscillation circuit has stopped operating.

  With the above operation, even if the oscillation startup time changes due to environmental conditions such as variations in the elements that make up the oscillation circuit, ambient temperature, and power supply voltage, oscillation startup can be reliably detected in conjunction with the operating state of the oscillation circuit. There is no need to set the standby state as in the prior art. Further, the operation stop state of the oscillation circuit can be detected.

<Second embodiment>
FIG. 2 shows an oscillation circuit operation state detection circuit 20 according to the second embodiment of the present invention. In this embodiment, the PMOS transistors MP1 and MP2 in the first embodiment are replaced with NMOS transistors MN3 and MN4, and the respective gate terminals are connected to the inverting input terminal INB and the non-inverting input terminal IN. In this case, the OFF resistances of the transistors MN1 and MN2 on the potential VSS side are set to a value smaller than the OFF resistances of the transistors MN3 and MN4 on the potential VDD side.

  In general, the threshold voltage of a MOS transistor varies depending on environmental conditions such as manufacturing variations, ambient temperature, and power supply voltage. Further, in a semiconductor integrated circuit, when the circuit is composed of only a PMOS transistor or an NMOS transistor, the change in threshold voltage of each MOS transistor becomes relative in the same direction, and the influence on the circuit operation is small.

  Therefore, the oscillation circuit operation state detection circuit 20 of this embodiment is different from the oscillation circuit operation state detection circuit 10 of the first embodiment in which the PMOS transistor and the NMOS transistor are mixedly mounted, manufacturing variation, ambient temperature, power supply voltage, etc. More stable operation can be realized with respect to environmental conditions.

  In the second embodiment, only the NMOS transistor is used. However, only the PMOS transistor can be used, and the same effect can be obtained. Also in this case, the OFF resistance of the transistor on the potential VSS side is set to a value smaller than the OFF resistance of the transistor on the potential VDD side.

<Third embodiment>
FIG. 3 shows an oscillation circuit operation state detection circuit 30 according to a third embodiment of the present invention. In this embodiment, low pass filters LPF1 and LPF2 are inserted between the nodes N1 and N2 and the input side of the logical sum negation circuit NOR1 in the second embodiment shown in FIG.

In the second embodiment, during the period from the time t1 to the time t2 in FIG. 4, that is, the period when the clock signal is supplied from the oscillation circuit, the nodes N1 and N2 undergo potential fluctuations due to charging / discharging of the capacitor C1. In particular, the node N1 immediately after time t1 in FIG. 4 transitions from a high level to a low level with potential fluctuation. When this transition is near the input threshold voltage of the logical sum negation circuit NOR1, the output logic of the logical sum negation circuit NOR1 may vibrate due to potential fluctuation.

  Therefore, in this embodiment, the low-pass filters LPF1 and LPF2 are inserted between the nodes N1 and N2 and the logical sum negation circuit NOR1 to remove the fluctuations. Thereby, an unstable operation near the input threshold voltage of the logical sum negation circuit NOR1 can be avoided.

<Fourth embodiment>
In the first to third embodiments, the OFF resistance of the transistor on the potential VDD side (MP1, MP2, or MN3, MN4) is set smaller than the OFF resistance of the transistor on the potential VSS side (MN1, MN2). If set, the average potential of the nodes N1 and N2 due to the charge accumulated in the capacitor C1 rises as much as the potential VDD as the OFF resistance of the transistor on the potential VDD side is smaller. In this case, by using a logical product (AND) circuit or a logical product negation (NAND) circuit instead of the logical sum negation circuit NOR1, the operating state of the oscillation circuit can be changed in the same manner as in the first to third embodiments. Can be detected.

10, 20, 30: Oscillator circuit operation state detection circuit I1, I2: Current sources MP1, MP2: PMOS transistors MN1 to MN4: NMOS transistors C1: Capacitance NOR1: Logical sum negation circuit N1, N2: Node IN: Non-inverting input terminal INB: Inverting input terminal OUT: Output terminal LPF1, LPF2: Low-pass filter

Claims (2)

Using the first node as a common connection point between the high potential power supply terminal and the low potential power supply terminal so that the first transistor is on the high potential power supply terminal side and the second transistor is on the low potential power supply terminal side. Between the first and second transistors connected in series, and between the high potential power supply terminal and the low potential power supply terminal, a third transistor is on the high potential power supply terminal side, and a fourth transistor is the low potential power supply. The third and fourth transistors connected in series with the second node as a common connection point so as to be on the terminal side, and a capacitor connected between the first node and the second node; A gate circuit to which the potentials of the first node and the second node are input, a first current source connected in series to the first and second transistors, and the third and fourth transistors. And a second current source columns connected,
The OFF resistance of the second and fourth transistors is set to a value smaller than the OFF resistance of the first and third transistors, and an OR circuit or an OR circuit is used for the gate circuit,
When the oscillation clock signal of the oscillation circuit is at the first logic, the first and fourth transistors are turned on and the second and third transistors are turned off. When the oscillation clock signal is at the second logic, the first and second transistors are turned on. 4. An oscillation circuit operating state detection circuit characterized in that the fourth transistor is turned off and the second and third transistors are turned on. Using the first node as a common connection point between the high potential power supply terminal and the low potential power supply terminal so that the first transistor is on the high potential power supply terminal side and the second transistor is on the low potential power supply terminal side. Between the first and second transistors connected in series, and between the high potential power supply terminal and the low potential power supply terminal, a third transistor is on the high potential power supply terminal side, and a fourth transistor is the low potential power supply. The third and fourth transistors connected in series with the second node as a common connection point so as to be on the terminal side, and a capacitor connected between the first node and the second node; A gate circuit to which the potentials of the first node and the second node are input, a first current source connected in series to the first and second transistors, and the third and fourth transistors. And a second current source columns connected,
The OFF resistance of the first and third transistors is set to a value smaller than the OFF resistance of the second and fourth transistors, and an AND circuit or an AND circuit is used for the gate circuit;
When the oscillation clock signal of the oscillation circuit is at the first logic, the first and fourth transistors are turned on and the second and third transistors are turned off. When the oscillation clock signal is at the second logic, the first and second transistors are turned on. 4. An oscillation circuit operating state detection circuit characterized in that the fourth transistor is turned off and the second and third transistors are turned on.

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