JP2011501443A - 半導体装置メタルプログラマブルプーリング及びダイ - Google Patents
半導体装置メタルプログラマブルプーリング及びダイ Download PDFInfo
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- JP2011501443A JP2011501443A JP2010530099A JP2010530099A JP2011501443A JP 2011501443 A JP2011501443 A JP 2011501443A JP 2010530099 A JP2010530099 A JP 2010530099A JP 2010530099 A JP2010530099 A JP 2010530099A JP 2011501443 A JP2011501443 A JP 2011501443A
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- die
- tile
- design
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- die design
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/06—Structured ASICs
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- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
211…I/Oリング
213…コア論理機能
215…コーナー
513…第1タイル
515…第2タイル
517…第3タイル
519…第4タイル
611…I/Oリング
613…I/Oスロット
615…コーナ
617…PLL
619…論理ブロック
621、623…装置特定論理機能ブロック
625a〜c…オンチップメモリブロック
627…コアロジックインターフェース部
629…変換部
631、633…ドライバ/レシーバ部
711…第1タイル
713…第2タイル
715…第1信号経路
717…第2信号経路
811…第1タイル
813…第2タイル
815…第3タイル
817…第4タイル
819…第1信号経路
Claims (9)
- ダイの製造に用いられるダイデザインのプールを形成する方法であって、
メタルプログラマブルベース層を提供するためのダイデザインのプールを受け取り、
前記ダイデザインの前記プールの中にあるダイデザインが所望の機能を提供する場合に、ダイの製造に用いられるダイデザインを選択し、
前記ダイデザインの前記プールの中にあるダイデザインが所望の機能の十分なレベルを提供する場合に、ダイのカスタマイズ及び製造のためのダイデザインを選択することであって、前記所望の機能の十分なレベルが、前記ダイデザインのカスタマイズ後の機能の望ましいレベルである機能を有するレベルであり、
前記ダイデザインをカスタマイズし、
前記ダイデザインの前記プールの中に、カスタマイズされたダイデザインを追加すること
を含む方法。 - 前記ダイデザインをカスタマイズすることは、メタルプログラマブルブロックを前記ダイデザインに追加することを含む請求項1に記載の方法。
- 前記ダイデザインをカスタマイズすることは、メタルプログラマブルブロックを前記ダイデザインから除去することを含む請求項1に記載の方法。
- 前記ダイデザインの前記プールの中にあるダイデザインが、所望の機能又は所望の機能の十分なレベルを提供しないと判断することと、
ダイの製造に用いられるカスタムダイデザインを形成することであって、前記カスタムダイデザインがメタルプログラマブルベース層を提供し、所望の機能を提供するものであり、
前記カスタムダイデザインを、前記ダイデザインの前記プールへ追加すること
を更に含む請求項1に記載の方法。 - 前記カスタムダイデザインが、メタルプログラマブルブロックを含むライブラリを用いて形成される請求項4に記載の方法。
- 前記カスタムダイデザインが、メタルプログラマブル構成要素を含むライブラリを用いて形成される請求項4に記載の方法。
- 前記ダイデザインの前記プールが、マルチタイルダイデザインを含む請求項1に記載の方法。
- 前記マルチタイルダイデザインが、タイル間ダイ間通信を行うために、前記ダイデザインのI/Oスロットのメタライゼーションのために選択可能な構成要素を含む請求項7に記載の方法。
- マルチタイルダイであって、
単一のダイを形成するウエハのタイルを複数備え、
前記タイルのそれぞれがI/Oスロットを含み、
前記I/Oスロットの少なくともいずれかが、オフダイ電気信号通信を実現するか、又はダイ内電気信号通信を実現するかのいずれかを構成可能なベース層を含み、
前記ベース層がメタライザーションによって構成可能であることを特徴とするマルチタイルダイ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/874,164 US7882453B2 (en) | 2007-10-17 | 2007-10-17 | Semiconductor device metal programmable pooling and dies |
US11/874,164 | 2007-10-17 | ||
PCT/US2008/080096 WO2009052247A2 (en) | 2007-10-17 | 2008-10-16 | Semiconductor device metal programmable pooling and dies |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011501443A true JP2011501443A (ja) | 2011-01-06 |
JP5335800B2 JP5335800B2 (ja) | 2013-11-06 |
Family
ID=40564787
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010530099A Expired - Fee Related JP5335800B2 (ja) | 2007-10-17 | 2008-10-16 | 半導体装置メタルプログラマブルプーリング及びダイ |
Country Status (5)
Country | Link |
---|---|
US (2) | US7882453B2 (ja) |
JP (1) | JP5335800B2 (ja) |
CN (1) | CN101828187B (ja) |
TW (1) | TWI430122B (ja) |
WO (1) | WO2009052247A2 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7882453B2 (en) | 2007-10-17 | 2011-02-01 | Rapid Bridge Llc | Semiconductor device metal programmable pooling and dies |
US8030119B2 (en) * | 2008-03-08 | 2011-10-04 | Crystal Solar, Inc. | Integrated method and system for manufacturing monolithic panels of crystalline solar cells |
US8154053B2 (en) * | 2009-02-20 | 2012-04-10 | Standard Microsystems Corporation | Programmable metal elements and programmable via elements in an integrated circuit |
WO2011107612A1 (en) * | 2010-03-05 | 2011-09-09 | Imec | Customizable interconnections between electronic circuits |
US8701057B2 (en) * | 2011-04-11 | 2014-04-15 | Nvidia Corporation | Design, layout, and manufacturing techniques for multivariant integrated circuits |
US10839125B1 (en) * | 2018-09-24 | 2020-11-17 | Xilinx, Inc. | Post-placement and post-routing physical synthesis for multi-die integrated circuits |
US11238206B1 (en) | 2021-03-26 | 2022-02-01 | Xilinx, Inc. | Partition wire assignment for routing multi-partition circuit designs |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS587847A (ja) * | 1981-07-07 | 1983-01-17 | Nec Corp | 半導体装置 |
JPH0786537A (ja) * | 1993-09-16 | 1995-03-31 | Kawasaki Steel Corp | 半導体装置およびその製造方法 |
JPH09160941A (ja) * | 1995-12-04 | 1997-06-20 | Mitsubishi Electric Corp | エンベッデッドアレイ用レイアウト設計支援システム及びベースアレイのマスクデータ生成装置 |
Family Cites Families (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5225771A (en) * | 1988-05-16 | 1993-07-06 | Dri Technology Corp. | Making and testing an integrated circuit using high density probe points |
US7161175B2 (en) | 1997-09-30 | 2007-01-09 | Jeng-Jye Shau | Inter-dice signal transfer methods for integrated circuits |
US6209118B1 (en) * | 1998-01-21 | 2001-03-27 | Micron Technology, Inc. | Method for modifying an integrated circuit |
US6225143B1 (en) | 1998-06-03 | 2001-05-01 | Lsi Logic Corporation | Flip-chip integrated circuit routing to I/O devices |
US6181011B1 (en) * | 1998-12-29 | 2001-01-30 | Kawasaki Steel Corporation | Method of controlling critical dimension of features in integrated circuits (ICS), ICS formed by the method, and systems utilizing same |
US6356958B1 (en) * | 1999-02-08 | 2002-03-12 | Mou-Shiung Lin | Integrated circuit module has common function known good integrated circuit die with multiple selectable functions |
US6163068A (en) | 1999-04-22 | 2000-12-19 | Yao; Hsia Kuang | Multi-chip semiconductor encapsulation method and its finished product |
US6961919B1 (en) * | 2002-03-04 | 2005-11-01 | Xilinx, Inc. | Method of designing integrated circuit having both configurable and fixed logic circuitry |
US7224696B2 (en) * | 2002-06-10 | 2007-05-29 | Nortel Networks, Ltd. | Access nodes in packet-based communications networks |
US6992503B2 (en) * | 2002-07-08 | 2006-01-31 | Viciciv Technology | Programmable devices with convertibility to customizable devices |
US7673273B2 (en) * | 2002-07-08 | 2010-03-02 | Tier Logic, Inc. | MPGA products based on a prototype FPGA |
US6952814B2 (en) | 2002-11-20 | 2005-10-04 | Sun Microsystems Inc. | Method and apparatus for establishment of a die connection bump layout |
US6900538B2 (en) | 2003-06-03 | 2005-05-31 | Micrel, Inc. | Integrating chip scale packaging metallization into integrated circuit die structures |
US7002419B2 (en) * | 2003-09-15 | 2006-02-21 | Lsi Logic Corporation | Metal programmable phase-locked loop |
US20050166170A1 (en) * | 2004-01-26 | 2005-07-28 | Payman Zarkesh-Ha | Field programmable platform array |
US7032191B2 (en) | 2004-02-27 | 2006-04-18 | Rapid Bridge Llc | Method and architecture for integrated circuit design and manufacture |
US7337425B2 (en) * | 2004-06-04 | 2008-02-26 | Ami Semiconductor, Inc. | Structured ASIC device with configurable die size and selectable embedded functions |
US7424696B2 (en) * | 2004-12-03 | 2008-09-09 | Lsi Corporation | Power mesh for multiple frequency operation of semiconductor products |
US7750669B2 (en) * | 2005-01-06 | 2010-07-06 | Justin Martin Spangaro | Reprogrammable integrated circuit |
US7620924B2 (en) * | 2005-03-14 | 2009-11-17 | Lsi Corporation | Base platforms with combined ASIC and FPGA features and process of using the same |
US7373629B2 (en) * | 2005-04-25 | 2008-05-13 | Lsi Logic Corporation | Distributed relocatable voltage regulator |
US7259586B2 (en) * | 2005-04-27 | 2007-08-21 | Lsi Corporation | Configurable I/Os for multi-chip modules |
US7292063B2 (en) * | 2005-05-02 | 2007-11-06 | Lsi Corporation | Method of interconnect for multi-slot metal-mask programmable relocatable function placed in an I/O region |
US7305646B2 (en) * | 2005-05-09 | 2007-12-04 | Lsi Corporation | Relocatable mixed-signal functions |
US7478354B2 (en) * | 2005-05-20 | 2009-01-13 | Lsi Corporation | Use of configurable mixed-signal building block functions to accomplish custom functions |
US7243315B2 (en) * | 2005-05-31 | 2007-07-10 | Altera Corporation | Methods for producing structured application-specific integrated circuits that are equivalent to field-programmable gate arrays |
US7439731B2 (en) * | 2005-06-24 | 2008-10-21 | Crafts Douglas E | Temporary planar electrical contact device and method using vertically-compressible nanotube contact structures |
EP1907957A4 (en) * | 2005-06-29 | 2013-03-20 | Otrsotech Ltd Liability Company | INVESTMENT METHODS AND SYSTEMS |
US7310758B1 (en) * | 2005-08-22 | 2007-12-18 | Xilinx, Inc. | Circuit for and method of implementing programmable logic devices |
US7380232B1 (en) * | 2006-03-10 | 2008-05-27 | Xilinx, Inc. | Method and apparatus for designing a system for implementation in a programmable logic device |
US7627838B2 (en) * | 2006-04-25 | 2009-12-01 | Cypress Semiconductor Corporation | Automated integrated circuit development |
US8124429B2 (en) * | 2006-12-15 | 2012-02-28 | Richard Norman | Reprogrammable circuit board with alignment-insensitive support for multiple component contact types |
US7642809B2 (en) * | 2007-02-06 | 2010-01-05 | Rapid Bridge Llc | Die apparatus having configurable input/output and control method thereof |
US7882453B2 (en) | 2007-10-17 | 2011-02-01 | Rapid Bridge Llc | Semiconductor device metal programmable pooling and dies |
-
2007
- 2007-10-17 US US11/874,164 patent/US7882453B2/en not_active Expired - Fee Related
-
2008
- 2008-10-07 TW TW097138601A patent/TWI430122B/zh not_active IP Right Cessation
- 2008-10-16 CN CN2008801119608A patent/CN101828187B/zh not_active Expired - Fee Related
- 2008-10-16 WO PCT/US2008/080096 patent/WO2009052247A2/en active Application Filing
- 2008-10-16 JP JP2010530099A patent/JP5335800B2/ja not_active Expired - Fee Related
-
2011
- 2011-01-31 US US13/018,055 patent/US8392865B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS587847A (ja) * | 1981-07-07 | 1983-01-17 | Nec Corp | 半導体装置 |
JPH0786537A (ja) * | 1993-09-16 | 1995-03-31 | Kawasaki Steel Corp | 半導体装置およびその製造方法 |
JPH09160941A (ja) * | 1995-12-04 | 1997-06-20 | Mitsubishi Electric Corp | エンベッデッドアレイ用レイアウト設計支援システム及びベースアレイのマスクデータ生成装置 |
Also Published As
Publication number | Publication date |
---|---|
CN101828187A (zh) | 2010-09-08 |
WO2009052247A3 (en) | 2009-07-30 |
TWI430122B (zh) | 2014-03-11 |
US8392865B2 (en) | 2013-03-05 |
TW200939059A (en) | 2009-09-16 |
CN101828187B (zh) | 2012-11-21 |
US7882453B2 (en) | 2011-02-01 |
US20090106723A1 (en) | 2009-04-23 |
US20110121467A1 (en) | 2011-05-26 |
WO2009052247A2 (en) | 2009-04-23 |
JP5335800B2 (ja) | 2013-11-06 |
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