WO2011107612A1

WO2011107612A1 - Customizable interconnections between electronic circuits

Info

Publication number: WO2011107612A1
Application number: PCT/EP2011/053395
Authority: WO
Inventors: Marco Facchini; Paul Marchal; Wim Dehaene
Original assignee: Imec; Katholieke Universiteit Leuven
Priority date: 2010-03-05
Filing date: 2011-03-07
Publication date: 2011-09-09

Abstract

The present invention provides a method for creating electrical connections (304, 305, 309) between a plurality of electronic circuit tiles (110) on a same semiconductor die (308). The method comprises: selecting a plurality of electronic circuit tiles (110) for being diced together, i.e. in one block, from a wafer so as to create a die comprising multiple electronic circuit tiles (110); and customizing one or more electrically conductive layers of the created die to make electrical connections between the selected plurality of electronic circuit tiles (110). In doing so, a mask set of the plurality of electronic circuit tiles is defined separately from a mask set of the customized electrically conductive layer. The mask set of the plurality of electronic circuit tiles is kept fixed over a plurality of circuits formed by the circuit tiles while the mask set of the one or more electrically conductive layers is customized.

Description

Customizable interconnections between electronic circuits Field of the invention

The present invention is situated in the field of 3D or stacked integrated circuits. More specifically, the present invention is situated in the field of customizable interconnections between electronic circuits on the same or different dies.

Background of the invention

3D-stackable dies with a configurable interface

Emerging 3D-IC technologies extend the SoC (System-on-a-Chip) philosophy by manufacturing the system components on a number of separate dies arranged in a unique stack. Indeed, technologies like flip-chip bonding techniques and Through Substrate Vias (TSVs) enable closely and densely interconnecting stacked dies by creating direct electrical links (3D-links) between them. As an example only, FIG. 16 represents a two tiers 3D-stack 10, comprising a first die 11 and a second die 12, electrically interconnected to one another by means of TSVs 13 and solder bumps 14.

The communication between the dies in the stack, e.g. the first and second dies 11, 12 in the stack 10, can be as fast as on-chip routes, as described by M. Facchini et al, in "System-level power/perfo rmance evaluation of 3D stacked D AMs for mobile applications", Proc. IEEE DATE Ό9, pp.923-928, April 2009. The communication between the dies 11, 12 can achieve high throughput for low energy consumption, thus relaxing the placement constraints for the system components. Also, it is possible to produce the different dies using different specialized technologies, thus obtaining the best performances for every system component. As a consequence, die functional specialization (e.g. memory die and logic die) is attracting the interest of a large portion of the IC companies pursuing reduced costs and increased performances.

However, at least for not too large IC designs, producing a set of custom dies and bonding them together may be more expensive than producing a single SoC design. This is described by X. Dong and Y. Xie, in "System-level cost analysis and design exploration for 3D ICs", ASP-DAC 2009, pp.234-241, January 2009. One alternative is to develop products at least partly based on the same 3D-stackable dies, thus replacing the custom design costs with the lower cost for mapping the application on the systems-design components provided from the platform dies. By re-using a common set of dies, also the per-unit production cost for those dies is reduced by distributing on a larger number of produced units their design and process-mask-set development cost.

To further increase the re-usability of a 3D-stackable die, it can be provided with a configurable interface. This way the die can be adapted to a larger spectrum of system-design requirements and thus can be re-used for many more different system designs. Interface configurability can be obtained by customizing the signals' routing using some soft-controlled logic components or by physically re-route the signals to one or more desired system components. Re-usable memory dies

Memory design is nowadays approached in different ways according to the addressed level in the memory hierarchy.

Low latency memories (normally <lMbits, e.g. S AMs) are typically integrated in the same die as the processing units of the system. A number of them is normally generated so as to match the requirements of the system (number of bits, data port bit-width, etc.), thus they have heterogeneous characteristics i.e. each bank has different bit-width, dimension, speed, periphery logic, etc. They can be interconnected using low latency on-chip busses or switch-based cross-bars.

Using 3D-IC technology most of the on-chip SRAMs can be migrated to a specialized memory die. Research is looking to commoditize the memory die by using configurable signal-routing schemes. The commoditized memory die comprises many memory banks (tiles), which can be configured for and reused across multiple systems. As an example, to have a larger memory, a plurality of memories can be connected together e.g. 64kbit bank + 64kbit bank = 128kbit service.

The only published work in this regard is by H. Saito et al, "A Chip-Stacked Memory for On- Chip SRAM-Rich SoCs and Processors", Proc. IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp.60-61, February 2009. In that work the memory tier comprises uniform memory tiles connected between them with a fabric of interconnects. At each intersection, software configurable switches decide in which direction the signal must be routed (up, down, left, right). 3D gateways interconnect this switch-based network with a logic die. Each IP block contained in the logic die can be interconnected with a number of memory tiles from a single gateway by configuring the switch network. After re-configuration, each IP block may access only that given set of memories (or domain), propagating its own clock frequency. The performance of this configurable memory die is limited by the switch network. In practice, a signal may need to traverse several switch boxes before reaching the targeted memory cells. The accumulated delay limits the maximum access frequency of the configured memory, as described by M. Facchini et al, in " An RDL-Configurable 3D Memory Tier to Replace On-Chip SRAM", Proc. IEEE DATE Ί0, March 2010.

In contrast to the above, high latency memories (e.g. DRAMs) are already produced as commodity dies. A cheaper process is possible by personalizing the dicing of the DRAM wafer and cut a number of DRAM tiles simultaneously. However, each die contains a single memory tile. To connect a plurality of these between one another and/or to the rest of the system, the memory tiles are bonded on a supporting PCB or on an interposer, e.g. a silicon interposer, that is normally processed only for routing resources (high latency busses). However, the D AMs are separated by the scribe line (or saw street). In this zone, no metal processing is available to avoid circuital oxidation by lateral infiltration after wafer dicing. Therefore, the different DRAMs cannot be connected together using regular metal deposition but just using post-passivation metal routes.

Summary of the invention

It is an object of embodiments of the present invention to provide good interconnections between electronic circuits on the same or different dies.

The above objective is accomplished by a method according to embodiments of the present invention.

Embodiments of the present invention disclose a method to configure connections between a plurality of electronic circuits on a same die or on different die-cores diced as a unique single die, a die-core being a set of electronic circuits that on a not yet diced wafer are contained into a perimeter of scribe lines as to be individually diced. The configuration of the connectivity between the plurality of electronic circuits is determined in accordance with embodiments of the present invention according to the application that is targeted. The invention permits the user to customize an electronic circuit design by personalizing part of the connections between a plurality of electronic circuit tiles. An electronic circuit tile is defined as a set of electronic circuits individuated as a unique block accessible from a set of well defined l/Os, e.g. a memory macro. Also an electronic circuit tile is already designed and a process-mask-set for processing on semiconductor wafers, e.g. silicon wafers, is already largely or fully available (fixed) except for a few masks corresponding to some electrically conductive, e.g. metal, routing layers that are left to be customized. The electronic circuit tiles can be located into a same die-core or into different die-cores.

A method according to particular embodiments of the present invention allows to create customized connections between a plurality of electronic circuit tiles fully processed and available on a same semiconductor wafer, e.g. silicon wafer. In this case the processing-mask-set is fully fixed and defined for the wafer production till after the passivation of the back-end routing. The wafer is mapped according to application requirement, which means that a plurality of die-cores (comprising electronic circuit tiles) is selected to be diced together (in a single block) to create a die with multiple electronic circuit tiles. Exposed (passivation openings) I/O contacts of the electronic circuit tiles can be interconnected to package, but can also be interconnected amongst each other via one or more redistribution layers (RDLs), being post-passivation electrically conductive, e.g. metal, layers. RDL can be added before or after dicing and can bridge the routing between tiles of different die-cores across saw streets. The method according to embodiments of the present invention enables to design a customized electronic integrated circuit design, assembled from a plurality of electronic circuit tiles from one or from more die-cores.

In one aspect, the present invention provides a method for creating electrical connections between a plurality of electronic circuit tiles on a same semiconductor die, e.g. silicon die. The method comprises:

- selecting a plurality of electronic circuit tiles for being diced together, i.e. in one block, from a wafer so as to create a die comprising multiple electronic circuit tiles; and

- customizing one or more electrically conductive, e.g. metal, layers of the created die to make electrical connections between the selected plurality of electronic circuit tiles. In doing so, a mask set of the plurality of electronic circuit tiles is defined separately from a mask set of the customized electrically conductive, e.g. metal, layer. The mask set of the plurality of electronic circuit tiles is kept fixed over a plurality of circuits formed by the circuit tiles while the mask set of the one or more electrically conductive layers, e.g. metal layers, is customized.

In a method according to embodiments of the present invention, selecting a plurality of electronic circuit tiles for being diced together comprises selecting electronic circuit tiles from a plurality of die-cores. This allow generating interconnections between separate die-cores.

A method according to embodiments of the present invention may furthermore comprise actually dicing the wafer so as to keep the selected plurality of electronic circuit tiles together in the die. The tiles may be part of different die-cores, hence the created die may comprise a plurality of die- cores.

In embodiments of the present invention, said electronic circuit tiles may be low latency memory circuits such as SRAM banks or any other configurable low latency memory type. In alternative embodiments of the present invention, said electronic circuit tiles may be high latency memory banks such as DRAM, RRAM, ZRAM, FLASH or any other type of external memory.

In a method according to embodiments of the present invention, customizing one or more electrically conductive layers, e.g. metal layers, may comprise customizing pre-passivation electrically conductive, e.g. metal, layers. In a method according to embodiments of the present invention, customizing one or more electrically conductive layers, e.g. metal layers, may comprise customizing post-passivation electrically conductive layers, e.g. metal layers. In a method according to embodiments of the present invention, customizing one or more electrically conductive layers, e.g. metal layers, may comprise customizing both pre-passivation and post-passivation electrically conductive layers, e.g. metal layers.

A method according to embodiments of the present invention may furthermore comprise using the created die as an interposer routing in between other dies or between a die and a package.

In particular methods according to embodiments of the present invention, customizing one or more electrically conductive layers, e.g. metal layers, may comprise customizing a redistribution layer.

A method according to embodiments of the present invention may furthermore comprise using the customized electrically conductive layers, e.g. metal layers, for forming interposing connections.

In one application, a method according to embodiments of the present invention can be used to interconnect a plurality of low latency memory circuits on one die (SRAM banks or any other configurable low latency memory type). If the memory circuits are located on one die-core, the customized connections between the different memory circuits can be created using either pre- or post-passivation routing layers. A post-passivation layer may be a redistribution layer (RDL). A redistribution layer can also be used to customize connections between different low latency memory circuits on different die-cores.

In another application, a method according to embodiments of the present invention can be used to interconnect a plurality of high latency memory circuits distributed on different die-cores (such as DRAM, RRAM, ZRAM, FLASH or any other type of external memory). To create the connections between the memory circuits of different dies post-passivation routing layers (RDL) may be used.

In an application of the invention, the designer can create a 3D stacked IC whereby one layer of the stack is dedicated to memory circuits forming a memory layer. The memory circuits may be connected to each other via a customized routing layer (being a post- or pre-passivation electrically conductive layer, e.g. metal layer). The memory layer may be connected to other layers of the 3D stacked IC via micro-bumps ^bumps), TSVs, or any other means.

In an application of the invention the configurable die may also be used as an interposer between two 3D-stacked dies or between some dies and the package.

In an application of the invention, the customized electrically conductive layers, e.g. metal layers, may be used, not only for configuring the die, but also for the interposing connections between dies and to the package. Using a method according to embodiments of the present invention, switch boxes can be avoided, while configuring once and for all the interface to the die and to the different memory tiles according to specific system requirements.

The routing required for personalizing the interface can then be added directly onto the DRAM interface. It can then be customized by using a method according to embodiments of the present invention. Thus, in accordance with embodiments of the present invention, one or more electrically conductive layers, e.g. metal layers, of the multiple-tiles DRAM die interface can be configured.

Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not merely as explicitly set out in the claims.

For purposes of summarizing the invention and the advantages achieved over the prior art, certain objects and advantages of the invention have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

The above and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.

Brief description of the drawings

The invention will now be described further, by way of example, with reference to the accompanying drawings, in which:

FIG. 1 shows a sectional view of one possible 3D-stack configuration: two dies arranged into a 3D-stack face to back. The interconnections between the two dies' active layers are realized through TSVs (109), RDL traces (106 - 107) and micro-bumps (108). One of the RDL traces (106) creates a short-circuit between the l/Os of three electronic circuit tiles (110) that thus are accessible from the logic die (102) using the same micro-bump (108).

FIG. 2 shows how a monolithic SoC design becomes a 3D-SoC with per-die functional specialization: memories can be on a dedicated tier of the stack. The tier can be configurable. FIG. 3 shows a sectional view of a fully processed semiconductor die, e.g. silicon die, that has been configured by customizing the routing of the last pre-passivation metal routing layer.

FIG. 4 shows a sectional view of a fully processed semiconductor die, e.g. silicon die, that has been configured by RDL deposition.

FIG. 5 shows a wafer populated with dies and a sectional view of the zone in between two dies that have been configured to be accessed together by depositing an RDL trace across the saw streets (dashed edges)

FIG. 6 shows a sectional view of a system in package, where many dies (a plurality of memory dies and a logic die) are packaged together and interconnected by means of metal traces printed on an interposer.

FIG. 7 shows a sectional view of a system in package, where two memory cores have been diced to have a single die with an area sufficiently large to replace the passive interposer with an active interposer, e.g. active silicon interposer, made of the memory dies itself.

FIG. 8 shows a configurable die before (a) and after (b) the application of the RDL layer in accordance with embodiments of the present invention. An RDL layer is used to interconnect a plurality of electronic circuit tiles. The inserted routings (connections) can e.g. be different memory connection, using the same single RDL.

FIG. 9 illustrates an example where a single RDL layer is used to short circuit memory banks to place them in parallel/series. The RDL layer is also used to dispose micro-bump landing pads on a larger surface (as the TSV pitch is much smaller than the micro-bump pitch).

FIG. 10 illustrates an example where 2 RDL layers are used to short circuit memory banks. This permits 2 users to access the four memory banks.

FIG. 11 illustrates another example where one or more layers are used to short circuit the memory banks.

FIG. 12 shows the total power consumption in the commodity memory tier for a considered design study-case. For this estimation a 0.2 toggling activity probability on the processor input pins is supposed.

FIG. 13: Simple matrix arrangement (a) blocks routing possibilities of today's RDL. Arranging the l/Os in arrays (b), RDL can be freely routed across adjacent memory l/Os.

FIG. 14: Configuring a 4x8-grains commodity tier as four separate memories. RDL pitch may limit horizontal routing. Each separate route has to be connected to a micro-bump (not shown).

FIG. 15: Complete horizontal routing is possible for certain memory grain choices. 2048w x 16b banks (a) allows horizontal routing on RDL while a 2048w x 32b (b) does not. FIG. 16 represents a two tiers 3D-stack, comprising a first die and a second die, electrically interconnected to one another by means of TSVs and solder bumps.

The drawings are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not necessarily correspond to actual reductions to practice of the invention.

Any reference signs in the claims shall not be construed as limiting the scope.

In the different drawings, the same reference signs refer to the same or analogous elements. Detailed description of illustrative embodiments

The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.

Moreover, the terms top, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein.

It is to be noticed that the term "comprising", used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

Similarly it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination.

It should be noted that the use of particular terminology when describing certain features or aspects of the invention should not be taken to imply that the terminology is being re-defined herein to be restricted to include any specific characteristics of the features or aspects of the invention with which that terminology is associated.

Following terminology is used throughout the present description:

A commoditized die is a die which re-usable in a large number of system designs. It can be configurable.

A configurable die is die that can offer different services and/or performances according to actual configuration of e.g. logic and interconnects. Configurability can be used to enable commodity.

A die-core is a set of electronic circuits that, on a not yet diced wafer, are contained into a perimeter of scribe lines for being individually diced.

An electronic circuit tile is defined as a set of electronic circuits individuated as a unique block accessible from a set of well defined l/Os e.g. a memory macro.

A semiconductor interposer, e.g. a silicon interposer, is a bare or minimally processed semiconductor die, e.g. silicon die, used as a support to compose different system semiconductor dies, e.g. silicon dies. The dies are bonded or glued to the interposer which is often processed with metal or other conductive traces required to interconnect the different dies. Also the interposer may typically be used to create package contacts. A semiconductor, e.g. silicon, interposer is more expensive than PCBs, which are nowadays preferred as an interposer.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

The following detailed description explains various features of various embodiments in detail. The invention can be embodied in numerous ways as defined and covered by the claims. In order to clarify certain parts of this description some concepts will be better illustrated with reference to the practical examples of memory circuits (configurable memory dies) also intended as a possible embodiment of the invention, the present invention, however, not being limited to memory circuits.

In accordance with embodiments of the present invention, a method is provided to produce configurable dies (e.g. configurable memory dies) at low cost by customizing one or more conductive layers, e.g. metal layers, while maintaining the rest of the process-mask-set fixed. Hence, only the mask set for the conductive layer, e.g. metal layer, is customized. In particular, one example will be described where the system-design is separated into a custom logic tier 200 and a commodity, e.g. configurable, memory tier 201, as illustrated in FIG. 2.

In one aspect, the present invention provides a method to configure connections between a plurality of electronic circuits by customizing one or more conductive, e.g. metal, layers. Customization is accomplished by creating (or not creating), hence the presence or absence of creating, an electrical connection between two different electrically connectable points (such as e.g. creating a conductive path between two die l/Os exposed through passivation openings). The customizable electrically conductive layers, e.g. metal layers, which may be routing layers in embodiments of the present invention, can be a standard pre-die-passivation metal layer or a post- passivation metal layer (in specific embodiments the DL - ReDistribution Layer). In accordance with embodiments of the present invention, one or more routing layers (pre- or post- passivation) of a semiconductor, e.g. silicon, wafer can be customized to configure the interconnections between different electronic circuit tiles.

A particular type or routing layer according to embodiments of the present invention, an RDL layer, is a conductive layer, e.g. a plated routing metal layer, that is commonly used to interconnect die l/Os with package l/Os, which are often not compatible in terms of required routing pitch and materials. In a 3D-stack, an RDL can also be used to create an electrical connection between dies having a different distribution of interface l/Os. An DL may be provided by surrounding a contact, such as e.g. a bond pad or an I/O, with a dielectric layer, then overlaying the contact and part of the dielectric layer with a conductive layer (e.g. a Ti/Cu/Ni stack), and then protecting the conductive layer with a second dielectric layer where no electrical contact needs to be made, thus covering the original contact and leaving exposed the conductive layer of the new (redistributed or relocated) contact.

An RDL has advantageous electrical characteristics such as low capacitance and low resistance compared to standard (pre-passivation) metal layers. Therefore this routing layer can be used to make long metal traces with reduced delay and capacitive penalty. Today, RDLs are processed by the packaging houses rather than foundries. As a result, they are processed at relatively low cost, but with limited precision (pitch limited to 10 um).

Electronic circuit tiles in embodiments of the present invention comprise or consist of sets of electronic circuits comprising active devices and interconnects, e.g. a memory bank macro is an electronic circuit tile.

The electronic circuits of each electronic circuit tile may either be arbitrarily distributed on a wafer area or they may be confined into a region where only the circuits of that tile are present. As an example, a memory bank macro is a tile with a unique semiconductor substrate-area, e.g. silicon- area, assignation. Tiles to be processed on a same wafer can be different from one another. Also tiles designed to be into a same die-core can be different between them. Here a die-core is intended as a set of electronic circuits that on a wafer that has not been diced yet are contained into a perimeter of scribe lines as to be individually diced.

Also an electronic circuit tile is already designed and a process-mask-set for processing the design on semiconductor, e.g. silicon, wafers is already largely or fully available (fixed). Only few mask-sets, corresponding to few electrically conductive layers, e.g. metal routing layers, are left undefined as to be customized according to the specific customer (application) requirements.

Two main embodiments of the present invention can be identified:

1. A first main embodiment of the present invention comprises or consists of configuring dies populated with electronic circuit tiles by customizing one (or more) conductive interconnection layers, e.g. metal layer(s). The interconnection layers, e.g. metal layer(s), can for example be pre- or post-passivation metal layers.

2. A second main embodiment of the present invention comprises or consists of making configurable dies by personalizing the wafer dicing and using a post-passivation metal layer (e.g. RDL) to create the connections between the different electronic circuit tiles and from the electronic circuit tiles to the system.

Reference is made to FIG. 3 to better illustrate the general concept of embodiments of the present invention by describing a specific embodiment. FIG. 3 shows a sectional view of a fully processed configurable semiconductor die 308, e.g. silicon die, configured with a customized pre- passivation conductive routing layer, e.g. routing metal layer 320, in accordance with embodiments of the present invention. The die 308 is produced on a wafer using fully fixed mask-sets, except for the one conductive routing layer mask set, e.g. routing metal layer mask-set, that is customized. Therefore, a fully fixed set of mask-sets is provided for processing the active region 307 of the die containing the front-end devices, as well as a partly fixed set of mask-sets for processing the routing in the back-end 306 (321 is the fixed part). Also the mask for the passivation 302 is fixed, thus exposing contacts in passivation openings 303 at standardized positions. In this case the openings 303 are filled with any suitable material 304 for making an electrical contact, e.g. some metal that does not substantially oxidize. The die has three identical electronic circuit tiles 110. One of the tiles 110 (the one illustrated at the right hand part of the illustration) is shown mirrored with respect to the others to stress the fact that this is a simple example and that, in general, electronic circuit tiles can be heterogeneous both for electronic circuits disposition and composition. While they can be designed freely, it is assumed within the context of the present invention that this designing has already been done, and the production-mask-set is fixed and available. In accordance with embodiments of the present invention, illustrated for the case of FIG. 3, the routing layer 320 is customized to short-circuit the shown I/O of the three tiles. As a result, by sending a signal on any of the three shown l/Os 304 the signals propagates in parallel to all three circuit tiles 110.

More in general, in accordance with embodiments of the present invention, the customized routing layer 320 may be used to create short-circuits between different I/O ports of different electronic circuit tiles 110 on a same die 308. The I/O ports can be on the front side (by means of openings in the passivation layer) or on the back side (by means of TSVs) of the die 308. Different I/O ports may be short-circuited according to customer design requirements, typically following some compatibility pattern. As an example, the clock pin Clk of one memory bank may be short-circuited with the clock pin Clk of another memory bank, the write enable pin WE of a memory bank may be short-circuited with the write enable pin WE of another memory bank, and so on. Some more customized option can be done. For example, if Tilel is a memory bank with 16 data l/Os and Tile2 is another memory bank with 32 data l/Os, it may be desired to short-circuit the data pins DataBl<0> to DataBl<15> of the first memory bank with data pins Data B2<0> to Data B2<15> of the second memory bank, or optionally connect the data pins Data B1<0> to DataBl<15> of the first memory bank with data pins Data B2<16> to Data B2<31> of the second memory bank.

When short-circuits are created between two or more ports, it may be desired to be able to discriminate between the accesses addressed to one or another tile. Tile selection can be done in accordance with embodiments of the present invention if a tile address is encoded or a TileEnable signal is provided. As an example, a configurable memory die may require distribution of a bank address or of some BankEnable signals (which is normally already present in memory macros). In the first case a tile address decoder may be placed on the memory die (tile identification ID can be unique or configurable), while in the second case it may be placed on the logic die (requiring the BankEnable signals to be connected to the logic die singularly). If configurable, the tile IDs can be programmed with logic-registers or by hard-coding using again short-circuits to be created with the same customized electrically conductive layer, e.g. metal layer.

The configurable routing layer, e.g. the DL, can be created on the configurable die or (with a potential larger load penalty) on the interfacing die.

FIG. 4 shows another specific embodiment of the present invention. The figure shows a sectional view of a fully processed configurable semiconductor die 308, e.g. silicon die, configured with a customized post-passivation (RDL) routing conductive layer, e.g. metal layer 305. The die 308 may be produced using fully fixed mask-sets for front-end 307, back-end 306 and passivation layer 302. The routing layer processing, e.g. RDL processing, in accordance with embodiments of the present invention requires an additional fully customized mask-set. The conductive routing layer 305, e.g. RDL, creates a short-circuit between the I/O of a plurality of circuit tiles 110. An extra passivation layer 301 may optionally be added and at some location the conductive routing layer 305, e.g. the RDL trace, may be exposed to contact at one contact 309 to access the conductive routing layer 305, e.g. RDL trace, from outside.

FIG. 5 shows another specific embodiment derived from the second of the two main embodiments introduced above. Here the customized routing layer, e.g. RDL connections 305, are not created between tiles of a same die-core 51 but between different die-cores 51 (optionally comprising multiple tiles 110) that are already processed as they should be separately diced. This implies that the processed wafer 52 containing the die-cores 51 is fully processed including the saw- streets 53 separating the different die-cores.

Saw streets 53 (also called scribe-lines) are substrate, e.g. silicon, areas devoid of back-end electrically conductive material, e.g. metal, processing and often also devoid of front-end processing to provide a secure sawing zone by avoiding post-sawing oxidations of electrically conductive material, e.g. metal. However, the dicing of a wafer 52 can be personalized e.g. creating dies 55 six times bigger than the core grain, including six die-cores 51 on a same diced die 55. As an example, for configurable memory dies, this is equivalent to have six times more memory space available on a six time bigger die 55. The saw streets 53 are processed on the wafer 52 as this is assumed to be a wafer 52 produced on large volumes (commoditized).

However, once the wafer dicing map 54 is defined it is allowed to process electrically conductive material, e.g. metal, on those saw streets 53 that are not going to be sawn because of the production of dies 55 comprising a plurality of die-cores 51. Therefore, a post-passivation conductive routing 305 (e.g. DL) can be customized and added to route across the die-cores 51, bridging the routing over those saw streets 53. The conductive routing 305, e.g. RDL, can be processed before or after the wafer 52 is diced according to the dicing map 54.

The number of ports available for each tile 110, their position, their I/O characteristics and the number of customizable electrically conductive routing layers, e.g. metal routing layers, in accordance with embodiments of the present invention affect the configuration flexibility. In FIG. 5, as an example only, a way is shown to use a single customized routing layer 305, e.g. RDL can be used to connect a plurality of single-port memory banks to a user having a single interface port.

In FIG. 6 an example is illustrated whereby two memory dies 604 are interconnected via one or more RDL layer(s) 605 in accordance with embodiments of the present invention. The RDL layers 605 are electrically connected with an interposer substrate 602 via solder bumps 601. A connection with a logic die 603 is realized via the interposer substrate 602.

In accordance with embodiments of the present invention, the tiles' access ports can be placed away from, e.g. not close to, the corresponding tile 110 so as to improve routing resources usage and connectivity. FIG. 7 illustrates a same die configuration as in FIG. 6 whereby a different disposition of the memory access ports is obtained (701 being a logic die, 702 being memory dies, 703 being one or more RDL layers according to embodiments of the present invention, and 704 being solder bumps).

A die configured in accordance with embodiments of the present invention (in case of both main embodiments 1 and 2) can be used as an active interposer, e.g. a silicon interposer, as long as the die has enough area to support the package.

An interposer, e.g. a silicon interposer, typically has no front-end processing, thus carrying substantially only, e.g. only, the conductive, e.g. metal, routing required to adapt the l/Os of the die(s) bonded to the interposer to the package l/Os. For this reason, as of today cheap poly-silicon interposers are preferred. However, interposer routing can be done on the surface of a semiconductor die, e.g. silicon die, containing active devices (front-end processing). For this routing an extra specialized post- passivation routing layer can be added. However, it is possible to re-use the same customized routing layer, e.g. RDL layer, according to embodiments of the present invention both to configure the electronic circuit tile 110 and to create the connections required for packaging. However, there must be sufficient routing resources available on that routing layer. This is the case for instance when we have a die 55 comprising one or more die-cores 51 being individual large memory bank tiles with an access port occupying little area compared with the memory bank total area (e.g. DRAM, ZRAM, Flash, etc.). Indeed, in case those ports must be configured (short-circuited) to receive the same signals, the required routing will occupy just a little fraction of the available area. In general large tiles with little interface ports are good candidates to be used as the packaging semiconductor, e.g. silicon, interposers.

The die can contain extra on-chip configurability and still adopt the electrically conductive layer, e.g. metal, customization for further "one-time configurability", every time this represents a system benefit. Multiple dies can be stacked and configured together or separately.

A ReDistribution Layer (RDL) is also normally used into a 3D-stack of dies. In particular in this case, the good electrical characteristics of the RDL allow to establish low latency communication between different dies of the same 3D-stack. While connecting the dies of the stack, the RDL can also take care of configuring a configurable die optionally present in the 3D-stack.

FIG. 1 shows another embodiment of a die according to embodiments of the present invention. The die according to embodiments of the present invention is used in a 3D-stack. The 3D stack illustrated comprises a fully custom die 102 and a commoditized configurable die 101, as an example only comprising four electronic circuit tiles 110 and 111. The figure shows the bulk of the dies 104 and the fully processed part of the dies 103 including back-end and front-end. The commoditized die contains Through Substrate Vias (TSV's) 109, being vertical conductive channels allowing creating the I/O access ports to the tiles 110, 111 on the backside of the die 101. Both front side and backside of the dies have passivation 105 but TSVs 109 are exposed to establish electrical connection with the bottom die 102.

As an example, the bottom die 102 requires to propagate the same signal to the three tiles 110 of the configurable die 101. Therefore, in accordance with embodiments of the present invention, a routing layer, e.g. an RDL routing 106 and 107, is processed on the backside of the die 101 to short-circuit the access port of the three tiles 110 and to extend the link to the tile 111 to the same level of the routing layer, e.g. RDL 106. Finally micro-bumps 108 may be used to connect any exposed part of the configurable routing layer, e.g. DL, traces with the correct ports of the bottom die 102.

This configuration can be thought of for die specialization and for creating configurable low and high access-latency memory dies.

ONE-TIME CONFIGURABLE COMMODITY MEMORIES (THROUGH RDL)

In a design according to embodiments of the present invention, a memory layer also comprises different memory grains. Rather than using switch-boxes, in accordance with embodiments of the present invention these memories are interconnect using a configurable routing layer, e.g. an RDL layer. In FIG. 1 the cross-section of one possible RDL-configured 3D-stack according to embodiments of the present invention is shown.

Excellent electrical characteristics of the RDL limit the additional access delay, requiring only minor changes during the system physical design. By creating appropriate short-circuits between the memory grains l/Os, they can be configured to work as a single unit with a wider word-width or a larger memory space. However, today the ΙΟμιτι pitch of the RDL limits routing flexibility. This puts significant floor-planning constraints and thus performances restrictions. Also the size of the memory influences performances and routing flexibility.

A. Commodity floor-plan matched with today's RDL

To describe and illustrate the floor-plan in accordance with embodiments of the present invention, a homogeneous memory grain with 128 words of 32 bits each is assumed (FIG. 13), while the effect of different grain size will be described. In FIG. 13a a regular organization of the memory tier 130 is shown, with l/Os 131 placed in a minimum pitch matrix close to each respective grain 132. This solution has minimum wiring requirement on the memory tier 131; however, it cannot be customized with today's RDL. Indeed, the width of an RDL routing trace is too large to allow routing in between the I/O contacts, thus isolating the l/Os inside the matrix. Multiple layers RDL would hardly solve this limitation. For this reason the floor-plan represented in FIG. 13b is proposed in accordance with embodiments of the present invention. Here, the l/Os of each memory grain 132 are arranged in a mono-dimensional array 135a, 135b, 135c, 135d. The mono-dimensional arrays 135a, 135b, 135c, 135d become normally longer than the long side of the grain 132 itself. For this reason a number of I/O arrays is placed side-by-side (I/O island) as in FIG. 13b.

In this scenario, the regular electrically conductive, e.g. metal, routing to/from l/Os may be obstructed from other memories' routing. However, in the specific case considered in FIG. 13b full connectivity can still be guaranteed having four electrically conductive, e.g. metal, layers (TSMC90nmG technology) available, including the one occupied from the I/O contact. In general, it is preferred to have the number of electrically conductive, e.g. metal, layers minimised. However, for each case a specific number of electrically conductive, e.g. metal, layers are required to guarantee full connectivity.

Also, buffering is required because of the long metal routing all along the l/Os array. The relative performances overhead will be quantified in the result section. In case a 3D-stack scenario is considered where TSVs are not in the memory tier, then the l/Os are passivation openings. Thus, one could place them over the memory macros, saving considerable quantity of substrate area, e.g. silicon area. However, routing requirements may limit the area savings. Also this arrangement requires additional metal routing layers, which add extra production cost, reducing benefits from area.

B. Customizing commodity memory routing on a single RDL

In FIG. 14 the RDL routing according to embodiments of the present invention is shown which may be used to configure a 4x8 commodity memory tier into four memories of given different characteristics. The four memories illustrated are a first memory 140 of 256 words of 64 bits each, a second memory 141 of 1024 words of 32 bits each, a third memory 142 of 384 words of 20 bits each and a fourth memory 143 of 512 words of 64 bits each. Adjacent memory l/Os are short-circuited in accordance with embodiments of the present invention to use them as unique memory area with wider bit-width or with larger memory space. To obtain a wider word-width, several memories have to work in parallel, thus their address, command and clock l/Os will be short-circuited while not their data l/Os. To obtain a larger addressing space also the data l/Os may be short-circuited while a user has to be able to address only one of the memory grains. To this purpose one option is not to short- circuit the different memory enable l/Os. In this way it is possible to select the desired memory grain with a dedicated signal, thus avoiding adding extra decoding on the commodity memory die. As this is a commodity product, one may not need all the resources available as in the case it is required a word-width narrower then the grain size. Also some memory grains 144 may be left unused, leaving their l/Os unconnected and thus automatically isolated from the RDL deposition process in accordance with embodiments of the present invention.

Memory grain size may limit the RDL routing possibilities. Indeed, the spacing between two parallel I/O islands is proportional to the height of the memory grain. Thus, the large pitch of the RDL may not allow complete routing between aligned I/O islands. However, it could still be possible to route the address, command and clock signals Also the logic die routing resources or an additional DL layer can be used to complete the routing of the data signals. If the RDL has a lower pitch, less routing constraints exist. Also, for significant pitch reductions the 3D l/Os can be placed in a more area efficient way, for example an array as indicated in FIG. 13a. In this case, no buffers need to be inserted between the 3D I/O pads and the memory port, resulting in lower power and delay.

C. Trade-offs in memory grain size

The commodity memory tier is designed for a specific application domain. Thus, the type of memory grain used is chosen mainly considering how to efficiently map the average domain memory requirements on the commodity memory tier. This decision involves several trade-offs in terms of configuration flexibility, performances and floor-plan feasibility. Power consumption and memory access delay are sensibly affected from the dimension of the memory grain port. Indeed, a large number of l/Os requires long electrically conductive, e.g. metal, routes to interconnect them to the memory port and thus more buffering. For instance the I/O array 150 of a memory with a word of 16 bits (FIG. 15a) is 39% shorter than the equivalent I/O array 151 of a memory with the double of the word-width (FIG. 15b). This allows for a faster access to the memory and a sensible power penalty reduction to access the memory grain. However, more banks in parallel will be required to satisfy wider word-width requirements, increasing again the power consumption for memory access.

Also, memory grain dimensions influence the overall commodity tier organization. Indeed, small memory grains require to align more memory together to obtain an area effective layout (compare FIG. 15 with FIG. 13). This could result in conductive routing, e.g. metal routing, congestions, thus less area efficiency. Moreover, since the memories in an embedded system have normally various characteristics, choosing a heterogeneous set of memory grains for the entire commodity memory may be more performance efficient than an homogeneous choice. Finally, one could choose multiple grains of different size as well as grains of different performances or different characteristics (case study described below).

ONE EXEMPLARY EMBODIMENT: CONFIGURABLE MEMORY DIES

A configurable memory die according to embodiments of the present invention can be made by placing a number of memory banks on a same die. The die can then be configured by interconnecting the memory banks with one (or more) customized routing layers in accordance with embodiments of the present invention.

1. In a first main embodiment of the invention (as described above), configurable low latency memory dies (SRAM or future technologies) can be made by customizing only one (or more) conductive layers, in particular conductive interconnect layers, e.g. metal layer(s). Conductive layers, in particular conductive interconnect layers, such as metal layer(s) can be pre- or post-passivation.

2. In a second main embodiment of the invention (as described above), configurable DRAM (or any other memory e.g. FDRAM, ZRAM, FLASH, etc.) can be made by personalizing the wafer dicing and using a post-passivation conductive layer, in particular conductive interconnect layer, e.g. metal layer (RDL) to create the connections between the different memories and from the memories to the system.

For both embodiments, the memory banks that are present on the single die do not need to be all the same (they can differ in size, interface, peripheral and internal circuitry, etc.). The die can host any other system component (e.g. controllers, interconnecting circuitry and logic, BIST engine or other system components).

Regarding the second embodiment: High latency memories (e.g. DRAMs) are already produced as commoditized dies. Each DRAM die contains a single DRAM core and it is typically interconnected to the rest of the system using high latency busses running on PCBs or on silicon interposers. A number of DRAM dies are then addressed in parallel to satisfy the system band-width requirements. However, this connection requires several dies to be bonded on a supporting interposer which is processed just for routing resources.

A cheaper process is possible by using the DRAM dies as interposer. However, the dimensions of a die containing a single DRAM core are limited. To have a unique large support one can personalize the dicing of the DRAM wafer by selecting a number of DRAM cores to be part of the same die. The DRAM cores can be connected again personalizing one or more electrically conductive, e.g. metal, routing layers. However, as the DRAM wafer was manufactured to separately dice all the DRAM, scribe lines (or saw street) are present to separate the different DRAM cores. Along the scribe lines and in their proximity no electrically conductive, e.g. metal, layers' processing is allowed to avoid circuital oxidation by lateral infiltration after wafer dicing. Therefore the different DRAMs cannot be connected together using regular electrically conductive, e.g. metal, deposition. However, they can be connected together by using post-passivation metal layer said RDL. CASE STUDY

A. Tier-arrangement scenarios

During the case study exploration, four different memory tier organizations are compared with a reference single-tier scenario. The interconnections for each of these scenarios are modeled as in FIG. 7.

1) Custom memory tier: The memory macros are just lifted from the logic die to a dedicated memory die, generating a customized memory tier;

2) Switch-boxes (re-configurable): Logic switch boxes are integrated in the tier to provide run-time re- configurability;

3) Back-side metallization ( DL): TSVs are integrated into the memory tier thus the RDL is created under the bulk of the silicon die. This is a specific case of a routing solution, e.g. RDL solution, according to embodiments of the present invention (FIG. 13b). In particular this is the worst case capacitive load on the interface because it requires a TSVs set for each memory grain and a micro- bumps set for each connection to the logic die.

4) Improved routing, e.g. RDL, on back-side metallization (Multi layers RDL with better pitch): It is the same as the third scenario; however the routing technology, e.g. RDL technology, is supposed to be improved to support finer routing pitch. This enables the memory organization to be the one represented in FIG. 13a, which requires less buffering thus providing better performances.

B. Design case and layout characteristics

The different tier-arrangement scenarios have been applied to a subsystem of the AVC H263, an MPEG video compression standard. For scenarios 2, 3 and 4 a heterogeneous commodity memory tier mapped as in Table 1 is assumed.

Two different memory grains with the same word width (32 bits) have been chosen. This is because it is desired to analyze the scenario 2 supposing a single on-chip network, thus requiring a homogeneous word-width. Also in that scenario it may be prohibitive to use wider words because of the required additional routing, logic cells and thus area resources. This would bring both power consumption and substrate, e.g. silicon, production cost to grow significantly. On the other side, the effect of a using 64 bit word-width grains in the scenario 3 (RDL) has been tested, experiencing no significant performance changes with respect to the 32 bit case. This is not necessarily the case for different design cases. It is to be noted that our design case has many small memories while few big ones. Mapping them on small grains, the area consumed to floor-plan the memory l/Os is relevant with respect to the total memory area. For this reason bigger memory grains would rather be chosen, and they would be used more efficiently. Also multiplexing/serialization solutions may help to reduce l/Os count but it would compromise power consumption. Table 1: MAPPING THE MEMORY MACROS OF THE CASE STUDY DESIGN ON THE COMMODITY

MEMORY. ALL MACROS HAVE A SINGLE ACCESS PORT

Advantages and performance

a) Commodity allows for better technology scaling

Today's SoC-ICs are produced using a technology optimized for both SRAM and logic. 3D- technology enables per die technology optimization, leading to improved performances and/or reduced production cost. Additionally, commodity design enables for cheap technology scaling.

Indeed, the cost of an IC mask set doubles every technology node. However, commodity products are used for a whole class of applications, sinking the higher mask set and machinery not-recurrent costs on a large volume of production.

Scaling the commodity memory reduces required area as well as power consumption while the speed of the SRAM accesses increase. These improvements are thus made available also for designs intended for low production volumes, which cannot afford the price of new technologies. In Table 2 the cost per chip is shown, estimated using the four memory tier scenario described above.

Also the effect of scaling on the routing RDL scenario in accordance with embodiments of the present invention is shown.

For estimating the logic die cost the production cost of a typical fab processing for large volumes has been used, applied to the cost model. Also the TSV processing cost and the mask-set cost projected on a production of 20M dies have been included. The cost of the memory die is the same as for a commodity memory (.028$/mm² -market spot price for 3 metal-layer DRAM memory). The routing scenario, e.g. RDL scenario, according to embodiments of the present invention becomes economically more efficient than the 2D scenario. Also the effect related to a different choice of the memory grain is shown. In this case the word-width of the memory grains has been doubled.

Table 2: COST PER CHIP

All values are expressed in $ per die

^* = includes mask cost (.031 $) and stacking cost (.041 $)

*^* = we use memory grain size with the double of the capacity

*^** = custom memory shows higher price/mm²

b) Performances

In Table 3 the access delay for the three commodity scenarios is shown, compared with reference scenario (single macro).

Table 3: ACCESS DELAY FOR THE MAIN TWO SCENARIOS. ALL MEMORIES HAVE 32BIT WORDS. THE MEMORY USED FOR THE TWO COMMODITY SCENARIO IS THE 2K WORDS. THE MATRIX IS 4X4

MEMORIES.

extimated values

increased buffer strenght to access memory tier

= horizontal RDL limited, thus routing on logic Table 3 shows that increasing the mapped memory area leads to higher interconnect penalty. Also in that case the advantage of using RDL scenarios (3 and 4) in accordance with embodiments of the present invention increases compared to the switch-box based scenario. Also it is noted that for memories larger than the one of the case study the RDL scenario in accordance with embodiments of the present invention may result in even better performances than a unique memory macro, thanks to the really low capacitance and resistance values of the redistribution layer routing.

The addressing space of the memories included in the study case design matches the addressing space of the commodity grains. This results in the best case delay penalty for commodity scenarios. For this reason timing violations are not observed in any of the studied scenarios. Incrementing the word width does not influence significantly the access delay, unless extra routing on the logic die is required to route together the different accessed l/Os. In FIG. 12 is shown the total power consumption of the entire memory tier for the different scenarios.

The reference scenario corresponds to the power consumed from the memories if placed on the logic die. The custom memory tier (scenariol) is adding only the TSV + micro-bump capacitance and the required buffering. This 14% increment of power is thus the price to pay for extracting those memories from the logic die using the 3D technology described before.

The switch box scenario consumes 56% more power than the reference scenario. This is mainly due to the extra logic and wiring required to route this kind of memory tier. Also there is a power penalty related to the use of multiple grains to map the required word-width. Eliminating the switch-boxes via the back-side metallization in accordance with embodiments of the present invention (scenario 3) reduces the power overhead to 41%. Most of this overhead is caused by the buffering required for signal routing on the long conductive, e.g. metal, routes. This is visible by looking at scenario 4 power consumption (only 24% overhead), which differs from scenario 3 mainly in its buffering requirements.

Power consumption may be further reduced with technology scaling. An SRAM in 65 nm technology is expected to consume less than the 80% of the corresponding SRAM in 90 nm technology. Thus, using 45 nm technology for the RDL scenario (3) according to embodiments of the present invention ends up consuming less power than the reference 2D scenario (FIG. 12). As discussed above, the use of advanced technologies for the commodity SRAM does not necessarily imply the use of these technologies also for the logic die. c) Conclusion

To illustrate an embodiment of the invention, a low latency, power efficient and flexible 3D- stacked commodity memory tier is described. The design organization is suited to be customized using an inexpensive routing, e.g. RDL, layer. Simulations show up to 40% faster access time to the memory tier and 10% less power consumption with respect to other solutions from literature. Also the design according to embodiments of the present invention reveals to be economically advantageous with respect to the 2D case if scaling to 45 nm is available for the commodity tier.

Claims

1. - A method for creating electrical connections (304, 305, 309) between a plurality of electronic circuit tiles (110) on a same semiconductor die (308), the method comprising:

- selecting a plurality of electronic circuit tiles (110) for being diced together from a wafer (52) so as to create a die (55) with multiple electronic circuit tiles (110); and

- customizing one or more electrically conductive layers of the created die (55) to make electrical connections between the selected plurality of electronic circuit tiles (110), a mask set of the plurality of electronic circuit tiles (110) being defined separately from a mask set of the customized electrically conductive layer.

2. - The method according to claim 1, wherein selecting a plurality of electronic circuit tiles for being diced together comprises selecting electronic circuit tiles from a plurality of die-cores.

3. - The method according to any of the previous claims, furthermore comprising dicing the wafer

(52) so as to keep the selected plurality of electronic circuit tiles (110) together in the die (55).

4.- The method according to any of the previous claims, wherein said electronic circuit tiles are low latency memory circuits.

5. - The method according to any of claims 1 to 3, wherein said electronic circuit tiles are high latency memory banks.

6. - The method according to any of the previous claims, wherein customizing one or more electrically conductive layers comprises customizing pre-passivation electrically conductive layers.

7. - The method according to any of the previous claims, wherein customizing one or more electrically conductive layers comprises customizing post-passivation electrically conductive layers.

8.- The method according to any of the previous claims, furthermore comprising using the created die (55) as an interposer routing in between other dies or between a die and a package.

9.- The method according to any of the previous claims, wherein customizing one or more electrically conductive layers comprises customizing a redistribution layer.