JP2011240158A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide game machine monitoring the condition of a power source when power supply is started, which is configured such that when the power source has an abnormal condition, the condition of the power source is monitored again after a predetermined period passes without increasing the program capacity and cost.SOLUTION: A CPU 56 confirms a power off signal in main processing, and confirms the power off signal again after a predetermined time (time-out time) passes, when the power off signal is not off. A VDP 109 executes an alpha test or alpha blending using alpha values set in pixels for image data, and a decoration symbol images are gradually and stepwisely changed during variable display. Further, based on a command from a symbol control CPU 101a, the VDP 109 previously stores image data of a component image frequently used from a CGROM 83 to a VRAM 84 when the VDP is actuated; and the image data is read out from the VRAM 84 for rendering when display is updated.

Description

  The present invention displays a plurality of types of effect images including a plurality of types of identification information that can identify each of them and establishes a variable display start condition after a predetermined variable display execution condition is satisfied. The present invention relates to a gaming machine that includes variable display means for performing variable display of identification information based on the game information, and that shifts to a specific gaming state that is advantageous to the player when the display result of variable display of identification information becomes a specific display result.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Furthermore, a variable display device capable of variably displaying the identification information (also referred to as “fluctuation”) is provided, which is advantageous to the player when the display result of the variable display of the identification information becomes the specific display result in the variable display device. Some are configured to be controllable to a specific gaming state.

  The specific game state means a state advantageous for a player who is given a predetermined game value. Specifically, the specific game state is, for example, a state in which a special variable winning device is advantageous for a player who is likely to win a ball (a big hit game state), or a state in which a right to become advantageous for a player In this state, a predetermined game value such as a state where conditions for paying out premium game media are easily established is given.

  In such a gaming machine, the fact that the display result in the variable display device that displays the special symbol as the identification information becomes a combination of specific display modes (specific display result) determined in advance is called “big hit”. When the big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state where the hit ball is easy to win. And in each open period, if there is a prize for a predetermined number (for example, 10) of the big prize opening, the big prize opening is closed. And the number of times the special winning opening is opened is fixed to a predetermined number (for example, 15 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and even if the number of winnings does not reach a predetermined number, the big winning opening is closed when the opening time elapses. Further, when a predetermined condition (for example, winning in a V zone provided in the big prize opening) is not established at the time when the big prize opening is closed, the big hit gaming state is configured to end. Sometimes.

  In addition, in the variable display device, the symbols other than the symbol that will be the final stop symbol (for example, the middle symbol of the left and right middle symbols) continue for a predetermined time and stop, swing, and expand in a state that matches the specific display result. The possibility of big hits continues before the final result is displayed due to a reduced or deformed state, or multiple symbols changing synchronously with the same symbol, or the position of the display symbol changing. An effect performed in a state in which the player is in a state (hereinafter, these states are referred to as reach states) is referred to as reach effect. Further, the reach state and the state thereof are referred to as a reach mode, and the reach state is referred to as reach establishment. Furthermore, variable display including reach production is called reach variable display. In the reach state, the interest of the game is enhanced by making the variation pattern different from the variation pattern in the normal state. Then, when the display result of the symbols variably displayed on the variable display device does not satisfy the condition for reaching the reach state, the state is “missed” and the variable display state is terminated. A player plays a game while enjoying how to generate a big hit.

  Patent Document 1 below monitors the state of the power failure detection signal when the power is turned on, loops the monitoring process until the power failure detection signal becomes a non-power failure detection state, and prevents the control state from proceeding. A structured gaming machine is disclosed.

  Further, in Patent Document 2 below, when reaching reach, when the fighter plane approaches the door constituted by symbols in the variable display device, the door opens and a new symbol is displayed behind it. A gaming machine in which a variable display of symbols is performed by repeating various image displays is disclosed.

  Also, in Patent Document 3 below, when reaching, the rightmost symbol display area is divided into two, and each area portion (upper left half and right lower half) is read from the character ROM. After overlaying the image and expanding the image, and masking the lower right half of the upper image to make it transparent, and then scrolling the image of the pattern in each area part in a different direction without interlocking A gaming machine that stops fluctuation and displays a stop symbol is disclosed.

  Further, in Patent Document 4 below, when power supply to the gaming machine is started, frequently used image data stored in the CGROM is decoded in advance and stored in a predetermined area of the VRAM (SDRAM). There is disclosed a gaming machine having a configuration in which image data is transferred and used to display image data stored in a predetermined area as needed.

JP 2001-190743 A (0052, FIG. 5) JP-A-9-131434 (0041-0045, FIG. 7) JP 2002-136698 A (0050, FIG. 10, FIG. 11) JP 2004-201859 A (0126-0129, FIG. 20)

  In the gaming machine described in Patent Document 1, when the state of the power failure detection signal is the non-power failure detection state, the process of monitoring the state of the power failure detection signal is repeatedly executed, but the state of the power failure detection signal is immediately monitored. Even so, the state of the signal may not change. For this reason, it is preferable to perform the monitoring process again after a certain period of time, because the state of the power failure detection signal can be monitored with a relatively stable voltage. However, in order to execute the monitoring process after a predetermined period in the process by software, it is necessary to create a program for that purpose (a program for delaying the monitoring process). Therefore, the capacity of the program executed when the power is turned on increases accordingly. Further, in order to execute the monitoring process after a predetermined period of time by specially providing a hardware circuit, the cost for providing the circuit is required.

  In addition, in the gaming machines described in Patent Documents 2 and 3, when the variable display of the final stop symbol is performed in the reach state, the next symbol is suddenly displayed instead of gradually changing the symbol. Therefore, it cannot be said that the player's expectation for the big hit is given, and the effect of the variable display of the symbols is not sufficiently enhanced.

  Furthermore, in the gaming machine described in Patent Document 4, control is performed in advance to transfer image data frequently used for image display from CGROM to VRAM. For image data that is not frequently used for image display, Then, control for transferring the image data from the CGROM to the VRAM is executed when the image is displayed. At this time, the CPU on the production control side is configured to perform an instruction to transfer image data (image data that is not frequently used) from the CGROM to the VRAM and an instruction to transfer image data from the VRAM to the frame buffer to the VDP. The CPU must instruct the VDP twice, which increases the control burden.

  Therefore, the present invention provides a gaming machine that monitors the state of the power supply when power supply is started, and the predetermined period has elapsed when the power supply state is abnormal without increasing the program capacity and cost. An object of the present invention is to provide a gaming machine that can monitor the state of a power supply again later.

  In addition, the present invention provides a gaming machine that can improve the effect of the variable display of identification information, improve the fun of the game, and reduce the control burden associated with the transfer of image data. Objective.

The gaming machine according to the present invention displays an image display of a plurality of types of effect images (for example, a decorative symbol image, a background image, a character image, etc.) including a plurality of types of identification information (for example, decorative symbols) that can be identified. In addition, after a predetermined variable display execution condition is satisfied (for example, a game ball is won at the start winning opening 14), a variable display start condition is satisfied (for example, final stop of special symbol and jackpot game) The variable display means (for example, the variable display device 9) for performing variable display of the identification information based on the end of the identification information) is provided, and the display result (for example, stop symbol) of the variable display of the identification information is the specific display result (for example, jackpot symbol) A gaming machine (for example, pachinko gaming machine 1) that shifts to a specific gaming state (for example, a big hit gaming state) that is advantageous to the player when After executing a predetermined initial setting process (for example, the process of steps S1 to S16), a game control process for controlling the progress of the game (for example, a process of steps S21 to S36 based on a timer interrupt: In the embodiment, the game control process is executed by the timer interruption process, but may be executed in the main process (for example, the game control microcomputer 560 including the CPU 56). And an electric component control microcomputer (for example, the symbol control microcomputer 100a including the symbol control CPU 101a) that gives a command for controlling the display operation of the variable display means, and the state of a predetermined power source used in the gaming machine. That the detection condition related to the stop of the power supply to the gaming machine is satisfied (for example, + 30V) Power supply monitoring means (for example, power supply monitoring circuit 920) that outputs a detection signal (for example, power-off signal) based on the fact that the voltage value of the source has decreased to + 22V), and measures a predetermined monitoring time (for example, timeout time) Timer means (e.g., watch dog timer 60) for resetting, and reset means (e.g., game control microcomputer 560 for resetting the game control microcomputer when the monitoring time is measured by the timer means) A built-in reset / interrupt controller 502), and image display control means (for example, VDP 109, CGROM 83, VRAM 84) for controlling the image display of the effect image on the variable display means in response to a command from the electric component control microcomputer. , Equipped with a microcomputer for game control The initialization processing means (for example, the game control microcomputer 560) periodically executes an initialization process for initializing the time measured by the timer means in a period shorter than the monitoring time in the game control process. The portion that executes step S36 in FIG. 4) and the variation data that can store the variation data that varies according to the progress of the game, even if the power supply to the gaming machine is stopped Power supply for storing data necessary for restoring the control state based on the output of the detection signal from the storage means (for example, the RAM 55 backed up by the power supply) and the power supply monitoring means Power supply stop time processing execution means for executing the stop time processing (for example, step S in the game control microcomputer 560) 50 to S481) and standby state transition means for transitioning to a standby state in which initialization processing is not performed after the power supply stop process is completed (for example, steps in the game control microcomputer 560) A part that executes an infinite loop process after S481) and a detection signal determination unit that determines whether or not a detection signal is output from the power supply monitoring unit when a predetermined initial setting process is executed (for example, A part for executing step S83 in the game control microcomputer 560), and a standby state transition unit for transitioning to a standby state in which the initialization process is not performed when the detection signal determination unit determines that the detection signal is output. (For example, infinite loop processing is performed after step S83 in the game control microcomputer 560. And an initial setting process starting means for starting a predetermined initial setting process from the standby state (for example, for game control) based on the resetting by the reset means when the standby state is entered. When the microcomputer 560 determines that the detection signal is not output by the detection signal determination means (the part that executes the process of starting the main process from step S1 based on the output of the timeout signal) (Y in step S83) ) Power supply start process for restoring the control state to the state before the power supply stop process is executed based on the stored contents stored in the fluctuation data storage means on condition that a predetermined recovery condition is satisfied Power supply start processing means for executing (for example, steps S7 to S9 in the game control microcomputer 560) , S91 to S93) and pre-determining means for determining whether or not the variable information display result of the identification information is set as the specific display result according to the establishment of the variable display start condition (for example, the game control micro The computer 560 executes step S56B), and the electric component control microcomputer determines display contents of the variable display means based on the determination result of the predetermination means (for example, the symbol control microcomputer 100a). The image display control means includes an image data storage means (for example, CGROM 83) for storing a plurality of types of image data including image data corresponding to the effect image, and an image display control means. Temporary storage means for temporarily storing image data read from the data storage means ( For example, a fixed address area 155A and an automatic transfer area 155B in the VRAM 84 and a plurality of areas including a specific storage area (for example, an automatic transfer area 155B) as a storage area in the temporary storage means corresponding to the activation of the electric component control microcomputer Based on the storage area setting command transmitted from the symbol control CPU 101a in the storage area setting command process of step S772, the drawing control unit 91 of the VDP 109 performs the storage area setting process of step S903. A portion to be executed), a transfer control means for controlling the transfer of the image data read from the image data storage means to the temporary storage means (for example, a part for which the drawing control unit 91 of the VDP 109 executes the transfer control process), a temporary Image data temporarily stored in the storage means Based on the display data creation means for creating the display data of the effect image in the variable display means (for example, the part where the drawing control unit 91 of the VDP 109 executes the drawing process) and the display data created by the display data creation means Display data storage means for storing data (for example, a frame buffer 156 in the VRAM 84; the frame buffer may be a storage means different from the VRAM 84), and display data read from the display data storage means Display data output means for outputting to the variable display means (for example, the display signal control unit 87 in the VDP 109), and the display content determination means stores the image data after the storage area is set by the storage area setting means. A rendering image corresponding to the image data among a plurality of types of image data stored in the means High-frequency image data (for example, an image of a decorative pattern or a background image) whose frequency of image display execution by an image is higher than the frequency of image display by an effect image corresponding to required image data is specified in the temporary storage means Start-up data transfer command means (for example, the part for which the symbol control CPU 101a executes the pre-transfer command process in step S773) for instructing transfer to an area other than the area (for example, fixed address area 155A), and reading of image data A display image update command means (for example, a command for updating the display image in the variable display means by notifying the image display control means of the position (eg, read address) and the write position (eg, write address) in the display data storage means) The symbol control CPU 101a executes the display update command processing of step S1841). The transfer control means reads the high-frequency image data from the image data storage means and transfers it to an area other than the specific storage area in response to a command from the startup data transfer command means (for example, drawing of the VDP 109 A portion where the control unit 91 executes the advance transfer process in step S905), and when the image data read-out position notified from the display image update command means is included in the image data storage means, the image from the read position in the image data storage means Normal data transfer means for reading out data and transferring it to a specific storage area in the temporary storage means (for example, the part where the drawing control unit 91 of the VDP 109 executes the automatic transfer control processing in step S907) and the image data storage means Display color data of each pixel constituting the effect image of the identification information (for example, R Image data reading means for reading image data including G and B color data (for example, a portion where the drawing control unit 91 of the VDP 109 executes the advance transfer process in step S905, or an automatic transfer control process in step S907) And control data setting means (for example, VDP 109) for setting control data (for example, an alpha value) for controlling the display operation of the identification information corresponding to the image data read by the image data reading means. The drawing control unit 91 includes the alpha test drawing process of step S1007 and the alpha synthesis process of step S1011 (of which the steps S1121 and S1122 are executed), and the display data creation means is the normal data transfer means. After the image data is transferred to the specific storage area by The first image display control means (for example, the drawing control section 91 of the VDP 109 causes the fixed address designation display in step S1003 to be read and stored in the writing position in the display data storage means notified from the display image update command means. A portion for executing processing) and when the image data read position notified by the display image update command means is included in the temporary storage means, the image data is read from the read position in the temporary storage means and notified from the display image update command means Second image display control means (for example, the part in which the drawing control unit 91 of the VDP 109 executes the automatic transfer display process in step S1005) for writing and storing in the writing position in the displayed display data storage means. The image display control means or the second image display control means is read by the image data reading means. Based on the image data and the control data set by the control data setting means, the display data of the display data is displayed so that the effect image of the identification information for which variable display is being executed is displayed or erased in stages over time. It is characterized by including stage display update means (for example, a part in which the drawing control unit 91 of the VDP 109 executes the alpha test process in step S1009 or the alpha synthesis process in step S1011) for performing the update. The temporary storage means only needs to have a faster reading speed of stored data than the image data storage means.
According to such a configuration, the state of the power supply can be confirmed again after a predetermined period when the state of the power supply is abnormal without increasing the program capacity and cost.

  In addition, the stage display update unit updates the display data so that the display image of the identification information is displayed or deleted step by step with time. As a result, it is possible to execute visually variable display of identification information, and it is possible to improve the presentation effect in variable display of identification information.

  Further, among the multiple types of image data, for the high-frequency image data indicating the component image set so that the display frequency on the variable display means is high, the start-up data is transmitted in response to a command from the start-up data transfer command means. The data transfer means reads from the image data storage means and transfers it to an area other than the specific storage area in the temporary storage means. When the display of the component image indicated by the high-frequency image data is instructed by the display image update command means, the high-frequency image data read from the read position in the area other than the specific storage area by the first image display control means Is written and stored in the writing position in the display data storage means. On the other hand, for the low frequency image data indicating the component image set so that the display frequency is lower than the component image shown in the high frequency image data, according to the command from the display image update command means, The normal data transfer means reads from the reading position in the image data storage means and transfers it to the specific storage area in the temporary storage area, and the second image display control means reads out the low frequency image data from the specific storage area and stores the data for display. It is written and stored in the writing position in the means. Thus, for low-frequency image data, if the reading position in the image data storage means and the writing position in the display data storage means are specified, the display data can be stored without specifying the storage position in the temporary storage area. It can be used for creation, can reduce the control burden of the electric component control microcomputer, facilitates address management, and can reduce the burden of program design. On the other hand, for high-frequency image data, the data already stored in the temporary storage means can be easily reused by designating the reading position in the temporary storage area, and it is necessary to read out from the image data storage means every time. Therefore, the control burden on the display effect can be reduced.

The display content determination means transfers the high-frequency image data to an area other than the specific storage area in the temporary storage means on condition that a predetermined transfer condition is satisfied after the game is started (for example, Y in step S1811). Including a post-game data transfer command means (for example, a portion where the symbol control CPU 101a executes the pre-transfer command process in step S1814), and the transfer control means responds to a command from the post-game data transfer command means. Thus, after the game start data transfer means for reading the high-frequency image data from the image data storage means and transferring it to an area other than the specific storage area (for example, based on the advance transfer command transmitted in the advance transfer command process in step S1814, The drawing control unit 91 of the VDP 109 includes a part that executes the advance transfer process of step S905). It may be with.
According to such a configuration, the image data is newly stored in an area other than the specific storage area in the temporary storage unit at a predetermined timing, and data obtained by storing the image data in the temporary storage unit for a long time. The possibility of the occurrence of noise corruption or the like can be reduced, and even if the data noise corruption or the like occurs, it can be automatically restored to the correct data.

The image display control means is a data management means for managing the image data transferred from the image data storage means to the temporary storage means by the start time data transfer means and the normal time data transfer means (for example, the drawing control unit 91 of the VDP 109 performs step S946). The data management means indicates that the transfer has been completed when the image data instructed by the display image update instruction means is stored in the temporary storage means from the image data storage means. Transfer completion data (for example, transfer completion flag) is set (for example, the transfer completion flag is set to ON in the index table in steps S946 and S966), and the display data creation means is provided on the condition that the transfer completion data has been set. Display data (for example, the drawing control unit 91 of the VDP 109 completes the transfer). Flag to perform a drawing processing when on) may be configured so.
According to such a configuration, all the image data necessary for the effect image is not transferred (expanded) in the temporary storage means, but the image data is not expanded in the display data storage means. Transfer can be synchronized, and incomplete image data can be prevented from being developed from the temporary storage means to the display data storage means.

The high-frequency image data is classified into a plurality of types of patterns and stored in the image data storage means (for example, image data that is frequently used for each production mode is stored in the CGROM 83), and the display content determination means is: A pattern different from the pattern of the high-frequency image data stored in the area other than the specific storage area in the temporary storage means on condition that a predetermined switching condition is satisfied after the game is started (for example, Y in step S1864). Transfer-time data transfer command means for commanding transfer of the high-frequency image data to an area other than the specific storage area (for example, the part where the symbol control CPU 101a executes the pre-transfer command process in step S1867), and transfer control In response to an instruction from the switching data transfer instruction means, the means transfers the high-frequency image data from the image data storage means. The data transfer means at the time of switching for transferring and transferring to an area other than the specific storage area (for example, the drawing control unit 91 of the VDP 109 performs the advance transfer in step S905 based on the advance transfer command transmitted in the advance transfer command process in step S1867. It may be configured to include a part for executing processing).
According to such a configuration, an area other than the specific storage area in the temporary storage unit can be used effectively, and the control burden can be reduced to the maximum.

The power supply stop process execution means creates check data (for example, a checksum) based on the stored contents of the fluctuation data storage means as data for restoring the control state in the power supply stop process, and the fluctuation data Including check data creation means (for example, a part for executing steps S454 to S463 in the game control microcomputer 560) to be stored in the storage means, based on the check data stored in the fluctuation data storage means. The memory determination means (for example, the part which performs step S9 in the game control microcomputer 560) for determining whether the stored content is normal or not is provided, and the power supply start process execution means is normal by the storage determination means. If it is determined that the predetermined recovery conditions are met, A power supply start process is executed to restore the control state to the state before the power supply stop process is executed based on the stored contents of the data storage means (for example, when Y in step S9 in the game control microcomputer 560) The game control microcomputer executes the game control process by repeatedly executing a predetermined range in the control program when executing the predetermined initial setting process. Delay delayed from the time when control processing in a microcomputer other than the game control microcomputer (for example, the symbol control microcomputer 100a, the sound / lamp control microcomputer 100b, the payout control microcomputer 370, etc.) can be executed. Processing (eg, software A delay processing execution means (for example, a portion for executing steps S81 and S84 to 88 in the game control microcomputer 560) for stopping the power supply until a predetermined initial setting process is executed. Execution of the time process is prohibited (for example, the power-off process is executed in the loop process (step S18) of the main process in FIG. 46 or the timer interrupt process in FIG. 55), and the detection signal determination unit performs the delay process. It is configured to repeatedly determine whether or not a detection signal is output within a predetermined range in the control program (for example, execute the process of step S83 between steps S81 and S88). May be.
According to such a configuration, it is possible to avoid that the electric component control microcomputer misses the command. Further, it is possible to prevent the stored contents of the fluctuation data storage means from being destroyed and the control state from being restored to the state when the power supply is stopped.

The electrical component control microcomputer cannot retain the stored contents when the power supply to the gaming machine is stopped, and the variation data storage means for effect (for example, the variation data storage means for storing the variation data that varies according to the game effect) The game state is not backed up by a RAM 100 built in or externally attached to the symbol control microcomputer 100a or the sound / lamp control microcomputer 100b). A specific display result is determined as a display result of variable display of identification information at a high rate, and a special game effect is executed that is different from the normal game effect when the electronic component control microcomputer is controlled to the normal game state. High probability state (for example, the number of fluctuations after the transition to the probabilistic state reaches 100 times) The state before the game; the process proceeds to Y in step S503 and the process in step S504), and the specific determination result is determined as the display result of the variable display of the identification information at a higher rate than the normal gaming state by the predetermining means. , A latent high probability state in which a normal game effect is executed when controlled to a normal game state by an electric component control microcomputer (for example, a state after the number of fluctuations reaches 100 times after shifting to a probability change state) The game state microcomputer stores data indicating the game state (flag indicating the game state) in the variation data storage means. Means (for example, steps S55E, S55F, S50 in the game control microcomputer 560) , S 509, S 511, S 513, S 514, S 516), and when the power supply start process is executed, the game state is determined based on the game state data stored in the variable data storage means. Recovery command transmission means (for example, step S93 in the game control microcomputer 560) that transmits an identifiable recovery command (for example, a normal display command, a special display command, or a high-probability latent display command) to the electrical component control microcomputer is executed. The electric component control microcomputer restarts the special game effect or the normal game effect based on the game state specified by the recovery command (for example, the symbol control microcomputer 100a executes the recovery command in step S7622). Show gaming state according to Data (for example, a flag) may be stored, and the process of step S777 may be executed based on the data indicating the gaming state).
According to such a configuration, it is possible to cause the electric component control microcomputer to execute a game effect according to the game state before the power supply is stopped, and it is possible to prevent the player from feeling distrust. Further, even if an illegal act that intentionally stops the power supply is performed, the high-latency state is not realized by an unauthorized person when the power supply is restored.

The game control microcomputer includes a plurality of special variable prize winning devices (for example, a first big prize opening and a second big prize opening) that change between a first state that is advantageous to the player and a second state that is disadvantageous. , Special variable winning device control means for changing any of the plurality of special variable winning devices to the first state when being controlled to the specific gaming state (for example, executing step S405 or S408 in the gaming control microcomputer 560) And a notification means (for example, a step in the game control microcomputer 560) that notifies the special variable prize-winning device before changing to the first state about which special variable prize-winning device is changed to the first state. A part for executing S389) and a notification command (for example, a flag indicating which special variable winning device is to be changed to the first state). Notification command transmitting means (for example, a part for executing step S388 in the game control microcomputer 560) that transmits the command to the electric component control microcomputer. The electric component control microcomputer is a game control microcomputer. Based on the notification command received from, control for notifying which special variable winning device is changed to the first state is executed (for example, the symbol control microcomputer 100a executes the process of step S777). It may be configured.
According to such a configuration, it is possible to prevent the player from being disadvantaged without being able to recognize which of the special variable winning devices changes to the first state.

It is the front view which looked at the pachinko game machine from the front. It is a block diagram which shows the structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a relay board | substrate, a sound / lamp control board, and a symbol control board. It is a block diagram which shows the circuit structural example of the part in connection with the image display control in a symbol control board. FIG. 10 is a block diagram showing a circuit configuration of a main board and signal lines of an effect control command transmitted from the main board to the sound / lamp control board. It is a block diagram which shows the structural example of a random number circuit. It is explanatory drawing which shows the example of an update rule selection register. It is explanatory drawing which shows the example of an update rule memory. It is explanatory drawing which shows the example in case a count value permutation change circuit changes the permutation of the count value which a counter outputs. It is explanatory drawing which shows the example of a count value permutation change register. It is explanatory drawing which shows the example of a random number maximum value setting register. It is explanatory drawing which shows the example of a period setting register. It is explanatory drawing which shows the example of a count value update register. It is explanatory drawing which shows the example of a random value taking-in register. It is explanatory drawing of an example of the random number update system selection register and the random number update system selection data written in the random number update system selection register. It is explanatory drawing which shows the example of a random number circuit starting register. It is a circuit diagram which shows one structural example of a random value memory circuit. It is a timing chart which shows the timing when each signal is input into a random value storage circuit, and the timing when a random value storage circuit outputs each signal. It is a block diagram which shows the structural example of the transmission part of a serial communication circuit. It is a block diagram which shows the structural example of the receiving part of a serial communication circuit. It is explanatory drawing which shows the example of the data format of the data which serial communication transmits / receives with the microcomputer mounted in each control board. It is explanatory drawing which shows the example of a baud rate register. It is explanatory drawing which shows the example of the control register A and communication format setting data. It is explanatory drawing which shows the example of the control register B and interrupt request setting data. It is a figure which shows the example of status register A and status confirmation data. It is a figure which shows the example of status register B and status confirmation data. It is explanatory drawing which shows the example of the control register C and error interrupt request setting data. It is explanatory drawing which shows the example of the data register with which a serial communication circuit is provided. It is explanatory drawing which shows an example of the address map of the storage area in the microcomputer for game control. It is explanatory drawing which shows an example of the address map in a user program management area. It is explanatory drawing which shows an example of initial value change system setting data. It is explanatory drawing which shows the structural example of a user program. It is explanatory drawing which shows the structural example of a random number circuit setting program. It is explanatory drawing which shows the operation | movement which updates the value of random R, or reads the value of random R, when the 1st random number update system is selected. It is explanatory drawing which shows the operation | movement which updates the value of random R, or reads the value of random R, when the 2nd random number update system is selected. It is explanatory drawing which shows each memory with which the microcomputer for game control is provided. It is explanatory drawing which shows the example of the table memory for jackpot determination. It is a block diagram which shows the structural example of a watchdog timer. It is a block diagram which shows the structural example of a power supply board. It is explanatory drawing which shows the bit allocation example of the output port in the microcomputer for game control. It is explanatory drawing which shows the bit allocation example of the input port in the microcomputer for game control. It is a timing diagram which shows operation | movement of each CPU and a watchdog timer at the time of an electric power supply start. It is a timing diagram which shows operation | movement of each CPU and a watchdog timer at the time of an electric power supply start. It is a timing diagram which shows operation | movement of each CPU and a watchdog timer at the time of an electric power supply stop. It is a timing diagram which shows operation | movement of each CPU and watchdog timer at the time of a power supply instantaneous stop. It is a flowchart which shows the main process which the microcomputer for game control performs. It is a flowchart which shows the main process which the microcomputer for game control performs. It is explanatory drawing which shows the example of an interruption process priority table. It is a flowchart which shows a random circuit setting process. It is a flowchart which shows a random number maximum value reset process. It is a flowchart which shows an initial value change process. It is a timing chart which shows the timing when each signal is input into a random number circuit, and the timing when each signal is generated in a random number circuit. It is a flowchart which shows a serial communication circuit setting process. It is a flowchart which shows a power-off process. It is a flowchart which shows a power-off process. It is a flowchart which shows a timer interruption process. It is explanatory drawing which shows each random number. It is a flowchart which shows a random circuit initial value update process. It is a flowchart which shows a count value permutation change process. It is a flowchart which shows an example of a special symbol process process. It is explanatory drawing which shows an example of a fluctuation pattern. It is explanatory drawing which shows an example of the content of an effect control command. It is a flowchart which shows a starting port switch passage process. It is a flowchart which shows a special symbol normal process. It is a flowchart which shows a special symbol stop symbol setting process. It is a flowchart which shows a fluctuation pattern setting process. It is a flowchart which shows a special symbol stop process. It is a flowchart which shows the big winning opening opening pre-processing. It is a flowchart which shows a big winning opening open process. It is a flowchart which shows a big winning opening open process. It is a flowchart which shows a big hit end process. It is explanatory drawing which shows an example of the content of the control signal output with respect to the payout control means from a game control means. It is explanatory drawing which shows an example of the content of the control command transmitted / received between a game control means and a payout control means. It is a block diagram which shows the signal line etc. which are used for transmission / reception of a control signal and a control command. It is a timing chart showing an example of how to output a payout control signal and a payout control command. It is a flowchart which shows a prize ball process. 6 is a flowchart illustrating an example of an interrupt process performed by the serial communication circuit in response to an interrupt request. It is explanatory drawing which shows the example of a prize ball number table. It is a flowchart which shows a prize ball number addition process. It is a flowchart which shows a prize ball control process. It is a flowchart which shows a prize ball transmission waiting process. It is a flowchart which shows a prize ball number command transmission process. It is a flowchart which shows a prize ball transmission completion waiting process. It is a flowchart which shows a prize ball ACK waiting process. It is a flowchart which shows a prize ball re-transmission process. It is a flowchart which shows a prize ball abnormality detection process. It is a flowchart which shows a main control communication process. It is a flowchart which shows the main process which the microcomputer for sound / lamp control performs. It is explanatory drawing which shows each random number used by a sound / lamp control process. It is a flowchart which shows the production content determination process which the microcomputer for sound / lamp control performs. It is explanatory drawing which shows the example of a display which changes a decoration design in steps in gradation in the case of reach. It is explanatory drawing which shows the example of a deformation | transformation display which a decoration design changes in steps with gradation. It is explanatory drawing which shows another modified display example in which a decoration design changes in steps with gradation. It is explanatory drawing which shows the example image display of a notice effect. It is a flowchart which shows the main process which the microcomputer for symbol control performs. It is a flowchart which shows the storage area setting process which the microcomputer for symbol control performs. It is a flowchart which shows the pre-transfer command process which the microcomputer for symbol control performs. It is a flowchart which shows the specific example of the command analysis process which the microcomputer for symbol control performs. It is explanatory drawing which shows an example of the register incorporated in VDP. It is explanatory drawing which shows an example of the address map in VRAM. It is explanatory drawing which shows an example of the method of expansion | deployment in the case of expand | deploying a component image from the display area of VRAM to a display area. It is explanatory drawing which shows an example of the usage method of VRAM. It is a flowchart which shows the presentation control process process which the microcomputer for symbol control performs. It is a flowchart which shows the decoration design normal process in an effect control process process. It is a flowchart which shows the decoration design change start process in an effect control process process. It is a flowchart which shows the decoration pattern change process in effect control process processing. It is a flowchart which shows the decoration symbol stop process in an effect control process process. It is a flowchart which shows a display update command process. It is a flowchart which shows the command process for alpha test display. It is explanatory drawing which shows an alpha reference value and a comparison function. It is a flowchart which shows the command process for alpha composition display. It is a flowchart which shows a 1st alpha synthetic | combination command process. It is a flowchart which shows a 2nd alpha synthetic | combination command process. It is a flowchart which shows various update object command processing. It is explanatory drawing which shows alpha value distribution setting data. It is explanatory drawing which shows the data structure of the image data of 1 pixel. It is a flowchart which shows the transfer control process which VDP performs. It is a flowchart which shows a storage area setting process. It is a flowchart which shows a pre-transfer process. It is a flowchart which shows an automatic transfer control process. It is a flowchart which shows the drawing process which VDP performs. It is a flowchart which shows a fixed address designation | designated display process. It is a flowchart which shows an automatic transfer display process. It is a flowchart which shows the drawing process for alpha tests, an alpha test process, and an alpha synthetic | combination process. It is explanatory drawing which shows the example of an image display by which the alpha synthetic | combination process was carried out. It is a block diagram which shows the other circuit structural example of a relay board | substrate, a sound / lamp control board, and a symbol control board. It is explanatory drawing which shows the example of the interruption process priority order table in other embodiment.

Embodiment 1 FIG.
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and can be applied to other gaming machines such as a slot machine.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding game boards described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. A surplus ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball supply tray 3 is provided below the hitting ball supply tray 3. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Further, a hitting operation handle (operation knob) 5 for adjusting the speed at which the hitting ball launching device launches the game ball (that is, the strength of the spring that plays the game ball) is provided below the hitting ball supply tray 3. . The player can adjust the momentum of the game ball launched from the hitting ball launching device by rotating the operation knob 5. Specifically, by rotating the operation knob 5 to the right, the speed of the game ball fired from the hitting ball launching device gradually increases, and when it exceeds a predetermined speed, Enters the left area of the gaming area 7 from above through the hitting rail. When the operation knob 5 is further rotated to the right, the launched game ball enters the right area of the game area 7 from above.

  Near the center of the game area 7, there is provided a variable display device (decorative symbol display device) 9 including a plurality of variable display portions that variably display a plurality of types of decorative symbols for presentation that can be identified. The variable display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. The variable display device 9 that performs variable display of decorative symbols is controlled by a symbol control microcomputer mounted on the symbol control board.

  Further, the variable display device 9 is provided with four decorative symbol start memory display areas (start memory display areas) 18 for displaying the number of effective winning balls entered into the start winning opening 14, that is, the start memory number. Each time there is a valid start prize, the display color changes (for example, changes from blue display to red display), and the start storage display area is increased by one. Each time the variable display of the variable display device 9 is started, the start memory number display area where the display color is changed is reduced by 1 (that is, the display color is returned to the original). In this example, since the symbol display area and the start memory display area are provided separately, the start memory number can be displayed even during variable display. The start memory display area may be provided in a part of the symbol display area. Further, the display of the start memory number may be interrupted during variable display. In this example, the upper limit of the starting memory number is 4, but it may be 4 or more or 4 or less. Although not shown in FIG. 1, it is assumed that a display (special symbol start memory display) for displaying the number of special symbol start memories is provided at a predetermined position in the game area 7. The special symbol start memory indicator displays the number of special symbol start memories according to the number of lights of the four lamps, and the display is controlled by a game control microcomputer mounted on a game control board (main board) described later. Is done.

  A special symbol display (special symbol display device) 8 that variably displays a special symbol as identification information is provided on the variable display device 9. In this embodiment, the special symbol display 8 is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9, for example. The special symbol display 8 may be configured to variably display a larger number of numbers such as 0 to 99 in order to make it difficult for the player to grasp a specific stop symbol. In addition, the variable display device 9 performs variable display of a decorative symbol as a symbol for decoration (for production) during the variable symbol display period of the special symbol by the special symbol indicator 8. That is, the special symbol variable display on the special symbol display 8 and the decorative symbol variable display on the variable display device 9 are synchronized. Synchronous means that the time when the symbol starts to change is the same as when the symbol ends.

  Below the variable display device 9, a variable winning ball device 15 is provided as a start winning port 14. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16 (see FIG. 2).

  On the left side of the lower portion of the variable winning ball apparatus 15, an opening / closing plate 201 that is opened by a solenoid 241 in a specific gaming state (big hit gaming state) is provided. An opening / closing plate 202 that is opened by a solenoid 242 in a specific gaming state is provided on the right side of the lower portion of the variable winning ball apparatus 15. Two large winning openings (special variable winning ball apparatus) are formed by two openable and closable plates 201 and 202. The left winning entrance is called the first winning entrance, and the right winning entrance is called the second winning entrance. The winning ball that has won the first grand prize opening and led to the back of the game board 6 is detected by the count switch 231. Similarly, the winning ball led to the back of the game board 6 after winning the second grand prize opening is detected by the count switch 232.

  In this embodiment, during the big hit game, one of the first grand prize winning opening and the second big winning prize opening is opened a predetermined number of times. Specifically, as the types of jackpots, the two round jackpots where the big prize opening is opened twice, the seven round jackpots where the big prize opening is opened seven times, and the big prize mouth is opened 15 times15 A round jackpot is provided. In this embodiment, the second big prize opening (right big prize opening) is opened at the time of two rounds, and the first big prize opening (left big prize opening) at the seventh round of big hits. Is opened and the second big prize opening (right big prize opening) is opened at the time of a big hit of 15 rounds.

  To the left of the first grand prize opening (the left opening and closing plate 201), the player is notified that the first big prize opening will be opened in the big hit game before the first big prize opening is first opened. A first big prize opening indicator lamp 38 is provided. Further, to the right of the second grand prize opening (the right opening / closing plate 202), the player is notified that the second big prize opening will be opened in the big hit game before the second big prize opening is first opened. A second big prize opening indicator lamp 39 is provided for notification. The player recognizes that the first grand prize opening is opened by turning on the first big prize opening indicator lamp 38, and the second big prize opening is turned on by turning on the second big prize opening display lamp 39. It can be recognized that it is opened. Accordingly, it is possible to prevent the player from being disadvantaged without being able to recognize which of the large winning award (special variable winning device) is open.

  When a game ball wins the gate 32 and is detected by the gate switch 32a, the variable display of the normal symbol display 10 is started. In this embodiment, left and right lamps (designs can be visually recognized when lit) are turned on alternately to perform variable display. If the right lamp (X) is lit, it is off. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of winning balls entered into the gate 32 is provided. Each time there is a prize at the gate 32, the normal symbol start memory display 41 increases the number of LEDs to be turned on by one. Each time the variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The game board 6 is provided with a plurality of winning holes 29 and 30, and winning of game balls to the winning holes 29 and 30 is detected by winning hole switches 29a and 30a, respectively. Each of the winning ports 29 and 30 constitutes a winning area provided on the game board 6 as an area for accepting game media and allowing winning. The start winning opening 14 and the big winning opening also constitute a winning area that accepts game media and allows winning.

  Around the left and right of the game area 7, there are provided decorative lamps 25 blinking and displayed during the game, and at the lower part there is an outlet 26 for absorbing a game ball that has not won a prize. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. A top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided on the outer periphery of the game area 7. The top frame lamp 28a, the left frame lamp 28b, and the right frame lamp 28c are examples of a decorative light emitter provided in the gaming machine.

  In this example, a prize ball LED 51 that is lit while paying out a prize ball is provided in the vicinity of the left frame lamp 28b, and a ball break LED 52 that is lit when the refill ball is cut is provided in the vicinity of the top frame lamp 28a. It has been. As described above, the pachinko gaming machine 1 of this embodiment is provided with lamps and LEDs as light emitters in various places. Furthermore, a prepaid card unit (hereinafter referred to as a card unit) that enables lending of a ball by inserting a prepaid card is installed adjacent to the pachinko gaming machine 1 (not shown).

  In this embodiment, a button 300 as an operation means that can be operated by the player is provided on the surface of the hitting ball supply tray (upper plate) 3. This button 300 is operated by the player during execution of a notice effect (see FIG. 94) described later. In this embodiment, the button 300 is called a chance button. When the chance button 300 is pressed by the player, it is turned on by the contact of the electrodes, and an on signal (detection signal) is mounted on the board (in this embodiment, the symbol control board 80a). It is output to the symbol control microcomputer 100a (see FIG. 3). In the example shown in FIG. 1, the chance button 300 is provided on the surface of the hitting ball supply tray 3, but may be provided at another location (for example, directly above the hitting operation handle 5).

  The game balls launched from the hit ball launching device enter the game area 7 through the hit ball rail, and then descend the game area 7. When the game ball enters the start winning port 14 and is detected by the start port switch 14a, if the variable display of the symbol can be started, the special symbol display 8 starts variable display (variation) of the special symbol, The variable display device 9 starts variable display (variation) of decorative symbols. If the variable display of the symbol is not started, the start memory number is increased by 1 (that is, the start memory display area is increased by 1) on the condition that the start memory number has not reached 4 (upper limit value).

  The variable display of the special symbol on the special symbol display 8 and the decorative symbol on the variable display device 9 stops when a certain time has passed. If the special symbol at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state (specific gaming state). That is, one of the open / close plates 201 and 202 is released until a predetermined time elapses or a predetermined number (for example, 10) of game balls wins. One round in the big hit gaming state is a period from when one of the opening / closing plates 201 and 202 is opened until a predetermined period of time elapses or a predetermined number of hit balls are won. When a predetermined number of game balls have won the big winning opening, or when a certain period has passed since the opening of the big winning opening, a continuation right is generated and the special variable winning ball apparatus is opened again. As described above, the generation of the continuation right is allowed a predetermined number of times (for example, 2 rounds, 7 rounds, and 15 rounds) according to the type of jackpot. Note that a V winning area may be provided in the grand prize opening, and the continuation right may be generated on condition that the hit ball has won the V winning area while the big prize opening is open.

  In this embodiment, when it is determined that the stop symbol of the special symbol is a jackpot symbol, the jackpot type is determined thereafter. As described above, there are 2 rounds, 7 rounds and 15 rounds of big hits as described above. Furthermore, depending on the gaming status after the end of the big hit game, the probability will vary. A big hit, a short time big hit, and a normal big hit are provided. The probable big hit is a big hit in which the gaming state shifts to a probable change state (the probability that the next big hit is a probability variation state (also referred to as a high probability state) higher than the normal gaming state and the short-time state) after the big hit game ends. The short-time big hit is a big hit where the gaming state shifts to the short-time state (time shortening state in which the variation time of the special symbol and the decorative symbol is shortened) after the big hit game ends. A normal jackpot is a jackpot in which the gaming state transitions to the normal gaming state after the jackpot game is over (only if the gaming state is not a probable change state before the jackpot game is started). Specifically, in this embodiment, there are provided two rounds of probable big hits, two rounds of big hits, seven rounds of big hits, 15 rounds of big hits, 15 rounds of big hits, 15 rounds of probable big hits, and 15 rounds of big and short hits. Yes.

  When it is determined that the jackpot type will be a probable big hit, the game is controlled to the probable change state (an example of a special game state advantageous to the player) after the big hit game is over. In the probability variation state as the special gaming state, as described above, the probability that the special symbol stop symbol variably displayed on the special symbol display 8 becomes a big hit symbol (specific display result: for example, odd number of 0 to 9) Is higher than the normal state and the short time state. Further, in this embodiment, until the number of times the special symbol fluctuates after the big hit is reached a predetermined number (100 times), the normal symbol display 10 has a higher probability of a stop symbol being a hit symbol than in a normal state. One or both of the opening time and the number of times of opening in the variable winning ball apparatus 15 are increased as compared with the normal state, and the player becomes more advantageous. Further, in this embodiment, the special symbol variable display time (fluctuation time) on the special symbol display 8 is longer than that in the normal gaming state until the number of times the special symbol fluctuates after the big hit ends reaches a predetermined number (100 times). Shortened. In that case, variable display of special symbols is frequently executed.

  In the probability variation state, the variable symbol display time (variation time) of the normal symbol on the normal symbol display 10 is shortened from that in the normal state until the number of times the special symbol fluctuates after the big hit is a predetermined number (100 times). You may do it. In such a case, it is likely that a start winning to the start winning opening 14 is likely to occur, and there is a possibility that the special symbol becomes a big hit symbol by increasing the number of special symbol display on the special symbol display 8 within a predetermined period. It becomes higher than the state and becomes a more advantageous state for the player.

  When it is determined that the jackpot type is a short-time big hit, the game is controlled to a short-time state (an example of a special game state advantageous to the player) after the big hit game is over. In the short game state as the special game state, as described above, the probability of occurrence of a big hit does not increase, but the variable symbol display time (variation time) of the special symbol is shorter than that in the normal game state. As described above, the special symbol variable display time is shortened, so that the special symbol variable display is frequently executed, and the possibility of occurrence of big hit per predetermined time is increased. Further, in the short time state, in the normal symbol display 10, the probability that the stop symbol becomes a winning symbol is higher than the normal state, and one or both of the opening time and the number of times of opening in the variable winning ball device 15 are in the normal state. It will be more advantageous for the player.

  In the short time state, the normal symbol variable display time (variation time) on the normal symbol display 10 may be shorter than that in the normal game state. In that case, the number of times the variable winning ball apparatus 15 is released per predetermined time is increased, which is more advantageous for the player. In this embodiment, the time reduction state is continued until the number of fluctuations of the special symbol after the end of the jackpot reaches a predetermined number (100 times).

  Next, game state transition will be described. In this embodiment, if a probable big hit occurs in the normal gaming state or the short time state, the gaming state is shifted from the normal gaming state or the short time state to the probable state. The probability variation state is continued until the next normal big hit or short time big hit occurs. When the probability variation big hit occurs in the probability variation state, the probability variation state is continued thereafter. By the way, in the probability variation state, as described above, the variation time of the special symbol is shortened, the probability that the stop symbol of the normal symbol becomes a winning symbol is increased, and the opening time and the number of times of opening in the variable winning ball apparatus 15 are increased. A special state in which one or both of them is raised is continued, but such a special state is continued only until the number of fluctuations of the special symbol after the end of the jackpot reaches a predetermined number (100 times).

  If a short-time big hit occurs in the normal gaming state or the probability change state, the gaming state is shifted from the normal gaming state or the probability change state to the short-time state, and if a normal big hit occurs in the probability change state, the gaming state is changed from the probability change state. Transition to short-time state. If the time-short hit occurs in the time-short state, the time-short state is continued thereafter. The short-time state is continued until the number of times the special symbol fluctuates after the big hit ends reaches a predetermined number (100 times). In the short time state, as in the case of the probable variation state, the variation time of the special symbol is shortened, the probability that the stop symbol of the normal symbol becomes a winning symbol is increased, and the opening time and the number of times of opening in the variable winning ball apparatus 15 One or both of them will be in a special state that can be enhanced.

  As described above, the special state is entered in both the probability variation state and the short-time state until the number of fluctuations of the special symbol after the big hit ends becomes a predetermined number (100 times). Therefore, the player cannot recognize whether the state has been changed to the probable change state or the short time state based on the variation time of the special symbol. Furthermore, in this embodiment, when the variable display device 9 is controlled to the normal game state until the predetermined number of times the special symbol fluctuates after the big hit ends in both the probability variation state and the short time state. A special game effect (special game effect) having a different form from the normal game effect (normal game effect) is executed. For example, the background or color of the screen changes from that in the normal gaming state, or a special mode effect such as a chance mode is executed. Therefore, the player cannot recognize whether the state has been changed to the probability change state or the short time state based on the aspect of the game effect executed in the variable display device 9.

  If the number of fluctuations of the special symbol after the big hit ends in the probability changing state, the probability changing state (the state in which the probability of becoming a big hit is improved) is maintained, but the special state ends. When the special state ends, the game effect executed on the variable display device 9 is also switched from the special game effect to the normal game effect. Thus, although the big hit symbol is determined as the special symbol stop symbol with a higher probability than the normal gaming state or the short time state, the state in which the normal game effect is executed in the variable display device 9 is referred to as a high probability latent state. Further, when the special symbol changes after the big hit in the short time state, the gaming state is shifted from the short time state to the normal gaming state, and as a result, the special state is also terminated. Also at this time, as in the case of the probability variation state, when the special state ends, the game effect executed on the variable display device 9 is switched from the special game effect to the normal game effect.

  As described above, when the number of fluctuations of the special symbol after the big hit ends becomes a predetermined number of times, the special state is terminated in any of the probability variation state and the short time state, and the game effect executed in the variable display device 9 is also special. The game effect can be switched to the normal game effect. Therefore, the player cannot recognize whether the state has been shifted to the high probability latent state or the normal gaming state based on the variation time of the special symbol, the mode of the game effect, or the like. Therefore, it is possible to make the player interested in which state the gaming state has been changed to.

  In this embodiment, the special symbol of “1”, “5”, or “9” is derived and displayed in the case of normal big hit, and “3” or “7” in the probability variation state or the time-short state. It is assumed that any special symbol is derived and displayed. In addition, in the case of a big hit, an even number of the same decorative symbols (for example, “2”) are derived and displayed. It shall be displayed. Therefore, the game state to which the player is transferred after the big hit game cannot be recognized by the special symbol and the decorative symbol stop symbol.

  Next, the reach display mode (reach) will be described. The reach display mode (reach) in this embodiment is a variable display (variable display) for decorative symbols that have not yet stopped when the stopped decorative symbols constitute part of the jackpot symbol. And all or part of the decorative symbols are in a state of being variably displayed synchronously while constituting all or part of the jackpot symbol.

  For example, a decorative display (for example, “7”) that is a part of the jackpot symbol is stopped and displayed in the left and right display areas of the variable display device 9, and the display area in the middle is still displayed in a variable manner. And all or part of the display area is in the form of all or a part of the jackpot symbol and is displayed in a synchronized manner (for example, all of the left, middle, and right display areas vary) Reach display mode or reach is a state in which the display is performed and the variable display is always performed in a state where the same symbols are always arranged.

  In addition, during the reach, an unusual performance is performed with a lamp or sound. The effect and the reach display mode in the variable display device 9 are called reach effects. Further, in the case of reach, a character (an effect display imitating a person or the like, which is different from a design) is displayed, or the background of the variable display device 9 (a ground color or pattern different from the design and the character). The display mode (for example, color) may be changed.

  FIG. 2 is a block diagram illustrating a configuration example of the game control board (main board). 2 also shows a payout control board 37, an interface board 66, a relay board 77, a sound / lamp control board 80b, and a symbol control board 80a mounted on the gaming machine. The main board 31 includes a basic circuit (corresponding to game control means) 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 32a, a start port switch 14a, count switches 231, 232, and winning port switches 29a, 30a. An input driver circuit 58 that supplies a signal to the basic circuit 53, a solenoid 16 that opens and closes the variable winning ball apparatus 15, a solenoid 241 that opens and closes the opening and closing plate 201, and a solenoid 242 that opens and closes the opening and closing plate 202 are driven according to commands from the basic circuit 53. The output circuit 59 is mounted.

  The gate switch 32a, the start port switch 14a, the count switches 231, 232, and the winning port switches 29a, 30a may be referred to as sensors. That is, the name of the game medium detection means is not limited as long as it is a game medium detection means (game ball detection means in this example) that can detect a game ball. Each of the start port switch 14a, the count switches 231, 232, and the winning port switches 29a, 30a that perform winning detection is also a winning detection means that detects the winning of a game ball in the winning area. Note that even if a passing gate such as the gate 32 is used, if a prize ball is paid out, a game ball entering the passing gate becomes a winning and a switch provided on the passing gate (for example, The gate switch 32a) becomes a winning detection means.

  The basic circuit 53 performs a control operation in accordance with a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as storage means (variation data storage means for storing fluctuation data) used as a work memory, and a program. A game control microcomputer 560 having a CPU 56 and a watch dog timer (WDT) 60 for monitoring whether or not the program is normally executed is included. In this embodiment, the CPU 56 refers to a central processing unit (a portion excluding storage means such as the ROM 54 and RAM 55, the I / O port unit 57, etc.) of the basic circuit 53 that operates according to a program. Main processing and interrupt processing (timer interrupt processing and interrupt processing by an interrupt request from the serial communication circuit 505) are executed. In addition to the CPU 56 in the basic circuit 53, the game control microcomputer 560 includes storage means such as a ROM 54 and a RAM 55, a watchdog timer 60, a random number circuit 503, a serial communication circuit 505, and an I / O port unit 57. In this case, various data are transmitted / received to / from a microcomputer mounted on each board (payout control board 37 and sound / lamp control board 80b).

  In this embodiment, expressions such as “the microcomputer transmits and receives” are used. Specifically, for example, when data transmission is performed, the CPU sets data in the transmission data register of the serial communication circuit, and The serial communication circuit transmits the data set in the transmission data register. In addition, the CPU transmits data via the I / O port unit. For example, when data reception is performed, the reception data is written into the reception data register of the serial communication circuit, and the CPU reads the reception data from the reception data register. In addition, the CPU receives data via the I / O port unit.

  In the present embodiment, a case where the game control microcomputer 560 performs serial communication with the payout control microcomputer 370 mounted on the payout control board 37 will be described.

  In this embodiment, as shown in FIG. 2, the game control microcomputer 560 includes a watchdog timer 60. The watchdog timer 60 resets and restarts the game control microcomputer 560 when the game control microcomputer 560 cannot execute the program normally. Details of the watchdog timer 60 will be described later (see FIG. 38). In the example shown in FIG. 2, the watchdog timer 60 is built in the game control microcomputer 560, but may be externally attached to the game control microcomputer 560.

  In this embodiment, the ROM 54, the RAM 55 serving as storage means as a work memory, and the I / O port unit 57 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to include at least the RAM 55, and the ROM 54 may be external or internal.

  In the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54. Therefore, hereinafter, the game control microcomputer 560 executes (or performs processing) specifically. Is that the CPU 56 executes control according to the program. The same applies to microcomputers mounted on substrates other than the main substrate 31. The game control means is realized by a basic circuit 53 including a game control microcomputer 560.

  The RAM 55 is a backup RAM as a non-volatile storage means, part or all of which is backed up by a backup power source created on the power supply substrate 910. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is stored for a predetermined period (until the capacitor as the backup power supply is discharged and the backup power supply cannot be supplied). In particular, at least data (special symbol process flag, etc.) corresponding to the game state, that is, the control state of the game control means, and data indicating the number of unpaid winning balls are stored in the backup RAM. The data corresponding to the control state of the game control means is data necessary for restoring the control state before the occurrence of a power failure or the like based on the data when the power is restored after a power failure or the like occurs. Further, data corresponding to the control state and data indicating the number of unpaid prize balls are defined as data indicating the progress state of the game. In this embodiment, it is assumed that the entire RAM 55 is backed up.

  A reset signal from the power supply board 910 is input to the reset terminal of the game control microcomputer 560. The reset signal from the power supply board 910 is also input to the reset terminal of the payout control microcomputer. When the reset signal becomes high level, the game control microcomputer 560 and the payout control microcomputer become operable, and when the reset signal becomes low level, the game control microcomputer 560 and the payout control microcomputer stop operating. It becomes a state. Accordingly, during the period in which the reset signal is at a high level, an allowable signal that allows the operation of the game control microcomputer 560 and the payout control microcomputer is output, and in the period in which the reset signal is at a low level, An operation stop signal for stopping the operations of the game control microcomputer 560 and the payout control microcomputer is output. A reset circuit may be mounted on each control board (including the main board 31), or a reset circuit is mounted on one or more of the plurality of control boards, and a reset signal is sent from there to another control circuit. You may make it supply to a board | substrate.

  Furthermore, a power-off signal indicating that the power supply voltage from the power supply board 910 has decreased to a predetermined value or less is input to the input port of the basic circuit 53 via the payout control board 37. A clear signal indicating that the clear switch for instructing to clear the contents of the RAM is operated is input to the input port of the basic circuit 53.

  The clear signal is input from the power supply board 910 to the payout control board 37 (see FIG. 39), branched at the payout control board 37, and supplied to the main board 31. The clear signal may be input from the power supply board 910 to the main board, branched at the main board 31, and supplied to the payout control board 37. Further, the state of the clear signal input by the game control microcomputer 560 via the input port may be output to the payout control board 37 via the output port. Further, the clear signal may be branched in the power supply board 910 and supplied to the main board 31 and the payout control board 37. Further, the power-off signal may also be branched at the power supply board 910 and supplied to the main board 31 and the payout control board 37.

  In this embodiment, the RAM built in the payout control microcomputer is also backed up.

  In this embodiment, the sound / lamp control means (configured by a sound / lamp control microcomputer) mounted on the sound / lamp control board 80 b is connected to the game control microcomputer 560 via the relay board 77. An effect control command is received, and sound output control of the speaker (sound output device) 27, display control of each of the lamps 25, 28a, 28b, 28c, and the like are performed. The sound / lamp control means transfers the received effect control command to the symbol control means (configured by a symbol control microcomputer) mounted on the symbol control board 80a. Further, a command (production content command) is generated based on the received production control command, and the generated command is transmitted to the symbol control means. The symbol control means receives a command from the sound / lamp control means and performs display control of the variable display device 9 for variably displaying the decorative symbol. As described above, in this embodiment, sound output control of the speaker 27, display control of the lamps 25, 28a, 28b, and 28c, and display control of the variable display device 9 are performed, whereby various game effects are executed. Is done.

  In this embodiment, the payout control means (configured by the payout control microcomputer 370) mounted on the payout control board 37 receives a prize ball command from the game control microcomputer 560, and By outputting a drive signal to the ball payout device 97 and causing the ball payout device 97 to rotate the payout motor, the payout processing of the winning ball is executed.

  FIG. 3 is a block diagram showing circuit configuration examples of the relay board, the sound / lamp control board, and the symbol control board. As shown in FIG. 3, the sound / lamp control board 80b is mounted with a sound / lamp control microcomputer 100b including a sound / lamp control CPU 101b and a RAM. The RAM may be externally attached. In the sound / lamp control board 80b, the sound / lamp control microcomputer 100b operates according to a program stored in a built-in or external ROM (not shown), and is input via the relay board 77. In response to the strobe signal (effect control INT signal) from, an effect control command is received via the input driver 102 and the input port 103.

  The effect control command and the effect control INT signal are first input to the input driver 102 on the sound / lamp control board 80b. The input driver 102 passes the signal input from the relay board 77 only in the direction toward the sound / lamp control board 80b (passes the signal in the direction from the sound / lamp control board 80b to the relay board 77). It is also a unidirectional circuit as signal direction regulating means.

  A signal that allows the signal input from the main board 31 to pass through the relay board 77 only in the direction toward the sound / lamp control board 80b (does not pass the signal in the direction from the sound / lamp control board 80b to the relay board 77). A unidirectional circuit is mounted as a direction regulating means. For example, a diode or a transistor is used as the unidirectional circuit. FIG. 3 illustrates a diode. A unidirectional circuit is provided for each signal.

  The sound / lamp control microcomputer 100 b outputs a signal for driving the lamp to the lamp driver 352. The lamp driver 352 amplifies a signal for driving the lamp and supplies the amplified signal to each lamp provided on the frame side such as the top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the button lamp 130. Further, it is supplied to a decorative lamp 25 provided on the frame side.

  Further, the sound / lamp control microcomputer 100b outputs sound number data to the speech synthesis IC 173. The voice synthesizing IC 173 generates a voice or a sound effect corresponding to the sound number data and outputs it to the amplifier circuit 175. The amplifier circuit 175 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 173 to a level corresponding to the volume set by the volume 176 to the speaker 27. The voice data ROM 174 stores control data corresponding to the sound number data. The control data corresponding to the sound number data is a collection of data indicating the sound effect or sound output mode in a time series in a predetermined period (for example, a decorative symbol variation period).

  The signal for driving the lamp and the sound number data are transmitted bidirectionally (a response signal is transmitted from the signal receiving side to the transmitting side) between the sound / lamp controlling microcomputer 100b, the lamp driver 352, and the voice synthesis IC 173. Communication).

  The sound / lamp control microcomputer 100b transfers the received effect control command to the symbol control board 80a via the input / output port 104, and generates a command based on the received effect control command. Is transmitted to the symbol control board 80a via the input / output port 104.

  As shown in FIG. 3, the symbol control board 80a is equipped with a symbol control microcomputer 100a including a symbol control CPU 101a and a RAM. The RAM may be externally attached. In the symbol control board 80a, the symbol control microcomputer 100a operates according to a program stored in a built-in or external ROM (not shown), and a strobe signal (symbol control INT signal) from the sound / lamp control board 80b. In response to this, a command is received via the input / output port 702. Then, the symbol control microcomputer 100a causes the VDP (video display processor) 109 to perform display control of the variable display device 9 using the LCD based on the received command.

  That is, the symbol control microcomputer 100a issues an image drawing instruction (development instruction) to the VDP 109 in accordance with the received command. The VDP 109 reads necessary data from a character ROM (not shown) based on an instruction from the symbol control microcomputer 100a, and expands the read data into a VRAM (not shown).

  The VRAM is a buffer memory for expanding image data generated by the VDP 109. The VDP 109 outputs image data in the VRAM (a frame buffer (also referred to as a drawing area or a development area) secured in the address space of the VRAM 84 shown in FIG. 4) to the variable display device 9. As a result, the image is displayed on the display screen of the variable display device 9.

  Further, the symbol controlling microcomputer 100 a inputs an ON signal from the chance button 300 via the input port 703. As will be described later, the symbol control microcomputer 100a executes display control of the variable display device 9 in response to an ON signal from the chance button 300. In this embodiment, the ON signal from the chance button 300 is configured to be output to the symbol control microcomputer 100a, but is configured to be output to the sound / lamp control microcomputer 100b. May be. In this case, the sound / lamp control microcomputer 100b inputs the ON signal from the chance button 300 in order to cause the symbol control microcomputer 100a to execute display control of the variable display device 9 in response to the ON of the chance button 300. Accordingly, a signal (command) indicating that the chance button 300 is turned on is output to the symbol control microcomputer 100a.

  FIG. 4 is a block diagram illustrating an example of a circuit configuration of a portion related to image display control in the symbol control board 80. As described above, when executing display control of the variable display device 9 (liquid crystal display device: LCD), the symbol control CPU 101a gives a command according to the effect control command to the VDP 109. The VDP 109 is also referred to as GCL (Graphics Controller LSI). The VDP 109 reads out necessary data from the CGROM 83. The CGROM 83 stores image data such as symbols, frequently used characters, and backgrounds, and image data of characters that are not frequently used. The frequently used character stored in the CGROM 83 is, for example, an image made up of a person, an animal, a character, a figure, a symbol, or the like displayed on the variable display device 9. Note that the character includes a moving image (video) and a still image obtained by actual shooting.

  The VDP 109 generates image data to be displayed on the variable display device 9 according to the input data, and outputs R (red), G (green), B (blue) signals and a synchronization signal to the variable display device 9. The variable display device 9 performs, for example, screen display by a dot matrix method using a large number of pixels (pixels). In this embodiment, the R, G, and B signals are each represented by 8 bits. Therefore, according to the instruction from the VDP 109, the variable display device 9 has 256 gradations for R, G, and B, and can perform multi-color display of about 16.7 million colors. Note that the number of bits of the R, G, and B signals may be other than 8 bits, and the number of bits of the R, G, and B signals may be different from each other.

  The symbol control board 80a is provided with various storage media such as a CGROM 83 and a VRAM (SDRAM) 84. The VRAM 84 stores data relating to a display image such as a frame buffer, character source data, palette data used for specifying or changing display colors, and the like. The source data is image data, and is expressed as source data in the sense of original image data.

  The VDP 109 stores various kinds of storage media such as a pallet data buffer 85 used for temporarily storing predetermined pallet data and a CG data buffer 86 used for temporarily storing predetermined CG data. In addition, the drawing control unit 91, a display signal control unit 87 for outputting a signal to the variable display device 9 based on the image data written in the frame buffer, and a DAC (digital analog converter) for converting the digital signal into an analog signal ) 88 and a moving image compression / decompression unit 89 that performs moving image compression processing and decompression processing. The drawing control unit 91 includes, for example, an attribute analysis unit, a VRAM address generation unit, a clipping unit, and a translucent luminance modulation unit. The attribute analysis unit analyzes parameters used when drawing the character. Information for designating an image drawing order, the number of colors, an enlargement / reduction ratio, a palette number, coordinates, and the like are set in the parameters. The moving image compression / decompression unit 89 may be configured to be controlled by the VDP 109 or may be configured to be controlled by the symbol control CPU 101a.

  Inside the VDP 109, a CG bus and a VRAM bus are provided. A CG bus interface (CG bus I / F) 93 is installed between the CGROM 83 and the CG bus. The CPU I / F 92 is also connected to the CG bus, and the symbol control CPU 101a can access the portion connected to the CG bus via the CPU I / F 92. Specifically, the symbol control CPU 101a can access the drawing control register 95 connected to the CG bus. The drawing control register 95 stores a command or the like from the symbol control CPU 101a to the drawing control unit 91. A VRAM I / F 94 is installed between the VRAM 84 and the VRAM bus. Note that the moving picture decompression unit 89 can access the VRAM 84 via the VRAM bus and can access the drawing control register 95 via the CG bus.

  FIG. 5 is a block diagram showing a circuit configuration of the main board 31 and signal lines of an effect control command transmitted from the main board 31 to the sound / lamp control board 80. As shown in FIG. 5, in this embodiment, the game control microcomputer 560 mounted on the main board 31 uses the eight signal lines CD0 to CD7 for transmitting the effect control signal to produce the effect control command. Is transmitted to the sound / lamp control board 80b. Further, between the main board 31 and the sound / lamp control board 80b, an effect control INT signal signal line for transmitting and receiving a strobe signal is also wired.

  As shown in FIG. 5, wiring from the start port switch 14a is connected to the main board 31. The main board 31 is also connected to wiring from various switches 29a and 30a for detecting a winning of a game ball to two big winning holes and other winning holes. Further, the main board 31 is connected to the solenoid 16 for opening and closing the variable winning ball device 15 and the solenoids 241 and 242 for opening and closing the opening and closing plates 201 and 202.

  The main board 31 includes a game control microcomputer 560, an input driver circuit 58, and an output circuit 59. The game control microcomputer 560 includes a clock circuit 501, a reset / interrupt controller 502 that functions as a system reset means, random number circuits 503a and 503b, a ROM 54 that stores a game control program, a RAM 55 that is used as a work memory, a program CPU 56 that operates according to the above, CTC 504 that sends an interrupt request signal (interrupt request signal by timer interrupt) to CPU 56, serial communication circuit 505 that performs asynchronous serial communication with a microcomputer provided in payout control board 37, and I / O port The unit 57 is incorporated. Although not shown in FIG. 5, the game control microcomputer 560 also includes a watch dog timer 60.

  In this embodiment, the serial communication circuit is used for communication with a microcomputer on a board (for example, the payout control board 37) different from the board (for example, the main board 31) on which the microcomputer incorporating the serial communication circuit 505 is mounted. Although the case where 505 is used will be described, the serial communication circuit 505 may perform serial communication with another microcomputer included in the board on which the microcomputer incorporating the serial communication circuit 505 is mounted. For example, when two microcomputers having the same configuration are mounted on the same substrate, serial communication circuits built in the microcomputers may perform serial communication with each other.

The clock circuit 501 outputs a reference clock signal CLK having a predetermined period generated by dividing the system clock signal by 2 ⁷ (= 128) to the random number circuits 503a and 503b. When a low level signal is input for a certain period, the reset / interrupt controller 502 outputs a predetermined initialization signal to the CPU 56 and the random number circuits 503a and 503b to reset the game control microcomputer 560.

  Further, in this embodiment, as shown in FIG. 5, the game control microcomputer 560 is equipped with two random number circuits 503a and 503b having different ranges of random value values that can be generated. The random number circuit 503a is a random number circuit (hereinafter also referred to as a 12-bit random number circuit) that generates a 12-bit pseudo-random number. The 12-bit random number circuit 503a has a function of generating a random number having a value within a range that can be generated by 12 bits (that is, a range from 0 to 4095). The random number circuit 503b is a random number circuit (hereinafter also referred to as a 16-bit random number circuit) that generates a 16-bit pseudo-random number. The 16-bit random number circuit 503b has a function of generating a random number having a value in a range that can be generated in 16 bits (that is, a range from 0 to 65535). In this embodiment, the case where the game control microcomputer 560 includes two random number circuits is described. However, the game control microcomputer 560 may include three or more random number circuits. In this embodiment, when the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are comprehensively expressed, or when indicating either the 12-bit random number circuit 503a or the 16-bit random number circuit 503b, This is called a random number circuit 503.

  Next, the configuration of the random number circuit 503 will be described. FIG. 6 is a block diagram illustrating a configuration example of the random number circuit 503. In this embodiment, the basic configurations of the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are the same. As shown in FIG. 6, the random number circuit 503 includes a counter 521, a comparator 522, a count value permutation changing circuit 523, a clock signal output circuit 524, a count value update signal output circuit 525, a random value read signal output circuit 526, and a random number update. A system selection signal output circuit 527, a selector 528, a random number circuit activation signal output circuit 530, a random value storage circuit 531, an inversion circuit 532, a latch signal generation circuit 533, and a timer circuit 534 are included.

  In this embodiment, the random number circuit 503 determines whether or not the display result of variable display of a plurality of types of identification information is a specific display result (that is, the special symbol stop symbol of the special symbol indicator 8 is regarded as a jackpot symbol). A random number for jackpot determination for determining whether or not to) is generated. When the CPU 56 of the gaming control microcomputer 560 determines that the specific display result is based on the random number generated by the random number circuit 503, the gaming state is shifted to a specific gaming state (big hit gaming state) advantageous to the player. .

  The counter 521 receives a predetermined signal selected by the selector 528 and outputs a count value C in response to the signal input from the selector 528. In this case, the counter 521 inputs a predetermined initial value, and cyclically updates the count value C from the initial value to a predetermined final value according to a certain rule, and outputs it. Further, when the count value C is updated to the final value, the counter 521 outputs a notification signal indicating that the count value C has been updated to the final value to the CPU 56. In this embodiment, when a notification signal is output from the counter 521, the CPU 56 updates the initial value.

  In this embodiment, every time a signal is input from the selector 528 (every time a rising edge in the signal from the selector 528 is input), the counter 521 increments the count value C from “0” to “4095” by one. Count up. Further, when the counter 521 counts up the count value C to “4095”, the counter 521 outputs a notification signal indicating that the count value C has been updated to the final value to the CPU 56. Then, the CPU 56 inputs a notification signal from the counter 521 and updates the initial value. Then, the counter 521 counts up the count value C again from the initial value updated by the CPU 56 to “4095”. Further, when counting up to “4095”, the counter 521 starts counting from “0” again. Then, the counter 521 outputs a notification signal to the CPU 56 when it counts up to a value (final value) immediately before the updated initial value. In this embodiment, the comparator 522 outputs a notification signal to the counter 521 when all the count values are input, as will be described later. In this case, when the notification signal is input from the comparator 522, the counter 521 resets the count value to “0”.

  The comparator 522 determines whether the input count value is larger than the random number maximum value set in the random number maximum value setting register 535, and the count value is larger than the random number maximum value (exceeded the random number maximum value). ), A notification signal may be output to the counter 521. In this case, for example, when the comparator 522 determines that the count value exceeds the random number maximum value, the notification signal is output to the counter 521 before the clock signal output circuit 524 next outputs the random number generation clock signal SI1. . For example, consider a case where the random number maximum value “256” is set in the random number maximum value setting register 535. In this case, when the counter 521 counts up from “0” to “256” and further outputs the count value “257”, the comparator 522 determines that the input count value “257” exceeds the random number maximum value “256”. Determine and output a notification signal to the counter 521. When the notification signal is input from the comparator 522, the counter 521 updates the count value to “258” and outputs it without waiting for the input of the random number generation clock signal SI1 from the clock signal output circuit 524. By repeatedly executing the above processing, the comparator 522 determines that the count value exceeds the random number maximum value while inputting from the count value “257” to “4095”. Output a notification signal. The counter 521 repeatedly updates and outputs the count value without waiting for the input of the random number generation clock signal SI1 from the clock signal output circuit 524 while the notification signal is input from the comparator 522. By doing so, until the clock signal output circuit 524 next outputs the random number generation clock signal SI1, the count value is controlled to be counted up from “257” to “4095” at a high speed, Control is performed so that random numbers from “257” to “4095” are skipped (not stored in the random value storage circuit 531).

  The count value permutation change circuit 523 includes a count value permutation change register (RSC) 536, an update rule selection register (RRC) 542, and an update rule memory 543. The count value permutation change register 536 stores count value permutation change data “01h” for changing the permutation (order of arrangement from the initial value to the final value), which is the update order of the count value C counted up by the counter 521. . When the numerical value permutation change data “01h” is stored in the count value permutation change register 536, the count value permutation change circuit 523 displays the count value C permutation that the counter 521 counts up and updates. The permutation is changed to a different permutation from when “01h” is not stored. In this case, when the numerical value permutation change data “01h” is stored, the count value permutation changing circuit 523 switches the update rule used for changing the permutation of the count values. In addition, when the counter 521 starts updating the count value after switching the update rule used for changing the count value permutation, the count value permutation change data in the count value permutation change register 536 is initialized from “01h” by the CPU 56. The value is returned to “0 (= 00h)” (cleared).

  Instead of clearing the count value permutation change data by the CPU 56, the random number circuit 503 may clear the count value permutation change data. For example, when the register value is set in the update rule selection register (RRC) 542 based on the count value permutation change data “01h” being written in the count value permutation change register 536, the count value permutation change circuit 523 The register value of the count value permutation change register 536 may be cleared.

  FIG. 7 is an explanatory diagram illustrating an example of the update rule selection register 542. The update rule selection register 542 is a register that sets an update rule used for rearranging the order of count values output from the counter 521 (changing the permutation). In this embodiment, an update rule used for changing the permutation of count values output from the counter 521 is set by setting a register value in the update rule selection register 542. As shown in FIG. 7, the update rule selection register 542 is an 8-bit register, and the initial value is set to “0 (= 00h)”. The update rule selection register 542 is configured in a state where bits 0 to 3 can be written and read. In addition, the update rule selection register 542 is configured in a state where bits 4 to 7 cannot be written or read. Therefore, even if control is performed to write values to bits 4 to 7 of the update rule selection register 542, it is invalid, and all the values read from bits 4 to 7 are “0 (= 0000b)”.

  The value (register value) of the update rule selection register 542 is changed from “0 (= 00h)” to “15” in response to the count value permutation change data “01h” being written in the count value permutation change register 536. (= 0Fh) ”is updated cyclically. That is, each time the count value permutation data “01h” is written to the count value permutation change register 536, the register value of the update rule selection register 542 is incremented by “1” from “0”. Return to "0".

  FIG. 8 is an explanatory diagram showing an example of the update rule memory 543. As shown in FIG. 8, the update rule memory 543 stores the value (register value) of the update rule selection register 542 and the count value update rule in association with each other. In the example shown in FIG. 8, for example, when the register value 1 is set in the update rule selection register 542, it can be seen that the permutation of the count values output by the counter 521 is changed using the update rule B. In FIG. 8, the update rule A is the same update rule as that for the counter 521 to update the count value C, and is stored in the update rule memory 543 in association with the register value “0”. Also, in the update rule memory 543, update rules B to P different from the update rule in which the counter 521 updates the count value C are stored in association with the register values “1” to “15”.

  When the count value permutation change data “01h” is written in the count value permutation change register 536, the count value permutation change circuit 523 first counts from the counter 521 until the final count value “4095” is first input. The count value is output as it is according to the currently set update rule. The count value permutation changing circuit 523 changes the count value update rule when the final value “4095” of the count value is input from the counter 521. When the initial value is changed by the CPU 56, the count value permutation changing circuit 523 inputs the final value after the change (the value immediately before the initial value) from the counter 521, and updates the count value. Will be changed.

  The count value permutation change circuit 523 selects an update rule corresponding to the register value of the update rule selection register 542 from the update rule memory 543, and sets it as an update rule used for changing the count value permutation. The count value permutation changing circuit 523 changes the permutation from the initial value of the count value to the final value according to the set update rule when the counter 521 starts updating the count value again from the initial value “0”. To do. When the initial value is changed by the CPU 56, the count value permutation changing circuit 523 starts counting in accordance with the set update rule when the counter 521 starts updating the count value in order from the changed initial value. The permutation from the initial value to the final value will be changed. Then, the count value permutation change circuit 523 outputs a count value according to the changed permutation.

  In this embodiment, when the maximum random number to be generated is limited by setting the maximum random number in a random number maximum value setting register 535 described later, the count value permutation changing circuit 523 counts The value C is limited to the maximum random number or less, and the permutation is changed and output. For example, it is assumed that the random number maximum value “256” is set in the random number maximum value setting register 535, and the count value permutation changing circuit 523 changes the update rule A to the update rule B to change the count value permutation. Shall. In this case, the count value permutation changing circuit 523 changes the count value permutation to “256 → 255” according to the update rule B based on the random number maximum value “256” set in the random number maximum value setting register 535 of the comparator 522. → → → 0 "and output. The count value permutation changing circuit 523 does not output a count value equal to or less than the maximum value, but the count value permutation changing circuit 523 outputs a value corresponding to the count value and determines whether the comparator 522 is equal to or greater than the maximum value. If it is determined that the value is equal to or greater than the maximum value, the random number value may be skipped (not stored in the random number value storage circuit 531).

  As described above, when the count value permutation change data “01h” is written in the count value permutation change register 536, the count value permutation change circuit 523 changes the update rule to use the permutation of the count value C. Change and output. Therefore, the randomness of the random number generated by the random number circuit 503 can be improved.

  FIG. 9 is an explanatory diagram illustrating an example in which the count value permutation changing circuit 523 changes the permutation of count values output from the counter 521. As shown in FIG. 9, the CPU 56 writes the count value permutation change data “01h” into the count value permutation change register 536 at a predetermined timing. Then, 1 is added to the register value of the update rule selection register 542. For example, the register value of the update rule selection register 542 is updated from “0” to “1”. When the register value is updated, the count value permutation changing circuit 523 updates the “update rule A” corresponding to the register value “0” before the update until the final value “4095” of the count value is input from the counter 521 for the first time. The count value is updated according to "." At this time, the count value permutation changing circuit 523 outputs the count values in a permutation of “0 → 1 →... → 4095” according to the update rule A.

  When the final value “4095” of the count value is input from the counter 521, the count value permutation changing circuit 523 selects “update rule B” corresponding to the updated register value “1” from the update rule memory 543. To set. When the count value permutation changing circuit 523 starts to input the count values after the initial value “0” from the counter 521 again, the count value permutation changing circuit 523 changes the permutation of the count values according to the selected “update rule B” and outputs it. In this example, the count value permutation changing circuit 523 changes the permutation from “0 → 1 →... → 4095” to “4095 → 4094 →... → 0” and outputs the count value.

  Thereafter, the count value permutation change register 536 is reset in response to the count value permutation change circuit 523 starting the count value updating operation in accordance with the updated update rule, as will be described later. Then, until the next count value permutation change data “01h” is written to the count value permutation change register 536, the count value permutation change circuit 523 counts the permutation as “4095 → 4094 →. Continue to output values.

  When the count value permutation change data “01h” is written again to the count value permutation change register 536 by the CPU 56, the register value of the count value permutation change register 536 is updated from “1” to “2”. When the final value “4095” of the count value is input from the counter 521, the count value permutation changing circuit 523 selects and sets “update rule C” corresponding to the register value “2” from the update rule memory 543. . When the count value permutation changing circuit 523 starts to input the count value after the initial value “0” again from the counter 521, the count value permutation changing circuit 523 updates and outputs the count value permutation in accordance with the “update rule C” selected and set. In this example, the count value permutation changing circuit 523 changes the permutation from “4095 → 4094 →... → 0” to “1 → 3 →... → 4095 → 0 →. Is output.

  As described above, after the count value permutation change register 536 is reset, the count value permutation data “01h” is written again in the count value permutation change register 536, so that the count value permutation can be further changed.

  FIG. 10 is an explanatory diagram illustrating an example of the count value permutation change register 536. The count value permutation change register 536 is a register that sets count value permutation change data “01h” for changing the permutation of count values counted up by the counter 521. As shown in FIG. 10, the count value permutation change register 536 is a readable 8-bit register, and the initial value is set to “0 (= 00h)”. Further, count value permutation change register 536 is configured such that only bit 0 can be written and read. That is, count value permutation change register 536 is configured such that bits 1 to 7 cannot be written or read. Therefore, even if control is performed to write values to bits 1 to 7 of the count value permutation change register 536, it is invalid, and all the values read from bits 1 to 7 are “0 (= 0000000b)”.

  Note that the value of the count value permutation change register 536 is reset by the CPU 56 in response to the count value permutation change circuit 523 starting a count value update operation in accordance with the updated update rule. In this case, the CPU 56 returns the value written in the count value permutation change register 536 from the count value permutation change data “01h” to the initial value “0 (= 00h)”.

  The comparator 522 includes a random number maximum value setting register (RMX) 535 that stores random number maximum value setting data for designating the maximum value of random R (random number maximum value). The comparator 522 limits the update range of the count value updated by the counter 521 according to the random number maximum value indicated in the random number maximum value setting data stored in the random number maximum value setting register 535. In this embodiment, the comparator 522 has a random number maximum value (for example, “00FFh”) indicated by the count value input from the counter 521 and the random number maximum value setting data (for example, “00FFh”) stored in the random number maximum value setting register 535. 256 "). When the comparator 522 determines that the input count value is equal to or less than the random number maximum value, the comparator 522 outputs the input count value to the random value storage circuit 531.

  In this embodiment, the comparator 522 specifically performs the following control. The comparator 522 obtains the initial value of the count value from the CPU 56 when updating the initial value of the count value, and obtains the number of count values from the initial value to the maximum random number. For example, when the initial value of the count value is “157” and the maximum random number value is “256”, the comparator 522 calculates the number of count values from the initial value to the maximum random number value as “100”. The comparator 522 counts up how many count values have been input from the initial value as the count values are input from the count value permutation changing circuit 523. When the number of input count values from the initial value reaches “100”, the comparator 522 determines that all count values from the initial value “157” to the maximum value “256” have been input. Then, the comparator 522 outputs a notification signal indicating that all count values have been input to the counter 521. By determining based on the number of count values, even when the count value permutation circuit 523 has changed the count value permutation, the comparator 522 limits the update range of the count value to the maximum random number or less. When all count values are input, a notification signal can be output to the counter 521.

  An operation in which the comparator 522 limits the update range of the count value will be described. In this example, a case where the count value permutation changing circuit 523 selects the update rule A and the random number maximum value “256” is set in the random number maximum value setting register 535 will be described.

  While the counter 521 is updating the count value from “0” to “256”, the count value permutation changing circuit 523 updates based on the random number maximum value “256” set in the random number maximum value setting register 535. In accordance with rule A, the count values from “0” to “256” are output to the comparator 522 as they are. In this case, the count value permutation changing circuit 523 receives the value of the random number maximum value “256” from the comparator 522, determines whether the count value input from the counter 521 is larger than the random number maximum value, and the update rule is changed. Even when it is set (for example, update rule B), the count values from “257” to “4095” are compared based on the random number maximum value “256” set in the random number maximum value setting register 535. Does not output to the device 522 For example, when the initial value is set to “0” and the count value is updated to the final value “256”, the counter 521 outputs a notification signal to the CPU 56. When the notification signal is output, the CPU 56 changes the initial value of the count value of the counter 521. In this example, it is assumed that the initial value is changed to “50” by the CPU 56.

  Note that the comparator 522 may determine whether the count value is greater than the random number maximum value “256”, instead of the count value permutation changing circuit 523. In this case, for example, the comparator 522 determines whether or not the count value is greater than the random number maximum value set in the random number maximum value setting register 535, and determines that the count value is greater than the random number maximum value. Is output to the counter 521. When the comparator 522 determines that the count value exceeds the random number maximum value, the comparator 522 outputs a notification signal to the counter 521 before the clock signal output circuit 524 next outputs the random number generation clock signal SI1. By doing so, the comparator 522 counts up the count value from “257” to “4095” at high speed until the clock signal output circuit 524 next outputs the random number generation clock signal SI1. Thus, the counter 521 is controlled. By doing so, the count value is output to the random value storage circuit 531 only when the value from the count value permutation changing circuit 523 is less than “257”, and the value from the count value permutation changing circuit 523 is “257”. When it is above, the count value can be updated at high speed.

  Based on the update rule A, while the count value is input from “0” to “255” from the count value permutation changing circuit 523, the comparator 522 inputs the count value below the maximum random number “256”. Therefore, the input count value is output to the random value storage circuit 531 as it is. Next, when the count value input from the count value permutation changing circuit 523 reaches “256”, the comparator 522 outputs the input count value to the random value storage circuit 531 and all the values from the initial value to the maximum value. A notification signal indicating that the count value is input is output to the counter 521. Specifically, the comparator 522 receives an initial value (“0” in this example) of the count value from the CPU 56 when changing the initial value of the count value, and the random number maximum value (the main value) from the initial value “0”. In the example, the number of count values up to “256” (in this example, “257”) is obtained. When the number of count values input from the count value permutation changing circuit 523 reaches 257, a notification signal indicating that all count values have been input is output to the counter 521. In this example, since the CPU 56 changes the initial value to “50”, the counter 521 does not reset the count value even when the notification signal is input from the comparator 522, and the changed initial value “50”. The count value is updated.

  While the counter 521 updates the count value from the changed initial value “50” to “256”, the count value permutation changing circuit 523 sets the random number maximum value “256” set in the random number maximum value setting register 535. Based on the update rule A, the count values from “50” to “256” are output to the comparator 522 as they are. Further, the count value permutation changing circuit 523 does not output the count values from “257” to “4095” to the comparator 522 based on the random number maximum value “256” set in the random number maximum value setting register 535. When the count value to be updated by the counter 521 makes one round (when updated 257 times), when the count value permutation change data is written in the count value permutation change register 536, the count value permutation change circuit 523 Change the permutation of count values and output. For example, when the update rule is changed to the update rule B, the count value permutation changing circuit 523 changes the count value permutation from “256 → 255 →... → 50” and outputs the result.

  While the count values from “256” to “50” are input from the count value permutation changing circuit 523, the comparator 522 outputs the input count value as it is to the random value storage circuit 531. Next, when the count value input from the count value permutation change circuit 523 reaches “50”, the comparator 522 outputs the input count value to the random value storage circuit 531 and all the values from the initial value to the maximum value. A notification signal indicating that the count value is input is output to the counter 521. Specifically, the comparator 522 receives the initial count value (“50” in this example) from the CPU 56 when the initial count value is changed, and the random number maximum value (this In the example, the number of count values up to “256” (in this example, “207”) is obtained. When the number of count values input from count value permutation changing circuit 523 reaches 207, a notification signal indicating that all count values have been input is output to counter 521.

  Even when the count value permutation changing circuit 523 changes the count value permutation, the comparator 522 outputs a notification signal to the counter 521 when the number of count values reaches 207. By doing so, even if the permutation of the count values is changed, the notification signal is counted based on the input of all the count values from the initial value “50” to the maximum value “256”. 521 can be output.

  When the notification signal is input from the comparator 522, the counter 521 resets the initial value of the count value and returns it to “0”. Then, the counter 521 updates the count value from “0”. When the value of the counter 521 is updated again from “0”, the count value permutation changing circuit 523 outputs the count values from “49” to “0” to the comparator 522 based on the count value from the counter 521. The comparator 522 outputs the count value to the random value storage circuit 531 based on the count value input from the count value permutation changing circuit 523. When the counter 521 updates the count value to the final value (“49” in this example), the counter 521 outputs a notification signal to the CPU 56. When the notification signal is output, the initial value of the count value of the counter 521 is changed again by the CPU 56.

  By repeating the operation as described above, the comparator 522 causes the counter 521 to continuously count up the count value from “0” to the random number maximum value “256”, and the value from “0” to “256”. Is stored in the random value storage circuit 531 as a random R (random number value). That is, the comparator 522 limits the update range of the count value to the random number maximum value “256” or less, and causes the counter 521 to update the count value.

  FIG. 11 is an explanatory diagram showing an example of the random number maximum value setting register 535. FIG. 11A shows an example of the random number maximum value setting register 535 installed in the 12-bit random number circuit 503a. FIG. 11B shows an example of the random number maximum value setting register 535 installed in the 16-bit random number circuit 503b. First, the random number maximum value setting register 535 mounted in the 12-bit random number circuit 503a will be described. As shown in FIG. 11A, in the 12-bit random number circuit 503a, the random number maximum value setting register 535 is a 16-bit register, and the initial value is set to “4095 (= 0FFFh)”. The random number maximum value setting register 535 is configured so that bits 0 to 11 can be written and read. The random number maximum value setting register 535 is configured such that bits 12 to 15 cannot be written or read. Therefore, in the 12-bit random number circuit 503a, even if control is performed to write values to bits 12 to 15 of the random number maximum value setting register 535, the values read from bits 12 to 15 are all “0 (= 0000b)”. Is.

  The random number maximum value set in the random number maximum value setting register 535 has a predetermined lower limit value. In this embodiment, when random number maximum value setting data “0000h” to “00FEh” designating a value smaller than the lower limit value “256” is written in the random number maximum value setting register 535, the CPU 56 stores the random number maximum value setting register. The random number maximum value setting data “0FFFh” for specifying the initial value “4095” is set again in 535. That is, the random number maximum value that can be set in the random number maximum value setting register 535 is from “256” to “4095”, and when the CPU 56 determines that a value smaller than the lower limit value “256” is set, the random number maximum value Is reset to a predetermined value “4095”. The CPU 56 controls the random number maximum value setting register 535 in which the random number maximum value setting data is written to be unwritable until the game control microcomputer 560 is system reset by the reset / interrupt controller 502. Instead of controlling the CPU 56 to disable writing, the random number maximum value setting register 535 may be formed so that writing is not possible until a reset signal is input after data is written.

  Next, the random number maximum value setting register 535 mounted in the 16-bit random number circuit 503b will be described. As shown in FIG. 11B, in the 16-bit random number circuit 503b, the random number maximum value setting register 535 is a 16-bit register, and the initial value is set to “65535 (= FFFFh)”. Further, in the 16-bit random number circuit 503b, the random number maximum value setting register 535 is configured in a state in which all of the bits 0 to 15 can be written and read.

  When random number maximum value setting data “0000h” to “01FEh” for designating a value smaller than the lower limit value “512” is written in the random number maximum value setting register 535, the CPU 56 stores the initial value in the random number maximum value setting register 535. The random number maximum value setting data “FFFFh” specifying the value “65535” is reset. That is, the random number maximum value that can be set in the random number maximum value setting register 535 is from “512” to “65535”, and when the CPU 56 determines that a value smaller than the lower limit value “512” is set, the random number maximum value Is reset to a predetermined value “65535”. The CPU 56 controls the random number maximum value setting register 535 in which the random number maximum value setting data is written to be unwritable until the game control microcomputer 560 is system reset by the reset / interrupt controller 502. In this case, the random number maximum value setting register 535 may be formed not to be writable until a reset signal is input after data is written, instead of being controlled so as not to be writable by the CPU 56.

  The clock signal output circuit 524 includes a cycle setting register (RPS) 537 for storing cycle setting data for designating the cycle of the clock signal output to the selector 528 and the inverting circuit 532 (that is, the count value update cycle). The clock signal output circuit 524 divides the reference clock signal CLK input from the clock circuit 501 mounted on the game control microcomputer 560 based on the cycle setting data stored in the cycle setting register 537, and generates a random number circuit. A clock signal (random number generating clock signal SI1) used to generate a random number value is generated inside 503. By doing so, the clock signal output circuit 524 operates to output the random number generation clock signal SI1 for updating the count value C to the counter 521 on condition that the clock signal has been input a predetermined number of times. . The period setting data is data for setting how many times the reference clock signal CLK input from the clock circuit 501 is to be divided. The clock output circuit 524 outputs the generated random number generating clock signal SI1 to the selector 528 and the inverting circuit 532. For example, when the cycle setting data “0Fh (= 16)” is written in the cycle setting register 537, the clock signal output circuit 524 divides the reference clock signal CLK input from the clock circuit 501 by 16, and generates random numbers. A clock signal SI1 is generated. In this case, the cycle of the random number generating clock signal SI1 generated by the clock signal output circuit 524 is “cycle of system clock signal × 128 × 16”.

  FIG. 12 is an explanatory diagram showing an example of the cycle setting register 537. As shown in FIG. 12, the cycle setting register 537 is an 8-bit register, and the initial value is set to “256 (= FFh)”. The cycle setting register 537 is configured in a state where both writing and reading are possible.

  In addition, a predetermined lower limit value is determined for the value of the cycle setting data set in the cycle setting register 537. In this embodiment, when the cycle setting data “00h to 06h” designating a value smaller than the lower limit value “system clock signal cycle × 128 × 7” is written in the cycle setting register 537, the CPU 56 In 537, the cycle setting data “07h” for specifying the lower limit value “system clock signal cycle × 128 × 7” is reset. That is, the period that can be set in the period setting register 537 is “system clock signal period × 128 × 7” to “system clock signal period × 128 × 256”, and the CPU 56 is set to a value smaller than the lower limit value. If it is determined that the cycle setting data is correct, the cycle setting data is reset. The CPU 56 controls the period setting register 537 in which the period setting data is written to be unwritable until the game control microcomputer 560 is reset by the reset / interrupt controller 502. Instead of controlling the CPU 56 to disable writing, the period setting register 537 may be formed so that writing is not possible until a reset signal is input after data is written.

  Note that, without setting the cycle setting data as the lower limit value in the cycle setting register 537, the clock signal output circuit 524, for example, directly supplies the reference clock signal CLK to the counter 521 and the inverting circuit 532 based on the set cycle setting data. You may make it output. In this case, the CPU 56 does not need to perform processing for setting the value of the cycle setting data set in the cycle setting register 537 by comparing it with the lower limit value. The counter 521 updates the count value C every time the reference clock signal CLK is input from the clock signal output circuit 524.

  The count value update signal output circuit 525 includes a count value update register (RGN) 538 that stores count value update data “01h”. The count value update data is data for requesting update of the count value. The count value update signal output circuit 525 outputs the count value update signal SI3 to the selector 528 in response to the count value update data “01h” being written in the count value update register 538.

  FIG. 13 is an explanatory diagram illustrating an example of the count value update register 538. As shown in FIG. 13, the count value update register 538 is an unreadable 8-bit register, and is configured so that only bit 0 can be written. Therefore, even if control is performed to write a value to bits 1 to 7 of the count value update register 538, it is invalid.

  The random value read signal output circuit 526 includes a random value take-in register (RLT) 539 for storing random value take-in data “01h”. The random value acquisition data is data for requesting acquisition of the count value to the random value storage circuit 531. The random value read signal output circuit 526 generates a random value read signal for requesting reading of the random value in response to the random value fetch data “01h” being written in the random value fetch register 539. Output to the circuit 533.

  FIG. 14 is an explanatory diagram showing an example of the random value fetch register 539. As shown in FIG. 14, the random value fetch register 539 is an unreadable 8-bit register. The random value fetch register 539 is configured so that only bit 0 can be written. In other words, even if control is performed to write a value to bits 1 to 7 of the random value fetch register 539, it is invalidated.

  The random number update method selection signal output circuit 527 includes a random number update method selection register (RTS) 540 that stores random number update method selection data. The random number update method selection data is data for designating one of the random number update methods that is a method for updating the value of the random R. The random number update method selection signal output circuit 527 responds to the random number update method selection data written in the random number update method selection register 540 with a random number corresponding to the random number update method specified by the written random number update method selection data. The update method selection signal is output to the selector 528 and the latch signal generation circuit 533.

  FIG. 15A is an explanatory diagram illustrating an example of the random number update method selection register 540. As shown in FIG. 15A, the random number update method selection register 540 is an 8-bit register, and the initial value is set to “00h”. The random number update method selection register 540 is configured in a state where bits 0 to 1 can be written and read. The random number update method selection register 540 is configured in a state where bits 2 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 2 to 7 of the random number update method selection register 540, it is invalid, and all the values read from bits 2 to 7 are “0 (= 000000b)”.

  FIG. 15B is an explanatory diagram of an example of random number update method selection data written to the random number update method selection register 540. As shown in FIG. 15B, the random number update method selection data is composed of 2-bit data. The random number update method selection data “01b” is used to specify the first random number update method. The random number update method selection data “10b” is used to specify the second random number update method. In this embodiment, the first random number update method is a method of updating the count value triggered by the output of the count value update signal SI3 from the count value update signal output circuit 525. The second random number update method is a method of updating the count value triggered by the output of the random number generation clock signal SI1 from the clock signal output circuit 524. Further, when the random number update method selection data “01b” or “10b” is written in the random number update method selection register 540, the random number circuit 503 is ready to be activated. On the other hand, when the random number update method selection data “00b” or “11b” is written to the random number update method selection register 540, the random number circuit 503 cannot be activated.

  The selector 528 selects either the count value update signal SI 3 output from the count value update signal output circuit 525 or the random number generation clock signal SI 1 output from the clock signal output circuit 524 and outputs the selected signal to the counter 521. When a random number update method selection signal (also referred to as a first random number update method selection signal) corresponding to the first random number update method is input from the random number update method selection signal output circuit 527, the selector 528 outputs a count value update signal. The count value update signal SI3 output from the circuit 525 is selected and output to the counter 521. On the other hand, when a random number update method selection signal (also referred to as a second random number update method selection signal) corresponding to the second random number update method is input from the random number update method selection signal output circuit 527, the selector 528 outputs a clock signal. The random number generation clock signal SI 1 output from the circuit 524 is selected and output to the counter 521. When the first update method selection signal is input from the random number update method selection signal output circuit 527, the selector 528 receives a clock signal according to the count value update signal SI3 output from the count value update signal output circuit 525. A numerical value update instruction signal for instructing update of numerical data synchronized with the random number generation clock signal SI1 output from the output circuit 524 may be output to the counter 521.

  The random number circuit activation signal output circuit 530 includes a random number circuit activation register (RST) 541 that stores random number circuit activation data “80h”. The random circuit activation data is data for requesting activation of the random number circuit 503. When the random number circuit activation data “80h” is written in the random number circuit activation register 541, the random number circuit activation signal output circuit 530 outputs a predetermined random number circuit activation signal to the counter 521 and the clock signal output circuit 537, and the counter 521 and the clock The signal output circuit 524 is turned on. The random number circuit 503 is activated by starting the count value updating operation by the counter 521 and the internal clock signal output operation by the clock signal output circuit 524.

  FIG. 16 is an explanatory diagram illustrating an example of the random number circuit activation register 541. As shown in FIG. 16, the random number circuit activation register 541 is an 8-bit register, and the initial value is set to “00h”. The random number circuit activation register 541 is configured such that only bit 7 can be written and read. The random number circuit activation register 541 is configured in a state in which bits 0 to 6 cannot be written or read. That is, even if control is performed to write a value to bits 0 to 6 of the random number circuit activation register 541, the value is invalid, and all values read from bits 0 to 6 are “0 (= 000000b)”.

  The random value storage circuit 531 is a 16-bit register, for example, and stores a random R value that is a random number used in the jackpot determination in the game control process. The random value storage circuit 531 stores the count value C output from the counter 521 via the comparator 522 as a random R value in response to the input of the latch signal SL from the latch signal generation circuit 533. Each time the latch signal SL is input from the latch signal generation circuit 533, the random value storage circuit 531 reads the count value C updated by the counter 521 and stores the random R value.

  FIG. 17 is a circuit diagram showing a configuration example of the random value storage circuit 531. As shown in FIG. 17, the random value storage circuit 531 includes two AND circuits 201 and 203, two NOT circuits 202 and 204, 16 flip-flop circuits 2101 to 2116, and 16 OR circuits. 2201-2216.

  As shown in FIG. 17, the input terminal of the AND circuit 201 is connected to the output terminal of the latch signal generation circuit 533 and the output terminal of the NOT circuit 204, and the output terminal is connected to the input terminal of the NOT circuit 202 and the flip-flop circuit 2101. Are connected to clock terminals Clk1 to Clk16. The input terminal of the NOT circuit 202 is connected to the output terminal of the AND circuit 201, and the output terminal is connected to one input terminal of the AND circuit 203.

  The input terminal of the AND circuit 203 is connected to the output terminal of the NOT circuit 202 and the CPU 56 mounted on the game control microcomputer 560, and the output terminal is connected to the input terminal of the NOT circuit 204. The input terminal of the NOT circuit 204 is connected to the output terminal of the AND circuit 203, and the output terminal is connected to one input terminal of the AND circuit 201 and one input terminal of the OR circuits 2201 to 2216.

  Input terminals D1 to D16 of the flip-flop circuits 2101 to 2116 are connected to an output terminal of the comparator 522. The clock terminals Clk1 to Clk16 of the flip-flop circuits 2101 to 2116 are connected to the output terminal of the AND circuit 201, and the output terminals Q1 to Q16 are connected to the other input terminals of the OR circuits 2201 to 2216.

  The input terminals of the OR circuits 2201 to 2216 are connected to the output terminal of the NOT circuit 204 and the output terminals of the flip-flop circuits 2101 to 2116, and the output terminals are connected to the CPU 56 mounted on the game control microcomputer 560. .

  The operation of the random value storage circuit 531 will be described. FIG. 18 is a timing chart showing the timing at which each signal is input to the random value storage circuit 531 and the timing at which the random value storage circuit 531 outputs each signal. As shown in FIG. 18, when the output control signal SC (high level signal in this example) is not input from the CPU 56 mounted in the game control microcomputer 560 (that is, to one input terminal of the AND circuit 203). When the latch signal SL is input from the latch signal generation circuit 533 (when the input is at a low level) (at the timings T1, T2, and T7 in the example shown in FIG. 18), the two input terminals of the AND circuit 201 are connected. Both inputs are high. Therefore, the signal SR output from the output terminal of the AND circuit 201 is at a high level. The signal SR output from the AND circuit 201 is input to the clock terminals Clk1 to Clk16 of the flip-flop circuits 2101 to 2116.

  The flip-flop circuits 2101 to 2116 respond to the rising edges of the signal SR input from the clock terminals Clk1 to Clk16, and receive the bit data C1 to C1 of the count value C input from the comparator 522 via the input terminals D1 to D16. C16 is latched and stored as bit data R1 to R16 of a random value. The flip-flop circuits 2101 to 2116 output random R bit data R1 to R16 to be stored from the output terminals Q1 to Q16.

  When the output control signal SC is not input (in the example shown in FIG. 18, the period up to the timing T3 and the period after the timing T6), the input to one input terminal of the AND circuit 203 is at the low level. The signal SG output from the output terminal of the circuit 203 is at a low level. The signal SG output from the AND circuit 203 is inverted in the NOT circuit 204 to be a high level signal. A high level signal is input from the NOT circuit 204 to one input terminal of the OR circuits 2201 to 2216.

  As described above, since the input to one of the input terminals of the OR circuits 2201 to 2216 is at a high level, the OR is input regardless of whether the signal input to the other input terminal is at a high level or a low level. The circuits 2201 to 2216 output high level signals. That is, the signals SO1 to SO16 output from the OR circuits 2201 to 2216 are all at a high level regardless of whether the values of the input random R bit data R1 to R16 are “0” or “1”. (“1”). By doing so, the value output from the random value storage circuit 531 is always “65535 (= 1111111111111111b)”, and the random R cannot be read from the random value storage circuit 531. That is, even if an attempt is made to read a random number from the random value storage circuit 531, only the same value “65535” can always be read from the random value storage circuit 531, and when the output control signal SC is not input, the random value storage circuit 531 becomes an unreadable (disabled) state. When the 16-bit random number circuit 503b is used, the value “65535” as the random number value may be used. In this case, even if the game control microcomputer 560 reads the value “65535”, it cannot determine whether the value is a random number or an unreadable state. Therefore, in the determination table for each jackpot determination shown in FIG. 37, when the random R is “65535”, it may be set to determine “lost” in advance.

  When the output control signal SC is input from the CPU 56 when the latch signal SL is not input from the latch signal generation circuit 533 (in the example shown in FIG. 18, the period from the timing T4 to the timing T6), Since the inputs to the two input terminals are both at the high level, the signal SG output from the output terminal of the AND circuit 203 is at the high level. The signal SG output from the AND circuit 203 is inverted in the NOT circuit 204 to be a low level signal. A low level signal is input from the NOT circuit 204 to one input terminal of the OR circuits 2201 to 2216.

  As described above, since the input to one input terminal of the OR circuits 2201 to 2216 is at a low level, when the signal input to the other input terminal is at a high level, the output from the output terminals of the OR circuits 2201 to 2216 is high. A level signal is output. In addition, when a signal input to the other input terminal of the OR circuits 2201 to 2216 is at a low level, a low level signal is output from the OR circuits 2201 to 2216. That is, the values of the random R bit data R1 to R16 input to the other input terminals of the OR circuits 2201 to 2216 are unchanged from the output terminals of the OR circuits 2201 to 2216 (that is, the values of the bit data R1 to R16 are “ “1” is output when it is “1” and “0” when it is “0”). By doing so, random R can be read from the random value storage circuit 531. That is, when the output control signal SC is input, the random value storage circuit 531 is in a readable (enable) state.

  However, if the latch signal SL is input from the latch signal generation circuit 533 before the output control signal SC is input from the CPU 56, the input to one input terminal of the AND circuit 203 is at a low level. Even if the output control signal SC is input while the signal SL is being input (in the example shown in FIG. 18, the period from the timing T3 to the timing T4), the signal SG output from the output terminal of the AND circuit 203. Remains low. The signal SG output from the AND circuit 203 is inverted in the NOT circuit 204 to be a high level signal. A high level signal is input from the NOT circuit 204 to one input terminal of the OR circuits 2201 to 2216.

  As described above, since the input to one of the input terminals of the OR circuits 2201 to 2216 is at a high level, the OR is input regardless of whether the signal input to the other input terminal is at a high level or a low level. The signals SO1 to SO16 output from the circuits 2201 to 2216 are all at a high level. Even though the output control signal SC is input, the random R cannot be read from the random value storage circuit 531. That is, when the latch signal SL is input, the random value storage circuit 531 cannot receive the output control signal SC. When the 16-bit random number circuit 503b is used, the value “65535” as the random number value may be used. In this case, even if the game control microcomputer 560 reads the value “65535”, it cannot determine whether the value is a random number or an unreadable state. Therefore, in the determination table for each jackpot determination shown in FIG. 37, when the random R is “65535”, it may be set to determine “lost” in advance.

  In addition, when the output control signal SC is input from the CPU 56 before the latch signal SL is input from the latch signal generation circuit 533, the input to one input terminal of the AND circuit 201 is at a low level. Even if the latch signal SL is input while the control signal SC is being input (timing T5 in the example shown in FIG. 18), the signal SR output from the output terminal of the AND circuit 201 remains at the low level. It becomes. Therefore, the signal SR input to the clock terminals Clk1 to Clk16 of the flip-flop circuits 2101 to 2116 does not rise from the low level to the high level, and the random R bit data R1 to R16 stored in the flip-flop circuits 2101 to 2116. Although the latch signal SL is input, the stored random number is not updated. That is, when the output control signal SC is input, the random value storage circuit 531 cannot receive the latch signal SL.

  The inverting circuit 532 generates the inverted clock signal SI2 in which the polarity of the clock signal is inverted by inverting the signal level in the random number generating clock signal SI1 input from the clock signal output circuit 524. Further, the inverting circuit 532 outputs the generated inverted clock signal SI2 to the latch signal generating circuit 533.

  Note that the random number circuit 503 may include a delay circuit instead of the inverting circuit 532. In this case, the delay circuit generates a delayed clock signal obtained by delaying the clock signal by delaying the random number generating clock signal SI1 input from the clock signal output circuit 524. The delay circuit outputs the generated delayed clock signal to the latch signal generation circuit 533. Therefore, the latch signal generation circuit 533 outputs a latch signal to the random value storage circuit 531 in synchronization with the delayed clock signal obtained by delaying the random number generation clock signal SI1.

  The latch signal generation circuit 533 is configured using a selector, a flip-flop circuit, and the like. The latch signal generation circuit 533 receives the random number read signal from the random number read signal output circuit 526 and the inverted clock signal SI2 from the inversion circuit 532, and stores the random value in the random value storage circuit 531. SL is output. The latch signal generation circuit 533 outputs the latch signal SL in accordance with the random value update method designated by the random number update method selection signal from the random number update method selection signal output circuit 527. In this case, when the first random number update method selection signal output circuit 527 receives the first random number update method selection signal output circuit 527, the latch signal generation circuit 533 selects the inverted clock signal SI2 output from the inversion circuit 532, and the latch signal It outputs to the random value storage circuit 531 as SL. On the other hand, when the second random number update method selection signal is input from the random number update method selection signal output circuit 527, the latch signal generation circuit 533 inverts the random value read signal output from the random value read signal output circuit 526. In synchronization with the rising edge of the inverted clock signal SI2 output from the circuit 532, the latch signal SL is output to the random value storage circuit 531.

  The timer circuit 534 inputs a winning detection signal SS indicating that a winning of a game ball to the starting port 14 has been detected from the starting port switch 14a. The timer circuit 534 measures the time during which the winning detection signal SS is continuously input from the start port switch 14a. Then, when the measurement time reaches a predetermined period (for example, 3 ms), the timer circuit 534 writes the random number value capture data “01h” in the random value capture register 539 of the random value read signal output circuit 526. For example, the timer circuit 534 is configured by an up counter or a down counter that is activated in response to the input of a high level signal. The timer circuit 534 receives the reference clock signal CLK sequentially input from the clock circuit 501 while the input from the start port switch 14a is at a high level (that is, while the winning detection signal SS is continuously input). Count up or down. Then, when the count value to be counted up or down reaches a value corresponding to 3 ms, the timer circuit 534 determines that the winning detection signal SS is input from the start port switch 14a, and receives the random number value capture data “01h”. Write to the random value fetch register 539.

  Next, the configuration of the serial communication circuit 505 will be described. The serial communication circuit 505 performs serial communication with a microcomputer of each control board (for example, the payout control board 37) in a data format using a full duplex system, an asynchronous system, and standard NRZ (non-return zero) encoding. The serial communication circuit 505 includes a transmission unit that transmits various data (for example, a prize ball number command and an effect control command) to the microcomputer of each control board, and various data (for example, a prize ball ACK) from the microcomputer of each control board. Command).

  FIG. 19 is a block diagram illustrating a configuration example of the transmission unit of the serial communication circuit 505. FIG. 20 is a block diagram illustrating a configuration example of a receiving unit of the serial communication circuit 505. The serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, two status registers 705 and 706, three control registers 707, 708, and 709, a transmission data register 710, a reception data register 711, a transmission shift register 712, and a reception. Shift register 713, interrupt control circuit 714, transmission format / parity generation circuit 715, and reception format / parity check circuit 716. As shown in FIG. 19, the transmission unit of the serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, a status register A 705, control registers 707, 708, and 709, and a transmission data register 710. , A transmission shift register 712, an interrupt control circuit 714, and a transmission format / parity generation circuit 715. As shown in FIG. 20, the receiving unit of the serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, status registers 705 and 706, control registers 707, 708, and 709, received data, among these components. The register 711, the reception shift register 713, the interrupt control circuit 714, and the reception format / parity check circuit 716 are configured.

  In the serial communication circuit 505, the transmission unit and the reception unit are actually configured using a common circuit. As described above, the serial communication circuit 505 functions as a transmission circuit or a reception circuit by properly using each component of the serial communication circuit 505.

  First, the data format of data transmitted and received by the serial communication circuit 505 with the microcomputer mounted on each control board will be described. FIG. 21 is an explanatory diagram showing an example of a data format of data transmitted / received by the serial communication 505 to / from a microcomputer mounted on each control board. As shown in FIG. 21, the data format of data transmitted and received by the serial communication circuit 505 is configured with a start bit, data, and stop bits as one frame. Further, the data length of data transmitted / received by the serial communication circuit 505 can be set to either 8 bits or 9 bits by performing an initial setting in a serial communication circuit setting process described later. FIG. 21A shows an example of a data format when the data length is set to 8 bits. FIG. 21B is an example of a data format when the data length is set to 9 bits.

  As shown in FIG. 21, the data format of data transmitted and received by the serial communication circuit 505 is a start bit (logic “0”) indicating the start of one frame after an idle line of high level (logic “1”). ")including. The data format includes 8-bit or 9-bit transmission / reception data after the start bit. The data format includes a stop bit (logic “1”) indicating the end of one frame after transmission / reception data.

  The serial communication circuit 505 transmits / receives data first from the least significant bit (bit 0) of transmission / reception data according to the data format shown in FIG. Further, if initial setting is performed in a serial communication circuit setting process described later, it is possible to set so that a parity bit is added to transmission / reception data. When a setting is made to add a parity bit, the most significant bit of the transmission / reception data is used as a parity bit (odd parity or even parity). For example, when the data length is set to 8 bits, bit 7 of transmission / reception data is used as a parity bit. For example, when the data length is set to 9 bits, bit 8 of transmission / reception data is used as a parity bit.

  The baud rate generation circuit 703 generates a baud rate used by the serial communication circuit 505 based on a clock signal output from the clock circuit 501 and a setting value (also referred to as a baud rate setting value) set in the baud rate register 702. In this case, the baud rate generation circuit 703 obtains the baud rate using a predetermined calculation formula based on the clock signal and the baud rate setting value. For example, the baud rate generation circuit 703 obtains the baud rate used by the serial communication circuit 505 using equation (1).

Baud rate = clock frequency / (baud rate set value x 16) Equation (1)

  FIG. 22 is an explanatory diagram showing an example of the baud rate register 702. The baud rate register 702 is a register that sets a predetermined setting value for designating a baud rate value generated by the baud rate generation circuit 703. For example, it is assumed that the baud rate register 702 obtains the baud rate using the equation (1) and the clock frequency is 3 MHz. In this case, if the desired target baud rate is 1200 bps, the setting value “156” is set in the baud rate register 702. Then, the baud rate generation circuit 703 generates the baud rate “1201.92 bps” using the equation (1) based on the clock frequency “3 MHz” and the baud rate set value “156”. The baud rate register 702 is a 16-bit register, and an initial value is set to “0 (= 00h)”. The baud rate register 702 is configured such that bits 0 to 12 can be written and read. Further, the baud rate register 702 is configured such that bits 13 to 15 cannot be written or read. Therefore, even if a control for writing a value to bits 13 to 15 of the baud rate register 702 is performed, it is invalid, and all the values read from the bits 13 to 15 are “0 (= 000b)”.

  FIG. 23A is an explanatory diagram illustrating an example of the control register A707. The control register A 707 is a register for setting the communication format of the serial communication circuit 505. In this embodiment, the communication format of the serial communication circuit 505 is set by setting the value of each bit of the control register A707. In the control register A707, communication format setting data for setting a communication format such as a data format of transmission / reception data and various communication methods is set. As shown in FIG. 23A, the control register A707 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register A 707 is configured such that bits 0 to 4 can be written and read. Control register A 707 is configured such that bits 5 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 5 to 7 of the control register A707, it is invalid, and all the values read from bits 5 to 7 are “0 (= 000b)”.

  FIG. 23B is an explanatory diagram of an example of communication format setting data set in the control register A707. As shown in FIG. 23B, setting data for setting the data length of data to be transmitted and received is set in bit 4 (bit name “M”) of the control register A707. As shown in FIG. 23B, by setting bit 4 to “0”, the data length of the transmission / reception data is set to 8 bits. Further, by setting bit 4 to “1”, the data length of the transmission / reception data is set to 9 bits.

  In bit 3 (bit name “WAKE”) of control register A707, setting data for setting a wake-up method for waking up a receiver circuit in the standby state (reception unit of serial communication circuit 505). Is set. As shown in FIG. 23 (B), by setting bit 3 to “0”, an idle line wakeup method for wakeup when an idle line is recognized is set. In addition, by setting bit 3 to “1”, an address mark wakeup method for wakeup by recognizing a predetermined address mark is set.

  In bit 2 (bit name “ILT”) of the control register A707, setting data for selecting an idle line detection method of received data is set. As shown in FIG. 23B, by setting bit 2 to “0”, a detection method for detecting the idle line after the start bit included in the received data is set. In addition, by setting bit 2 to “1”, a detection method for detecting an idle line after a stop bit included in received data is set.

  Setting data for setting whether or not to use the parity function is set in bit 1 (bit name “PE”) of the control register A707. As shown in FIG. 23B, the parity function is not used by setting bit 1 to “0”. Further, by setting bit 1 to “1”, the parity function is set to be used.

  Setting data for setting the type of parity when the parity function is used is set in bit 0 (bit name “PT”) of the control register A707. As shown in FIG. 23B, by setting bit 0 to “0”, even parity is set as the parity type. Also, by setting bit 0 to “1”, odd parity is set as the parity type.

  FIG. 24A is an explanatory diagram illustrating an example of the control register B708. The control register B 708 is a register for setting whether to permit an interrupt request from the serial communication circuit 505. In this embodiment, whether the interrupt request from the serial communication circuit 505 is permitted or prohibited is set by setting the value of each bit of the control register B708. In the control register B708, interrupt request setting data indicating whether or not various interrupt requests are permitted is mainly set. In addition to the interrupt request setting data, setting data for performing various settings of the serial communication circuit 505 is also set in the control register B708. As shown in FIG. 24A, the control register B 708 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register B 708 is configured such that bits 0 to 7 can be written and read.

  FIG. 24B is an explanatory diagram showing an example of interrupt request setting data set in the control register B708. As shown in FIG. 24B, setting data indicating whether or not a transmission interrupt request, which is an interrupt request to be performed at the time of data transmission, is permitted is set in bit 7 (bit name “TIE”) of the control register B708. Is done. As shown in FIG. 24B, by setting bit 7 to “0”, the transmission interrupt request is set to be prohibited. Also, by setting bit 7 to “1”, the transmission interrupt request is set to be permitted.

  Bit 6 (bit name “TCIE”) of the control register B708 is set with setting data indicating whether or not to permit a transmission completion interrupt request, which is an interrupt request to be made when data transmission is completed. As shown in FIG. 24B, by setting bit 6 to “0”, the transmission completion interrupt request is set to be prohibited. Also, by setting bit 6 to “1”, the transmission completion interrupt request is set to be permitted.

  Bit 5 (bit name “RIE”) of the control register B 708 is set with setting data indicating whether or not a reception interrupt request, which is an interrupt request when data is received, is permitted. As shown in FIG. 24B, by setting bit 5 to “0”, the reception interrupt request is set to be prohibited. Further, by setting bit 5 to “1”, the reception interrupt request is set to be permitted.

  Bit 4 (bit name “ILIE”) of the control register B708 is set with setting data indicating whether or not an idle line interrupt request that is an interrupt request to be performed when an idle line of received data is detected is permitted. As shown in FIG. 24B, by setting bit 4 to “0”, an idle line interrupt request is set to be prohibited. Further, by setting bit 4 to “1”, it is set to permit an idle line interrupt request.

  In bit 3 (bit name “TE”) of the control register B708, setting data indicating whether to use the transmission circuit (the transmission unit of the serial communication circuit 505) is set. As shown in FIG. 24B, by setting bit 3 to “0”, the transmission circuit is set not to be used. Further, by setting bit 3 to “1”, the transmission circuit is set to be used.

  In bit 2 (bit name “RE”) of the control register B708, setting data indicating whether or not to use the receiving circuit is set. As shown in FIG. 24B, by setting bit 2 to “0”, the receiving circuit is set not to be used. Further, by setting bit 2 to “1”, the receiving circuit is set to be used.

  Setting data indicating whether or not to use the wakeup function of the receiving circuit is set in bit 1 (bit name “RWU”) of the control register B708. As shown in FIG. 24B, by setting bit 1 to “0”, the wakeup function is set not to be used. Further, by setting bit 1 to “1”, the wakeup function is set to be used.

  Setting data indicating whether or not to use a predetermined break code transmission function is set in bit 0 (bit name “SBK”) of the control register B708. As shown in FIG. 24B, by setting bit 1 to “0”, the break code transmission function is set not to be used. Further, by setting bit 1 to “1”, the break code transmission function is set to be used. When bit 1 is set to “1”, the serial communication circuit 505 transmits a break code (for example, a signal continuously including “0”) to the microcomputer mounted on the control board (for example, the payout control board 37).

  FIG. 25A is an explanatory diagram illustrating an example of the status register A705. The status register A 705 is a register for confirming various statuses of the serial communication circuit 505. In this embodiment, the CPU 56 can confirm various statuses of the serial communication circuit 505 by confirming the value of each bit of the status register A 705. As shown in FIG. 25A, the status register A705 is an 8-bit register, and the initial value is set to “0 (= 00h)”. In addition, the status register A705 is configured so that bits 0 to 7 can only be read. Therefore, even if control is performed to write a value to bit 0 to bit 7 of the status register A705, it is invalidated.

  In the present embodiment, as will be described later, when transmission data is not stored in the transmission data register 710 (transmission data empty) or transmission of transmission data stored in the transmission shift register 712 is completed, interrupt control is performed. Circuit 714 sets the corresponding bit in status register A705. Then, the CPU 56 reads the value of each bit set in the status register A705.

  FIG. 25B is a diagram showing an example of status confirmation data stored in the status register A705. As shown in FIG. 25B, transmission data indicating that transmission data is not stored in transmission data register 710 in bit 7 (bit name “TDRE”) of status register A 705 (transmission data empty). Stores an empty flag. As shown in FIG. 25B, when “0” is stored in the bit 7, the transmission data is not yet transferred from the transmission data register 710 to the transmission shift register 712, and transmitted to the transmission data register 710. Indicates that the data is still stored. When “1” is stored in bit 7, the transmission data is transferred from the transmission data register 710 to the transmission shift register 712, and there is no transmission data in the transmission data register 710 (transmission data empty). ).

  Bit 6 (bit name “TC”) of the status register A 705 stores a transmission completion flag indicating that transmission of transmission data from the serial communication circuit 505 has been completed. As shown in FIG. 25B, when “0” is stored in bit 6, the transmission data stored in the transmission shift register 712 is being transmitted, and the transmission data from the serial communication circuit 505 is not transmitted. Indicates that transmission has not been completed. Further, when “1” is stored in bit 6, the transmission data stored in the transmission shift register 712 has been transferred, and transmission of transmission data from the serial communication circuit 505 has been completed. It shows that.

  Note that the transmission of the transmission data is completed, and the game control microcomputer 560 waits for a reception confirmation signal from the transmission destination microcomputer. In this embodiment, when a transmission interrupt is set as will be described later, the serial communication circuit 505 sets the bit 6 of the status register A 705 to “1” and confirms reception when detecting the completion of transmission of transmission data. An interrupt request (referred to as an interrupt request during transmission) is made to the CPU 56 as a signal waiting state.

  Bit 5 (bit name “RDRF”) of status register A 705 stores a reception data full flag indicating that reception data is stored in reception data register 711 (reception data full). As shown in FIG. 25B, when “0” is stored in bit 5, it indicates that the reception data register 711 contains no reception data. When “1” is stored in bit 5, the value of the reception shift register 713 is transferred to the reception data register 711, and reception data is stored in the reception data register 711 (reception data Full).

  When the reception data is stored in the reception data register 711, the CPU 56 is ready to perform reception processing by reading the reception data from the reception data register 711. In this embodiment, when the serial communication circuit 505 detects that the received data is full, the bit 5 of the status register A 705 is set to “1” and an interrupt request (interrupt upon reception) is made to the CPU 56 that reception processing is possible. Request).

  Bit 4 (bit name “IDLE”) of status register A705 stores an idle line detection flag indicating that the receiving circuit has detected an idle line. As shown in FIG. 25B, when “0” is stored in bit 4, it indicates that the receiving unit of the serial communication circuit 505 has not detected an idle line. When “1” is stored in bit 4, it indicates that the receiving unit of the serial communication circuit 505 has detected an idle line.

  In bit 3 (bit name “OR”) of the status register A 705, the reception shift register 713 has received the next data before the CPU 56 reads the reception data stored in the reception data register 711 (overload). An overrun flag indicating (run) is stored. As shown in FIG. 25B, when “0” is stored in bit 3, it indicates that the receiving circuit has not detected an overrun. If “1” is stored in bit 3, it indicates that the receiving circuit has detected an overrun.

  If an overrun occurs, the next received data is stored in the receiving shift register 713 before the received data in the received data register 711 is read, so that the received data is overwritten and the CPU 56 receives the received data. It cannot be read correctly. For this reason, communication with the microcomputer mounted on each control board cannot be performed correctly, causing the CPU 56 to malfunction. In this embodiment, when detecting an overrun, the serial communication circuit 505 sets bit 3 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 2 (bit name “NF”) of status register A 705 stores a noise error flag indicating that noise has been detected in the received data. As shown in FIG. 25B, when “0” is stored in bit 2, it indicates that the receiving circuit is not detecting noise in the received data. Further, when “1” is stored in bit 2, it indicates that the receiving circuit has detected noise in the received data.

  For example, when detecting each bit of the received data, the serial communication circuit 505 detects “1” or “0” having a predetermined bit length using the baud rate generated by the baud rate generation circuit 703. In this case, when the detected length of “1” or “0” is less than the predetermined bit length, the serial communication circuit 505 detects a noise error as noise generated in the received data. When a noise error occurs, there is a high possibility that correct received data cannot be received due to the noise, which causes the CPU 56 to malfunction. In this embodiment, when detecting a noise error, the serial communication circuit 505 sets bit 2 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 1 (bit name “FE”) of the status register A 705 indicates that it is detected that the position of the stop bit of the received data is “0” (originally, the stop bit is “1”) (framing error). A framing error flag is stored. As shown in FIG. 25B, when “0” is stored in bit 1, it indicates that the receiving circuit has not detected a framing error in the received data. When “1” is stored in bit 1, it indicates that the receiving circuit has detected a framing error.

  When a framing error occurs, it is in a state where the stop bit of the received data has not been correctly received, and therefore there is a high possibility that correct received data cannot be received, causing the CPU 56 to malfunction. In this embodiment, when detecting a framing error, the serial communication circuit 505 sets bit 1 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 0 (bit name “PF”) of the status register A 705 has a parity error flag indicating that the parity value obtained from the received data does not match the parity value included in the received data (parity error). Is stored. As shown in FIG. 25B, when “0” is stored in bit 0, it indicates that the receiving circuit has not detected a parity error in the received data. Further, when “1” is stored in bit 0, it indicates that the receiving circuit has detected a parity error.

  When a parity error occurs, it is in a state where each data bit or parity bit of the received data has not been correctly received, so there is a high possibility that correct received data cannot be received, causing the CPU 56 to malfunction. In this embodiment, when the serial communication circuit 505 detects a parity error, the serial communication circuit 505 sets bit 0 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 on the assumption that an error has occurred during communication.

  FIG. 26A is an explanatory diagram illustrating an example of the status register B706. The status register B 706 is a register for confirming the reception state (reception status) of the serial communication circuit 505. In this embodiment, the CPU 56 can confirm the reception status of the serial communication circuit 505 by confirming the value of the bit of the status register B 706. As shown in FIG. 26A, the status register B 706 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Further, the status register B 706 is configured so that bit 0 can only be read. Therefore, even if control is performed to write a value to bit 0 of status register A 705, it is invalid. Status register B 706 is configured such that bits 1 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 1 to 7 of the status register A 705, the value is invalid and all the values read from bits 1 to 7 are “0 (= 0000b)”.

  FIG. 26B is a diagram showing an example of status confirmation data stored in the status register B706. As shown in FIG. 26B, a reception active flag indicating that the reception circuit is receiving reception data (reception active) is stored in bit 0 (bit name “RAF”) of the status register B706. . As shown in FIG. 26B, when “0” is stored in bit 0, it indicates that the reception circuit is not receiving reception data. Further, when “1” is stored in bit 0, it indicates that the reception circuit is receiving reception data. When the serial communication circuit 505 detects the start bit, it assumes that reception of received data has started, and sets bit 0 of the status register B 706 to “1”.

  FIG. 27A is an explanatory diagram illustrating an example of the control register C709. The control register C709 is a register for setting whether to permit an interrupt request when a communication error occurs in the serial communication circuit 505. In this embodiment, by setting the value of each bit of the control register C709, it is set whether to permit or prohibit an interrupt request during communication from the serial communication circuit 505. In the control register C709, error interrupt request setting data indicating whether or not various interrupt requests at the time of a communication error are permitted is mainly set. In addition to the error interrupt request setting data, the control register C709 stores 9th bit data when the data length is set to 9 bits. Various settings of the serial communication circuit 505 are also set. As shown in FIG. 27A, the control register C709 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register C709 is configured such that bits 0 to 3 and bits 6 and 7 can be written and read. Further, the control register C709 is configured such that bits 4 and 5 cannot be written or read. Therefore, even if control is performed to write a value to bits 4 and 5 of the control register C709, it is invalid, and all values read from bits 4 and 5 are “0 (= 0000b)”.

  FIG. 27B is an explanatory diagram showing an example of error interrupt request setting data set in the control register C709. As shown in FIG. 27B, bit 7 (bit name “R8”) of the control register C709 stores the 9th bit of the received data when the data length is set to 9 bits. Further, bit 6 (bit name “T8”) of the control register C709 stores the ninth bit of transmission data when the data length is set to nine bits.

  In bit 3 (bit name “ORIE”) of the control register C709, setting data indicating whether or not to permit an overrun flag interrupt request, which is an interrupt request to be performed when an overrun is detected, is set. As shown in FIG. 27B, by setting bit 3 to “0”, the overrun flag interrupt request is set to be prohibited. Further, by setting bit 3 to “1”, the overrun flag interrupt request is set to be permitted.

  Bit 2 (bit name “NEIE”) of the control register C709 is set with setting data indicating whether or not to permit a noise error flag interrupt request, which is an interrupt request to be performed when a noise error is detected. As shown in FIG. 27B, by setting bit 2 to “0”, the noise error flag interrupt request is set to be prohibited. Also, by setting bit 2 to “1”, the noise error flag interrupt request is set to be permitted.

  Bit 1 (bit name “FEIE”) of the control register C709 is set with setting data indicating whether or not to permit a framing error flag interrupt request, which is an interrupt request to be performed when a framing error is detected. As shown in FIG. 27B, by setting bit 1 to “0”, the framing error flag interrupt request is set to be prohibited. Further, by setting bit 1 to “1”, the framing error flag interrupt request is set to be permitted.

  Bit 0 (bit name “PEIE”) of the control register C709 is set with setting data indicating whether or not to permit a parity error flag interrupt request which is an interrupt request to be performed when a parity error is detected. As shown in FIG. 27B, by setting bit 0 to “0”, the parity error flag interrupt request is set to be prohibited. Further, by setting bit 0 to “1”, the parity error flag interrupt request is set to be permitted.

  FIG. 28 is an explanatory diagram illustrating an example of a data register included in the serial communication circuit 505. The data register 701 is a register that stores data transmitted and received by the serial communication circuit 505. As shown in FIG. 28, the data register is an 8-bit register, and the initial value is set to “0 (= 00h)”. Data register 701 is configured such that bits 0 to 7 can be written and read.

  In this embodiment, when the serial communication circuit 505 transmits transmission data, the data register is used as the transmission data register 710. When the data length is set to 9 bits, bit 6 of the data register and control register C709 is used as the transmission data register 710. In this case, bits 0 to 7 of the data register are used as bits 0 to 7 of the transmission data register 710, and bit 6 of the control register C709 is used as bit 8 of the transmission data register 710.

  When the serial communication circuit 505 receives received data, the data register is used as the received data register 711. When the data length is set to 9 bits, bit 7 of the data register and control register C709 is used as the reception data register 711. In this case, bits 0 to 7 of the data register are used as bits 0 to 7 of the reception data register 711, and bit 7 of the control register C709 is used as bit 8 of the reception data register 711.

  The interrupt control circuit 714 makes various interrupt requests to the CPU 56. In this embodiment, when the bit 6 (TCIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 notifies the CPU 56 when transmission of transmission data to the transmission data register 710 is completed. In addition to outputting an interrupt signal, an interrupt request is made by setting bit 6 (TC) of status register A705 to “1”. The interrupt control circuit 714 may output a different interrupt signal to the CPU 56 for each interrupt factor, instead of making the interrupt factor identifiable by the set value of the bit of the status register A705.

  In addition, when bit 5 (RIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 enters a state where reception data is stored in the reception data register 711 (when reception data full is detected). ), An interrupt signal is output to the CPU 56, and an interrupt request is made by setting bit 5 (RDRF) of the status register A705 to “1”.

  Further, when any of the bits 0 to 3 of the control register C709 is set to “1”, the interrupt control circuit 714 outputs an interrupt signal to the CPU 56 and also indicates the type of communication error. In response to this, an interrupt request is made by setting "1" to bits 0 to 3 of the status register A705. For example, if bit 3 (ORIE) of the control register C709 is set to “1”, “1” is set to bit 3 (OR) of the status register A705 when an overrun is detected and an interrupt request is made. To do. For example, when bit 2 (NEIE) of the control register C709 is set to “1”, when a noise error is detected and an interrupt request is made, “1” is set to bit 2 (NF) of the status register A705. Set. For example, when bit 1 (FEIE) of the control register C709 is set to “1”, when a framing error is detected and an interrupt request is made, “1” is set to bit 1 (FE) of the status register A705. Set. For example, when bit 0 (PEIE) of the control register C709 is set to “1”, when a parity error is detected and an interrupt request is made, “1” is set to bit 0 (PF) of the status register A705. Set. When a plurality of communication errors are detected, the interrupt control circuit 714 sets the corresponding bits of the status register A705 to “1” when making an interrupt request based on the plurality of communication errors.

  The transmission format / parity generation circuit 715 generates a data format of transmission data. In this embodiment, the transmission format / parity generation circuit 715 generates a data format by adding a start bit and a stop bit to the transmission data stored in the transmission data register 710 and transfers the data format to the transmission shift register 712. When bit 1 (PE) of the control register A707 is set to “1” and the parity function is set to be used, the transmission format / parity generation circuit 715 adds a parity bit to the transmission data. Generate a data format.

  The reception format / parity check circuit 716 detects the data format of the reception data. In this embodiment, the reception format / parity check circuit 716 detects the start bit and the stop bit from the reception data stored in the reception shift register 713, detects the data portion included in the reception data, and receives the reception data register. Forward to 711. When bit 1 (PE) of the control register A707 is set to “1” and the parity function is set to be used, the reception format / parity check circuit 716 obtains the parity of the reception data and receives the reception data. It is detected whether or not it matches the parity included in. If the obtained value does not match the parity included in the received data, the reception format / parity check circuit 716 detects a parity error. If it is set in the serial communication circuit setting process to be described later that an interrupt request at the time of a communication error is permitted, the interrupt control circuit 714, when detecting a parity error, requests the CPU 56 to interrupt the occurrence of the communication error as a cause of interruption. I do.

  FIG. 29 is an explanatory diagram showing an example of an address map of a storage area in the game control microcomputer 560. As shown in FIG. 29, the area from address 0000h to address 1FFFh in the storage area of the game control microcomputer 560 is allocated to the ROM 54. An area from addresses 7E00h to 7FFFh is allocated to the RAM 55. Further, the area from the address FD00h to the address FE00h is allocated to a built-in register such as the random number maximum value setting register 535.

  As shown in FIG. 29, the area of addresses 0000h to 1FFFh allocated to the ROM 54 includes a user program area and a user program management area. A program (user program) 550 created in advance by a user (for example, a game machine manufacturer) is stored in the user program area in the area of addresses 0000h to 1F7Fh. Further, data (user program execution data) necessary for the CPU 56 to execute the user program 550 is stored in the user program management area in the area of addresses 1F80h to 1FFFh. Of the areas 7E00h to 7FFFh allocated to the RAM 55, the areas 7E00h to 7EFFh are unused areas, and the areas 7F00h to 7FFFh are used as work areas.

  FIG. 30 is an explanatory diagram showing an example of an address map in the user program management area. As shown in FIG. 30, the initial value changing method selected by the user among the initial value changing methods, which is a method for changing the initial value input to the counter 521 of the random number circuit 503, is stored in the area of address 1F97h. The initial value change method setting data for designating is stored. Further, in the areas 1F98h and 1F99h, RAM address data for specifying an address in the RAM 55 (designated RAM address) designated in advance by the user among addresses 7F00h to 7FFFh allocated to the RAM 55 is stored. The In this case, of the values indicating the designated RAM address, the lower value of the designated RAM address is stored in the 1F98h address, and the higher value of the designated RAM address is stored in the 1F99h address.

  FIG. 31 is an explanatory diagram of an example of the initial value change method setting data. As shown in FIG. 31, the initial value change data is composed of 8-bit data. The initial value change data “00h” is data specifying that the initial value is not changed as the initial value change method. In this embodiment, when the initial value change data “00h” is set, the counter 521 of the random number circuit 503 updates the count value from a predetermined initial value “0” to a predetermined final value. Become. Further, the initial value change data “01h” is data specifying that the initial value input to the counter 521 is changed to a value based on an ID number for identifying the game control microcomputer 560 as an initial value change method. It is. In this embodiment, when the initial value change data “01h” is set, the initial value of the counter value updated by the counter 521 is changed from “0” to a value based on the ID number. The count value is updated from the initial value to a predetermined final value.

  The user program 550 stored in the user program area will be described. FIG. 32 is an explanatory diagram showing a configuration example of the user program 550. As shown in FIG. 32, in this embodiment, the user program 550 includes a random number circuit setting program 551 composed of a plurality of types of program modules, a display result determination program 552, a count value permutation change program 554, and a random program. A numerical value update program 555, a serial communication circuit setting program 556, and an interrupt priority setting program 557 are included.

  The random number circuit setting program 551 is a program for executing a random number circuit setting process for performing initial setting for causing the random number circuit 503 to update the value of the random R. That is, the CPU 56 functions as random number circuit initial setting means by executing processing according to the random number circuit setting program 551.

  FIG. 33 is an explanatory diagram showing a configuration example of the random number circuit setting program 551. As shown in FIG. 33, the random number circuit setting program 551 includes a random number maximum value setting module 551a, a random number update method selection module 551b, a cycle setting module 551c, a random number circuit activation module 551d, as a plurality of types of program modules. An initial value changing module 551e and a random number circuit selecting module 551f are included.

  The random number maximum value setting module 551a is a program module for causing the random number circuit 503 to set the maximum value of the random R preset by the user (for example, the manufacturer of the gaming machine). The CPU 56 executes processing according to the random number maximum value setting module 551a, thereby writing random number maximum value setting data for specifying the maximum value of the random R preset by the user in the random number maximum value setting register 535. By doing so, the CPU 56 sets the maximum value of the random R preset by the user in the random number circuit 503. For example, when “255” is set in advance as the maximum value of the random R by the user, the CPU 56 writes the random number maximum value setting data “00FFh” in the random number maximum value setting register 535 and the random R maximum value “255”. Is set in the random number circuit 503.

  The random number update method selection module 551b is a program module for causing the random number circuit 503 to set the random number update method (first random number update method or second random number update method) selected by the user. The CPU 56 writes the random number update method selection data “01b” or “10b” designating the random number update method selected by the user in the random number update method selection register 540 by executing the process according to the random number update method selection module 551b. By doing so, the CPU 56 sets the random number update method selected by the user in the random number circuit 503. Therefore, the game control microcomputer 560 has a function of selecting either the first random number update method or the second random number update method as the random number update method used by the random number circuit 503 for the random number update.

  The cycle setting module 551c is a program for causing the random number circuit 503 to set the cycle of the internal clock signal preset by the user (that is, the cycle in which the clock signal output circuit 524 outputs the clock signal to the selector 528 and the inverting circuit 532). It is a module. The CPU 56 writes processing in the cycle setting register 537 for designating the cycle of the internal clock signal preset by the user by executing processing in accordance with the cycle setting module 551c. By doing so, the CPU 56 sets the cycle of the internal clock signal preset by the user in the random number circuit 503. For example, when the cycle of the internal clock signal is set in advance as “system clock signal cycle × 128 × 16” by the user, the CPU 56 writes the cycle setting data “0Fh” in the cycle setting register 537 and sets the internal clock signal The period “system clock signal period × 128 × 16” is set in the random number circuit 503.

  The random number circuit activation module 551d is a program module for activating the random number circuit 503. The CPU 56 activates the random number circuit 503 by writing the random number circuit activation data “80h” into the random number circuit activation register 541 by executing processing according to the random number circuit activation module 551d.

  The initial value change module 551e is a program module for changing the initial value of the count value updated by the counter 521. The CPU 56 functions as an initial value changing unit by executing processing according to the initial value changing module 551e. The CPU 56 executes the initial value changing module 551e to change the initial value of the count value updated by the counter 521 by the initial value changing method selected by the user. By doing so, the CPU 56 has a function of selecting an initial value changing method.

  In this embodiment, when the initial value change method setting data “01h” is stored in the area 1F97h in the user program management area, the CPU 56 sets the initial value of the count value for each game control microcomputer 560. The value is changed to a value calculated based on the assigned unique ID number.

  For example, the game control microcomputer 560 associates, in a predetermined storage area of the ROM 54, the ID number of the game control microcomputer 560 with a calculated value obtained by performing a predetermined calculation based on the ID number. I remember it. In this case, for example, if the ID number of the game control microcomputer 560 is “100”, the calculated value “150” obtained by adding the predetermined value “50” to the ID number “100” is set in advance as the ID number. Are stored in association with each other. Further, for example, the calculated value “50” obtained by subtracting the predetermined value “50” from the ID number “100” is stored in advance in association with the ID number. Further, for example, only a predetermined value may be stored in advance in association with the ID number. Then, the CPU 56 of the game control microcomputer 560 adds a value “150” obtained by adding an ID number (for example, “100”) to a predetermined value (for example, “50”) stored in advance, and sets the initial count value. The CPU 56 may also use a value “50” obtained by subtracting a predetermined value (eg, “50”) stored in advance from the ID number (eg, “100”) as an initial value of the count value. The game control microcomputer 560 may store the ID number of the game control microcomputer 560 in a predetermined storage area of the ROM 54 as long as data writing is prohibited in the storage area. Often, a predetermined storage area of the RAM 55 (however, the RAM 55 is not erased (cleared) even when the power supply of the gaming machine is stopped). There may be stored in a condition).

  When the initial value change method setting data “01h” is stored, the CPU 56 changes the initial value of the count value to the calculated value based on the ID number stored in advance. By doing so, the randomness of the random number generated by the random number circuit 503 can be further improved, and the initial value of the random number can be made difficult to recognize simply by looking at the ID number of the game control microcomputer 560. . Therefore, it is possible to more reliably prevent the transition condition to the big hit state from being illegally established by an action such as generating a captured signal using a radio signal to the gaming machine, and improving security. Can be improved.

  For example, when initial value change method setting data “01h” is stored, the CPU 56 calculates the ID number of the game control microcomputer 560 and a predetermined value (for example, adds a predetermined value to the ID number). The initial value of the count value is changed to the calculated value obtained. In this case, for example, the CPU 56 may calculate a value that is randomly changed using a random number as an ID number, thereby randomly updating a value used for the calculation and obtaining an initial value. By doing so, the randomness of the random numbers generated by the random number circuit 503 can be further improved.

  The random number circuit selection module 551f is a program module for setting a random number circuit to be used when executing a timer interrupt process including a game control process from among the random number circuits 503 built in the game control microcomputer 560. The CPU 56 executes processing in accordance with the random number circuit selection module 551f, so that any of the two random number circuits (12-bit random number circuit 503a and 16-bit random number circuit 503b) built in the game control microcomputer 560 is selected. Set whether to use when executing timer interrupt processing. For example, the CPU 56 uses a 12-bit random number circuit 503a or 16-bit as a random number circuit used when executing the timer interrupt process according to a predetermined set value (a value set in advance by the user) stored in a predetermined storage area of the ROM 54. The random number circuit 503b is set.

  Note that both the 12-bit random number circuit 503a and the 16-bit random number circuit 503b may be set as random number circuits used when the timer interrupt process is executed. In this case, for example, the CPU 56 may determine the variation pattern based on the random number generated by the 12-bit random number circuit 503a and perform the jackpot determination based on the random number generated by the 16-bit random number circuit 503b. In this embodiment, the random value storage circuit 531 exists in each of the 12-bit random number circuit 503a and the 16-bit random number circuit 503b (that is, a random-value storage circuit that stores a random number for 12 bits and a 16-bit random-number storage circuit). A random value storage circuit for storing random numbers exists separately). When both the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are set, the CPU 56 is provided in the RAM 55 with the random number read from the 12-bit random number circuit 503a and the random number read from the 16-bit random number circuit 503b. Stored in separate buffer areas. Therefore, even when the timing for reading a random number from the 12-bit random number circuit 503a and the timing for reading a random number from the 16-bit random number circuit 503b are the same, two different random numbers can be extracted and stored in different buffer areas.

  The random value update program 555 is a program for updating the value of the random R stored in the random value storage circuit 531 when the first random number update method is selected as the random number update method. The CPU 56 functions as a random value updating unit by executing processing according to the random value updating program 555. When the first random number update method is selected, the CPU 56 executes the random number value update program 555 and writes the count value update data “01h” in the count value update register 538, whereby the count value is stored in the counter 521. And the value of the random R stored in the random value storage circuit 531 is updated. When the second random number update method is selected as the random number update method, the counter 521 is updated with the random number generation clock signal output from the clock signal output circuit 537, and the random value storage circuit 531 is updated. The value of random R stored in is updated.

  The display result determination program 552 is a program for determining whether or not the display result on the special symbol display 8 is a jackpot symbol. The CPU 56 functions as a display result determination unit by executing processing according to the display result determination program 552.

  In this embodiment, the CPU 56 follows the display result determination program 552 in response to the fact that the game ball has won the variable winning ball device 15 and the condition (execution condition) for executing the variable symbol special display is established. Execute the process. Then, the CPU 56 reads the updated random R value from the random value storage circuit 531, and determines whether or not the display result on the special symbol display 8 is a jackpot symbol.

  FIG. 34 is an explanatory diagram illustrating an operation in which the CPU 56 updates the random R value or reads the random R value when the first random number update method is selected. As shown in FIG. 34, when the first random number update method is selected, the CPU 56 writes the count value update data “01h” to the count value update register 538, thereby storing the random number value storage circuit 531. The value of R (for example, “2”) is updated. Then, the CPU 56 receives a random R value from the random value storage circuit 531 in response to the fact that the game ball has won the variable winning ball device 15 and the condition (execution condition) for executing the variable symbol special display is established. (For example, “2”) is read.

  When the random R value stored in the random value storage circuit 531 is further updated, an interval equal to or longer than the period of the system clock signal output from the clock circuit 501 has elapsed since the random R value was updated at the previous update. Sometimes, the count value update data “01h” must be written to the count value update register 538. This is because it is necessary to secure time for reading the updated random R value from the random value storage circuit 531.

  FIG. 35 is an explanatory diagram showing an operation in which the CPU 56 reads the value of the random R when the second random number update method is selected. As shown in FIG. 35, when the second random number update method is selected, the timer circuit 534 writes the random number value take-in data “01h” into the random value take-in register 539, so that the counter 521 outputs it. The count value (for example, “2”) is taken into the random value storage circuit 531 and the random R value stored in the random value storage circuit 531 is updated. Then, the CPU 56 reads the updated random R value (for example, “2”) from the random value storage circuit 531.

  Specifically, when the second random number update method is selected, the counter 521 updates the count value C using the input of the random number generation clock signal SI1 as a trigger. Thereafter, when the random value fetch data “01h” is written into the random value fetch register 539, the latch signal generation circuit 533 outputs the latch signal SL to the random value storage circuit 531. Then, the random value storage circuit 531 reads and stores the count value output from the counter 521 with the input of the latch signal SL as a trigger. Then, the CPU 56 reads the value of random R stored in the random value storage circuit 531.

  If the timer circuit 534 does not write the random number value acquisition data “01h” to the random number value acquisition register 539, even if the counter 521 updates the count value, the random number value storage circuit 531 does not update the counter 521. Do not memorize numerical values. For example, the timer circuit 534 writes the random value take-in data “01h” into the random value take-in register 539, the count value “3” output from the counter 521 is taken into the random value storage circuit 531, and the random value storage circuit 531 , The random R value “3” stored therein is updated. In this case, the count value output from the counter 521 is updated from “3” to “4” or “5” unless the timer circuit 534 writes the random number value acquisition data “01h” into the random number acquisition register 539 again. However, the random value stored in the random value storage circuit 531 is not updated, and the random value read from the random value storage circuit 531 remains “3”.

  The count value permutation change program 554 writes count value permutation change data “01h” to the count value permutation change register 536, and executes count value permutation change processing for changing the permutation of count values stored in the random value storage circuit 531. It is a program for. The CPU 56 functions as numerical data permutation changing means by executing processing according to the count value permutation changing program 554. The CPU 56 executes the count value permutation change program 554 and writes the count value permutation change data “01h” in the count value permutation change register 536, whereby the count value permutation change circuit 523 outputs and inputs to the random value storage circuit 531. The permutation of the count values to be changed is changed.

  The serial communication circuit setting program 556 executes a serial communication circuit setting process for performing an initial setting for serial communication with a microcomputer (in this example, a payout control microcomputer) mounted on each control board in the serial communication circuit 505. It is a program to make it. That is, the CPU 56 functions as serial communication circuit initial setting means by executing processing in accordance with the serial communication circuit setting program 556.

  The interrupt priority setting program 557 is a program for initially setting the priority of interrupt processing executed in response to an interrupt request from the serial communication circuit 505. That is, the CPU 56 functions as priority order initial setting means by executing processing according to the interrupt priority order setting program 556.

  As shown in FIG. 36, the game control microcomputer 560 includes a special figure holding memory 570, a big hit determination table memory 571, a flag memory 572, and a start winning port switch timer memory 573.

  In the special figure holding memory 570, the game ball is won in the variable winning ball apparatus 15 and the execution condition of the variable symbol display is satisfied, but the variable display start condition is not yet satisfied (for example, the special symbol indicator 8 is a memory (storage area) for storing pending data including the number of times the execution condition for variable display is satisfied (8 is still executing variable display). The special figure holding memory 570 includes four entries. Each entry includes a holding number and a random R read from the random number storage circuit 531 according to the winning order in the order in which the game balls win the variable winning ball device 15. A value is stored in association with each other. Each time the variable display of the special symbol on the special symbol display 8 is finished once or the big hit gaming state is finished, the variable display start condition based on the highest level information in the special figure holding memory 570 is set. It is established, and variable display based on the top information of the special figure holding memory 570 is executed. In this case, when the condition for starting the variable display of special symbols is satisfied, the information registered in the second or lower place in the special figure holding memory 570 is moved up by one place. In addition, when a game ball newly wins the variable winning ball apparatus 15 during the variable display of the special symbol, the value of the random R read from the random value storage circuit 531 based on the new winning is the special R value. It is registered in the empty entry in the figure holding memory 570.

  The jackpot determination table memory 571 stores a plurality of jackpot determination tables used by the CPU 56 to determine whether or not the display result of the special symbol display 8 is a jackpot symbol. Specifically, as shown in FIG. 37A, the big hit determination table memory 571 stores a normal time big hit determination table 571a used in a gaming state (referred to as a normal state) other than the probability variation state. Also, the jackpot determination table memory 571 stores a probability change jackpot determination table 571b used in the probability change state, as shown in FIG. Note that, when the big hit determination is performed using the determination table shown in FIG. 37, the probability of determining a big hit depends on the random number maximum value set in the random number maximum value setting register 535. In this case, for example, if the set random number maximum value is too small, the difference in the probability of determining a big hit between the case where the normal big hit determination table 571a is used and the case where the probability variation big hit determination table 571b is used is small. As a result, the player's interest in the game is diminished. Therefore, a plurality of determination tables (a plurality of normal big hit determination tables 571a and a plurality of probability variation big hit determination tables 571b) are stored in the big hit determination table memory 571 in association with the random number circuit 503 and the random number maximum value. Also good. Then, the CPU 56 uses the random number circuit 503 to be used and the determination tables 571a and 571b corresponding to the maximum random number among the determination tables stored in the big hit determination table memory 571, and displays the special symbol according to the display result determination program 552. It may be determined whether or not the display result of the device 8 is a jackpot symbol. By doing so, even if the type of random number circuit 503 to be used and the maximum random number value are different, it is possible to control so that the probability of determining a big hit is somewhat the same.

  In this embodiment, a 16-bit random number circuit 503b is used. That is, it is assumed that it is decided to use the 16-bit random number circuit 503b in the process of step S151. Therefore, a value in a range (range from 0 to 65535) that can be generated in 16 bits can be taken as random R.

  In the flag memory 572, various flags used in the game control process for controlling the progress of the game are set. For example, in the flag memory 572, a probability change flag indicating that the gaming state is a probability change state and a big hit flag indicating that the game state is a big hit state are set.

  The start port switch timer memory 573 stores a timer value that is added or cleared in accordance with the winning detection signal SS input from the start port switch 14a.

  Next, the watchdog timer 60 will be described. FIG. 38 is a block diagram illustrating a configuration example of the watchdog timer. The watchdog timer (WDT) 60 sets the operation enable / disable of the watchdog timer 60 and the operation by setting data in the WDT setting (KWDT; not shown in FIG. 30) 61 of the program management area. When permitted, the clock cycle is set. In this embodiment, in order to operate the watchdog timer 60, the operation permission of the watchdog timer 60 is set. Also, the time-out time of the watchdog timer 60 is a predetermined time (specifically, the time for the CPU 56 to monitor the power-off signal state in a state where the voltage is relatively stable as will be described later: FIGS. 43 to 45 The cycle of the clock selected by the count clock selection circuit 65 is set so that

  The WDT control circuit 63 is a circuit that controls the operation of the watchdog timer 60. The WDT control circuit 63 controls the operation of the watchdog timer 60 when the operation permission is set in the WDT setting 61 of the program management area. Further, the WDT control circuit 63 sets the clock cycle selected by the count clock selection circuit 65 based on the set value of the WDT setting 61 in the program management area. The count clock selection circuit 65 selects a clock signal from the clock circuit according to the setting by the WDT control circuit 63, and outputs the selected clock signal to the 15-bit up counter as a count clock. Thereby, the time-out time (time-up time) in the watchdog timer 60 is set.

  The watchdog timer 60 clears and restarts the watchdog timer 60 by setting predetermined data in a built-in WDT clear register (WCL) 62. Specifically, “$ 55” is written into the WDT clear register 62 by the CPU 56, then “$ AA” is written by the CPU 56, and then “$ 33” is written by the CPU 56. After “$ 33” is written, the WDT control circuit 63 executes clear and restart. That is, the WDT control circuit 63 outputs a clear & restart signal to the 15-bit up counter 66 via the OR circuit 64, and restarts clearing of the count value and restart of count up. When “$ 55” and “$ AA” are written, the WDT control circuit 63 continues the current operation.

  The setting of the WDT clear register 62 by the CPU 56 is executed periodically (every 2 ms) by a WDT clear process (step S36) of a timer interrupt process described later.

  The 15-bit up counter 66 counts the count clock from the count clock selection circuit 65. When the CPU 56 is executing the program normally, the WDT clear register 62 is periodically set, and the count value is cleared and restarted before the 15-bit up counter 66 times out (start counting again). ) Will be executed. On the other hand, when the CPU 56 is not executing the program normally, specifically, when a transition is made to a standby state (infinite loop) (N in step S83 in FIG. 46, after step S481 in FIG. 55), the WDT is cleared. The register 62 is not set, and the count value of the 15-bit up counter 66 reaches a predetermined value (corresponding to the timeout time), resulting in timeout. When timeout occurs, the 15-bit up counter 66 outputs a timeout signal to the output control circuit 67. The output control circuit 67 outputs the timeout signal from the 15-bit up counter 66 to the reset / interrupt controller 502 of the game control microcomputer 560.

  When the watchdog timer 60 generates a time-out signal, the reset / interrupt controller 502 receives the time-out signal, thereby generating a user reset, and an address indicated by the user program vector table (the first address of the main process described later) ), The CPU 56 re-executes the user program. When a user reset is generated by the watchdog timer 60, the CPU 56 outputs a low level signal as a reset signal to the external device. This reset signal is output to the 15-bit up counter 66 via the OR circuit 64 of the watchdog timer 60, and the count value is cleared.

  Next, the configuration of the power supply substrate 910 will be described with reference to the block diagram of FIG. The power supply board 910 is provided with a power switch 914 for executing or shutting off power supply to each electrical component control board and mechanism component in the gaming machine. Note that the power switch 914 may be provided outside the power supply board 910 in the gaming machine. When the power switch 914 is in a closed state (on state), AC power (AC 24 V) is applied to the input side (primary side) of the transformer 911. The transformer 911 is for electrically insulating the AC power supply (AC24V) and the inside of the power supply substrate 910, and its output voltage is also AC24V. A varistor 918 as an overvoltage protection circuit is installed on the input side of the transformer 911.

  The power supply board 910 is installed independently of the electric component control board (the main board 31, the payout control board 37, etc.), and generates a voltage used by each board and mechanism component in the gaming machine. In this example, AC24V, VSL (DC + 30V), VLP (DC + 24V), VDD (DC + 12V) and VCC (DC + 5V) are generated. Further, a capacitor 916 serving as a storage holding means for holding the stored contents in the backup power supply (VBB), that is, the backup RAM, is charged from DC + 5V (VCC), that is, a power supply line for driving an IC or the like on each substrate. Further, a backflow prevention diode 917 is inserted between the +5 V line and the backup +5 V (VBB) line. Note that VSL is generated by rectifying and boosting AC 24 V with a rectifying element in the rectifying and smoothing circuit 915. VSL is a solenoid driving power source. VLP is a lamp lighting voltage, and is generated by rectifying AC24V with a rectifier element in the rectifier circuit 912.

  The DC-DC converter 913 serving as a power supply voltage generation unit has one or a plurality of regulator ICs (two regulator ICs 924A and 924B are shown in FIG. 39), and generates VDD and VCC based on VSL. Relatively large capacitors 923A and 923B are connected to the input sides of the regulator ICs (switching regulators) 924A and 924B. Accordingly, when the power supply to the gaming machine from the outside is stopped, the DC voltages such as VSL, VDD, VCC, etc., decrease relatively slowly.

  As shown in FIG. 39, AC24V output from the transformer 911 is supplied to the connector 922B as it is. The VLP is supplied to the connector 922C. VCC, VDD and VSL are supplied to connectors 922A, 922B and 922C.

  The cable connected to the connector 922A is connected to the main board 31. The cable connected to the connector 922B is connected to the payout control board 37. Therefore, VBB is also supplied to the connectors 922A and 922B. For example, the cable connected to the connector 922C is connected to the sound / lamp control board 80b. Each voltage is supplied to the symbol control board 80a via the sound / lamp control board 80b.

  In addition, a clear switch 921 having a push button structure is mounted on the power supply board 910. When the clear switch 921 is pressed, a low level (ON state) clear signal is output and transmitted to the payout control board 37 via the connector 922B. If the clear switch 921 is not pressed, a high level (off state) signal is output. The clear switch 921 may have a configuration other than the push button structure. Further, the clear switch 921 may be provided other than the power supply board 910 in the gaming machine.

  Further, the power supply board 910 generates a reset signal for the microcomputer mounted on the electric component control board, amplifies the reset signal from the power supply monitor circuit 920 that outputs a power-off signal, and the power supply monitor circuit 920. And an output driver circuit 925 that amplifies the power-off signal and outputs the amplified signal to the connector 922B. The reset signal for the symbol control microcomputer 100a is transmitted to the symbol control board 80a via the sound / lamp control board 80b.

  The power supply monitoring circuit 920 is a circuit that realizes power supply monitoring means for outputting a power-off signal and reset signal generation means for generating a reset signal. As the power supply monitoring circuit 920, a commercially available power failure monitoring reset module IC should be used. Can do. The power supply monitoring circuit 920 outputs a power-off signal when a period during which a predetermined voltage (for example, VSL + 30V) used in the gaming machine becomes equal to or lower than a predetermined value (for example, + 22V) continues for a predetermined time (for example, 56 ms). . Specifically, the power-off signal is turned on (low level). For example, the power supply monitoring circuit 920 sets the reset signal to a low level when VCC becomes +9 V or less.

  In this embodiment, the function of outputting the power-off signal and the function of outputting the reset signal are realized by one power supply monitoring circuit 920, but they may be realized by different circuits. In that case, a watchdog timer built-in IC can be used as a circuit for outputting a reset signal.

  When the power supply to the gaming machine is stopped, the power supply monitoring circuit 920 sets the reset signal to a low level on condition that a predetermined period has elapsed since the power-off signal was output (set to a low level). The predetermined period is a time sufficient for the game control microcomputer 560 mounted on the main board 31 and the payout control microcomputer 370 mounted on the payout control board 37 to execute a power-off process described later. is there. That is, after the power supply monitoring circuit 920 outputs the power-off signal as the voltage drop detection signal, the game control microcomputer 560 and the payout control microcomputer 370 complete the execution of the power-off process, and then the operation stop signal ( Reset signal low level). The power monitoring circuit 920 also serves as first power monitoring means for outputting a voltage drop detection signal and second power monitoring means for outputting an operation stop signal. In addition, when power supply to the gaming machine is started and VSL exceeds +5.0 V, for example, the reset signal is set to a high level. Then, when VSL exceeds +22 V, for example, the power-off signal is not output (set to high level).

  The power-off signal from the power supply monitoring circuit 920, that is, the detection signal from the power supply monitoring means, is input to the payout control microcomputer 370 via the input port 372g on the payout control board 37. That is, the payout control microcomputer 370 can confirm the occurrence of the stop of the power supply to the gaming machine by monitoring the input signal of the input port 372g. In the main board 31, the power-off signal from the power supply monitoring circuit 920 is input to the game control microcomputer 560 via the payout control board 37 and the input port mounted on the main board 31. That is, the gaming control microcomputer 560 can confirm the occurrence of the stop of the power supply to the gaming machine by monitoring the input signal of the input port.

  In this embodiment, the power supply monitoring means monitors the output of the power supply of a predetermined potential, and the voltage from the outside of the gaming machine (this implementation) is used as a detection condition related to the stop of the supply of power supplied to the gaming machine from the outside. In this embodiment, it is used that the predetermined DC voltage created from AC 24 V) is equal to or lower than a predetermined value (the predetermined DC voltage may be equal to or lower than the reference value for a predetermined period). However, the detection condition is not limited thereto. However, other conditions may be used as long as it is possible to detect that power from the outside has been cut off. For example, the AC wave itself may be monitored and the AC wave may be interrupted (the AC wave may not be at a predetermined voltage value for a predetermined period) as a detection condition, or a signal obtained by digitizing the AC wave may be used. Monitoring may be performed to detect that the AC wave has stopped when the digital signal becomes flat (the digitized signal may be flat for a predetermined period).

  FIG. 40 is an explanatory diagram showing an example of output port assignment in the game control means. As shown in FIG. 40, 8-bit data (effect control signal) of the effect control command transmitted to the sound / lamp control board 80 b is output from the output port 1. Note that the logic (for example, 0 is on) opposite to the “logic” shown in FIG. 40 (for example, 0 is on) may be used. “Logic” is determined so that the payout control microcomputer 370 always detects an off state when the signal line to the board 37 is disconnected or when the cable is disconnected (including no cable connection). It is done. Specifically, generally, when disconnection or cable disconnection occurs, a high level is detected on the signal receiving side, so the high level on the signal line between the main board 31 and the payout control board 37 is the game control means. The “logic” is determined to be in the off state at the output port. Therefore, if necessary, an output buffer circuit for logically inverting the signal is provided outside the output port on the main board 31.

  Further, an effect control INT signal (capture signal) for an effect control command transmitted to the sound / lamp control board 80b is also output from the output port 2. The effect control INT signal is a signal for instructing the sound / lamp control means to take in (receive) 8-bit data of the effect control command. In addition, a signal indicating the type of jackpot, a signal indicating the gaming state, and a signal indicating the number of symbols determined are output from the output port 2 to an external device (management device) via an information output circuit (not shown). Further, a connection confirmation signal indicating that the main board 31 is connected is also output from the output port 2.

  Further, solenoids (large winning opening door solenoids) 241 and 242 for opening and closing the opening and closing plates 201 and 202 (first winning prize opening and second winning prize opening) and the variable winning ball apparatus 15 are opened and closed from the output port 3. The drive signal for the solenoid (ordinary electric accessory solenoid) 16 is output. In addition, a control signal for the special prize opening indicator lights 38 and 39 is also output from the output port 3.

  A port for outputting a prize ball command to the payout control board 37 may be assigned to the output port. In this case, since a prize ball command is transmitted by serial communication, a 1-bit port may be allocated.

  FIG. 41 is an explanatory diagram showing an example of bit assignment of input ports in the game control means. As shown in FIG. 41, the detection signals of the count switches 231, 232, the gate switch 32a, the winning port switches 29a, 30a, and the start port switch 14a are input to bits 0 to 5 of the input port 0, respectively. Further, the power-off signal from the payout control board 37 and the detection signal of the clear switch 921 are input to the bits 0 and 1 of the input port 1, respectively. In addition, a random number confirmation signal for confirming whether or not the random number circuit 503 normally updates the random number is input to bit 2 of the input port 1.

  Next, the operation of each CPU and watchdog timer 60 at the start of power supply will be described. FIG. 42 is a timing chart showing the operation of each CPU and watchdog timer at the start of power supply. FIG. 42 shows a case where the predetermined power supply voltage (VSL) normally rises to +30 V after the power supply is turned on.

  As shown in FIG. 42, when the power supply is turned on, the voltage value of VSL increases. When the voltage value becomes +9 V, the power supply monitoring circuit 902 sets the reset signal to a high level. When the input level of the reset terminal to which the reset signal is input becomes high, each CPU (CPU 56, payout control CPU, sound / lamp control CPU 101b, symbol control CPU 101a) becomes operable. When the CPU (main CPU) 56 becomes operable, it executes a security check process that is a process for confirming whether or not the content of the program is valid, and then starts the main process. The other CPUs (sub CPUs) immediately start the main process when they become operable.

  When the voltage value becomes + 22V, the power supply monitoring circuit 902 turns off the power-off signal (high level). At this time, in the example shown in FIG. 42, the CPU 56 is still executing the security check process. When the CPU 56 finishes the security check process, the CPU 56 starts the main process. In the main process, the CPU 56 checks whether the power-off signal is in an off state after performing necessary initial settings. In the example shown in FIG. 42, the power-off signal has already been turned off. When the power-off signal is in the off state, the CPU 56 executes a software delay process for delaying the start of the game control process and confirms whether the random number circuit 503 is normally updating the random number. It is confirmed whether or not a random number confirmation signal is input to. If the random number confirmation signal is input, the CPU 56 executes an initialization process for initializing the storage contents of the RAM 55. Note that if a predetermined restoration condition is satisfied when the power-off process described later is executed when the power supply is stopped and the power supply is resumed after that, the control is performed based on the backup data held in the RAM 55 for a predetermined period. Recovery processing for recovering the state is executed. Thereafter, the CPU 56 starts a game control process based on a timer interrupt described later.

  When starting the main process, the sub CPU (for example, a payout control CPU) executes an initialization process, and thereafter starts a control process (for example, a payout control process) based on a timer interrupt. In this embodiment, the RAM built in the payout control microcomputer is also backed up, and the payout control microcomputer performs power-off processing when power supply is stopped. Therefore, similarly to the game control microcomputer 560, the payout control microcomputer executes the power-off process when the power supply is stopped, and when a predetermined recovery condition is satisfied when the power supply is resumed after that. The recovery process for recovering the control state is executed based on the backup data held in the RAM for a predetermined period. Other sub CPUs (such as a sound / lamp control CPU) are not backed up by the RAM, so that the recovery process is not executed.

  The watchdog timer 60 built in the game control microcomputer 560 starts an operation of counting up (operation for measuring a timeout time) based on the initial setting by the CPU 56 in the built-in register. Thereafter, when the game control process is started, the CPU 56 periodically sets data in the WDT clear register of the watchdog timer 60 via the internal bus in the game control process, whereby the count value of the watchdog timer 60 is set. Is executed to restart (count restart). Thereby, the watchdog timer 60 is not timed out and reset during execution of the game control process. In order to prevent the watchdog timer 60 from timing out while the CPU 56 is executing the software delay processing, the CPU 56 periodically sends data to the WDT clear register of the watchdog timer 60 even during execution of the software delay processing. The count value of the watchdog timer 60 is cleared and restarted.

  As shown in FIG. 42, since the CPU 56 executes the software delay process before starting the game control process, the execution of the game control process is started by the control process (for example, payout control process or Sound / lamp control processing etc.) can be delayed. As a result, when the CPU 56 transmits a command to the sub CPU based on the game control process, it is possible to avoid missing the command because the control process in the sub CPU is not started.

  FIG. 43 is also a timing chart showing the operation of each CPU and watchdog timer at the start of power supply, as in FIG. However, FIG. 43 shows a case where the predetermined power supply voltage (VSL) does not normally rise to +30 V after the power supply is turned on, that is, a case where the rise of the power supply voltage is slow.

  As shown in FIG. 43, when the power supply is turned on, the voltage value of VSL increases. When the voltage value becomes +9 V, the power supply monitoring circuit 902 sets the reset signal to a high level. When the input level of the reset terminal to which the reset signal is input becomes high, each CPU (CPU 56, payout control CPU, sound / lamp control CPU 101b, symbol control CPU 101a) becomes operable. Then, after executing the security check process, the CPU (main CPU) 56 starts the main process, and the other CPUs (sub CPUs) immediately start the main process.

  When the CPU 56 finishes the security check process, the CPU 56 starts the main process. In the main process, the CPU 56 checks whether the power-off signal is in an off state after performing necessary initial settings. At this time, in the example shown in FIG. 43, since the rise of the power supply voltage is slow and the voltage value has not reached + 22V, the power-off signal is not yet in the off state (it remains in the on state). When the power-off signal is in the on state, the CPU 56 shifts the control state to the standby state (infinite loop). On the other hand, when starting the main process, the sub CPU (for example, a payout control CPU) executes an initialization process, and then starts a control process (for example, a payout control process) based on a timer interrupt.

  As shown in FIG. 43, when the voltage value subsequently becomes + 22V, the power supply monitoring circuit 902 turns off the power-off signal (high level). At this time, the CPU 56 is controlled in a standby state.

  The watchdog timer 60 built in the game control microcomputer 560 starts counting up based on the initial setting by the CPU 56 in the built-in register. When the CPU 56 is in a standby state, the process of clearing and restarting the count value of the watchdog timer 60 is not executed. Accordingly, the count value of the watchdog timer 60 reaches a predetermined value and times out. When time-out occurs, the watchdog timer 60 outputs a time-out signal to the reset / interrupt controller 502 of the game control microcomputer 560.

  When the watchdog timer 60 generates a time-out signal, the reset / interrupt controller 502 generates a user reset, and causes the CPU 56 to re-execute the program from the address (first address of the main process) indicated by the user program vector table. When a user reset is generated by the watchdog timer 60, the CPU 56 outputs a low level signal as a reset signal to the external device. This reset signal is output to the 15-bit up counter 66 via the OR circuit 64 of the watchdog timer 60, and the count value of the watchdog timer 60 is cleared.

  When the main process is resumed by the user reset, the CPU 56 performs necessary initial settings and then checks again whether or not the power-off signal is in the off state. At this time, in the example shown in FIG. 43, the power-off signal is in an off state (high level). Therefore, as described above, the CPU 56 executes a software delay process, executes a random number check process, executes an initialization process, and then executes a game control process based on a timer interrupt. When the game control process is started, the CPU 56 clears the count value of the watchdog timer 60 by periodically setting data in the WDT clear register of the watchdog timer 60 via the internal bus in the game control process. Then, restart the process. Further, the count value of the watchdog timer 60 is cleared and restarted even during execution of the software delay processing so that the watchdog timer 60 does not time out while the CPU 56 executes the software delay processing. Execute.

  As shown in FIG. 43, the power-off signal is confirmed, and when the power-off signal is not turned off, the power-off signal is confirmed again after a predetermined time (time-out time of the watchdog timer 60). As a result, the state of the power-off signal can be monitored while the voltage is relatively stable. In the configuration shown in FIG. 43, monitoring of the power-off signal after a predetermined period is not executed by processing by software, so it is not necessary to create a program for that purpose, and the program capacity does not increase. Absent. Further, in the configuration shown in FIG. 43, a watchdog timer 60 built in the game control microcomputer 560 (this watchdog timer 60 is also used for detecting a momentary power interruption during power supply, which will be described later). Therefore, the hardware circuit is not specially provided, and the cost for providing the special circuit is not increased.

  FIG. 44 is a timing chart showing the operation of each CPU and watchdog timer when power supply is stopped. As shown in FIG. 44, when the voltage value of VSL gradually decreases from + 30V and the voltage value becomes + 22V, the power supply monitoring circuit 902 turns the power-off signal on (low level). When the power-off signal is turned on, the CPU 56 executes a power-off process for storing data necessary for restoring the control state in the power-backed RAM 55, and sets the control state to the standby state (infinite loop). ). Thereafter, when the voltage value decreases to +9 V, the power supply monitoring circuit 902 sets the reset signal to a low level. When the input level of the reset terminal to which the reset signal is input becomes a low level, each CPU (CPU 56, CPU for payout control, CPU 101b for sound / lamp control, CPU 101a for symbol control) is stopped.

  The watchdog timer 60 counts up even when the power-off process is being executed, but stops its operation when the voltage value drops to an operable voltage value of the watchdog timer 60 (for example, +5 V). At this time, the watchdog timer 60 has not timed out.

  After that, when the power supply is resumed, if a predetermined restoration condition is satisfied, the CPU 56 executes a restoration process based on the stored contents of the RAM 55. In this embodiment, the payout control CPU also executes the power-off process based on the fact that the power-off signal is turned off.

  FIG. 45 is a timing chart showing the operation of each CPU and watchdog timer during instantaneous power supply interruption. As shown in FIG. 45, when the voltage value of VSL gradually decreases from + 30V and the voltage value becomes + 22V, the power supply monitoring circuit 902 turns the power-off signal on (low level). When the power-off signal is turned on, the CPU 56 executes the power-off process and then shifts the control state to the standby state (infinite loop). After that, the voltage value gradually decreases, but in the example shown in FIG. 45, the voltage value increases before the voltage value reaches +9 V, and returns to +30 V again. At this time, the control state of the CPU 56 is maintained in a standby state.

  On the other hand, the watchdog timer 60 starts counting when the power-off process is started (more precisely, when the clear and restart processes in the game control process are not executed). The count is performed even after the control state is shifted to the standby state. When the count value reaches a predetermined value and times out, the watchdog timer 60 outputs a time-out signal to the reset / interrupt controller 502 of the game control microcomputer 560.

  When the watchdog timer 60 generates a time-out signal, the reset / interrupt controller 502 generates a user reset, and causes the CPU 56 to re-execute the program from the address (first address of the main process) indicated by the user program vector table.

  When the main process is started by the user reset, the CPU 56 performs necessary initial settings and then checks whether or not the power-off signal is in an off state. At this time, in the example shown in FIG. 45, the power-off signal is in an off state (high level). Accordingly, the CPU 56 executes a software delay process, executes a random number check process, executes a recovery process, and then executes a game control process based on a timer interrupt. When the game control process is started, the CPU 56 executes a process for clearing and restarting the count value of the watchdog timer 60 in the game control process. Even during execution of the software delay process, a process for clearing and restarting the count value of the watchdog timer 60 is executed.

  As shown in FIG. 45, the watchdog timer 60 performs a user reset after a predetermined period even if the control state is shifted to a standby state based on the occurrence of an instantaneous power supply interruption or the like. Therefore, the control state can be easily returned from the standby state.

  Next, the operation of the game control microcomputer 560 will be described. 46 and 47 show main processing executed by the CPU 56 of the game control microcomputer 560 in response to the start of power supply to the game machine and the reset signal to the game control microcomputer 560 becoming high level. It is a flowchart which shows. When the input level of the reset terminal to which the reset signal is input becomes a high level, the CPU 56 of the game control microcomputer 560 executes a security check process that is a process for confirming whether the contents of the program are valid. The main processing after step S1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode of the maskable interrupt is set to interrupt mode 2 (step S2), and a stack pointer designation address is set to the stack pointer (step S3). In step S2, the address synthesized from the value (1 byte) of the specific register (I register) of the game control microcomputer 560 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is Set to the mode indicating the interrupt address. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Next, the built-in device register is set (initialized) (step S4). By the processing in step S4, the CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits) are set (initialized). The internal register (WDT setting 61) of the watchdog timer 60 is also set.

  The game control microcomputer 560 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC) 504.

  Next, the CPU 56 executes a software delay process for delaying the start timing of the game device control process (game control process) for controlling the progress of the game by software. Specifically, first, the initialization wait number specification value 1 is set in the wait counter 1 (step S81). Next, a process of setting and clearing and restarting data in the WDT clear register 62 of the watchdog timer 60 is executed (step S82). And the power-off signal confirmation process which confirms whether the power-off signal is an OFF state by the state of the bit 0 of the input port 1 is performed (step S83). When the power supply to the gaming machine is started, the output voltage of various power sources such as the + 30V power source gradually reaches a specified value. However, the processing of step S83, that is, the power-off signal is in an off state (high By confirming that the power supply voltage is stable, the CPU 56 can confirm that the power supply voltage is stable. Since there is a possibility of erroneous detection due to the influence of noise or the like, the confirmation of the power-off signal is continuously executed a predetermined number of times (for example, 5 times).

  When the power-off signal is in the on state (low level) (N in Step S83), the CPU 56 shifts the control state to the standby state by repeatedly executing the infinite loop process. When the power-off signal is in the off state (high level) (Y in step S83), the CPU 56 sets the initialization wait number specification value 2 in the wait counter 2 (step S84). Note that general-purpose registers built in the game control microcomputer 560 are used as the wait counters 1 and 2. Then, the value of the wait counter 2 is decremented by 1 until the value of the wait counter 2 becomes 0 (steps S85 and S86). When the value of the weight counter 2 becomes 0, the value of the weight counter 1 is decremented by 1 (step S87). When the value of the weight counter 1 is not 0 (step S88), the process returns to step S82. If the value of the wait counter 1 is 0, the software delay process is terminated.

  By the software delay processing as described above, the software delay processing is not executed substantially by [(initialization wait number specification value 1) × (initialization wait number specification value 2) × (processing time of steps S83, S84)]. Compared to the case, the start timing of the game control process can be delayed. In other words, the initialization weight count designation values 1 and 2 are determined so that the start timing of the game control process can be delayed by a desired time. Note that the values of the initialization wait times designation values 1 and 2 are set in the ROM 54. The software delay processing described here is an example, and the software delay processing may be realized by other methods. The game control microcomputer 560 may include means for inputting the values of the weight counter 1 and the weight counter 2 set in steps S81 and S84. The wait counter 1 and the wait counter 2 are parameters that determine the length of the delay time. Therefore, if a means for inputting the values of the weight counter 1 and the weight counter 2 is provided, the versatility regarding the setting of the delay time can be improved.

  When the software delay processing is finished, the CPU 56 sets (initializes) (step S5) the CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits), and then stores the RAM 55 in the RAM 55. An accessible state is set (step S6).

  Next, the CPU 56 checks whether or not the clear switch is turned on (step S7). Note that the CPU 56 may confirm the state of the clear signal only once through the input port 1, but may confirm the state of the clear signal a plurality of times. For example, if it is confirmed that the state of the clear signal is an off state, after a delay time of a predetermined time (for example, 0.1 seconds), the state of the clear signal is reconfirmed. If it is confirmed that the clear signal is in the on state at that time, it is determined that the clear signal is in the on state. Further, at this time, if it is confirmed that the state of the clear signal is the off state, after a delay time of a predetermined time, the state of the clear signal may be confirmed again. Here, the number of reconfirmations is not limited to once or twice, but may be three or more times. It is also possible to check twice and check again when the check results do not match.

  If the clear switch is not turned on in step S7, the data protection processing of the backup RAM area (for example, power supply stop processing (power-off processing) such as addition of parity data) is performed when power supply to the gaming machine is stopped. It is confirmed whether it has been performed (step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. When it is confirmed that such power supply stop processing has been performed, the CPU 56 determines that the power supply stop processing has been performed, that is, the control state at the time of power supply stop is stored. . When it is confirmed that the power supply stop process is not performed, the CPU 56 executes an initialization process.

  Whether or not the power supply stop process has been performed is determined by the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process corresponding to the execution of the power supply stop process (for example, 2). ) Is confirmed by whether or not. Note that such a confirmation method is an example. For example, a flag indicating that the power supply stop process has been executed is set in the backup flag area in the power supply stop process, and the flag is set in step S8. If it is confirmed that the power supply is stopped, it may be determined that the power supply stop process has been performed.

  If it is determined that the control state at the time of stopping power supply is stored, the CPU 56 performs data check (parity check in this example) in the backup RAM area (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above process is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area may be different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the initialization process (the process of steps S10 to S14) executed at the time of power-on that is not the time of recovery from the stop of the power supply is performed. Execute.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control means and the control state of the electrical component control means such as the effect control means to the state when the power supply is stopped. Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S91), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S92). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S91 and S92, the saved contents of the work area that should not be initialized remain. The parts that should not be initialized include, for example, data indicating the gaming state before the power supply is stopped (special symbol process flag, etc.), the area where the output state of the output port is saved (output port buffer), unpaid prize balls This is the part where data indicating the number is set.

  Further, the CPU 56 sets the head address of the backup command transmission table stored in the ROM 54 as a pointer (step S93), and proceeds to step S15. In step S93, a command (restoration command) for restoring the control state of the microcomputer (sound / lamp control microcomputer 100b, symbol control microcomputer 100a) on another control board is transmitted. As a recovery command, a normal display command (E401 (H)), a special display command (E402 (H)), and a high-probability latent display command (E403 (H) that specify execution of a game effect according to the gaming state when power supply is stopped. )) Is provided (see FIG. 62). The CPU 56 checks flags (probability change flag, time reduction flag, and high probability latent state flag, which will be described later) according to the gaming state, and issues a recovery command for specifying execution of the game effect according to the gaming state when the power supply is stopped. It transmits to the microcomputer of the control board. The microcomputer of the other control board executes a game effect according to the game state using various effect devices (electrical parts) based on the reception of such a recovery command. In this embodiment, the recovery command is transmitted from the sound / lamp control microcomputer 100b to the symbol control microcomputer 100a after being transmitted to the sound / lamp control microcomputer 100b. At this time, the sound / lamp control microcomputer 100b may transmit the recovery command from the game control microcomputer 560 as it is to the symbol control microcomputer 100a, or may receive the recovery command from the game control microcomputer 560. After processing, it may be transmitted to the symbol controlling microcomputer 100a.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). Note that the predetermined data may be left as it is without initializing the entire area of the RAM 55. Also, the initial address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12).

  Control states such as a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol buffer, a total prize ball number storage buffer, a special symbol process flag, an award ball flag, an out-of-ball flag, etc. An initial value is set in a flag for selectively performing processing according to the above. In addition, a bit corresponding to the output port that outputs the connection confirmation signal in the output port buffer is set (corresponding to the ON state of the connection confirmation signal).

  Further, the CPU 56 sets the start address of the initialization command transmission table stored in the ROM 54 as a pointer (step S13), and transmits an initialization command for initializing the sub board according to the contents to the sub board. Processing is executed (step S14). As an initialization command, a command indicating an initial symbol displayed on the variable display device 9, an initialization command to the payout control board 37, or the like can be used.

  Further, the CPU 56 executes a random number circuit setting process for initially setting the random number circuits 503a and 503b (step S15a). In this case, the CPU 56 performs settings in accordance with the random number circuit setting program 551 to make the random number circuits 503a and 503b update the random R value.

  Further, the CPU 56 executes serial communication circuit setting processing for initial setting of the serial communication circuit 505 (step S15b). In this case, the CPU 56 performs processing according to the serial communication circuit setting program 556, thereby setting the serial communication circuit 505 to perform serial communication with the payout control microcomputer.

  When the serial communication circuit 505 is initialized, the CPU 56 initializes the priority of interrupt processing to be executed in response to the interrupt request from the serial communication circuit 505 (step S15c). In this case, the CPU 56 initializes the priority of interrupt processing by executing processing according to the interrupt priority setting program 557.

  For example, the CPU 56 initializes the priority of each interrupt process according to a predetermined interrupt process priority table including the default priority of each interrupt process. FIG. 48 is an explanatory diagram of an example of an interrupt processing priority table. In this embodiment, the CPU 56 is initially configured to preferentially execute an interrupt process whose cause is a communication error in the serial communication circuit 505 in accordance with the interrupt process priority table shown in FIG. Set. In this case, for example, the CPU 56 sets an interrupt priority execution flag at the time of communication error indicating that priority is given to an interrupt process whose cause is an interrupt.

  In this embodiment, when a timer interrupt and an interrupt request from the serial communication circuit 505 are generated at the same time, the CPU 56 preferentially performs an interrupt process by the timer interrupt.

  In addition, the default priority of each interrupt process can be changed by the user. For example, the game control microcomputer 560 stores specification information for specifying an interrupt process set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 sets the priority of interrupt processing according to the designation information stored in a predetermined storage area of the ROM 54.

  The processing in steps S15a to 15c may be executed in the processing for setting the built-in device register in step S4.

  The execution order of the serial communication circuit setting process (step S15b) and the interrupt priority setting process (step S15c) described above may be switched. That is, the serial communication circuit setting process (step S15b) may be performed after setting the interrupt priority order. In such a configuration, priorities of interrupts are determined before setting the serial communication circuit 505 and setting a timer interrupt.

  Next, a random number confirmation process for confirming whether or not a random number confirmation signal is input according to the state of bit 2 of the input port 1 is executed (step S89). In this embodiment, the random number confirmation signal is a clock signal output from the clock signal output circuit 537. If the clock signal is not output from the clock signal output circuit 537, the random number circuit 503 cannot update the random number, so that it can be determined that an abnormality has occurred in the random number circuit 503. As another process for confirming whether or not the random number circuit 503 is operating normally, a clock signal output from the clock signal output circuit 537 is sent to a watchdog timer (a watchdog timer different from that for returning from the standby state). The watchdog timer starts counting when the clock signal from the clock signal output circuit 537 is no longer input, and outputs a signal indicating abnormality of the random number circuit 503 to the CPU 56 when time-out occurs. Good. Alternatively, a random number may be extracted from the random number circuit 503 a plurality of times, and it may be determined whether or not the extracted random values are the same value. According to such processing, if the random number value is the same value, it can be determined that the random number circuit 503 has not updated the random number.

  If the CPU 56 determines that the random number confirmation signal has not been input (N in step S89), it executes a process for notifying the abnormality of the random number circuit 503 (step S90). For example, a lamp (not shown) for notifying the abnormality of the random number circuit 503 is turned on. Further, an effect control command for notifying the abnormality of the random number circuit 503 is transmitted to the sound / lamp control board 80b, and an error sound for notifying the abnormality of the random number circuit 503 is output as a sound, or the abnormality of the random number circuit 503 is notified. The lamp is turned on with a predetermined lighting pattern. Further, a command for notifying the abnormality of the random number circuit 503 is transmitted to the symbol control board 80a via the sound / lamp control board 80b, and the variable display device 9 executes screen display for notifying the abnormality of the random number circuit 503. Or

  Then, the CPU 56 executes a timer interrupt setting process for setting a CTC register built in the game control microcomputer 560 so that a timer interrupt is periodically taken every predetermined time (for example, 2 ms) ( Step S16). That is, a value corresponding to, for example, 2 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 2 ms.

  When the setting of the timer interrupt is completed, the CPU 56 executes a power-off process (power-off detection process) for detecting whether or not a power-off signal has been output (whether or not it has been turned on) (step S18). The power-off process may be executed in a timer interrupt process (game control process) executed every 2 ms. Further, the CPU 56 repeatedly executes the display random number update process (step S19a) and the initial value random number update process (step S19b). When the power-off process, the display random number update process, and the initial value random number update process are executed, the CPU 56 disables the interrupt (step S17), and the display random number update process and the initial value random number update process are executed. When completed, the interrupt is permitted (step S20).

  When the interrupt enabled state is set in step S20, the timer interrupt or the interrupt request from the serial communication circuit 505 is permitted until the processing in step S18 is executed and the interrupt disabled state is set next time. . If a timer interrupt occurs while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 executes a timer interrupt process to be described later. In addition, when an interrupt request is generated from the serial communication circuit 505 while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 causes each interrupt process (communication error interrupt process and reception) to be described later. Execute time interruption processing and transmission completion interruption processing). In the present embodiment, priority is given to interrupt processing before the timer interrupt or interrupt request is set to be permitted by executing step S15b before the loop processing from step S17 to step S20. Processing for setting or changing the order is performed.

  The display random number is a random number for determining the display of the special symbol display 8. In this embodiment, as a display random number, a random number for determining a variation pattern for determining a variation pattern of a special symbol, or a random number for determining a reach for determining whether or not to reach when a big hit is not generated, is used. Used. The display random number update process is a process for updating the count value of the counter for generating the display random number.

  The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. A random number for initial value is a random number for determining the type of jackpot (for example, a jackpot symbol determining random number for determining a special symbol for generating a jackpot, or a jackpot type determining for determining the type of jackpot In order to determine an initial value of a count value such as a counter (determination random number generation counter) for generating a random number for use, a random number for determination per normal design for determining whether or not to generate a hit based on a normal design It is a random number. A game control process described later (a process in which a game control microcomputer controls itself a game device such as a variable display device 9, a variable winning ball device 15, a ball payout device 97 provided in the game machine, or When the count value of the determination random number generation counter makes one round in a process of transmitting a command signal to cause another microcomputer to control, or a gaming apparatus control process), an initial value is set in the counter.

  Note that when the display random number update process and the initial value random number update process are executed, the interrupt disabled state is set even when the display random number update process and the initial value random number update process are performed by the timer interrupt process described later. This is because it is executed (that is, the same process is also executed in steps S24 and S25 of the timer interrupt process), so that it does not conflict with the process in the timer interrupt process. That is, if a timer interrupt is generated during the processing of steps S19a and S19b and the count value of the counter for generating the display random number and the initial value random number is updated during the timer interrupt processing, The continuity of values may be impaired. However, such an inconvenience does not occur if the interrupt is prohibited during the processing of steps S19a and S19b.

  As described above, a game clerk or the like can easily perform initial initialization by starting the power supply to the gaming machine (for example, turning on the power switch 914) while the clear switch 921 is turned on and the clear signal is output. Can be executed. That is, RAM clear or the like can be performed.

  Next, the random number circuit setting process (step S15a) in the main process will be described. FIG. 49 is a flowchart showing random number circuit setting processing. In the random number circuit setting process, the CPU 56 first executes the process according to the random number circuit selection module 551f included in the random number circuit setting program 551, and from among the random number circuits 503a and 503b built in the game control microcomputer 560, the game A random number circuit to be used when executing the timer interrupt process including the control process is set (step S151). For example, the game control microcomputer 560 stores, in a predetermined storage area of the ROM 54, designation information for designating the random number circuit 503 used when executing a timer interrupt process set by a user (for example, a game machine manufacturer). I remember it. Then, the CPU 56 selects either the 12-bit random number circuit 503a or the 16-bit random number circuit 503b according to the designation information stored in the predetermined storage area of the ROM 54, and uses the selected random number circuit when executing the timer interrupt process. Set as a random number circuit. Note that both the 12-bit random number circuit 503a and the 16-bit random number circuit 503b may be set as random number circuits used when the timer interrupt process is executed.

  As described above, in step S151, whether or not each of a plurality of random number circuits (12-bit random number circuit 503a and 16-bit random number circuit 503b) having different predetermined ranges of numerical data that can be updated can be used is set. Therefore, it is possible to prevent unnecessary random numbers from being processed during the execution of the timer interrupt process, and the control burden on the game control microcomputer 560 can be reduced. For example, when the game control microcomputer 560 performs the game control process using only the random number generated by one of the two random number circuits 503a and 503b, the random number in the random circuit that is not used for the game control process is updated. Thus, the control load of the game control microcomputer 560 can be reduced.

  When the CPU 56 sets the random number circuit 503 to be used in step S151, the CPU 56 stops the operation of the counter 521 and the clock signal output circuit 524, for example, by not writing data to the random number circuit activation register 541 so that the random number circuit 503 is not used. The counter 521 of the set random number circuit is prevented from updating the count value C. Further, for example, the counter 521 of the random number circuit that is set not to use updates the count value C, but the CPU 56 does not output the output control signal SC so that the random number cannot be read from the random value storage circuit 531. You may control to. Further, for example, the CPU 56 prevents the random number value fetching data “01h” from being written in the random number fetching register 539 of the random number circuit that is set not to be used for the timer circuit 534, and the latch signal generation circuit 533 Control may be performed so that the latch signal SL is not output to the random value storage circuit 531.

  As described above, by setting the random number circuit 503 to be used, by setting only the random number circuit 503 to be used, the range of the random number value to be generated can be appropriately set. Further, it is possible to prevent unnecessary random numbers from being processed during the execution of the timer interrupt process, and the control burden on the game control microcomputer 560 can be reduced. For example, when the big hit determination is performed using a determination table including a distant value (for example, “1” and “100”) as the big hit determination value, the big hit is determined with a predetermined big hit probability (for example, 1/100). In this case, the number of types of determination values to be processed is smaller when the random number by the 12-bit random number circuit 503a is used than when the random number by the 16-bit random number circuit 503b is used, and the game control microcomputer 560 is used. The control burden is reduced.

  Further, the CPU 56 executes processing in accordance with the random number maximum value setting module 551a included in the random number circuit setting program 551, and generates random number maximum value setting data for designating a random number maximum value preset by the user as a random number maximum value setting register 535. (Step S152). By doing so, the random number maximum value of random R preset by the user is set in the random number circuit 503. When the 12-bit random number circuit 503a is set as the random number circuit used when the timer interrupt is executed, the CPU 56 sets the random number maximum value that specifies the random number maximum value (any value from “0” to “4095”). Data is written into the random number maximum value setting register 535 of the 12-bit random number circuit 503a. When the 16-bit random number circuit 503b is set as the random number circuit used when the timer interrupt is executed, the CPU 56 sets the random number maximum value that specifies the maximum random number value (any value from “0” to “65535”). Data is written into the random number maximum value setting register 535 of the 16-bit random number circuit 503b.

  In this embodiment, when “0” to “255” are set as the random number maximum value, the random number maximum value is reset to a predetermined value in the random number maximum value resetting process described later. Even when control is performed to write a value greater than “256” as the random number maximum value, values “0” to “255” are set in the random number maximum value setting register 535 due to data corruption or the like. In the case where it is lost, the random number maximum value is reset to a predetermined value in the random number maximum value resetting process described later.

  As described above, since the maximum value of the random number to be generated is set in advance in the random number maximum value setting register 535 in step S152, a random number having a value larger than the range of random numbers used during execution of the timer interrupt process is generated. Can be prevented, and the processing load of the random number circuit 503 and the game control microcomputer 560 can be reduced.

  Further, the CPU 56 checks whether or not the random number maximum value set in the random number maximum value setting register 535 in step S152 is not less than a predetermined lower limit value. A random number maximum value resetting process for resetting the random number maximum value set in 535 is executed (step S153).

  Further, the CPU 56 executes a process according to the initial value change module 551e included in the random number circuit setting program 551, and executes an initial value change process for changing the initial value of the count value updated by the counter 521 of the random number circuit 503 (step). S154).

  Further, the CPU 56 executes processing in accordance with the random number update method selection module 551b included in the random number circuit setting program 551, and writes the random number update method selection data in the random number update method selection register 540 (step S155). By doing so, the random number update method of the random number circuit 503 is set. In this embodiment, the CPU 56 writes the random number update method selection data “10h” in the random number update method selection register 540. That is, in this embodiment, the second random number update method is set as the random number update method of the random number circuit 503.

  Further, the CPU 56 executes processing according to the cycle setting module 551c included in the random number circuit setting program 551, and sets the cycle setting data (the reference clock signal by how many minutes) that specifies the cycle of the random number generation clock signal SI1 preset by the user. The data for setting whether to circulate) is written in the period setting register 537 (step S156). By doing so, the cycle of the random number generating clock signal SI1 preset by the user is set in the random number circuit 503.

  Further, the CPU 56 sets whether or not to update the initial value input to the counter 521 when the count value is updated to a predetermined final value by the counter 521 of the random number circuit 503 (step S157). For example, the game control microcomputer 560 sets in advance a setting value indicating whether or not to update the initial value input to the counter 521 when the count value is updated to a predetermined final value by the counter 521. And stored in a predetermined area of the ROM 54. Whether or not the CPU 56 updates the initial value input to the counter 521 when the counter 521 updates the count value to a predetermined final value in accordance with a predetermined set value stored in a predetermined storage area of the ROM 54. Set In this embodiment, when the CPU 56 determines to update the initial value input to the counter 521 in step S157, the count value is updated to a predetermined final value (when a notification signal is input from the counter 521). An initial value update flag indicating that the initial value is updated is set. In this embodiment, a case will be described in which an initial value update flag is set according to a predetermined set value in step S157. Then, the CPU 56 updates the initial value of the count value output from the counter 521 based on the initial value update flag being set in the random number circuit initial value update process described later.

  Instead of changing the initial value of the count value by the CPU 56, the initial value of the count value may be changed to a predetermined value on the random number circuit 503 side based on the update of the count value to the final value. For example, the random number circuit 503 includes an initial value update data register that stores initial value update data indicating that the initial value is updated, and an initial value change circuit that changes the initial value. Value update data is set in the initial value update data register. In this case, when the counter 521 updates the count value to the final value, it outputs a notification signal to the initial value change circuit. Then, the initial value change circuit checks whether or not initial value update data is set in the initial value update data register. Then, when the initial value change circuit confirms that the initial value update data is set, the initial value change circuit changes the initial value of the count value to a predetermined value. Note that the initial value changing circuit may change the initial value of the count value whose permutation has been changed in the count value permutation changing process described later.

  Further, the CPU 56 sets whether or not to change the permutation of the count values updated by the counter 521 when the count value is updated to a predetermined final value by the counter 521 of the random number circuit 503 (step S158). For example, the game control microcomputer 560 sets in advance a set value indicating whether or not to change the permutation of the count values output by the counter 521 when the counter 521 updates the count value to a predetermined final value. Is stored in a predetermined area of the ROM 54. Then, the CPU 56 changes the permutation of count values output by the counter 521 when the count value is updated by the counter 521 to a predetermined final value according to a predetermined set value stored in a predetermined storage area of the ROM 54. Set whether or not. In this embodiment, if the CPU 56 determines in step S158 that the permutation of the count values output from the counter 521 is to be changed, the CPU 56 changes the permutation of the count values when the count values are updated to a predetermined final value. The indicated count value permutation change flag is set. In this embodiment, the case where the count value permutation change flag is set in step S158 according to a predetermined set value will be described. Then, the CPU 56 changes the permutation of the count values output by the counter 521 based on the fact that the count value permutation change flag is set in the count value permutation changing process described later.

  Instead of changing the permutation of the count values under the control of the CPU 56, the permutation of the count values may be changed on the random number circuit 503 side based on the update of the count values up to the final value. For example, the random number circuit 503 includes a permutation change data register that stores permutation change data indicating that the permutation of count values is to be changed. In step S158, the CPU 56 sets the permutation change data in the permutation change data register. In this case, when the counter 521 updates the count value to the final value, the notification signal is output to the count value permutation change circuit 523, and the count value permutation change circuit 523 that has received the notification signal receives the permutation change data in the permutation change data register. Check whether it is set. When the count value permutation changing circuit 523 confirms that the permutation change data is set, it changes the permutation of the count values.

  Then, the CPU 56 executes processing according to the random number circuit activation module 551d included in the random number circuit setting program 551, and writes the random number circuit activation data “80h” in the random number circuit activation register 541 (step S159). By doing so, the CPU 56 activates the random number circuit 503.

  Next, the random number maximum value resetting process (step S153) in the random number circuit setting process will be described. FIG. 50 is a flowchart showing the random number maximum value resetting process. In the random number maximum value resetting process, the CPU 56 reads the random number maximum value set in the random number maximum value setting register 535 (step S153a). When the 12-bit random number circuit 503a is set as the random number circuit used when the timer interrupt process is executed, the CPU 56 reads the random number maximum value set in the random number maximum value setting register 535 of the 12-bit random number circuit 503a. When the 16-bit random number circuit 503b is set as the random number circuit used when the timer interrupt process is executed, the CPU 56 reads the random number maximum value set in the random number maximum value setting register 535 of the 16-bit random number circuit 503b.

  The CPU 56 determines whether or not the read random number maximum value is equal to or less than a predetermined lower limit value (step S153b). When the 12-bit random number circuit 503a is set, the maximum random number value that can be set in the 12-bit random number circuit 503a is from “256” to “4095”. It is determined whether or not the maximum random number read from is lower limit value “256” or less. When the 16-bit random number circuit 503b is set, the maximum random number that can be set in the 16-bit random number circuit 503b is “512” to “65535”. It is determined whether or not the maximum random number read from the register 535 is equal to or lower than the lower limit “512”.

  When the read random number maximum value is less than or equal to the lower limit value, the CPU 56 resets the random number maximum value set in the random number maximum value setting register 535 to a predetermined value (step S153c). When the 12-bit random number circuit 503a is set, if the random number maximum value read from the random number maximum value setting register 535 of the 12-bit random number circuit 503a is determined to be less than or equal to the lower limit “256”, the CPU 56 determines the random number maximum value setting register 535. The random number maximum value set in is reset to a predetermined value “4095”. When the 16-bit random number circuit 503b is set, if the random number maximum value read from the random number maximum value setting register 535 of the 16-bit random number circuit 503b is determined to be less than or equal to the lower limit “512”, the CPU 56 sets the random number maximum value. The random number maximum value set in the register 535 is reset to a predetermined value “65535”.

  As described above, when the random number maximum value set in the random number maximum value setting register 535 is equal to or smaller than the predetermined lower limit value, the random number maximum value is reset to a predetermined value. Therefore, it is possible to prevent an excessively small value from being set as the maximum value of the random number due to a malfunction of the game control microcomputer 560 or an action such as generating a capture signal using a radio signal for the game machine. be able to. Therefore, it is possible to prevent a situation in which a random number having an excessively small value range from the minimum value to the maximum value is generated.

  Next, the initial value changing process (step S154) in the random number circuit setting process will be described. FIG. 51 is a flowchart showing the initial value changing process. In the initial value changing process, the CPU 56 first reads the initial value changing method setting data stored in the area 1F97h in the user program execution data area, and specifies the initial value changing method selected by the user. In this case, the CPU 56 determines whether or not the value of the read initial value changing method setting data is “01h” (step S154a), thereby specifying the initial value changing method selected by the user.

  When the value of the initial value change method setting data is “01h”, the CPU 56 sets the initial value input to the counter 521 of the random number circuit 503 to a value set based on the ID number unique to the game control microcomputer 560. Change (step S154b). For example, the game control microcomputer 560 associates, in a predetermined storage area of the ROM 54, the ID number of the game control microcomputer 560 with a calculated value obtained by performing a predetermined calculation based on the ID number. I remember it. In step S154b, the CPU 56 changes the initial value of the count value to the calculated value based on the ID number stored in advance. Further, for example, in step S154b, the CPU 56 calculates the ID number of the game control microcomputer 560 and a predetermined value (for example, the ID number (for example, “100”) to a predetermined value (for example, “100”). The initial value of the count value is set to the calculated value (for example, “200”). When the initial value input to the counter 521 is changed, the CPU 56 sets an initial value change flag indicating that the initial value of the count value has been changed (step S154c).

  When the CPU 56 changes the initial value input to the counter 521 in step S154b, the CPU 56 checks the value of the random number maximum value setting register 535 of the comparator 522 of the random number circuit 503, and the value set based on the ID number is determined. It is determined whether or not it is greater than the maximum random number. If it is determined that the value set based on the ID number is equal to or greater than the maximum random number, the CPU 56 does not change the initial value input to the counter 521 (for example, resets the initial value to “0”). By doing so, it is possible to prevent a situation where the initial value of the count value is set to a value equal to or greater than the maximum random number.

  If the value of the initial value change method setting data is not “01h” in step S154a (that is, the value of the initial value change method setting data stored in the area 1F97h of the user program execution data area is “00h”). In the case), the CPU 56 does not change the initial value of the count value, ends the initial value changing process as it is, and proceeds to step S155.

  By executing the random number circuit setting process, various signals are input to the random number circuit 503 when the timer interrupt process including the game control process is performed, and various signals are generated in the random number circuit 503. FIG. 52 is a timing chart showing the timing at which each signal is input to the random number circuit 503 and the timing at which each signal is generated in the random number circuit 503.

  As shown in FIG. 52, the clock circuit 501 increases the signal level of the output terminal from a low level to a high level at predetermined intervals (timing T11, T21,... Shown in FIG. 52). A reference clock signal CLK (see FIG. 52A) is input to 503.

  The clock signal output circuit 524 divides the reference clock signal CLK supplied from the clock circuit 501 to generate a random number generation clock signal SI1 (see FIG. 52B). For example, the clock signal output circuit 524 raises the signal level of the output terminal from the low level to the high level at timings T11, T12,..., And changes the signal level from the high level to the low level at timings T21, T22,. To output a random number generating clock signal SI1.

  In the example shown in FIG. 52, for the sake of easy understanding, the clock signal output circuit 524 divides the reference clock signal CLK by two to generate the random number generating clock signal SI1. However, in the actual random number circuit, the period that can be set in the period setting register 537 is from “system clock signal period × 128 × 7” to “system clock signal period × 128 × 256”. Therefore, in an actual random number circuit, the clock signal output circuit 524 is set in the cycle setting register 537 in a range from “system clock signal cycle × 128 × 7” to “system clock signal cycle × 128 × 256”. The reference clock signal CLK is divided by a division ratio corresponding to the cycle setting data “07h” to “FFh” to generate a random number generating clock signal SI1. The random number generating clock signal SI 1 generated by the clock signal output circuit 524 is output to the selector 528 and the inverting circuit 532.

  In this embodiment, since the second random number update method is set in the random number circuit setting process, the second random number update method selection signal is input from the random number update method selection signal output circuit 527 to the selector 528. When the second random number update method selection signal output circuit 527 receives the second random number update method selection signal output circuit 527, the selector 528 selects the random number generation clock signal SI1 input from the clock signal output circuit 524 and outputs it to the counter 521. . Each time the rising edge of the random number generating clock signal SI1 supplied from the selector 528 is input, the counter 521 updates the count value C and outputs it to the count value permutation changing circuit 523.

  The inversion circuit 532 generates the inverted clock signal SI2 (see FIG. 52C) by inverting the signal level of the random number generation clock signal SI1 input from the clock signal output circuit 524. For example, the inverting circuit 532 lowers the signal level of the output terminal from the high level to the low level at timings T11, T12,. As a result, the inverted clock signal SI2 is output. Further, the inverted clock signal SI <b> 2 generated by the inverting circuit 532 is output to the latch signal generating circuit 533.

  When a predetermined time (for example, 3 milliseconds) elapses after the winning detection signal SS (see FIG. 52D) is input to the timer circuit 534, the latch signal generation circuit 533 receives a disturbance from the random value read signal output circuit 526. A numerical reading signal is input. For example, when the signal level of the output terminal of the random number read signal output circuit 526 rises from a low level to a high level, the random value read signal is input to the latch signal generation circuit 533. The latch signal generation circuit 533 inverts the random value read signal input from the random value read signal output circuit 526 in response to the input of the second random number update method selection signal from the random number update method selection signal output circuit 527. In synchronization with the rising edge of the inverted clock signal SI2 supplied from 532, the latch signal SL (see FIG. 52E) is output.

  As described above, the random number circuit 503 updates the count value C at the timings T11, T12, T13..., And outputs the latch signal SL at the timing T22 different from the timings T11, T12, T13. The random number value is stored in 531.

  Next, the serial communication circuit setting process (step S15a) in the main process will be described. FIG. 53 is a flowchart showing the serial communication circuit setting process. In the serial communication circuit setting process, the CPU 56 first executes the process according to the serial communication circuit setting program 556 to set the baud rate of the serial communication circuit 505 (step S1511). In this case, the CPU 56 writes a setting value corresponding to the baud rate to be set in the baud rate register 702 of the serial communication circuit 505. For example, the game control microcomputer 560 stores specification information for specifying a set value set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 writes the setting value in the baud rate register 702 according to the designation information stored in a predetermined storage area of the ROM 54. For example, when the baud rate set value “156” is set by the CPU 56, the baud rate “1201.92 bps” is generated by the baud rate generation circuit 703 using the equation (1) and the clock frequency “3 MHz”.

  Further, the CPU 56 sets a data format of data transmitted / received by the serial communication circuit 505 (step S1512). In this case, the CPU 56 sets the data length (8 bits or 9 bits) of the transmission / reception data and the use / nonuse of the parity function by setting the value of each bit of the control register A707. For example, the game control microcomputer 560 stores specification information for specifying the value of each bit of the control register A707 set by the user (for example, the manufacturer of the game machine) in a predetermined storage area of the ROM 54 in advance. Yes. Then, the CPU 56 sets the value of each bit of the control register A707 according to the designation information stored in a predetermined storage area of the ROM 54.

  In addition, the CPU 56 sets whether to permit each interrupt request generated by the serial communication circuit 505 (step S1513). In this case, the CPU 56 sets the value of bits 5, 6, and 7 of the control register B708 to thereby send an interrupt request at the time of transmission (a transmission interrupt request that is an interrupt request when transmitting data, or a transmission completion interrupt that is performed when transmission is completed). Request) and whether or not to accept interrupt request at reception. The CPU 56 can also be set to allow both a transmission interrupt request and a reception interrupt request, and allows only one of a transmission interrupt request and a reception interrupt request. It is also possible to set. Further, the CPU 56 sets whether or not to permit an interrupt request at the time of each communication error by setting the values of the bits 0 to 3 of the control register C709. For example, the gaming control microcomputer 560 stores, in advance, a predetermined storage area in the ROM 54 for specifying information for specifying the value of each bit of the control register B 708 and the control register C 709 set by the user (for example, the manufacturer of the gaming machine). I remember it. Then, the CPU 56 sets the value of each bit of the control register B 708 and the control register C 709 according to the designation information stored in a predetermined storage area of the ROM 54.

  54 and 55 are flowcharts showing an example of the power-off process in step S18. In the power-off process, the CPU 56 first checks whether or not a power-off signal is output (whether it is in an on state) (step S450). If not on, the value of the backup monitoring timer formed in the RAM 55 is cleared to 0 (step S451). If it is on, the value of the backup monitoring timer is incremented by 1 (step S452). If the value of the backup monitoring timer matches the determination value (for example, 2) (step S453), the power supply stop processing after step S454, that is, the preparation processing for power supply stop is executed. That is, the state shifts from the state in which the progress of the game is controlled to the state in which the power supply stop process (the power-off control process) for saving the game state is executed. Note that “formed in the RAM” means an area in the RAM.

  By using the backup monitoring timer and the determination value, if the power-off signal is kept on for a time corresponding to the determination value, the power supply stop process is started. That is, even when the power-off signal is turned on for a moment due to noise or the like, the power supply stop process is not erroneously started. Note that the value of the backup monitoring timer is stored by the backup power source for a predetermined period even when power supply to the gaming machine is stopped. Therefore, in step S8 in the main process, it is possible to confirm that the processing result of the power supply stop process is stored because the value of the backup monitoring timer is the same value as the determination value.

  In the power supply stop process, the CPU 56 creates parity data (steps S454 to S463). That is, first, clear data (00) is set in the checksum data area (step S454), and the checksum calculation start address corresponding to the start address of the RAM area in which the contents are to be stored even when power supply is stopped is set in the pointer. (Step S455). Further, the number of checksum calculations corresponding to the final address of the RAM area where the contents are to be stored even when the power supply is stopped is set (step S456).

  Next, an exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S457). The calculation result is stored in the checksum data area (step S458), the pointer value is incremented by 1 (step S459), and the value of the checksum calculation count is decremented by 1 (step S460). Then, the processes in steps S457 to S460 are repeated until the value of the checksum calculation count becomes 0 (step S461).

  When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S462). Then, the inverted data is stored in the checksum data area (step S463). This data becomes parity data to be checked when the power is turned on. Next, an access prohibition value is set in the RAM access register (step S471). Thereafter, the built-in RAM 55 cannot be accessed.

  Further, the CPU 56 sets the head address of the port clear setting table stored in the ROM 54 as a pointer (step S472). In the port clear setting table, the number of processes (the number of output ports to be cleared) is set to the head address, and then the output port address and output value data (clear data: the value of the off state of each bit of the output port) However, the output ports for the number of processes are sequentially set.

  The CPU 56 loads data at the address pointed to by the pointer (that is, the number of processes) (step S473). Further, the value of the pointer is incremented by 1 (step S474), and the data of the address pointed to by the pointer (that is, the address of the output port) is loaded (step S475). Further, the value of the pointer is incremented by 1 (step S476), and the data of the address pointed to by the pointer (that is, output value data) is loaded (step S477). Then, the output value data is output to the output port (step S478). Thereafter, the number of processes is reduced by 1 (step S479), and if the number of processes is not 0, the process returns to step S474. If the number of processes is 0, that is, if all the output ports to be cleared are cleared, the timer interrupt is stopped (step S481) and the loop process is started. Thus, the control state is shifted to the standby state by entering the loop processing.

  When the power supply is stopped by the above process, the power supply stop process in steps S454 to S481 is executed, and data indicating that the power supply stop process has been executed (specified value with backup and checksum) Is stored in the backup RAM, the RAM access is disabled, the output port is cleared, and the timer interrupt for executing the game control process is disabled.

  In this embodiment, the RAM 55 is backed up by a backup power source (the contents of the RAM 55 are preserved for a predetermined period even when the power supply to the gaming machine is stopped). In this example, the checksum based on the content of the RAM 55 when the power-off signal is output is stored in the backup area of the RAM 55 together with the value of the backup monitoring timer by the processing of steps S452 to S479. After the power supply to the gaming machine is stopped, when the power supply is restored within a predetermined period, the game control means performs data stored in the RAM 55 (immediately before the power supply is stopped) by the processing of steps S91 to S94 described above. In accordance with the data indicating the game state that is the control state by the game control means (for example, including the process flag state, the big hit flag state, the probability change flag state, the output port output state, etc.) It is possible to return to the state immediately before the supply is stopped. If the power supply stop period exceeds the predetermined period, the value of the backup monitoring timer and the checksum should be different from the regular values. In this case, the initialization process of steps S10 to S14 is executed. The

  As described above, the power supply stop process (preparation process for stopping the power supply) ensures that the data for returning the gaming state to the state immediately before the power supply stopped is the fluctuation data storage means (in this example) Stored in a part of the RAM 55). Therefore, even if the power is cut off due to a power failure or the like, if the power is restored within a predetermined period, the gaming state can be returned to the state immediately before the power supply is stopped.

  When the watchdog timer 60 times out during the standby state, the process returns to step S1. Also in this case, it is confirmed in the main process whether or not the power-off signal is in an off state (see step S83). When the power supply stop process is normally executed, data indicating that the power supply stop process has been executed is set, so that the game state recovery process of steps S91 to S93 is executed. Therefore, when the timer-out signal from the watchdog timer 60 is input, the state returns to a state in which the progress of the game is controlled. Therefore, even if a power interruption or the like occurs, the game control process does not stop, and the game control process is automatically continued.

  The connection confirmation signal transmitted to the payout control board 37 is set to the off state by the process of clearing the output port. In the setting of the work area in steps 92 and S12, the content of the output port buffer corresponding to the connection confirmation signal is set to a value corresponding to the ON state of the connection confirmation signal. When the prize ball processing in step S31 is executed, the contents of the output port buffer are output to the output port, so that the connection confirmation signal to the payout control board 37 is turned on. Therefore, the connection confirmation signal is output (turned on) when the main board 31 rises. Note that a connection confirmation signal is also output when the power supply is recovered from an instantaneous power interruption or the like.

  Note that timer interruption may be set to be prohibited during the power-off process. If interrupts are prohibited during execution of the power-off process, the process of step S481 becomes unnecessary.

  54 and 55 are executed in step S17 in the main process, but may be configured to be executed in the timer interrupt process shown below.

  Next, the game control process will be described. FIG. 56 is a flowchart showing the timer interrupt process. When a timer interrupt occurs during execution of the main process, specifically, during a period in which the interrupt is permitted during the execution of the loop process of steps S17 to S20, the CPU 56 of the game control microcomputer 560 A game control process is executed in a timer interrupt process activated in response to the occurrence of a timer interrupt. In the timer interrupt process, the CPU 56 first inputs detection signals of the gate switch 32a, the start port switch 14a, the count switches 231, 232, and the winning port switches 29a, 30a via the switch circuit 58, and inputs them. State determination is performed (switch processing: step S21). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided corresponding to each switch is incremented by one.

  Next, the CPU 56 confirms whether or not the initial value is set to be updated when the count value is updated to a predetermined final value in the random number circuit setting process (see step S157), and the counter of the random number circuit 503 is checked. Processing for updating the initial value input to 521 is performed (random circuit initial value updating processing: step S22).

  Next, a process of updating the count value of each counter for generating each determination random number used for game control is performed (step S23). Further, the CPU 56 performs a process of updating the count value of the counter for generating the initial value random number (initial value random number update process: step S24). Further, the CPU 56 performs a process of updating the count value of the counter for generating the display random number (display random number update process: step S25).

FIG. 57 is an explanatory diagram showing each random number. Each random number is used as follows.
(1) Random 1: For special symbol detachment symbol determination (2) Random 2: To determine a special symbol for generating a big hit (for big hit symbol determination).
(3) Random 3: Determine the variation pattern of the special symbol (for variation pattern determination)
(4) Random 4: Decide whether or not to reach when no big hit is generated (for reach determination)
(5) Random 5: Determines whether or not to generate a hit based on a normal symbol (for normal symbol hit determination)
(6) Random 6: Determine the initial value of random 2 (for determining the random 2 initial value)
(7) Random 7: Determine the initial value of random 5 (for determining the random 5 initial value)
(8) Random 8: Determine the type of jackpot (for determining the jackpot type)
(9) Random 9: Determine initial value of random 8 (for determining random 8 initial value)

  In step S23 in the game control process shown in FIG. 56, the CPU 56 generates (2) a big hit symbol determining random number, (5) a normal symbol determining random number, and (8) a big hit type determining random number. Counter is incremented (added by 1). That is, they are determination random numbers, and other random numbers are display random numbers or initial value random numbers. Further, in order to enhance the gaming effect, random numbers related to ordinary symbols other than the random numbers (1) to (9) may be used.

  When the determination random number update process, the initial value update process, and the display random number update process are performed, the CPU 56 causes the count value permutation change circuit 523 to change the count value permutation output from the counter 521 of the random number circuit 503. Processing is performed (step S26). In this embodiment, whether or not to execute the count value permutation change process is determined depending on whether or not the count value permutation change flag is set in step S158 of the random number circuit setting process. Then, the CPU 56 executes the count value permutation change process based on the fact that the count value permutation change flag is set.

  Further, the CPU 56 performs special symbol process processing (step S27). In the special symbol process, the corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S28). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of sending an effect control command by setting an effect control command related to the decorative symbol synchronized with the change of the special symbol in a predetermined area of the RAM 55 (decorative symbol command control process: step S29). Note that the fact that the variation of the decorative symbol is synchronized with the variation of the special symbol means that the variation time (variable display period) is the same.

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S30).

  Further, the CPU 56 executes prize ball processing for setting the number of prize balls based on detection signals from the prize opening switches 29a, 30a, etc. (step S31). Specifically, a payout command command such as a prize ball number command indicating the number of prize balls is output to the payout control board 37 in response to detection of a winning based on turning on the prize opening switches 29a, 30a and the like. The payout control microcomputer 370 mounted on the payout control board 37 drives the ball payout device 97 in response to receiving a prize ball number command indicating the number of prize balls.

  And CPU56 performs the memory | storage process which checks the increase / decrease in a pending | holding memory | storage number (step S32). In addition, a test terminal process, which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S33). In addition, the CPU 56 executes an output setting process for outputting a control signal (command signal) for instructing lighting of one of the two large winning opening indicator lights 38 and 39 (step S34). In the output setting process, a setting value for instructing lighting of one of the special winning opening indicator lamps 38, 39 is set in the buffer. In the output process (step S35), a control signal based on the setting value set in the buffer. May be output. In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided, but the CPU 56 outputs the contents related to the solenoid in the RAM area of the output port 3 to the output port. (Step S35: Output processing). Further, the CPU 56 executes WDT clear processing for clearing and restarting the count value by setting data in the WDT clear register 62 of the watchdog timer 60 via the internal bus (step S36). Thereafter, the CPU 56 sets the interrupt permitted state (step S37) and ends the process.

  In this embodiment, the game control process is started periodically (for example, every 2 ms). In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process has a flag. It may be executed in the main process based on the setting.

  In addition, for example, in the timer interrupt process, the switch process (see step S21), the initial value random number update process (see step S24), the decorative symbol command control process (see step S29), and an interrupt to be described later. Only the count process (see steps S3201a and S3202) may be executed, and other processes in the game control process may be executed in the main process. In this case, the CPU 56 of the game control microcomputer 560 includes steps S22 to S28 (except for the interrupt count processing) and steps of the game control process in the loop process from step S17 to step S20 in the main process. Processing from S31 to step S36 (excluding step S33) is executed. In addition, the CPU 56 of the game control microcomputer 560 counts the number of interrupts (the number of times the timer interrupt process is executed after detecting the winning detection signal) in the timer interrupt process (see step S3201a). When it is detected that the number of executions of the timer interrupt process has reached a predetermined number (for example, 3 times) (see step S3202), a condition for reading a random number value from the random number circuit 503 is satisfied (the execution condition for variable display is satisfied). ) And a random number read flag indicating that the random number read condition is satisfied is set. Whether the random number read flag is set when the CPU 56 of the game control microcomputer 560 executes the start port switch passage process (see step S312) in the special symbol process (see step S27) in the main process. If it is determined that the random number read flag is set, an output control signal SC is output to the random value storage circuit 531 of the random number circuit 503 (see step S3203). The stored random R value is read (see step S3204). Then, in the main process, the CPU 56 determines whether or not to make a big hit based on the read random number value when executing the special symbol normal process (see step S300) in the special symbol process (see step S27). It will be. In this embodiment, the processes in steps S21 to S36 (except for steps S30 and S33) correspond to a game control process for controlling the progress of the game.

  Next, the random number circuit initial value update process (step S22) in the timer interrupt process will be described. FIG. 58 is a flowchart showing random number circuit initial value update processing. In the random number circuit initial value update process, the CPU 56 checks the state of the notification signal indicating that the count value C output from the counter 521 of the random number circuit 503 has been updated to the final value (step S220). When it is detected that the notification signal is in the on state, the CPU 56 checks whether or not the initial value update flag is set (step S221). That is, in the random number circuit setting process, the CPU 56 checks whether or not the setting for updating the initial value is made when the count value is updated to a predetermined final value (see step S157).

  When the initial value update flag is set, the CPU 56 determines to update the initial value input to the counter 521 when the counter 521 of the random number circuit 503 updates the count value to a predetermined final value. When the initial value update flag is set, the CPU 56 checks whether or not the initial value change flag is set (step S222). That is, the CPU 56 determines whether or not the initial value of the count value is currently changed (that is, whether or not it is changed to a value based on the ID number of the game control microcomputer 560).

  When the initial value change flag is set (that is, when the initial value is currently changed based on the ID number of the game control microcomputer 560), the CPU 56 uses the initial value input to the counter 521 as the game control. The value based on the ID number of the microcomputer 560 is returned to the original value (for example, “1”) (step S223). Then, the CPU 56 resets the initial value change flag (step S224) and ends the initial value update process.

  If the initial value change flag is not set (that is, the initial value is not currently changed), the CPU 56 changes the initial value input to the counter 521 to a value based on the ID number of the game control microcomputer 560. (Step S225). In this case, for example, if the ID number of the game control microcomputer 560 is “100”, the initial value input to the counter 521 is calculated by adding a predetermined value “100” to the ID number “100”. Change to the value “200”. Further, for example, the initial value input to the counter 521 is changed to the calculated value “50” obtained by subtracting the predetermined value “50” from the ID number “100”. Then, the CPU 56 sets an initial value change flag (step S226) and ends the initial value update process.

  When the update speed of the random number of the random number circuit 503 is high, it may be updated to the next count value from the timing when the notification signal is turned on to the timing when the initial value is changed. By adjusting the frequency of the clock signal output from the output circuit 524 to the counter 521 and adjusting the update speed of the random number of the random number circuit 503, the timing from when the notification signal is turned on to when the initial value is changed is next. It is also possible not to update the count value.

  When both the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are set, in step S225, the CPU 56 sets the random number read from one random number circuit (for example, the 12-bit random number circuit 503a) as a predetermined value as an ID number. The initial value input to the counter 521 may be obtained. Then, the CPU 56 may use a random number read from the other one (for example, a 16-bit random number circuit 503b) as a random number for determining the big hit.

  When the CPU 56 updates the initial value input to the counter 521 in step S225, the CPU 56 checks the value of the random number maximum value setting register 535 of the comparator 522 of the random number circuit 503, and the value set based on the ID number is obtained. It is determined whether or not it is greater than the maximum random number. If the CPU 56 determines that the value set based on the ID number is equal to or greater than the maximum random number, the CPU 56 does not update the initial value input to the counter 521 with a predetermined value (for example, updates with the predetermined value “0”). do not do). By doing so, it is possible to prevent a situation where the initial value of the count value is set to a value equal to or greater than the maximum random number.

  If it is determined in step S220 that the notification signal is in the OFF state, or if it is determined in step S221 that the initial value update flag is not set, the CPU 56 does not update the initial value input to the counter 521. Then, the random number circuit initial value update process is finished as it is, and the routine goes to Step S23.

  Next, the count value permutation change process (step S26) in the timer interrupt process will be described. FIG. 59 is a flowchart showing the count value permutation changing process. The CPU 56 performs a count value permutation change process by executing a process according to the count value permutation change program 554. In the count value permutation change process, the CPU 56 checks the state of the notification signal indicating that the count value C output from the counter 521 of the random number circuit 503 has been updated to the final value (step S241). When it is detected that the notification signal is in the on state, the CPU 56 checks whether or not the count value permutation change flag is set (step S242). That is, the CPU 56 determines whether or not the setting for changing the permutation of the count values updated by the counter 521 when the count values are updated to a predetermined final value has been made in the random number circuit setting process (see step S158). Check.

  When the count value permutation change flag is set, the CPU 56 determines that the permutation of the count values updated by the counter 521 is changed when the counter 521 of the random number circuit 503 updates the count value to a predetermined final value. Then, the CPU 56 writes the count value permutation change data “01h” in the count value permutation change register 536 (step S243). That is, the CPU 56 causes the count value permutation change circuit 523 to change the permutation of the count values C input to the random value storage circuit 531 by writing the count value permutation change data “01h”.

  As described above, in the count value permutation changing process, when the random number is updated to a predetermined final value, the permutation of the count value updated by the counter 521 is changed, so that the randomness generated by the random number circuit 503 is more random. Can be improved.

  Next, the special symbol process (step S27) in the main process will be described. FIG. 60 is a flowchart showing an example of a special symbol process processing program executed by the CPU 56 of the game control microcomputer 560. The CPU 56 of the game control microcomputer 560 has the start opening switch 14a for detecting that a game ball has won the start winning opening 14 provided in the game board 6 turned on, that is, the game ball has a start winning prize. If a start winning to win the mouth 14 has occurred (step S311), the start opening switch passing process (step S312) is performed, and then any one of steps S300 to S308 is performed according to the internal state. .

  Special symbol normal processing (step S300): A state where variable symbol special display can be started (for example, the symbol variation has not been made in the special symbol display 8, and the previous symbol variation in the special symbol display 8 has ended) Waits for a predetermined period of time to elapse, and not a big hit game). When the special symbol variable display can be started, the start winning memory number for the special symbol is confirmed. If the number of start winning memories is not 0, check whether the gaming state is a probabilistic state or a short-time state. It is determined whether or not the number of times has reached a predetermined number (100 times). When the number of changes reaches a predetermined number, the game state transition control is executed. Further, based on the random R generated by the random number circuit 503 stored in the special figure holding memory 570, it is determined whether or not the display result of the variable symbol special display is a big hit. When it is determined that the display result of the variable display is a big hit, the type of the big hit is determined. Then, the internal state (special symbol process flag) is updated so as to shift to step S301.

  Special symbol stop symbol setting process (step S301): A stop symbol after variable display of the special symbol is determined. Then, the internal state (special symbol process flag) is updated so as to shift to step S302.

  Variation pattern setting process (step S302): A variation pattern is determined, and the variation time in the variation pattern (variable display time: time from the start of variable display until the display result is derived and displayed (stop display)) is a special symbol. It is determined to be a variable display variable time. Then, the internal state (special symbol process flag) is updated so as to shift to step S303.

  Special symbol variation processing (step S303): When a predetermined time (time indicated by the variation time timer in step S302) elapses, the internal state (special symbol process flag) is updated to shift to step S304.

  Special symbol stop process (step S304): The special symbol on the special symbol display 8 is stopped. If the stop symbol of the special symbol is a big hit symbol, the internal state (special symbol process flag) is updated to shift to step S305. If not, the internal state is updated to shift to step S300.

  Preliminary winning opening opening process (step S305): Control for opening the large winning opening is started. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the grand prize opening) and a flag (a flag used when detecting a winning at the prize opening) are initialized, and the solenoids 241 and 242 are turned on. Drive to open the first grand prize winning opening or the second big winning prize opening. In addition, the process timer sets the execution time of the special winning opening opening process. Then, the internal state (special symbol process flag) is updated so as to shift to step S306.

  Processing for opening a special prize opening (step S306): control for sending a presentation control command for round display of the special prize opening to the sound / lamp control board 80b and conditions for closing the special prize opening (for example, a predetermined number (for example, a special prize opening) A process of confirming that 10) gaming balls have won) is performed. Whether or not the maximum number of rounds (2 rounds, 7 rounds, 15 rounds) according to the type of jackpot (2 rounds, 7 rounds, 15 rounds) has been reached when the closing conditions for the big prize opening are met If the maximum number of rounds has not been reached, the internal state (special symbol process flag) is updated to shift to step S305. If the maximum number of rounds has been reached, the internal state shifts to step S307. Update to

  Big hit end processing (step S307): Control is performed to cause the sound / lamp control means and the symbol control means to perform voice output control, display control, and the like for notifying the player that the big hit gaming state has ended. Then, the internal state is updated so as to shift to step S300.

  FIG. 61 is an explanatory diagram showing an example of a variation pattern used in this embodiment. In FIG. 61, “EXT” indicates EXT data of the second byte in the effect control command having a two-byte structure. “Time” indicates the variation time of the special symbol (variable display period of identification information).

  The variation pattern in which the EXT data is “00H” is a variation pattern of the normal variation of the special symbol on the special symbol display 8 in the normal gaming state and the high probability latent state. The variation patterns in which the EXT data is “01H” to “06H” are variation patterns with reach in the normal gaming state and the high probability latent state, respectively. The variation pattern in which the EXT data is “01H” to “03H” is used when the special symbol stop symbol is used as a symbol. Further, the fluctuation pattern of EXT data “04H” to “06H” is used when the special symbol stop symbol is a big hit symbol. Reach A, reach B, and reach C are reach in different production modes.

  The variation pattern of the EXT data “07H” is a variation pattern of the normal variation of the special symbol on the special symbol display 8 in the probability variation state (excluding the high probability latent state) and the short time state. The variation patterns in which the EXT data is “08H” to “0DH” are variation patterns with reach in the probability variation state (excluding the high probability latent state) and the short time state, respectively. The variation pattern in which the EXT data is “08H” to “0AH” is used when the special symbol is stopped and the stop symbol is used as the symbol. Further, the fluctuation pattern of EXT data “0BH” to “0DH” is used when the special symbol stop symbol is a big hit symbol. Reach A, reach B, and reach C are reach in different production modes. The variation pattern of normal variation (“07H”) in the probability variation state (excluding the high probability latent state) and the short time state is more than the variation pattern of normal variation (“00H”) in the normal gaming state and the high probability latent state. Also, the variation time is set short. By selecting such a variation pattern in the probability variation state (except for the high probability latent state) and the short time state, the variation time of the special symbol is shortened. In the case of a variation pattern with reach, the variation time is not set short even in the probability variation state and the short time state.

  As described above, the variation pattern is divided depending on whether the gaming state is a normal gaming state, a high probability latent state, a probability variation state (excluding a high probability latent state), or a time-short state, so specify the variation pattern The sound / lamp control microcomputer 100b that has received the effect control command can grasp the current gaming state by the effect control command designating the variation pattern. Similarly, the symbol control microcomputer 100a that has received a command from the sound / lamp control microcomputer 100b can grasp the current gaming state by a command designating a variation pattern. Therefore, the sound / lamp control microcomputer 100b and the symbol control microcomputer 100a can grasp the game state by the command and execute a game effect according to the grasped game state.

  FIG. 62 is an explanatory diagram showing an example of the contents of the effect control command sent to the sound / lamp control board 80b. In the example shown in FIG. 62, commands 8000 (H) to 800D (H) are effect control commands (variation) that designates a variation pattern of decorative symbols that are variably displayed on the variable display device 9 in response to variable display of special symbols. Pattern command). The effect control command for designating the variation pattern is also a command for designating the variation start.

  The command 8100 (H) is an effect control command (offset designation command) for designating that the display result of the variable display device 9 is an outlier symbol. The command 8101 (H) is an effect control command (2R probability variation big hit designation command) for designating that the display result of the variable display device 9 is a two round probability variation big hit. The command 8102 (H) is an effect control command (2R short / long hit designation command) for designating that the display result of the variable display device 9 is a short / long big hit for 2 rounds. The command 8103 (H) is an effect control command (7R normal big hit designation command) for designating that the display result of the variable display device 9 is a normal big hit for seven rounds. The command 8104 (H) is an effect control command (15R normal big hit designation command) for designating that the display result of the variable display device 9 is a normal big hit for 15 rounds. The command 8105 (H) is an effect control command (15R probability variation big hit designation command) for designating that the display result of the variable display device 9 is a probability round big hit for 15 rounds. A command 8106 (H) is an effect control command (15R hour / long jackpot designation command) that designates that the display result of the variable display device 9 is a round / big jackpot of 15 rounds.

  In addition, as will be described later, unlike the cases of 7 rounds and 15 rounds, the rounds of probable big hits for 2 rounds and short-time big hits for 2 rounds do not proceed in order, but suddenly, The game state is shown to the player as if the game state has shifted to a probable change state or a short-time state (note that the game effect of the same effect mode is executed in any of the probabilistic state (excluding the high probability latent state) and the short-time state). A special performance is performed. Therefore, the two-round probability change big hit is called “sudden probability change big hit” or simply “sudden probability change”. Also, the two rounds of short-and-short time hits are referred to as “sudden short-term hits” or simply “sudden short-term hits”.

  Since the commands 8100 (H) to 8106 (H) are effect control commands for designating the display result of the variable display device 9, the commands 8100 (H) to 8106 (H) are referred to as display result commands.

  The command A000 (H) is an effect control command (decorative symbol stop designation command) for designating stop of variable display (variation) of decorative symbols on the variable display device 9.

  The command BXXX (H) is an effect control command that is sent from the start of the big hit game to the end of the big hit game. The commands D000 (H) to EXXXX (H) are effect control commands relating to the display state of the variable display device 9 that is not related to the variation of the decorative symbols and the big hit game.

  Command B000 (H) is an effect control command (fanfare 1 command) that specifies that a two-round jackpot game is to be started. Command B001 (H) is an effect control command (fanfare 2 command) that specifies that a 7-round jackpot game is to be started. Command B002 (H) is an effect control command (fanfare 3 command) that specifies that a 15-round jackpot game is to be started.

  The production microcomputer notifies the start of the jackpot game based on the fanfare command. At this time, it also notifies whether the type of jackpot is a big hit of 7 rounds or a big hit of 15 rounds. Then, the player is also notified of the opening position of the big winning opening corresponding to the type of jackpot (which big winning opening is opened). However, in addition to the fanfare command, a command indicating which big winning opening is opened is transmitted to the production microcomputer, and the production microcomputer determines the opening position of the big winning opening based on the command. You may be comprised so that it may alert | report (for example, the open position of a big prize opening is displayed on the display screen of the variable display apparatus 9). In this case, it is not necessary to divide the fanfare command according to the type of jackpot as shown in FIG. Also, when a big round of two rounds has occurred, a command indicating which winning prize opening is to be opened should not be sent to the production microcomputer, and the production microcomputer will not send the command. In such a case, control for notifying the player about the open position of the special winning opening is not executed. In addition, even when a fanfare command capable of specifying the type of jackpot is transmitted, the microcomputer for production determines that the jackpot type is a jackpot of two rounds based on the display result command. The control for notifying the player about the open position may not be executed. Furthermore, it may be configured to transmit a command indicating that none of the big winning openings is opened when a two-round big hit occurs to the production microcomputer.

  The command B1XX (H) is an effect control command (display command during opening of the big prize opening) that designates display during the round during the big hit game. Note that the number of rounds displayed in “XX” is set. The command B2XX (H) is an effect control command (count number designation command) that designates the number of winning balls (the number of winning detections of the count switches 231 and 232) to the big prize opening during each round. The number of winning balls (count number) is set in “XX”. The command B3XX (H) is an effect control command (display command after opening the big prize opening) that specifies display after the round (display of the interval between rounds) during the big hit game. Note that the number of rounds displayed in “XX” is set. Command B400 (H) is an effect control command (a jackpot end designation command) that designates that the jackpot game is to be terminated.

  Command D000 (H) is an effect control command for designating a customer waiting demonstration. The command E401 (H) is an effect control command (normal display command) that designates execution of a game effect (normal game effect) when the game state is the normal game state (low probability state). The command E402 (H) is an effect control command (special display command) that designates execution of a game effect (special game effect) when the game state is a probability change state (high probability state) and a short time state. Command E403 (H) is an effect control command (high probability latent display command) that specifies execution of a game effect (normal game effect) when the game state is a high probability latent state.

  When the sound / lamp control microcomputer 100b mounted on the sound / lamp control board 80b receives the above-described effect control command from the game control microcomputer 560 mounted on the main board 31, it is shown in FIG. Depending on the contents, sound output control of the speaker 27 is executed, and lamp lighting control is executed. The sound / lamp control microcomputer 100b transmits the received effect control command to the symbol control microcomputer 100a, generates a command based on the received effect control command, and generates the generated command. It transmits to the computer 100a. When receiving the command from the sound / lamp control microcomputer 100b, the symbol control microcomputer 100a executes display control of the variable display device 9 in accordance with the received command.

  An effect control command other than the effect control command shown in FIG. 62 is also transmitted from the main board 31 to the sound / lamp control board 80b.

  FIG. 63 is a flowchart showing the start port switch passage process (step S312). In the start port switch passing process, the CPU 56 of the game control microcomputer 560 sets the start winning memory number indicated by the start winning counter (or the start winning memory number stored in the special figure holding memory 570) to 4 which is the maximum value. It is confirmed whether it has reached (step S3201). If the start winning memorized number has not reached 4, the CPU 56 adds 1 to the value of the interrupt counter indicating the number of times the timer interrupt process has been executed (step S3201a). That is, the CPU 56 executes a process of counting the number of times that the timer interrupt process has been executed. In this embodiment, by executing step S3201a, the CPU 56 counts up an interrupt counter that indicates the number of times the timer interrupt process has been executed each time the timer interrupt process is executed. When the value of the interrupt count counter is incremented by 1, the CPU 56 checks whether or not the number of executions of the timer interrupt process indicated by the interrupt execution count counter has reached a predetermined number (for example, 3 times) (step S3202). ). Then, after the game ball has won the start winning opening 14, the CPU 56 checks whether or not the interrupt execution counter has reached a predetermined number. When it is detected that the game ball has won the start winning opening 14 (that is, when YES is determined in step S3202), the CPU 56 resets the interrupt execution counter.

  The value set in advance as the predetermined number of times in step S3202 is determined as follows. As described above, the timer circuit 534 of the random number circuit 503 measures the time that the winning detection signal SS is continuously input from the start port switch 14a, and detects that the measurement time has reached a predetermined period, Write numerical value capture data “01h”. In this embodiment, a predetermined period (for example, 3 ms) measured by the timer circuit 534 is a period in which a predetermined number of timer interrupt processes are executed (for example, when the timer interrupt process for every 2 ms is executed three times). The predetermined number (for example, 3 times) used in step S3202 is set so as to be shorter than 6 ms). By setting in this way, it is possible to prevent the random number from being read again after the random number is read and before the random number value stored in the random value storage circuit 531 is updated. It is possible to prevent a random number having the same value as the random number read from the circuit 531 from being read again. The timer circuit 534 does not measure the input time of the winning detection signal SS, but the CPU 56 measures the input time of the winning detection signal SS and writes the random number value fetch data “01h” into the random value fetch register 539. May be.

  When the number of executions of the timer interrupt process has reached a predetermined number, the CPU 56 can output the output control signal SC to the random number storage circuit 531 of the specified random number circuit 503 and read the random number storage circuit 531 (enable). The state is controlled (step S3203).

  The CPU 56 reads the random R value stored as the random number value from the random value storage circuit 531 of the random number circuit 503 (step S3204). Further, the CPU 56 stores the read random R value in the storage area (special symbol determination buffer (special symbol holding memory 570)) corresponding to the value of the number of start winning memories (step S3205). When the CPU 56 stores the value of the random R in the buffer area, the CPU 56 stops outputting the output control signal SC to the random value storage circuit 531 and controls the random value storage circuit 531 to be unreadable (disabled) (step). S3206). Further, the CPU 56 resets the interrupt execution number counter (step S3207). Then, the CPU 56 sets the random R value stored in the predetermined buffer area at the head of the empty entry in the special figure reservation memory 570 (step S3208), and increments the count of the start prize counter by 1 to store the start prize memory. The number is increased by 1 (step S3209).

  Further, the CPU 56 extracts values of random numbers (software random numbers) such as determination random numbers and display random numbers, and stores them in a storage area (special symbol determination buffer) corresponding to the value of the start winning memory number ( Step S3210). Note that extracting a random number means reading a count value from a counter for generating a random number and setting the read count value as a random value. In step S3210, random 1 to random 4 and random 8 are extracted from the random numbers shown in FIG.

  If the start winning memorization is stored in step S3201, but the maximum value of 4 has been reached, and if the number of executions of the timer interrupt process has not reached the predetermined number in step S3202, the start port switch passing process is terminated.

  As described above, the timer interrupt process has been executed a predetermined number of times when reading the random R from the random value storage circuit 531 in the starting port switch passing process (that is, continued while the timer interrupt process is executed a predetermined number of times). The random number is read from the random value storage circuit 531 on the condition that the winning detection signal SS is input). Therefore, it is possible to prevent the random number from being read again after the random number is read and before the value of the random number stored in the random value storage circuit 531 is updated. Further, it is possible to prevent a random number having the same value as the random number read from the previous random number value storage circuit 531 from being read again.

  Next, the special symbol normal process (step S300) in the special symbol process will be described. FIG. 64 is a flowchart showing special symbol normal processing. In the special symbol normal process, the CPU 56 of the game control microcomputer 560 can start the variation of the special symbol (for example, when the value of the special symbol process flag is a value indicating step S300) ( Step S51), the value of the start winning memory number (holding memory number) is confirmed (step S52). Specifically, the count value of the start winning storage counter is confirmed. The case where the value of the special symbol process flag is a value indicating step S300 is a case where the symbol is not changed in the variable display device 9 and is not in the big hit game. On the other hand, if it is not possible to start fluctuation in step S51, or if the number of reserved memories is 0 in step S52, the CPU 56 ends the special symbol normal process as it is.

  If the number of reserved memories is not 0, each random value (random R, random numbers for determination, random numbers for display) stored in the storage area corresponding to the number of reserved memories = 1 is read and stored in the random number buffer area of the RAM 55. At the same time (step S53), the value of the reserved storage number is decreased by 1 (the value of the start winning storage counter is decreased by 1), and the contents of each storage area are shifted (step S54). That is, each random number value stored in the storage area corresponding to the reserved memory number = n (n = 2, 3, 4) is stored in the storage area corresponding to the reserved memory number = n−1. Therefore, the order in which the random number values stored in the respective storage areas corresponding to the number of reserved memories is extracted always matches the order of the number of reserved memories = 1, 2, 3 and 4. Yes. That is, in this example, every time the variable display start condition is satisfied, the CPU 56 executes a process of shifting the contents of each storage area.

  Next, the CPU 56 checks whether or not the probability variation flag or the time reduction flag is set (step S55A). The probability change flag is a flag indicating that the number of times the special symbol has changed is less than or equal to a predetermined number (100 times) after the gaming state is shifted to the probability change state. The probability variation flag is set when the probability variation state is entered, that is, when the probability variation big hit occurs and the big hit game ends, and when the special symbol variation count reaches the predetermined number of times after entering the probability variation state. And when it shifts to the probable change state and before the number of fluctuations of the special symbol reaches the predetermined number of times, it is reset when the short hit big hit or the normal big hit occurs and the big hit game ends (see the big hit end processing etc. in FIG. 71) ). Further, the time reduction flag is a flag indicating that the gaming state is a time reduction state. The time-short flag is set when the time-short state is shifted, that is, when a time-hit big hit occurs and the big hit game ends, and when the probability change state, a normal big hit occurs and the big hit game ends. When the time-short state ends, that is, when the number of changes in the special symbol reaches a predetermined number since the transition to the time-short-term hit, and after the transition to the time-short state, the normal symbol hits before the number of changes in the special symbol reaches the predetermined number Is reset when the big hit game ends (see the big hit end processing in FIG. 71).

  If the probability variation flag or the time reduction flag is not set (N in Step S55A), the process proceeds to Step S56A. If the probability variation flag or the time reduction flag is set (Y in step S55A), the CPU 56 decrements the value of the variation counter by -1 (step S55B). The fluctuation number counter is a counter that counts the number of fluctuations of the special symbol after the gaming state is shifted to the probability changing state or the time saving state. A predetermined number of times (100 times) is set in this variation number counter when the gaming state is shifted to the probability variation state or the short-time state (see the big hit end processing and the like in FIG. 71). Next, the CPU 56 checks whether or not the value of the variation counter is 0 (step S55C). At this time, the value of the variation counter being 0 means that the number of variations has reached a predetermined number since the gaming state has shifted to the probability variation state or the time-short state. When the value of the variation counter is 0 (Y in step S55C), the CPU 56 checks whether or not the probability variation flag is set (step S55D). If the probability variation flag is set, the CPU 56 has a high probability. A latent state flag is set (step S55E). The high-probability latent state flag has a high probability that a big hit will occur, but the game effect is a high-probability latent state in which the normal game effect is executed. It is a flag indicating that the number of times has been reached. Next, the CPU 56 resets the probability variation flag or the time reduction flag (step S55F).

  When the probability variation flag or the time reduction flag is set, the CPU 56 increases the probability that the stopped symbol of the normal symbol becomes a winning symbol in the normal symbol process (step S28), and releases the variable winning ball device 15. Control for increasing one or both of time and the number of times of opening is executed.

  Next, the CPU 56 reads the jackpot determination random number (random R) stored in the random number buffer area (step S56A), and based on the read value of the jackpot determination random number, displays the display result of the special symbol display 8 as the jackpot symbol. It is determined whether or not to perform (step S56B). In this case, when the gaming state is the normal gaming state or the short-time state (when the gaming state is not the probability variation state), the CPU 56 determines whether or not to make a big hit using the normal big hit determination table (FIG. 37A). When the gaming state is in the probability changing state, it is determined whether or not to make the jackpot using the probability changing jackpot determination table (FIG. 37B). Whether or not the gaming state is a probability variation state can be confirmed by whether or not the probability variation flag or the high probability latent state flag is set.

  Note that the jackpot determination is performed in the special symbol normal process (step S300) of the special symbol process (step S27) in the timer interrupt process, but when the loop process in the main process is being performed (for example, step (Between S17 and step S20).

  When it is determined that a big hit is made (Y in step S56C), the CPU 56 sets a big hit flag indicating that it is a big hit (step S57A). Also, the big hit type determining random number (random 8) is read from the storage area (step S57B), and the big hit type (two rounds probable big hit, two rounds short hit big hit, seven rounds normal) based on the read big hit type determining random number value Big hit, 15 round normal big hit, 15 round probability variation big hit, 15 round short time big hit) are determined (step S57C). Then, a work setting table provided in the ROM 54 is selected according to the determined jackpot type, and the indicator lamp designated value set in the selected work setting table is set in the RAM 55 (step S57D). The work setting table is a table in which various designated values for executing game control are set. The CPU 56 executes various types of game control with reference to the specified values set in the work setting table when executing the game control. The indicator light designated value is a designated value indicating which of the two large winning opening indication lights 38 and 39 is to be displayed. As described above, the second big prize opening is opened when the second round big hit and the 15th round big hit, so when the second round big hit or the 15th round big hit is determined as the big hit type, the second big prize winning indicator light 39 The work setting table in which the indicator lamp specification value that specifies the lighting of is set is selected. The first big winning opening is opened when the seventh round big hit, so when the seventh round big winning is determined as the big hit type, an indicator lamp designating value for designating lighting of the first big winning opening indicator lamp 38 is set. The work setting table is selected. Then, the indicator lamp designation value of the selected work setting table is set in the RAM 55. It should be noted that the display control of the special winning opening indicator lamps 38 and 39 based on the indicator lamp designation value set in the RAM 55 is executed in step S389 of FIG. 67 described later.

  Next, the CPU 56 executes control to transmit a display result designation command to the sound / lamp control board 80b in accordance with the type of the big hit when it is decided to make the big hit or not, or the big hit (step S58). ).

  Specifically, the address of the command transmission table corresponding to the display result designation command is set in the pointer. When the address of the command transmission table corresponding to the display result designation command is set to the pointer, the display result designation command is transmitted in the decorative design command control process (step S29). In this embodiment, “transmit an effect control command” indicates that such processing is performed. The command transmission table is an area of the ROM 54 in which each effect control command illustrated in FIG. 62 is set. The pointer is data used for designating an address where the corresponding command is stored in the area, and is formed in the RAM 55.

  It should be noted that, based on the fact that the address of the command transmission table corresponding to the production control command is set in the pointer, it is not limited to the configuration in which the production control command is transmitted in the decorative symbol command control process (step S29). In the process of S58 or the like, a configuration in which an effect control command is transmitted may be used. The same applies to the command transmission processing in this embodiment.

  Then, the CPU 56 updates the value of the special symbol process flag to a value corresponding to the special symbol stop symbol setting process (step S59).

  In step S57C described above, the jackpot type is determined based on the value of the random number for determining the jackpot type. However, the present invention is not limited to such a configuration. Corresponding in advance, the jackpot type may be determined based on the value of the jackpot symbol determining random number (random 2).

  FIG. 65 is a flowchart showing an example of the special symbol stop symbol setting process (step S301) in the special symbol process. In the special symbol stop symbol setting process, the CPU 56 of the game control microcomputer 560 first checks whether or not the big hit flag is set (step S361). If the big hit flag is not set, the CPU 56 determines a special symbol stop symbol (out of symbol) based on the loss symbol determination random number (random 1) stored in the special symbol determination buffer (step S362). ). Further, the CPU 56 determines whether or not to reach based on the reach determination random number (random 4) stored in the special symbol determination buffer (step S363).

  When it is determined that the reach is to be achieved (that is, the decorative symbol stop symbol is not to be the big hit symbol after the reach mode is set) (step S364), the CPU 56 sets a reach flag (step S365).

  If the jackpot flag is set, the CPU 56 determines a special symbol stop symbol (hit block symbol) based on the jackpot symbol determination random number (random 2) stored in the special symbol determination buffer (step S366). ). At this time, since the jackpot symbol of the special symbol differs depending on the jackpot type, it is necessary to determine the jackpot symbol corresponding to the jackpot type. In order to determine the jackpot symbol corresponding to the jackpot type, the table used for determining the jackpot symbol is switched according to the jackpot type.

  Then, the CPU 56 updates the value of the special symbol process flag to a value corresponding to the variation pattern setting process (step S367).

  FIG. 67 is a flowchart showing an example of the variation pattern setting process (step S302) in the special symbol process. In the variation pattern setting process, the CPU 56 of the game control microcomputer 560 determines to use a variation pattern table according to the set status of the big hit flag, reach flag, probability variation flag, and time reduction flag (step S371).

  Specifically, when the big hit flag is set and neither the probability variation flag nor the hourly flag is set, it is determined to use a variation pattern table in which variation patterns of “04H” to “06H” are set. When the reach flag is set and neither the probability variation flag nor the time reduction flag is set, it is determined to use a variation pattern table in which variation patterns of “01H” to “03H” are set. When neither the big hit flag nor the reach flag is set, and neither the probability variation flag nor the hourly flag is set, it is decided to use the variation pattern table in which the variation pattern of “00H” is set. When the big hit flag is set and the probability variation flag or the time reduction flag is set, it is determined to use a variation pattern table in which variation patterns of “0BH” to “0DH” are set. When the reach flag is set and the probability variation flag or the time reduction flag is set, it is determined to use a variation pattern table in which variation patterns of “08H” to “0AH” are set. When neither the big hit flag nor the reach flag is set, and the probability variation flag or the hourly flag is set, it is decided to use the variation pattern table in which the variation pattern of “07H” is set.

  The high probability latent state flag is set when neither the probability variation flag nor the time reduction flag is set. In this case, a variation pattern table for determining a variation pattern in the normal gaming state is selected. Therefore, in the high probability latent state, the same normal variation pattern as that in the normal gaming state is determined as the normal variation pattern of the special symbol.

  Next, the CPU 56 reads the variation pattern determination random number (random 3), and determines the variation pattern using the variation pattern table determined in step S371 based on the read variation pattern determination random number (step S372). . Then, control is performed to transmit a variation pattern command designating the determined variation pattern to the sound / lamp control microcomputer 100b of the sound / lamp control board 80b (step S373).

  Next, the CPU 56 sets the variation time of the variation pattern in the special symbol process timer (step S374), starts the special symbol process timer, and starts measuring the variation time of the special symbol (step S375). Then, the CPU 56 updates the value of the special symbol process flag to a value corresponding to the special symbol variation process (step S376).

  FIG. 67 is a flowchart showing special symbol stop processing. In the special symbol stop process, the CPU 56 stops the variation of the special symbol on the special symbol display 8 and derives and displays the stop symbol (step S381). Further, the CPU 56 performs control to transmit a decoration design variation stop designation command for designating stoppage of the design variation on the variable display device 9 to the sound / lamp control microcomputer 100b (step S382). In addition, when the decorative symbol stop designation command is transmitted, a flag indicating that it has been transmitted is set, and when the flag is confirmed in the subsequent special symbol stop processing, the processing of steps S381 and S382 is not executed. It shall be. With such a configuration, it is possible to avoid the decorative symbol stop designation command being transmitted a plurality of times.

  Also, the value of the special symbol process timer is decremented by 1 (step S383). At this time, in the special symbol changing process (step S303), a special symbol stop time is set for the special symbol process timer to stop and display the special symbol. Next, the CPU 56 determines whether or not the special symbol process timer has timed out (step S384). If the special symbol process timer has not timed out, the process is terminated.

  If the special symbol process timer has timed out, it is confirmed whether or not the jackpot flag is set (step S385). If the big hit flag is not set, the internal state (special symbol process flag) is updated to a value corresponding to step S300 (step S386).

  If the big hit flag is set, the CPU 56 notifies the player that the big win game is started to the big win port control timer that measures the time for controlling the opening / closing of the big win port ( The execution time of fanfare production (big hit display time) is set (step S387).

  Note that different jackpot display times may be set according to the jackpot type.

  Next, the CPU 56 performs control to transmit a fanfare command corresponding to the type of jackpot to the sound / lamp control microcomputer 100b (step S388). Thus, since the fanfare command corresponding to the type of jackpot is transmitted, the sound / lamp control microcomputer 100b and the symbol control microcomputer that receives commands from the sound / lamp control microcomputer 100b are configured. 100a can recognize the type of jackpot by the fanfare command. Therefore, it is possible to notify the player using a production device such as the variable display device 9 which pre-determined big winning opening is opened according to the type of jackpot. For example, when a big hit game is started, a character such as “left big prize opening (attacker) opens” is displayed on the screen of the variable display device 9 or an arrow indicating the big prize opening to be opened is displayed. Or

  Then, the CPU 56 performs display control of the special winning opening indicator lights 38 and 39 in accordance with the indicator lamp designated value (set value) set in the RAM 55 (step S389). Specifically, a RAM area (output port buffer) corresponding to the output state of the output port is provided, and in step S389, the CPU 56 displays the contents related to turning on / off the big prize opening indicator lamp in the RAM area of the output port. Set. Then, the contents set in the RAM area of the output port in the output setting process in step S34 are output to the output port. As a result, a drive command signal is output from the output port to the special winning opening indicator lamp, and display control of the special winning prize indicator lamp is executed. The player can know which of the two prize winning openings is opened depending on which of the prize winning indication lamps 38 and 39 is lit. In this embodiment, the display control of the big prize opening indicator lamp is performed until the big prize opening is released after the big hit symbol is stopped and displayed (see steps S408 and S412). Then, CPU 56 updates the internal state (special symbol process flag) to a value according to step S305 (step S390).

  It should be noted that the display control of the special winning opening indicator lights 38 and 39 is not limited to the case where the special symbol stop process is executed (started). For example, it may be configured to execute (start) in the pre-opening process for the big winning opening before the big winning opening is first opened.

  FIG. 68 is a flowchart showing the pre-opening process for the special winning opening in the special symbol process (step S305). In the big winning opening opening pre-processing, the CPU 56 decrements the value of the big winning opening control timer by 1 (step S401). Then, it is confirmed whether or not the value of the special winning opening control timer is 0 (step S402). If the value is not 0 (N in step S402), the process is terminated as it is. If the value of the big prize opening control timer is 0 (Y in step S402), it is determined whether or not the big hit is a two round big hit (step S403). Whether or not the jackpot is a two-round jackpot can be realized, for example, by setting a flag indicating the type of jackpot and confirming the flag when the jackpot type is determined. .

  If it is not a big hit of 2 rounds, that is, if it is a big hit of 7 rounds or a big hit of 15 rounds (N in step S403), the CPU 56 designates the display state corresponding to the number of rounds when the big prize opening is open (during the round). Control is performed to transmit the display command for winning a prize opening to the sound / lamp control microcomputer 100b (step S404). The number of rounds is recognized by checking the value of a round number counter that counts the number of rounds in the big hit game. Then, the CPU 56 drives the solenoid 241 or the solenoid 242 to control to open the special winning opening (opening / closing plate 201 or opening / closing plate 202) (step S405), and increments the value of the round number counter by 1 (step S406). . In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided, and in step S405, the CPU 56 determines the contents related to on / off of the solenoid in the RAM area of the output port. Set according to the open / close state of the solenoid to be driven. Then, the contents set in the RAM area of the output port in the output process of step S35 are output to the output port. As a result, a drive command signal is output from the output port to the output circuit 59. The output circuit 59 outputs a drive signal for driving the solenoid to the solenoid in accordance with the drive command signal to drive the solenoid. Hereinafter, in the process of opening and closing the solenoid, such an operation is performed.

  In addition, the maximum time (round time) that can be opened in each round is set in the big prize opening control timer (step S407). In addition, a control for turning off the special winning opening indicator lamp is executed (step S408).

  If it is a big hit of two rounds in step S403 (Y in step S403), the CPU 56 drives the solenoid 242 to open the second big winning opening (step S409) and increments the value of the round number counter by +1. (Step S410). Also, the round time is set in the special winning opening control timer (step S411). Unlike the round times for 15 rounds and 7 rounds, the round time for 2 rounds is an extremely short time, for example, 0.1 seconds. Therefore, in the case of a big hit of two rounds, it is unlikely that a game ball will win a big winning opening during the round. Further, control for turning off the special winning opening indicator lamp is executed (step S412).

  Then, the CPU 56 updates the internal state (special symbol process flag) to a value according to step S306 (step S413).

  FIG. 69 and FIG. 70 are flowcharts showing the special prize opening process during the special symbol process (step S306). In the special winning opening opening process, the CPU 56 first decrements the value of the special winning prize control timer by -1 (step S421). Then, it is confirmed whether or not the type of jackpot is a two-round jackpot (step S422).

  If it is two rounds big hit (Y of step S422), the CPU 56 checks whether or not the value of the big winning opening control timer is 0 (step S423), and the value of the big winning opening control timer is not zero. If so (N in step S423), the process is terminated as it is. When the value of the big prize opening control timer is 0 (Y in step S423), the solenoid 242 is driven to control to close the big prize opening (opening / closing plate 202) (step S424). Next, the CPU 56 checks whether or not the value of the round number counter is 2 (step S425).

  If the value of the round number counter is not 2 (N in step S425), the CPU 56 sets the time (interval time) from the end of the round to the start of the next round in the big prize opening control timer. (Step S429), and the value of the special symbol process flag is updated to a value corresponding to Step S305 (preliminary winning opening opening process) (Step S430). Note that the interval time for two rounds is an extremely short time, for example, 0.1 seconds.

  If the value of the round number counter is 2 (Y in step S425), the CPU 56 performs control to transmit a jackpot end designation command for designating the jackpot end to the sound / lamp control microcomputer 100b (step S426). ). Then, the execution time (big hit end time) of the effect (ending effect) for notifying the player of the end of the big hit is set in the big prize opening control timer (step S427), and the value of the special symbol process flag is set in step S307 (big hit end processing) ) Is updated to a value according to (step S428).

  If it is not a big hit for two rounds in step S422 (N in step S422), the CPU 56 checks whether or not the value of the big prize winning control timer is 0 (step S431). When the value of the big prize opening control timer is not 0 (N in step S431), it is confirmed whether or not the count switch 231 or the count switch 232 is turned on, thereby winning the game ball to the big prize opening. It is confirmed whether or not there has been (step S432). If the count switch 231 or the count switch 232 is not turned on (N in step S432), the processing is ended as it is. If the count switch 231 or the count switch 232 is on (Y in step S432), the CPU 56 increments the value of the winning number counter that counts the number of winning game balls to the big winning opening (step S433). Then, control is performed to transmit a count number designation command for designating the number of winning balls to the big winning opening during the round to the sound / lamp control microcomputer 100b (step S434). Next, the CPU 56 checks whether or not the value of the winning number counter is a predetermined number (for example, 10) (step S435). If the value of the winning number counter is not the predetermined number (N in step S435), the process is terminated as it is.

  When the value of the big prize opening control timer is 0 (Y in step S431), or when the value of the winning number counter is a predetermined number (Y in step S435), the CPU 56 selects the solenoid 241 or the solenoid. Control to close the special winning opening (opening / closing plate 201 or opening / closing plate 202) by driving 242 is performed (step S436). Then, the value of the winning number counter is cleared (set to 0) (step S437).

  Next, the CPU 56 checks whether or not it is a big hit of 15 rounds (step S438). If it is a big hit of 15 rounds, it checks whether or not the value of the round number counter is 15 (step S440). If it is not a big hit of 15 rounds, it is confirmed whether or not the value of the round number counter is 7 (step S439). When the value of the round number counter is not 15 in step S440 (N in step S440) and in the case where the value of the round number counter is not 7 in step S439 (N in step S439), the CPU 56 will open the round winning opening (round). After the completion of the operation, control is performed to transmit a display designation command to the sound / lamp control microcomputer 100b after the special winning opening is opened, which designates the display state according to the number of rounds (step S441). Then, the time (interval time) from the end of the round to the start of the next round (interval time) is set in the big winning opening control timer (step S442), and the value of the special symbol process flag is set to step S305 (opening the big winning opening. The value is updated according to (pre-processing) (step S443).

  When the value of the round number counter is 15 in step S440 (Y in step S440) and when the value of the round number counter is 7 in step S439 (Y in step S439), the CPU 56 transmits a jackpot end designation command. Control is performed (step S444), and the big hit end time is set in the big prize opening control timer (step S445). Then, the value of the special symbol process flag is updated to a value corresponding to step S307 (big hit end process) (step S446).

  FIG. 71 is a flowchart showing the jackpot end process (step S307) in the special symbol process. In the big hit end process, the CPU 56 first decrements the value of the big prize opening control timer by -1 (step S501). Then, it is confirmed whether or not the value of the special winning opening control timer is 0 (step S502). If the value of the big prize opening control timer is not 0 (N in step S502), the process is terminated.

  If the value of the big prize winning control timer is 0 (Y in step S502), it is confirmed whether or not the big hit is a probable big hit (step S503). If it is a probable big hit (Y in step S503), a probable change flag is set (step S504). If the flag has already been set, it is not necessary to set it. Further, the CPU 56 sets 100 times in the variation counter (step S505). Then, the big hit flag is reset (step S506), and the internal state (value of the special symbol process flag) is updated to a value corresponding to step S300 (special symbol normal process) (step S507).

  If it is not a probable big hit in step S503, it is confirmed whether or not it is a time-hit big hit (step S508). If it is a time-saving hit (Y in step S508), a time-saving flag is set (step S509). If the flag has already been set, it is not necessary to set it. Next, it is confirmed whether or not the probability variation flag is set (step S510). If the probability variation flag is set, the flag is reset (step S511). Thereafter, the processes in steps S505 to S507 described above are executed.

  If it is not a time and big hit in step S508, it means that the big hit is a normal big hit. At this time, the CPU 56 checks whether or not the probability variation flag is set (step S512). If the probability variation flag is set, the probability variation flag is reset (step S513), and the time reduction flag is set (step S514). Thereafter, the processes in steps S505 to S507 described above are executed.

  If the probability variation flag is not set, it is confirmed whether or not the time reduction flag is set (step S515). When the time reduction flag is set, the time reduction flag is reset (step S516). Thereafter, the processes of steps S506 and S507 described above are executed.

  In addition, you may make it perform the process of said step S503-S505, S508-S516 not in the big hit | end process, but in a special symbol stop process. Further, only the processing for ending a predetermined gaming state based on the occurrence of a predetermined type of jackpot, that is, the processing for resetting the flag in steps S511, S513, and S516 is executed in the special symbol stop processing. The process of shifting to a predetermined gaming state based on the occurrence of the type of jackpot, that is, the process of setting the flag in steps S504, S509, and S514, may be executed in the jackpot end process.

  Next, payout control signals and payout control commands transmitted and received between the main board 31 and the payout control board 37 will be described. FIG. 72 is an explanatory diagram showing an example of the content of a control signal output from the game control means to the payout control means. In this embodiment, a connection confirmation signal is transmitted and received as a control signal between the main board 31 and the payout control board 37 in order to perform various controls relating to payout control and the like. As shown in FIG. 72, the connection confirmation signal is output when the main board 31 rises (when the game control means starts the game control process), indicating that the main board 31 has risen with respect to the payout control board 37. This is a signal for notification (connection confirmation signal for the main board 31). The connection confirmation signal indicates that the winning ball can be paid out.

  Similarly to the game control microcomputer 560, the payout control microcomputer 370 includes a serial communication circuit 375. Various payout control commands are transmitted and received between the serial communication circuit 505 built in the game control microcomputer 560 and the serial communication circuit 375 built in the payout control microcomputer 370. The configuration and function of the serial communication circuit 375 built in the payout control microcomputer 370 are the same as the configuration and function of the serial communication circuit 505 built in the game control microcomputer 560.

  FIG. 73 is an explanatory diagram showing an example of the contents of control commands transmitted and received between the game control means and the payout control means. In this embodiment, various control commands are transmitted and received between the microcomputers of the main board 31 and the payout control board 37 in order to perform various controls relating to the payout control and the like.

  The award ball number command is a command that is output to designate the number of game balls (0 to 15) for which a payout request is made. In this embodiment, four prize balls are paid out when a game ball is detected by the start opening switch 14a, and seven prize balls are paid out when a game ball is detected by any one of the prize opening switches 29a and 30a. When a game ball is detected by the count switches 231, 232, 15 prize balls are paid out. Therefore, when a game ball is detected by the start port switch 14a, a prize ball number command “04” for notifying the number of prize balls of 4 is transmitted, and the game ball is detected by one of the prize port switches 29a and 30a. In the case where a winning ball number command “07” for notifying the number of winning balls is transmitted, and a game ball is detected by the count switches 231 and 232, a winning number for notifying 15 prize balls is transmitted. A ball number command “0F” is transmitted. The award ball number command may be composed of 2 bytes. In this case, for example, the CPU 56 first writes the lower 1 byte data of the prize ball number command to the transmission data register 710. When the transmission of the lower 1 byte data of the prize ball number command from the transmission shift register 712 is completed, the CPU 56 responds to the transmission interrupt request from the serial communication circuit 505, and the CPU 56 receives the upper 1 byte of the prize ball number command. Data is written to the transmission data register 710, and the upper byte data of the prize ball number command is transmitted from the transmission shift register 712.

  The prize ball ACK command “D2” is a command for notifying the game control means that the payout control means has received the prize ball number command. The prize ball ACK command corresponds to a reception confirmation signal indicating that a prize ball number command has been received.

  74 is a block diagram showing signal lines and the like used for transmission / reception of the control signal shown in FIG. 72 and the control command shown in FIG. 71. FIG. 74 also shows a power-off signal. As shown in FIG. 74, the connection confirmation signal is output by the game control microcomputer 560 via the output circuit 67 and input to the payout control microcomputer 370 via the input circuit 373A. The power-off signal is output via the output circuit 373B and input to the game control microcomputer 560 via the input circuit 68. The prize ball number command is output from the serial circuit 505 built in the game control microcomputer 560 and is input to the serial circuit 375 built in the payout control microcomputer 370. The award ACK command is output from the serial circuit 375 built in the payout control microcomputer 370 and input to the serial circuit 505 built in the game control microcomputer 560.

  Each of the connection confirmation signal and the power-off signal is 1-bit data and is transmitted through one signal line. Also, between the main board 31 and the payout control board 37, the signal line for the power-off signal to the game control microcomputer 560 and the signal line for the control signal (connection confirmation signal) related to the payout control are wired together. can do. Therefore, in the gaming machine, the wiring space related to the power-off signal to the gaming control microcomputer 560 can be saved.

  In this embodiment, the game control microcomputer 560 serially transmits a prize ball number command to the payout control microcomputer 370, and the payout control microcomputer 370 sends a prize ball ACK command to the game control microcomputer 560. Although the case of performing bidirectional communication for serial transmission will be described, the game control microcomputer 560 and the payout control microcomputer 370 may perform one-way serial communication. For example, the game control microcomputer 560 may perform one-way serial communication in which a prize ball number command is sent to the payout control microcomputer 370, and the payout control microcomputer 370 may not send a prize ball ACK command. .

  FIG. 75 is a timing chart showing an example of how to output a payout control signal and a payout control command. As shown in FIG. 75, when the winning detection switch detects a winning of a game ball, the game control means (game controlling microcomputer 560) pays out a winning ball number command corresponding to the number of winning balls paid out in accordance with the winning. This is transmitted to the control means (dispensing control microcomputer 370). Specifically, when the gaming control microcomputer 560 detects that a game ball has won a winning area provided in the gaming machine by a detection signal of the winning detection switch, the gaming control microcomputer 560 calculates a predetermined number of winning balls. It is added to the content of the total number of winning balls stored in the backup RAM. When the content of the total winning ball number storage buffer becomes a non-zero value, a winning ball number command corresponding to the number of winning balls paid out in accordance with winning is transmitted to the payout control microcomputer 370.

  In this embodiment, when a game ball is detected by the start port switch 14a, four prize balls are paid out, and when a game ball is detected by any one of the prize port switches 29a, 30a, seven prize balls are paid out. When a ball is paid out and a game ball is detected by the count switches 231, 232, 15 prize balls are paid out. Specifically, the game control microcomputer 560 determines that the number of prize balls is four when the number of prize balls is four according to the number of prize balls to be paid out. When the number of prize balls is 7, a prize ball number command “07” indicating that the number of prize balls is 7, and the number of prize balls is 15 when the number of prize balls is 15. A prize ball number command “0F” indicating 15 is transmitted.

  When the transmission of the award ball number command is completed, the serial communication circuit 505 of the game control microcomputer 560 makes a transmission interrupt request to the CPU 56 of the game control microcomputer 560, as shown in FIG. Due to the transmission interrupt request, the CPU 56 recognizes that the transmission of the award ball number command has been completed, and waits for a reception confirmation signal from the payout control microcomputer.

  When the payout control microcomputer 370 confirms reception of the prize ball number command, it stores the number of prize balls indicated in the received prize ball number command in the reception buffer of the payout control microcomputer 370. Also, the payout control microcomputer 370 adds the number of prize balls to a prize ball non-payout number counter provided in a predetermined area of the RAM. Then, the payout control microcomputer 370 transmits a prize ball ACK command “D2” to the game control microcomputer 560. Note that the payout control microcomputer 370 may store the number of prize balls in the reception counter in the interrupt process based on the reception interrupt request from the serial communication circuit 375 built in the payout control microcomputer 370. In this case, when the serial communication circuit 375 built in the payout control microcomputer 370 receives the prize ball number command, the serial communication circuit 375 makes an interrupt request during reception to the CPU of the payout control microcomputer 370. Then, the CPU of the payout control microcomputer 370 stores the prize ball number in the reception buffer by executing an interrupt process in response to an interrupt request from the serial communication circuit 375.

  When the prize ball ACK command is received and the prize data ACK command is stored in the reception data register 711, the serial communication circuit 505 of the game control microcomputer 560, as shown in FIG. A reception interrupt request is made to the CPU 56 of 560. The CPU 56 recognizes that the serial communication circuit 505 has received the data by executing the interrupt process by the interrupt request at the time of reception, and receives a prize ball ACK command from the reception data register 711 in the prize ball ACK wait process described later. Read.

  FIG. 76 is a flowchart showing an example of the prize ball processing in step S31. In the prize ball process, the game control microcomputer 560 executes a prize ball number addition process (step S1201) and a prize ball control process (step S1202). Then, the contents of the port 0 buffer formed in the RAM 55 are output to port 0 (step S1203). The contents of the port 0 buffer are updated in the prize ball control process.

  In the loop process from step S17 to step S19 in the main process, if there is an interrupt request from the serial communication circuit 505 during the interrupt enabled state, the CPU 56 of the game control microcomputer 560 causes the serial communication circuit 505 to generate an interrupt request. Execute interrupt processing according to the cause of the interrupt. FIG. 77 is a flowchart showing an example of interrupt processing performed by the serial communication circuit 505 in response to an interrupt request. FIG. 77A shows a communication error interrupt process executed by the CPU 56 when the serial communication circuit 505 makes an interrupt request with a communication error as an interrupt cause. FIG. 77 (b) shows a reception interrupt process executed by the CPU 56 when an interrupt request is issued with the serial communication circuit 505 receiving reception data as an interrupt cause. FIG. 77 (c) shows a transmission completion interrupt process executed by the CPU 56 when an interrupt request is issued with the interruption caused by the serial communication circuit 505 completing transmission of transmission data.

  The CPU 56 determines whether or not any interrupt process is preferentially executed. For example, the CPU 56 determines whether or not any interrupt process is preferentially executed. In this embodiment, the CPU 56 gives priority to an interrupt process that causes the occurrence of a communication error in the serial communication circuit 505 based on the fact that the communication error interrupt priority execution flag is set. And execute.

  When there is an interrupt request from the serial communication circuit 505, the CPU 56 checks each bit of the status register A 705 of the serial communication circuit 505 to identify the cause of the interrupt. In this case, the CPU 56 determines whether or not any interrupt process is preferentially executed. For example, the CPU 56 determines whether or not any interrupt process is preferentially executed. In this embodiment, the CPU 56 gives priority to an interrupt process that causes the occurrence of a communication error in the serial communication circuit 505 based on the fact that the communication error interrupt priority execution flag is set. And execute.

  The CPU 56 preferentially checks bit 0 to bit 3 of the status register A705 based on the fact that the communication error interrupt priority execution flag is set, and identifies the cause of the interrupt. That is, the CPU 56 determines whether another interrupt cause (reception of received data has been received) as to whether or not an interrupt request has occurred due to the occurrence of a communication error (overrun, noise error, framing error or parity error) in the serial communication circuit 505. Or, determination is performed with priority over transmission data transmission completion). If the CPU 56 determines that one or more of the bits 0 to 3 of the status register A 705 is “1”, the CPU 56 specifies that the cause of the interruption is that a communication error has occurred in the serial communication circuit 505. To do.

  If it is determined that the cause of the interruption is that a communication error has occurred in the serial communication circuit 505, the CPU 56 changes the communication error interrupt process shown in FIG. 77A to another interrupt process (FIG. 77B and FIG. 77). It is executed with priority over the interrupt processing shown in (c). In this case, the CPU 56 sets a communication error flag indicating that a communication error has occurred in the serial communication circuit 505 (step S41).

  When a communication error is detected, the CPU 56 transmits an effect control command (communication error display command) for designating the occurrence of communication error in order to notify the effect control means that a communication error has occurred in the serial communication circuit 505. Perform the process. When the CPU for sound / lamp control receives the communication error display command, the sound / lamp control CPU performs an effect using sound, display, light emitter, etc., and notifies that a communication error has occurred.

  Note that the CPU 56 may be configured to prohibit communication with the payout control microcomputer 370 mounted on the payout control board 37 in the communication error interrupt process of FIG. In this case, the CPU 56 controls the data transmission to the payout control microcomputer 370 mounted on the payout control board 37 by, for example, stopping the function of the transmission unit of the serial communication circuit 505. Further, the CPU 56 may be configured to perform a process of transmitting an effect control command (communication error display command) for designating a communication error occurrence display in the communication error interrupt process of FIG. 77 (a).

  If the cause of the interruption is not the occurrence of a communication error in the serial communication circuit 505, the CPU 56 checks bit 5 of the status register A. That is, the CPU 56 determines whether or not the cause of the interrupt is that the serial communication circuit 505 has received the received data. When determining that the bit 5 of the status register A is “1”, the CPU 56 specifies that the cause of the interruption is that the serial communication circuit 505 has received the reception data.

  If it is determined that the cause of the interruption is that the serial communication circuit 505 has received the received data, the CPU 56 executes a reception interrupt process shown in FIG. 77 (b). In this case, the CPU 56 sets a reception interrupt flag indicating that the serial communication circuit 505 is receiving reception data (step S42).

  In step S42, the CPU 56 may set a reception interrupt flag and read data from the reception data register 711 of the serial communication circuit 505. In this case, for example, the CPU 56 determines whether or not the read received data is a prize ball ACK command. If it is determined that the prize ball ACK command is received, the CPU 56 sets a prize ball ACK reception flag indicating that the prize ball ACK command has been received. Note that the CPU of the payout control microcomputer 370 also executes the same process as the reception interrupt process of FIG. 77 (b). In this case, when executing the reception interrupt process, the serial communication circuit 375 Data may be read from the reception data register. In this case, it is determined whether or not the read received data is a prize ball command. If it is determined that the received data is a prize ball command, a flag indicating that the prize ball command has been received is set.

  If the cause of the interrupt is not a communication error occurring in the serial communication circuit 505 or a reception interrupt, the CPU 56 checks bit 6 of the status register A. That is, the CPU 56 determines whether or not the cause of the interrupt is that the serial communication circuit 505 has completed transmission of transmission data. When determining that the bit 6 of the status register A is “1”, the CPU 56 specifies that the cause of the interruption is that the serial communication circuit 505 has completed transmission of transmission data.

  If it is determined that the interrupt cause is that the serial communication circuit 505 has completed transmission of transmission data, the CPU 56 executes a transmission completion interrupt process shown in FIG. In this case, the CPU 56 sets a transmission interrupt flag indicating that the serial communication circuit 505 has completed transmission of transmission data (step S43).

  By executing the processing described above, the CPU 56 of the game control microcomputer 560 identifies an interrupt cause when an interrupt request is received from the serial communication circuit 505, and a flag corresponding to the identified interrupt cause. (Communication error flag, reception interrupt flag or transmission interrupt flag) is set. When the flag is set according to the specified interrupt cause, the CPU 56 recognizes that a communication error has occurred in the serial communication circuit 505, that data has been received, or that data transmission has been completed.

  Note that the CPU mounted on the payout control microcomputer 370 also identifies the cause of the interrupt according to the same process as the process shown in FIG. 77 when an interrupt request is received from the serial communication circuit 375, and the identified interrupt cause. Set the flag according to.

  For example, consider a case where a prize ball number command is transmitted from the game control microcomputer 560 to the payout control microcomputer 370 by one-way communication. In this case, the game control microcomputer 560 is configured to generate a timer interrupt to the payout control microcomputer 370, for example, every 2 ms. After the prize ball number command is transmitted, the next interrupt process is performed. Assume that the award ball number command is transmitted again after 2 ms. The payout control microcomputer 370 is configured to generate a timer interrupt every 4 ms, for example, and can receive a prize ball number command every 4 ms. Then, even though the game control microcomputer 560 has not read the first prize ball number command transmitted, the payout control microcomputer 370 may receive the next prize ball number command. If the CPU of the payout control microcomputer 370 is set to receive the award ball number command in response to the interrupt request at the time of reception from the serial communication circuit 375, the award ball number command from the game control microcomputer 560 is surely received. Can be received.

  In the prize ball number adding process, a prize ball number table shown in FIG. 78 is used. The prize ball number table is set in the ROM 54. The number of processes (in this example, “4”) is set in the first address of the winning ball number table, and then the lower address of the switch-on buffer (the one corresponding to input port 0 of the 2-byte switch-on buffer) The switch input bit determination value and the number of winning balls for each switch of the winning opening that will pay out the winning ball by winning are sequentially set corresponding to each of the switches of the winning opening. The switch input bit determination value is a value corresponding to a bit to which the detection signal of each switch at the input port 0 is input. The upper address of the switch-on buffer is a fixed value (for example, 7F (H)). In the prize ball number table, the same data is set in each of the lower addresses of the four switch-on buffers. In this embodiment, the addresses of the ROM 54 and the RAM 55 are designated by 16 bits.

  FIG. 79 is a flowchart showing the prize ball number adding process. In the winning ball number adding process, the CPU 56 sets the start address of the winning ball number table in the pointer (step S1211). Then, the data at the address pointed to by the pointer (in this case, the number of processes) is loaded (step S1212). Next, the upper address (8 bits) of the switch-on buffer is set in the upper 1 byte of the 2-byte check pointer (step S1213).

  Then, the value of the pointer is incremented by 1 (step S1214), the prize ball number table data pointed to by the pointer (in this case, the lower address of the switch-on buffer) is set in the lower 1 byte of the check pointer (step S1215), The pointer value is incremented by 1 (step S1216). Next, the address data pointed to by the check pointer, that is, the contents of the switch-on buffer is loaded into the register (step S1217). ) And the logical product (step S1218). As a result, 7 bits other than the bit corresponding to the detection signal of the switch to be inspected become 0 in the register loaded with the contents of the switch-on buffer. Then, the pointer value is increased by 1 (step S1219).

  If the calculation result in step S1218 is 0, that is, if the detection signal of the switch to be inspected is on, the prize ball number table data pointed to by the pointer (in this case, the number of prize balls) is the prize ball addition value. (Steps S1220 and S1221), and the prize-ball addition value is added to the contents of the 16-bit total prize-ball number storage buffer formed in the RAM 55 (step S1222). If a carry occurs as a result of the addition, the content of the total number of winning balls storage buffer is set to 65535 (= FFFF (H)) (steps S1223 and 1224).

  In step S1225, the number of processes is reduced by 1. If the number of processes is 0, the process ends. If the number of processes is not 0, the process returns to step S1214 (step S1226). In step S1220, when it is confirmed that the calculation result in step S1218 is 0, that is, the detection signal of the switch to be inspected is in an OFF state, the process proceeds to step S1225.

  FIG. 80 is a flowchart showing the prize ball control process in step S1202. In the prize ball control process, after executing the prize ball abnormality detection process in step S1230, the CPU 56 executes any one of steps S1231 to S1235 according to the value of the prize ball process code.

  FIG. 81 is a flowchart showing a prize ball transmission waiting process (step S1231) executed when the value of the prize ball process code is zero. In the award ball transmission waiting process, the CPU 56 checks whether or not a communication error flag is set (step S1241). That is, the CPU 56 first checks whether or not a communication error has occurred in the serial communication circuit 505. When the communication error flag is set, the CPU 56 ends the process as it is. That is, since a communication error has occurred in the serial communication circuit 505, the CPU 56 controls to prohibit communication with the payout control microcomputer 370 mounted on the payout control board 37.

  If the communication error flag is not set, the CPU 56 confirms the contents of the total winning ball number storage buffer (step S1242). If the value is 0, the process ends. If not, the prize ball process code value is set to 1 (step S1243), and the process ends.

  FIG. 82 is a flowchart showing a prize ball number command transmission process (step S1232) executed when the value of the prize ball process code is 1. The CPU 56 checks whether or not a communication error flag is set in the prize ball transmission process (step S1251). That is, the CPU 56 first checks whether or not a communication error has occurred in the serial communication circuit 505. When the communication error flag is set, the CPU 56 prohibits communication with the payout control microcomputer 370 mounted on the payout control board 37 and ends the process as it is. That is, since a communication error has occurred in the serial communication circuit 505, the CPU 56 controls to prohibit communication with the payout control microcomputer 370. In this case, the CPU 56 controls the data transmission to the payout control microcomputer 370 mounted on the payout control board 37 by, for example, stopping the function of the transmission unit of the serial communication circuit 505. For example, the CPU 56 prohibits data transmission to the payout control microcomputer 370 by setting bit 3 of the control register B 708 of the serial communication circuit 505 to “0” and not using the transmission circuit. Note that, for example, the CPU 56 sets bit 3 of the control register B 708 to “0” in the communication error interrupt processing shown in FIG. 77A, and prohibits data transmission to the payout control microcomputer 370. Good. After data transmission to the payout control microcomputer 370 is prohibited, the communication error flag is cleared based on the operation of an error release switch (not shown) for releasing the error state, and the error state is reset. When the CPU 56 reads the value of the data register of the serial communication circuit 505, the communication error flag may be cleared and the error state may be automatically recovered.

  If the communication error flag is not set, the CPU 56 checks whether or not the content of the total prize ball number storage buffer is smaller than the prize ball command maximum value (“15” in this example) (step S1252). If the content of the total prize ball number storage buffer is equal to or greater than the prize ball command maximum value, the prize ball command maximum value is set in the prize ball number buffer (step S1253). If the content of the total prize ball number storage buffer is smaller than the maximum value of the prize ball command, the content of the total prize ball number storage buffer is set in the prize ball number buffer (step S1254).

  Thereafter, the CPU 56 writes the contents of the prize ball number buffer as a prize ball number command in the transmission data register 710 of the serial communication circuit 505 (step S1255), sets the value of the prize ball process code to 2 (step S1256), and performs processing. Exit. In this embodiment, the maximum value of the prize ball command is “15”. Therefore, a prize ball number command for designating the maximum number of payouts of “15” is written in the transmission data register 710. Thereafter, the award ball number command written in the transmission data register 710 is transferred to the transmission shift register 712 and transmitted from the transmission shift register 712 to the payout control microcomputer.

  FIG. 83 is a flowchart showing a prize ball transmission completion waiting process (step S1233) executed when the value of the prize ball process code is 2. In the award ball transmission completion waiting process, the CPU 56 checks whether or not a communication error flag is set (step S1261). That is, the CPU 56 first checks whether or not a communication error has occurred in the serial communication circuit 505. When the communication error flag is set, the CPU 56 ends the process as it is. That is, since a communication error has occurred in the serial communication circuit 505, the CPU 56 controls to prohibit communication with the payout control microcomputer 370 mounted on the payout control board 37.

  If the communication error flag is not set, the CPU 56 checks whether or not the transmission interrupt flag is set (step S1262). If the transmission interrupt flag is set, the CPU 56 proceeds to the process of step S1263. If the transmission interrupt flag is not set, the CPU 56 ends the process as it is. That is, the CPU 56 determines whether or not the serial communication circuit 505 has already completed transmission of the prize ball number command written in the transmission data register 710 in the prize ball number command transmission process, and has completed transmission of the prize ball number command. If this is confirmed, the process after step S1263 is performed.

  If the transmission interrupt flag is set, the CPU 56 resets the transmission interrupt flag (step S1263). Then, the CPU 56 subtracts the contents of the prize ball number buffer (the number of prize balls paid out to the payout control means) from the contents of the total prize ball number storage buffer (step S1264). Note that the game control microcomputer 560 may subtract the number of prize balls to be paid out from the contents of the total prize ball number storage buffer before writing the prize ball number command to the transmission data register 710 in step S1255.

  Further, the CPU 56 sets an ACK reception completion determination time value in the prize ball timer (step S1266). Then, the value of the prize ball process code is set to 3 (step S1267), and the process is terminated. The ACK reception completion determination time value is a time value for monitoring whether or not a prize ball ACK command is received from the payout control means.

  FIG. 84 is a flowchart showing a prize ACK waiting process (step S1234) executed when the value of the prize ball process code is 3. In the award ball ACK waiting process, the CPU 56 checks whether or not a communication error flag is set (step S1271). That is, the CPU 56 first checks whether or not a communication error has occurred in the serial communication circuit 505. When the communication error flag is set, the CPU 56 prohibits communication with the payout control microcomputer 370 mounted on the payout control board 37 and ends the process as it is. That is, since a communication error has occurred in the serial communication circuit 505, the CPU 56 controls to prohibit communication with the payout control microcomputer 370. In this case, the CPU 56 controls the reception of data from the payout control board 37 by prohibiting the function of the receiving unit of the serial communication circuit 505, for example. For example, the CPU 56 sets the bit 2 of the control register B 708 of the serial communication circuit 505 to “0” and sets the reception circuit not to be used, so that the payout control microcomputer 37 mounted on the payout control board 37 Data reception is prohibited. For example, the CPU 56 may set the bit 2 of the control register B 708 to “0” in the communication error interrupt process shown in FIG. 77A and prohibit data reception from the payout control microcomputer 370. Good. After data transmission to the payout control microcomputer 370 is prohibited, the communication error flag is cleared based on the operation of an error release switch (not shown) for releasing the error state, and the error state is reset. When the CPU 56 reads the value of the data register of the serial communication circuit 505, the communication error flag may be cleared and the error state may be automatically recovered.

  If the communication error flag is not set, the CPU 56 checks whether or not the reception interrupt flag is set (step S1272). That is, the CPU 56 checks whether or not the serial communication circuit 505 receives the received data and the received data register 711 stores the data. If the reception interrupt flag is set, the CPU 56 proceeds to the process of step S1273. On the other hand, if the reception interrupt flag is not set, the CPU 56 proceeds to the process of step S1275.

  If the reception interrupt flag is set, the CPU 56 reads data from the reception data register 711 of the serial communication circuit 505 (step S1273). Further, the CPU 56 determines whether or not the read data is a prize ball ACK command (whether or not it is a command “D2”) (step S1274).

  If the reception interrupt flag is set and the reception data has already been read from the reception data register 711 in the reception interruption process shown in FIG. 77 (b), the CPU 56 receives the prize ball in steps S1273 and S1274. It may be determined whether or not an ACK reception flag is set. When the prize ball ACK reception flag is set, the CPU 56 may determine that the prize ball ACK command has been received.

  If the reception interrupt flag is not set in step S1272, or if the data read in step S1274 is not a prize ball ACK command, the CPU 56 still receives a prize ball ACK command from the payout control microcomputer 370. Judge that it is not in the state. In this case, the CPU 56 decrements the value of the prize ball timer by 1 (step S1275), and ends the process if the value is not 0 (step S1276). When the value of the prize ball timer reaches 0, it is determined that the payout control microcomputer 370 has not transmitted the prize ball ACK command, a retransmission flag is set (step S1277), and the value of the prize ball process code is set to 4. (Step S1278), and the process ends. When the value of the prize ball process code becomes 4, the prize ball re-transmission process (step S1235) is executed. When the retransmission flag is set, a payout abnormality notification start command is transmitted to the sound / lamp control board 80b in the prize ball abnormality detection process (step S1230).

  In step S1274, when confirming that the data read from the reception data register 711 is a prize ball ACK command, the CPU 56 resets the reception interrupt flag (step S1279), and sets the value of the prize ball process code to 0. (Step S1280). If the retransmission flag is set because the communication is normally completed, the retransmission flag is reset (steps S1281 and S1282).

  Through the above processing, the game control means stores the total number of game balls as prize balls to be paid out based on the establishment of the payout condition in the total prize ball number storage buffer so as to be specified. The game control means also issues a payout command command (award ball number command) for designating a payout number of a predetermined number of prize balls to the payout control means based on the number of prize balls stored in the total prize ball number storage buffer. Send. Here, the predetermined number is 15 if the number of prize balls stored in the total prize ball number storage buffer is 15 or more, and is stored in the total prize ball number storage buffer if it is less than 15. The number of prize balls. Then, when a prize ball number command designating the prize ball payout is transmitted, a subtraction process is performed to subtract the payout number designated by the prize ball number command from the prize ball number stored in the total prize ball number storage buffer. Since the payout control microcomputer 370 transmits a prize ball ACK command immediately after receiving the prize ball number command, communication regarding the prize ball number command can be completed regardless of the prize ball payout from the ball payout device 97. The control microcomputer 560 can continuously transmit the next award ball number command before the payout of the number of payouts designated by the award ball number command is completed.

  In this embodiment, in order to store the total number of premium game media to be paid out based on the establishment of the payout conditions in an identifiable manner, the total prize ball number storage buffer for storing the total number itself is used as an example. The number of winnings in each winning area is stored, or the number of winnings for each winning area having the same number of winning balls (for example, winning mouth 14 corresponding to 4 winning balls, winning corresponding to 7 winning balls) A buffer or the like may be used that stores the number of winning prizes corresponding to the number of mouths 29 and 30 and 15 winning balls, and the number of winning balls that have not yet been paid out. In that case, a prize ball number command in which a number corresponding to the number of prize balls for each winning area is set is transmitted from the game control microcomputer 560 to the payout control microcomputer 370. In such a configuration, it may be configured to transmit from a payout command command with a large number of payouts. For example, in a state where four winnings at the big winning opening corresponding to 15 winning balls and one winning winning 29, 30 corresponding to 7 winning balls are generated, A payout command command for designating the number of payouts of individual prize balls is transmitted four times, and then a payout command command for designating the number of payouts of seven prize balls is transmitted. Further, instead of transmitting a winning ball number command indicating the number of winning balls, a game command microcomputer 560 transmits a payout command command indicating that there has been a winning or a winning number to the payout control microcomputer 370. It may be.

  FIG. 85 is a flowchart showing a prize ball re-transmission process (step S1235) executed when the value of the prize ball process code is 4. The CPU 56 checks whether or not the communication error flag is set in the winning ball re-transmission process (step S1291). That is, the CPU 56 first checks whether or not a communication error has occurred in the serial communication circuit 505. When the communication error flag is set, the CPU 56 prohibits communication with the payout control microcomputer 370 mounted on the payout control board 37 and ends the process as it is. That is, since a communication error has occurred in the serial communication circuit 505, the CPU 56 controls to prohibit communication with the payout control microcomputer 370. In this case, for example, the CPU 56 controls to prohibit data transmission to the payout control microcomputer 370 by stopping the function of the transmission unit of the serial communication circuit 505. For example, the CPU 56 prohibits data transmission to the payout control microcomputer 370 by setting bit 3 of the control register B 708 of the serial communication circuit 505 to “0” and not using the transmission circuit.

  If the communication error flag is not set, the CPU 56 rewrites the contents of the prize ball number buffer in the transmission data register 710 of the serial communication circuit 505 as a prize ball number command (step S1292). Further, the CPU 56 sets the ACK reception completion determination time value again in the prize ball timer (step S1293). Then, the value of the prize ball process code is set to 3 (step S1294), and the process ends.

  Since the value of the prize ball process code is set to 3, the prize ball ACK waiting process is executed again. In the award ball ACK waiting process to be executed again, if it is not detected that the award ball ACK command has been received again, specifically, if the award ball timer times out in step S1276, the award ball again A retransmission process is executed. As described above, when the game control microcomputer 560 cannot receive the winning ball ACK command as the reception confirmation signal indicating that the payout amount data has been received, the winning ball number command is received until the winning ball ACK command can be received. Repeat retransmissions.

  FIG. 86 is a flowchart showing the prize ball abnormality detection processing in step S230. In the prize ball abnormality detection process, when the CPU 56 detects that the retransmission flag has changed from the reset state to the set state, the CPU 56 uses the payout abnormality notification start command as an effect control command to the sound / lamp control board 80b (specifically, Is transmitted to the sound / lamp control microcomputer 100b (steps S1301 and S1302). Note that the CPU 56 does not transmit the payout abnormality notification start command after executing the prize ball retransmit processing, but executes the prize ball retransmit processing after transmitting the payout abnormality notification start command to the sound / lamp control board 80b. You may make it do.

  When transmitting the effect control command to the sound / lamp control microcomputer 100b, the CPU 56 pointers the address of a command transmission table (preliminarily set for each command in the ROM 54) according to the type of effect control command. Set to. Then, the address of the command transmission table corresponding to the effect control command is set in the pointer, and the effect control command is transmitted in the decorative symbol command control process (step S29).

  Further, the CPU 56 detects that the re-transmission flag is changed from the set state to the reset state (therefore, it is detected only when the reset state is first set when the set state continues). Then, control is performed to transmit a payout abnormality notification end command to the sound / lamp control board 80b (specifically, to the sound / lamp control microcomputer 100b) (steps S1303 and S1304).

  In this embodiment, when the retransmission flag is reset, the CPU 56 transmits a payout abnormality notification end command in step S1304, but may be configured not to transmit it. In this case, the burden on the game control microcomputer 560 is reduced. In that case, the sound / lamp control microcomputer 100b is configured to terminate the payout abnormality notification independently after a predetermined time, for example.

  Next, an operation in which the payout control microcomputer 370 transmits and receives various commands will be described. As shown in FIG. 74, the payout control microcomputer 370 includes a serial communication circuit 375 for serially communicating various commands with the game control microcomputer 560. The payout control microcomputer 370 uses the serial communication circuit 375 to receive a prize ball number command shown in FIG. 73 from the game control microcomputer 560. When the prize ball number command is received, the payout control microcomputer 370 uses the serial communication circuit 375 to transmit the prize ball ACK command “D2” shown in FIG. 73 as a reception confirmation signal.

  Similarly to the CPU 56 of the game control microcomputer 560, if the CPU of the payout control microcomputer 370 receives an interrupt request from the serial communication circuit 375 while it is in the interrupt enabled state, the serial communication circuit 375 Execute interrupt processing according to the cause of the interrupt. In this embodiment, when the CPU of the payout control microcomputer 370 specifies that the cause of the interruption is that the serial communication circuit 375 has received the received data, the reception interrupt is performed according to the same processing as in FIG. 77 (b). Execute the process. In this case, the CPU of the payout control microcomputer 370 sets a reception interrupt flag indicating that the serial communication circuit 375 is receiving reception data.

  FIG. 87 is a flowchart showing main control communication processing in which the CPU of the payout control microcomputer 370 communicates with the game control means (game control microcomputer 560) of the main board 31. In the main control communication process, the CPU of the payout control microcomputer 370 confirms whether or not the connection confirmation signal is on (step S541). Note that the connection confirmation signal being in the on state means that power is supplied and the game control means can control the progress of the game, and that the connection confirmation signal is in the off state means This means that the supply stop process is started and the game control means cannot progress the game (the connection confirmation signal is turned off by the output port clear process in the power supply stop process).

  The CPU of the payout control microcomputer 370 confirms whether or not the reception interrupt flag is set (step S542). That is, the CPU of the payout control microcomputer 370 confirms whether or not the serial communication circuit 375 receives the received data and the data is stored in the reception data register of the serial communication circuit 375.

  If the reception interrupt flag is set, the CPU of the payout control microcomputer 370 reads data from the reception data register of the serial communication circuit 375 (step S543). Further, the CPU of the payout control microcomputer 370 determines whether or not the read data is a prize ball number command (whether the command is “04”, “07” or “0F”). (Step S544).

  When it is confirmed that the data read from the reception data register of the serial communication circuit 375 is a prize ball number command, the CPU of the payout control microcomputer 370 resets the reception interrupt flag (step S545), and the prize ball The number of winning balls indicated by the number command is added to the winning ball unpaid number counter (step S546). Then, the CPU of the payout control microcomputer 370 writes the prize ball ACK command to the transmission data register 710 of the serial communication circuit 505 (step S547) and ends the process. Thereafter, the winning ball ACK command written in the transmission data register is transferred to the transmission shift register of the serial communication circuit 375 and is transmitted from the transmission shift register of the serial communication circuit 375 to the game control microcomputer 560.

  The CPU of the payout control microcomputer 370 executes a payout control process for driving and controlling the ball payout device 97 to pay out an unpaid number of prize balls stored in a prize ball unpaid-out number counter. Specifically, when it is confirmed that the value of the award ball unpaid number counter is not 0, the payout motor is driven to pay out the prize ball. The number of prize balls that are paid out is counted by a payout count switch. The payout motor is driven until payout processing is executed until all unpaid prize balls are paid out.

  Next, the operation of the sound / lamp control microcomputer 100b will be described. FIG. 88 is a flowchart showing main processing executed by the sound / lamp control microcomputer 100b. When power supply to the gaming machine is started and the reset signal becomes high level, the sound / lamp control microcomputer 100b starts main processing. In the main process, the sound / lamp control microcomputer 100b first performs an initialization process for clearing the RAM area, setting various initial values, initializing a timer for determining the activation control activation interval, and the like. This is performed (step S781). Thereafter, the sound / lamp control microcomputer 100b shifts to a loop process for monitoring the timer interrupt flag (step S782). When a timer interrupt occurs, the sound / lamp control microcomputer 100b sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the sound / lamp control microcomputer 100b clears the flag (step S783) and executes the following sound / lamp control process.

  A timer interrupt takes, for example, every 2 ms. That is, the sound / lamp control process is activated every 2 ms, for example. In this embodiment, only the flag is set in the timer interrupt process, and the specific sound / lamp control process is executed in the main process, but the sound / lamp control process is executed in the timer interrupt process. Also good.

  In the sound / lamp control process, the sound / lamp control microcomputer 100b first analyzes the received effect control command (command analysis process: step S784). Next, the sound / lamp control microcomputer 100b performs an effect content determination process (step S785). In the effect content determination process, the sound / lamp control microcomputer 100b uses the variable display device 9 based on the effect control command (variation pattern command or display result designation command) (whether or not to perform the notice effect). Kaya, the type of notice effect). In addition, the sound / lamp control microcomputer 100b generates an effect content designation command indicating the determined effect content.

  Next, the sound / lamp control microcomputer 100b performs sound output processing (step S786). In this case, the sound / lamp control microcomputer 100b outputs sound number data (for example, sound number data corresponding to the variation pattern indicated by the variation pattern command) to the speech synthesis IC 173. Then, the voice synthesis IC 173 generates a voice or a sound effect corresponding to the sound number data and outputs it to the amplifier circuit 175.

  Next, the sound / lamp control microcomputer 100b performs lamp display processing (step S787). In this case, the sound / lamp control microcomputer 100b performs lamp control based on the lamp control execution data set in the process data.

  The process data is composed of data obtained by collecting a plurality of combinations of process timer set values and presentation control execution data. The effect control execution data includes lamp control execution data and sound number data. In the lamp control execution data, data indicating the lamp display state during the symbol variation period is set. In addition, as the sound number data, data indicating output timings such as fluctuating sounds and sound effects during the symbol variation period is set. When the timing for switching the display state (for example, the timing at which a new character appears on the variable display device 9 or the timing at which the lamp is switched from the lit state to the unlit state) arrives during the symbol variation period, the effect control means The display state of the lamp and the sound output from the speaker 27 are controlled according to the next effect control execution data in the data. In the process timer set value, a time corresponding to the switching timing is set.

  The process data is stored in the ROM of the sound / lamp control board 80b. The process data is prepared for each of the symbol variation patterns. In this way, the sound / lamp control means controls the rendering device based on the program and process data stored in the ROM, and controls a plurality of rendering devices (speakers 27 and lamps in this embodiment). The related program is stored in the ROM mounted on the sound / lamp control board 80b. And ROM which stores those programs can be comprised as one ROM.

  Further, the sound / lamp control microcomputer 100b executes a process of updating the random number counter (step S788). Further, the sound / lamp control microcomputer 100b performs a process of sending the effect control command received from the main board 31 and the effect content designation command generated in the effect content determination process in step S785 to the symbol control board 80a ( Command control processing: Step S789). Thereafter, the process returns to the process of checking the timer interrupt flag in step S782.

  An INT signal for effect control from the main board 31 is input to an interrupt terminal of the sound / lamp control microcomputer 100b. For example, when the INT signal from the main board 31 is turned on, the sound / lamp control microcomputer 100b is interrupted. Then, the sound / lamp control microcomputer 100b executes an effect control command reception process in the interrupt process. In the effect control command reception process, the sound / lamp control microcomputer 100b stores the received effect control command data in the command reception buffer.

  In this embodiment, process data stored in the ROM of the sound / lamp control board 80b (hereinafter also referred to as sound / lamp control side process data) includes process timer set values, sound number data, and lamp control execution. The data includes a plurality of combinations of presentation control execution data including data. Further, the process data stored in the ROM of the symbol control board 80a (hereinafter also referred to as symbol control side process data) is a collection of a plurality of combinations of process timer setting values and presentation control execution data including only display control execution data. Consists of data.

  FIG. 89 is an explanatory diagram showing random numbers used in the sound / lamp control process. Each random number is used as follows.

(1) Random 1: Decide whether or not to execute the notice effect (for determining the notice effect execution). In this embodiment, when the variable display device 9 performs variable display of the decorative pattern in the reach mode, the sound / lamp control microcomputer 100b, for example, has a random 1 that matches a predetermined determination value. On the other hand, it is determined that a notice effect will be performed. Note that the sound / lamp control microcomputer 100b may determine whether or not to perform the notice effect using random 1 regardless of whether or not the variable display of the reach mode is performed.
(2) Random 2: When performing the notice effect, the type of the notice effect performed using the variable display device 9 is determined (for determining the notice effect type).

  FIG. 90 is a flowchart showing the effect content determination process (step S785) shown in FIG. In the effect content determination process, the sound / lamp control microcomputer 100b checks whether or not the variation pattern reception flag is set (step S1851). The fluctuation pattern reception flag is set when it is determined in the command analysis process (step S784) of the sound / lamp control main process that a fluctuation pattern command has been received.

  If the variation pattern reception flag is set, the sound / lamp control microcomputer 100b resets the variation pattern reception flag and identifies the variation pattern of the decorative design based on the received variation pattern command. Further, the sound / lamp control microcomputer 100b determines whether or not the variable display to be executed using the variable display device 9 is a variation accompanied by reach based on the identified variation pattern (step S1852). For example, in the sound / lamp control microcomputer 100b, when the variation pattern indicated in the received variation pattern command is a pattern with reach (for example, EXT data “01H” to “06H”, “08H” to “0DH”). The sound / lamp control microcomputer 100b determines that the variation is accompanied by reach. If the variation pattern reception flag is not set in step S1851, the sound / lamp control microcomputer 100b ends the process.

  If it is determined that the variation is accompanied by reach, the sound / lamp control microcomputer 100b determines whether or not to perform the notice effect based on the notice effect execution determination random number (random 1) (step S1853). For example, the sound / lamp control microcomputer 100b determines to perform a notice effect using the variable display device 9 when the random 1 matches the determination value. If NO in step S1852, the sound / lamp control microcomputer 100b ends the process.

  If it is determined in step S1854 that the notice effect is not performed, the sound / lamp control microcomputer 100b receives the variation pattern command and the display when the variation pattern command is received and the display result designation command is received. The result designation command is transferred to the symbol control microcomputer 100a, and the symbol control microcomputer 100a executes variable display of decorative symbols and game effects using the variable display device 9. In this case, if the sound / lamp control microcomputer 100b determines not to perform the notice effect in step S1854, the sound / lamp control microcomputer 100b generates a notification command for designating that the notice effect is not performed, and transmits it to the symbol control microcomputer 100a ( Step S1857).

  If it is decided to perform the notice effect (step S1854), the sound / lamp control microcomputer 100b uses the variable display device 9 to perform the kind of the notice effect that is performed based on the random number for determining the notice effect type (random 2). Is determined (step S1855). For example, the sound / lamp control microcomputer 100b can change the speed of the decorative symbol and the rotation direction of the decorative symbol in the notice effect based on the random 2, variable display device. 9 determines which character is to appear. If it is determined in step S1854 that the notice effect is not to be executed, the sound / lamp control microcomputer 100b executes the process of step S1857 and then ends the process.

  In this embodiment, a case will be described in which the effect content is determined by specifying whether or not the reach is based on the variation pattern command. However, the sound / lamp control microcomputer 100b uses the display result designation command as a display result designation command. The content of the production may be determined by specifying that it is a non-probable big hit or a probable big hit.

  Further, the sound / lamp control microcomputer 100b generates an effect content designation command indicating the determined effect content (whether or not to perform the notice effect and the type of the notice effect). Then, the sound / lamp control microcomputer 100b performs a process of transmitting the generated effect content designation command to the symbol control board 80a (step S1856). The sound / lamp control microcomputer 100b transfers (transmits) the display result designation command and the variation pattern command received from the game control microcomputer 560 to the symbol control board 80a together with the effect content designation command. Then, the symbol control microcomputer 100a of the symbol control board 80a can change the decorative symbol variable and game based on the effect content designation command, the display result designation command and the variation pattern command received from the sound / lamp control microcomputer 100b. Produce. In this case, the symbol control microcomputer 100a reads the display control execution data from the ROM based on the received effect content designation command, and uses the variable display device 9 for the VDP 109 based on the read display control execution data. To do.

  In step S1856, the sound / lamp control microcomputer 100b may add the determined effect content to the variation pattern command or the display result specification command instead of generating the effect content specifying command. For example, the sound / lamp control microcomputer 100b adds an effect content to a variation pattern command or a display result designation command by adding a value indicating the effect content to the header portion of the command. In this case, the sound / lamp control microcomputer 100b may add a value indicating the effect content to the header portion of only the variation pattern command. Then, the sound / lamp control microcomputer 100b may perform a process of transmitting the variation pattern command to which the effect content is added to the symbol control board 80a. Further, the sound / lamp control microcomputer 100b may add a value indicating the content of the effect to the header portion of only the display result command. Then, the sound / lamp control microcomputer 100b may perform a process of transmitting the display result command to which the contents of the effect are added to the symbol control board 80a. When the notice effect is not performed, the sound / lamp control microcomputer 100b directly transfers the variation pattern command or display result command received from the game control microcomputer 560 to the symbol control microcomputer 100a. Become.

  Further, in this embodiment, information indicating whether it is a big hit, whether it is a probable big hit, a fluctuation pattern, and presence / absence of a notice is added together in a fluctuation pattern command or a display result command, and the added command is a symbol control board. You may perform the process transmitted with respect to 80a. In this case, since only one command is required, the number of commands for the symbol control board 80a can be reduced.

  In this embodiment, the command for specifying the contents of the effect is performed by executing the command control process (see step S790) in the sound / lamp control main process based on the setting of the address of the transmission table in step S1856. Is transmitted to the symbol control board 80a.

  In addition, when adding the effect content determined in step S1856 to the variation pattern command or the display result designation command, the sound / lamp control microcomputer 100b adds the determined effect content (for example, the background color or the appearing character). A variation pattern command or a display result designation command may be transmitted to the symbol control microcomputer 100a. The symbol control microcomputer 100a reads display control execution data from the ROM based on the received variation pattern command and display result designation command, and produces an effect using the variable display device 9 based on the read display control execution data. You may go.

  Further, process data including both display control execution data and lamp control execution data may be stored in the ROM of the sound / lamp control board 80b. In this case, the sound / lamp control microcomputer 100b may extract display control execution data corresponding to the determined effect content from the ROM, and transmit the display control execution data to the symbol control microcomputer 100a together with the generated effect content designation command. . Then, the symbol control microcomputer 100a may produce an effect using the variable display device 9 based on the received display control execution data.

  When process data including both display control execution data and lamp control execution data is stored in the ROM of the sound / lamp control board 80b, the sound / lamp control microcomputer 100b responds to the determined contents of the effect. The display control execution data may be extracted from the ROM and transmitted to the symbol control microcomputer 100a. Then, the symbol control microcomputer 100a may produce an effect using the variable display device 9 based on the received display control execution data.

  As described above, in this embodiment, the sound / lamp control microcomputer 100b uniquely determines the contents of the effect (whether or not to perform the notice effect and the type of the notice effect) based on the change pattern command. decide. Further, the symbol control microcomputer 100a uses the variable display device 9 to execute a game effect according to the effect content determined by the sound / lamp control microcomputer 100b. Therefore, the game control microcomputer 560 does not have to determine the contents of the effects. Therefore, the processing load of the game control microcomputer 560 can be reduced.

  In this embodiment, the sound / lamp control microcomputer 100b may generate a decorative symbol change time designation command indicating the decorative symbol change time and transmit it to the symbol control board 80a. Further, upon receiving the effect content designation command, the symbol control microcomputer 100a on the symbol control board 80a causes the VDP 109 to execute the variable display of the decorative symbols on the variable display device 9 based on the received effect content designation command. Make a notice effect.

  In this embodiment, an effect control command from the main board 31 is first received by the sound / lamp control board 80b, and further, an effect control command and an effect content designation command are sent from the sound / lamp control board 80b to the symbol control board 80a. In the above description, the effect control command from the main board 31 may be first received by the symbol control board 80a.

  In the example shown in FIG. 90, when a variation pattern command is received, it is determined whether or not the variation is accompanied by reach. If the variation is accompanied by reach, the presence / absence of execution of the notice effect is determined. At the same time, processing for generating production content commands was performed. However, the present invention is not limited to such a configuration. For example, when a variation pattern command is received, it is determined whether the variation pattern is for big hit. Whether to execute or not may be determined, and processing for generating an effect content command may be performed. Even with such a configuration, the control burden of the game control microcomputer 560 can be reduced.

  Next, an image display example displayed on the variable display device 9 will be described. FIG. 91 is an explanatory diagram illustrating a display example in which the decorative design changes stepwise with gradation in the case of reach. As shown in FIG. 91 (a), when the left, middle and right decorative symbols are variably displayed on the variable display device 9, as shown in FIG. 91 (b), It is assumed that the left and right decorative symbols are in a reach state because they are stopped at “7”. The arrow in the screen of the variable display device 9 indicates that the decorative symbol is variably displayed.

  Thereafter, as shown in FIG. 91 (c), the decorative pattern inside is temporarily stopped at “7”. Then, as shown in FIGS. 91 (d) and 91 (e), the decorative pattern “7” in the middle gradually disappears from the left to the right. Specifically, the decorative pattern “7” is divided into a left area, a middle area, and a right area, and the color of the left area is first erased and then the color of the middle area is erased. Is thinner. In this embodiment, “the color becomes light” indicates that the ratio of the number of pixels (the number of pixels and the number of dots) displaying a predetermined color in the region is reduced. For example, pixels in which colors are displayed at predetermined intervals (for example, every other pixel) from a state in which all of the pixels in the region aligned vertically and horizontally display colors (A state in which pixels displaying colors are thinned out at a predetermined interval).

  Then, as shown in FIGS. 91 (f), (g), and (h), the decorative pattern “7” in the middle gradually disappears, and “8” that is the decorative pattern next to the decorative pattern “7” is displayed. Displayed in stages from left to right. Specifically, when the color of the right region of “7” becomes light, the color of the left region of “8” is displayed lightly, and when the color of the right region of “7” is erased, “8” The color of the middle region is displayed lightly (slightly darker) and the color of the left region of “8” is displayed darker. When the color of the right area “8” is displayed light, the colors of the middle area and the left area “8” are displayed dark. In this way, the decorative pattern “8” is gradually darkened in the direction from the left side. In this embodiment, “the color becomes darker” indicates that the ratio of the number of pixels displaying a predetermined color in the region is increased. For example, pixels that do not display color from a state where all of the pixels in the region aligned vertically and horizontally do not display color, pixels that display color at a predetermined interval (for example, every other pixel) This indicates that the state has been switched to.

  Next, as in the case of the decorative pattern “7” (FIGS. 91 (d) and (e)), the decorative pattern “8” gradually disappears from the left to the right (FIGS. 91 (i) and (j)). . Then, as shown in FIG. 91 (k), when the color of the right region “8” becomes light, the color of the left region “7” is displayed lightly. Thereafter, the variable display of the decorative pattern with gradation (gradual change in color shading) as shown in FIGS. 91D to 91K is repeatedly performed, and the end timing of the variable display (variation) is reached. In addition, "7" or "8" is stopped and displayed (derived display) as the decorative pattern inside.

  The variable display mode with gradation at the time of reach shown in FIG. 91 is called gradation reach. The gradation reach may be reach A, reach B, or reach C shown in FIG.

  As described above, the display image of the decorative pattern “7” in the middle is erased or displayed stepwise from the left to the right, and the decorative image “8” in the middle is gradually changed from the left to the right (gradually). Since the display image of the decorative design can be changed stepwise by adding gradation, the player can select which decorative design (“7” or “8” in the reach state). It becomes difficult to understand whether or not “)” is stopped, and the effect of variably displaying decorative symbols in the reach state can be improved.

  In the example shown in FIG. 91, the area in which the color density of the decorative design changes is divided into three areas, the left area, the middle area, and the right area. However, the area is divided into two or more areas. It may be divided. Further, although the darkness level, the light color, and the absence of color are set as the level (level) of the color density, it may be divided into more stages. As the number of divided areas increases and the number of color darkness stages increases, the decorative design changes smoothly.

  In addition, although the example in which two decorative symbols (“7” and “8”) are alternately displayed with gradation is shown, three or more decorative symbols (for example, “6”, “7”, “8”) are shown. May be displayed with gradation in order. In addition, the decorative symbols are digested and displayed stepwise from the left to the right, but may be erased and displayed stepwise from the right to the left.

  Further, the timing at which one decorative symbol disappears and the timing at which the other decorative symbol is displayed are not limited to the example shown in FIG. For example, in the example of FIG. 91, when the color of the left region of “7” is erased (FIG. 91 (e)) and then the color of the middle region of “7” is erased, the left region of “8” Is displayed lightly (FIG. 91 (f)), but when the color of the left region of “7” is erased, the color of the left region of “8” may be displayed lightly. .

  In addition, the colors of decorative symbols (for example, “7” and “8”) displayed before and after may be the same color. However, if the front and back decorative designs have the same color, changes in the decorative designs may be difficult to understand. For this reason, it is preferable that the color of the decorative design is different. For example, if “7” is made red and “8” is made blue, it becomes easy to understand that the display is changing to a different pattern during the display with gradation. As a result, it is possible to improve the player's sense of expectation during the reach.

  FIG. 92 is an explanatory diagram showing a modified display example in which the decorative design changes stepwise with gradation. In the display example shown in FIG. 91, the size of the decorative design did not change, but in the display example shown in FIG. 92, when the decorative design “7” is erased step by step, the decorative design “7” As the decorative pattern “8” is displayed in stages, the decorative pattern “8” gradually increases in stages (gradually). Such an image display can also improve the production effect and enhance the player's sense of expectation for the big hit.

  In the example shown in FIG. 92, the number of areas where the color density changes in the decorative design is subdivided, and the color density is changed in multiple stages so that the color changes smoothly. Also good. In addition, the colors of the decorative patterns before and after being displayed may be the same color or different colors. Further, the direction in which the color changes is not limited to the direction from the left side to the right side, but may be the direction from the right side to the left side. Also, the timing at which the decorative symbols are erased step by step and the timing at which they are displayed are not limited to the timing shown in FIG.

  FIG. 93 is an explanatory diagram showing another modified display example in which the decorative design changes stepwise with gradation. FIG. 93 shows the following modified display example. This is a modified display example (vertical direction) in which the decorative design “7” disappears stepwise from the upper side in a downward direction and the decorative design “8” is displayed stepwise from the upper side in a downward direction. Further, this is a modified display example (concentric circle) in which the decorative pattern “7” disappears stepwise from the center in a concentric direction and the decorative pattern “8” is displayed stepwise from the center in a concentric direction. In addition, the decorative pattern “7” disappears in stages as the line from the center rotates clockwise, and the decorative pattern “8” is displayed in stages as the line from the center rotates clockwise. This is a modified display example (rotation direction).

  Note that, in the modified display example in the vertical direction shown in FIG. 93, the color changes from the upper side to the lower side, but the color may change from the lower side to the upper direction. In the concentric deformation display example, the color changes from the center to the outer side in the concentric direction, but the color may change from the outer side to the center. Further, in the modified display example in the rotation direction, the color changes clockwise, but the color may change counterclockwise.

  Further, the enlarged / reduced modified display example (FIG. 92) and the modified display example in the vertical direction, concentric circle shape, or rotational direction (FIG. 93) may be displayed in combination. Further, the number of areas in which the color density of the decorative design changes may be finely divided, and the color density may be changed in multiple stages so that the color changes smoothly. In addition, the colors of the decorative patterns before and after being displayed may be the same color or different colors. Also, the timing at which the decorative symbols are erased step by step and the timing at which they are displayed are not limited to the timing shown in FIG.

  FIG. 94 is an explanatory diagram showing an example of an image display of a notice effect. In this embodiment, a notice effect for notifying the player that a specific effect that is likely to be a big hit or a big hit is likely to be executed is executed at a predetermined timing during variable display of decorative symbols.

  As shown in FIG. 94, when it is time to execute the notice effect, the characters “button repeated!” Are displayed on the screen of the variable display device 9 to prompt the player to repeatedly hit the chance button 300. At this time, the image of the human character, which is a preview image, can be displayed on the screen of the variable display device 9. However, the character image is not actually displayed on the screen until the chance button 300 is pressed.

  If the chance button 300 is not pressed by the player, the image of the human character is not displayed on the screen as it is. On the other hand, when the chance button 300 is pressed by the player, the character image of the person on the screen is displayed step by step each time the chance button 300 is pressed. That is, the color of the image of the person character becomes darker in steps. Specifically, the ratio of the number of pixels displaying a predetermined color in the character image area increases.

  In this way, before the chance button 300 is pressed, the notice character image is not displayed, and every time the chance button 300 is pressed, the notice character image is displayed step by step. It is possible to improve the production effect of the notice effect. As will be described later, such a cut-in display of a preview image can be realized without requiring complicated control.

  The notice image is not limited to a human character image, and may be an animal character or the like. The period during which the button can be repeatedly hit is determined in advance. Further, in the above example, when the chance button 300 is repeatedly hit, the notice image is displayed in a stepwise manner, but when the chance button 300 is pressed once, the notice button is displayed. The image may be displayed so as to become darker in stages. In this case, the character prompting the operation of the chance button 300 displayed on the screen is displayed, for example, “Press the chance button!”.

  Next, the operation of the symbol control microcomputer 100a will be described. FIG. 95 is a flowchart showing main processing executed by the symbol control CPU 101a of the symbol control microcomputer 100a. When power supply to the gaming machine is started and the reset signal becomes high level, the symbol control CPU 101a starts main processing. In the main process, the symbol control CPU 101a first performs an initialization process for clearing the RAM area, setting various initial values, initializing a timer for determining the start interval of effect control, and the like (step S771). ).

  Subsequently, the symbol control CPU 101a executes a storage area setting command process for issuing a command for setting the storage area (storage area) in the VRAM 84 to the fixed address area 155A and the automatic transfer area 155B as shown in FIG. (Step S772). The contents of the storage area setting command process will be described later (see FIG. 96).

  After executing the storage area setting command processing, the symbol control CPU 101a temporarily stores the image data set so as to increase the display frequency in the variable display device 9 in the storage area which becomes the fixed address area 155A of the VRAM 84. The pre-transfer command process for performing the command is executed (step S773).

  In the advance transfer command process, the symbol control CPU 101a instructs the VDP 109 to transfer image data of frequently used component images from the CGROM 83 to the VRAM 84. The image data transfer instruction designates an address in the CGROM 83 where the image data to be transferred is stored and an address (fixed address) of an area (fixed address area 155A shown in FIG. 100) where the image in the VRAM 84 is developed in advance. Is done. The VDP 109 reads out image data from a predetermined address in the CGROM 83 based on a transfer instruction from the symbol control CPU 101a, and executes processing for transferring the read image data to a predetermined address in the fixed address area 155A in the VRAM 84.

  The part image is a group of images such as an image of a character displayed on a part of the display screen and an image of identification information (decorative pattern). Component images include still images that are used mainly when displaying background images, sprite images that are used when displaying moving images in a simple manner, such as characters appearing or changing, and mainly live-action images. A movie image used when displaying a realistic moving image by a multicolor image typified by an image is included. Examples of frequently used component images include background images, decorative design images, and frequently used notice images.

  In this way, when power supply to the gaming machine is started, if image data of frequently used component images is transferred from the CGROM 83 to the VRAM 84 in advance, the CGROM 83 to the VRAM 84 are displayed when displaying frequently used component images. Therefore, the control load for display control of the variable display device 9 can be reduced. The detailed contents of the advance transfer command process will be described later (see FIG. 97).

  Thereafter, the symbol control microcomputer 100a shifts to a loop process for checking the timer interrupt flag (step S774). When a timer interrupt occurs, the symbol control microcomputer 100a sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the symbol controlling microcomputer 100a clears the flag (step S775) and executes the following effect control process.

  A timer interrupt takes, for example, every 2 ms. That is, the effect control process is activated, for example, every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the specific effect control process is executed in the main process, but the effect control process may be executed in the timer interrupt process.

  As will be described later, when the display screen of the variable display device 9 is switched every 33.3 ms, the symbol control microcomputer 100a creates data instructing the image development on the VDP 109 by the display update command processing. If the process (step S1841) does not need to be executed frequently, the timer interrupt may be set to take every 33.3 ms, for example.

  In the effect control process, the symbol control microcomputer 100a first analyzes the received effect control command (command analysis process: step S776). Next, the symbol control microcomputer 100a performs an effect control process (step S777). In the effect control process, a process corresponding to the current control state (effect control process flag) is selected from the processes corresponding to the control state, and display control of the variable display device 9 is executed. Further, a process for updating the random number counter is executed (step S778). Thereafter, the process returns to the process of checking the timer interrupt flag in step S774.

  The INT signal from the sound / lamp control board 80b is input to the interrupt terminal of the symbol control microcomputer 100a. For example, when the INT signal from the sound / lamp control board 80b is turned on, the symbol control microcomputer 100a is interrupted. Then, the symbol controlling microcomputer 100a executes a receiving process of the effect control command and the effect content command in the interrupt process. In the command reception process, the symbol control microcomputer 100a stores the received command data in the command reception buffer.

  FIG. 96 is a flowchart showing an example of the storage area setting command process executed in step S772. In the storage area setting command processing, the symbol control CPU 101a sends STADD setting data and ENADD setting data from the ROM 132 as data for setting a storage area to be the automatic transfer area 155B as shown in FIG. Read (steps S161 and S162). Then, based on the setting data read out in steps S161 and S162, a display control command serving as a storage area setting command is created and transmitted to the VDP 109 (step S163).

  In this embodiment, as shown in FIG. 100, the VRAM 84 is divided into a frame buffer 156, a temporary expansion area 155C, a fixed address area 155A, and an automatic transfer area 155B, but the frame buffer 156 and the temporary expansion area 155C are It is assumed that a predetermined fixed area in the VRAM 84 is set. Therefore, in the storage area setting command process, in the areas other than the frame buffer 156 and the temporary expansion area 155C in the VRAM 84, the setting of the start address and the end address of the automatic transfer area 155B is instructed, and the automatic transfer area 155B is set to the VDP 109. Let it be done. As a result, the automatic transfer area 155B and the fixed address area 155A are set. It is assumed that the frame buffer 156 and the temporary expansion area 155C are not set in the VRAM 84 in advance, and the symbol control CPU 101a determines the head address of each area (for example, the temporary expansion area 155C, the fixed address area 155A, and the automatic transfer area 155B). It may be configured to instruct the setting of the end address and cause the VDP 109 to set each area.

  FIG. 97 is a flowchart showing an example of the advance transfer command process executed in step S773 and the like. In the pre-transfer command process, the symbol control CPU 101a first sets a pre-transfer setting table corresponding to the effect mode flag (step S171).

  The effect mode flag is a flag indicating which effect mode of the plurality of effect modes is the current effect mode. Some gaming machines can change the background or sound displayed on the screen of the variable display device 9 at a predetermined timing. For example, a game in which a spring mode in which cherry blossom petals are dancing, a summer mode in which the sun is shining, an autumn mode in which autumn leaves are flying, and a winter mode in which snow falls are switched at a predetermined timing. Machine. Such spring mode, summer mode, autumn mode, and winter mode are referred to as production modes. In this embodiment, when a predetermined change condition is satisfied, the effect mode is changed (switched) (see steps S1864 and S1865 described later).

  The advance transfer setting table displays image data indicating a component image set so as to increase the display frequency on the variable display device 9 among a plurality of types of image data, and the component image is displayed on the screen of the variable display device 9. It is a table used for instructing to transfer from the CGROM 83 to the VRAM 84 in advance prior to being displayed. In this embodiment, the advance transfer setting table is composed of, for example, 3N + 1 (N is an arbitrary natural number) table data, and the table data read from the advance transfer setting table is a count value in the advance transfer counter. Determined by the pre-transfer count value.

  In the advance transfer setting table, as table data for specifying image data to be transferred from the CGROM 83 to the VRAM 84 in advance, the number of processes, read addresses # 1 to #N, write addresses # 1 to #N, image data Data indicating the quantities # 1 to #N and the like are stored. Here, the frequency with which each component image is displayed on the screen of the variable display device 9 varies depending on the aspect of the effect operation in the pachinko gaming machine 1. For example, as a background image, cherry blossom petals are used in the spring mode, the sun is used in the summer mode, autumn leaves are used in the autumn mode, and snow is used in the winter mode. Further, for example, as the image of the identification information (decorative pattern), an image with a number “1” to “9” is used in the spring mode or the autumn mode, and “A” to “I” in the summer mode or the winter mode. The image of the alphabet design is used. Therefore, even if the image data of the component image set to increase the display frequency in the spring mode is temporarily stored in the VRAM 84 even though the effect mode is set to the summer mode, these images are displayed. There is no opportunity for data to be used, and the usage efficiency of the VRAM 84 decreases. Therefore, in this embodiment, a plurality of advance transfer setting tables corresponding to the production mode are prepared in advance, and image data indicating component images set so as to increase the display frequency corresponding to the aspect of the production operation is provided. The data is transferred from the CGROM 83 to the VRAM 84 in advance.

  The effect mode flag is provided in the RAM of the symbol controlling microcomputer 100a. The advance transfer setting table is provided in the ROM of the symbol control microcomputer 100a. For example, when the value of the effect mode flag is “0”, a pre-transfer command is transmitted to the VDP 109 with a pre-transfer setting table corresponding to the effect mode of the pachinko gaming machine 1 being the spring mode. Decide which table to use. Further, when the value of the effect mode flag is “1”, a pre-transfer command is transmitted to the VDP 109 with a pre-transfer setting table corresponding to the effect mode of the pachinko gaming machine 1 being the summer mode. Decide which table to use.

  Subsequently, the symbol control CPU 101a clears the pre-transfer counter provided in the RAM, and initializes the pre-transfer count value, which is the count value, to “0” (step S172). Then, the number of processes is set by reading the table data of the advance transfer setting table corresponding to the advance transfer count value being “0” (step S173).

  Thereafter, the symbol control CPU 101a updates the advance transfer count value, for example, by adding 1 (step S174). Then, the reading address indicating the reading position of the image data in the CGROM 83 is specified by reading the table data of the pre-transfer setting table corresponding to the pre-transfer count value updated in step S174 (step S175).

  Further, the symbol control CPU 101a updates the advance transfer count value, for example, by adding 1 or the like (step S176), and reads the table data of the advance transfer setting table corresponding to the updated count value. A write address indicating a write position where image data is temporarily stored in the storage area serving as the fixed address area 155A is specified (step S177).

  Further, the symbol control CPU 101a updates the pre-transfer count value by adding, for example, 1 (step S178), and reads the transfer data by reading the table data of the pre-transfer setting table corresponding to the updated count value. The amount is specified (step S179). Based on the read address, write address, and transfer data amount thus specified, the symbol control CPU 101a creates a pre-transfer command and transmits it to the VDP 109 (step S180). At this time, the number of processes is updated, for example, by subtracting 1 (step S181).

  Subsequently, it is determined whether or not the number of processes updated in step S181 has reached a predetermined end determination value (eg, “0”) (step S182). At this time, if the number of processes does not reach the end determination value (N in step S182), the process returns to step S174. On the other hand, if the number of processes reaches the end determination value (Y in step S182), the pre-transfer counter is cleared, the count value is initialized to “0” (step S183), and the pre-transfer command process Exit.

  FIG. 98 is a flowchart showing a specific example of command analysis processing (step S776). The effect control command and the effect content command received from the sound / lamp control board 80b are stored in the reception command buffer, but in the command analysis process, the symbol control microcomputer 100a receives the command stored in the command reception buffer. checking the content.

  In the command analysis process, the symbol control microcomputer 100a first checks whether or not a reception command is stored in the command reception buffer (step S7611). Whether it is stored or not is determined by comparing the value of the command reception number counter with the read pointer. The case where both match is the case where the received command is not stored. If the received command is stored in the command receiving buffer, the symbol controlling microcomputer 100a reads the received command from the command receiving buffer (step S7612). When read, the value of the read pointer is incremented by 1 (step S7613).

  If the received effect control command or the like is an effect control command for designating a variation pattern (step S7614), the symbol controlling microcomputer 100a stores the EXT data of the command in the variation pattern data storage area (step S7615). In this case, the symbol controlling microcomputer 100a sets a variation pattern reception flag indicating that the variation pattern command has been received (step S7616). Then, the gaming state is determined based on the variation pattern command (step S7617). Specifically, as shown in FIG. 61, the variation pattern is distinguished from the variation pattern in the normal gaming state and the high probability latent state, and the variation pattern in the probability variation state and the short time state. Therefore, the symbol controlling microcomputer 100a can determine whether the gaming state is the normal gaming state / high probability latent state or the probability variation state / short time state based on the EXT data of the variation pattern command. When it is necessary to change the content (mode) of the game effect according to the determination result of the game state performed in step S7617, the symbol control microcomputer 100a stores the data indicating the game state in a predetermined storage area. While memorizing, the contents of the game effect are changed (step S7618). For example, when the change pattern in the normal game state / high probability latent state is switched to the change pattern in the probability change state / short time state, the game effect is changed from the normal game effect to the special game effect.

  Note that the processing of steps S7614 to S7618 is also executed in command analysis processing executed by the sound / lamp control microcomputer 100b.

  If the effect control command or the like confirmed to be received in step S7611 is an effect control command for designating the display result (step S7619), the symbol controlling microcomputer 100a displays the EXT data of the command as the display result ( It is stored in the display result storage area as a special symbol display result (step S7620). Next, a stop symbol of a decorative symbol (left middle right symbol) corresponding to the display result specified by the display result specifying command is determined and stored in the decorative symbol storage area (step S7621). The decorative symbol stop symbol is determined based on a decorative symbol determining random number. In addition, it is confirmed whether or not the variation pattern specified by the variation pattern command is a variation pattern with reach, and in the case of a variation pattern with reach, a reach symbol (for example, left and right ornaments) Designs having the same design but different decorative designs are determined.

  If the received command read in step S7612 is another effect control command, the symbol control microcomputer 100a sets a command reception flag corresponding to the received command, and stores the received command if necessary (step S7622).

  For example, if the received command is a recovery command (a normal display command, a special display command, or a high probability latent display command), data (for example, a flag) indicating a gaming state corresponding to the recovery command is stored. Such processing is also executed in command analysis processing executed by the sound / lamp control microcomputer 100b.

  FIG. 99 is an explanatory diagram showing an example of a register built in the VDP 109. The register shown in FIG. 99 is provided in the drawing control unit 91. The symbol control CPU 101a can write data to the register by transmitting a command to the VDP 109 via the CPU I / F 92 and the CG bus.

  In the example shown in FIG. 99, the execution instruction register instructs the drawing control unit 91 to execute drawing on the VRAM 84 (instruction to expand source data such as characters set outside the drawing area of the VRAM 84 in the drawing area), data transfer To set instructions (instructions for transferring source data such as characters from the CGROM 83 to the outside of the drawing area of the VRAM 84) and decoding execution instructions (instructions for decoding the encoded movie data stored in the CGROM 83) Used. For example, 3 bits of the 8-bit execution instruction register are assigned to a drawing execution instruction, a data transfer instruction, and a decoding execution instruction, and when any of the bits becomes “1”, the drawing control unit 91 or the video decompression unit 89 performs the indicated operation.

  The drawing horizontal coordinate register and the drawing vertical coordinate register are used by the symbol control CPU 101a to specify the upper left horizontal coordinate (X coordinate) and vertical coordinate (Y coordinate) of the drawing area in the VRAM 84. The horizontal size register and the vertical size register are used for designating the horizontal and vertical sizes of the drawing area.

  The alpha value register is used to specify the alpha value (α value) of each pixel constituting the component image. As will be described later, the alpha value is information indicating the transparency of each pixel in the image data (see FIGS. 115 and 116). The test value register is used to specify a test value (also referred to as an alpha reference value) to be compared with the alpha value in an alpha test process (see step S1009 in FIG. 121, FIG. 124B) described later.

  The CGROM address register is used for designating the start address of the storage area in the CGROM 83 for data such as characters transferred outside the drawing area of the VRAM 84.

  The VRAM horizontal coordinate register and the VRAM vertical coordinate register are used to specify the horizontal coordinate and the vertical coordinate (address of the fixed address area 155A in the VRAM 84) of the storage area in the VRAM 84 of the source data such as the character transferred from the CGROM 83. The VRAM horizontal size register and VRAM vertical size register are used to specify the horizontal size and vertical size of the storage area in the VRAM 84 of source data such as characters transferred from the CGROM 83.

  The video data transfer mode register is used for designating how the video data transferred from the CGROM 83 is expanded outside the drawing area of the VRAM 84 after being decoded. As the video data transfer mode, for example, a mode in which all frame images in a stream (a collection of frame images constituting a series of moving images) are developed in the VRAM 84, or a predetermined number (for example, three or four) of the streams are used. There is a mode in which the frame image is developed on the VRAM 84.

  The display ON / OFF register is used for designating ON / OFF of display. When the set value of the display ON / OFF register is turned on, the drawing control unit 91 outputs the image signal based on the image data developed in the display area in the VRAM 84 to the variable display device 9. To instruct. The display area register is a register for designating which of the two display areas reserved in the VRAM 84 is to output the image signal based on the image data to the variable display device 9. The symbol control CPU 101a sets data indicating one of the display areas in the display area register so that an image signal based on the current display area (at that time, the image data in the current display area is sent to the variable display device 9). It is possible to determine which display area is the current display area according to the contents of the display area register.

  Although not shown in FIG. 99, there is also provided a register for designating the start address and the end address of the automatic transfer area 155B set in the storage area setting designation process (step S772).

  FIG. 100 is an explanatory diagram showing an example of an address map in the VRAM. As shown in FIG. 100, in the address space of the VRAM 84, a frame buffer (also referred to as a drawing area or a display area) 156 in which image data displayed on the display screen of the variable display device 9 is drawn (expanded) is a predetermined area. The fixed address area 155A is secured in a predetermined area as a storage area for temporarily storing image data of frequently used component images transferred from the CGROM 83 and transferred from the CGROM 83. Before the image data stored in the fixed address area 155A and the automatic transfer area 155B is drawn (developed) in the frame buffer 156, the automatic transfer area 155B is secured in a predetermined area as a storage area for temporarily storing the image data. Temporary expansion area 155C is a predetermined storage area for temporary expansion. It is secured in the area.

  The temporary development area 155C temporarily stores image data in order to set an alpha value corresponding to the color data of each pixel of the image data constituting the component image stored in the fixed address area 155A and the automatic transfer area 155B. This is a storage area to be expanded.

  The image data of the component image that is frequently used is transferred from the CGROM 83 to the fixed address area 155A of the VRAM 84 in advance based on the transfer instruction in steps S773, S1814, and S1867. That is, when the symbol control CPU 101a issues a transfer instruction of image data of a plurality of component images frequently used in the advance transfer command processing (FIG. 97) in steps S773, S1814, and S1867, image data is stored. An address in the CGROM 83 and an address in the fixed address area 155A in the VRAM 84 are designated. The VDP 109 sequentially reads the image data at the address designated by the symbol control CPU 101a from the CGROM 83, and stores the read image data at a predetermined address in the fixed address area 155A designated by the symbol control CPU 101a. Thereafter, when there is a drawing instruction (steps S204, S696) of frequently used component image data from the symbol control CPU 101a, the VDP 109 does not read the image data of the component image from the CGROM 83, but the fixed address area. The image data stored at the predetermined address 155A is developed at a predetermined position in the frame buffer 156 specified in the drawing instruction.

  The fixed address area 155A is divided at equal intervals, and the head address of the area divided at equal intervals is called a fixed address. Image data of each frequently used component image transferred from the CGROM 83 is stored in the fixed address area 155A with each fixed address as the head address.

  Also, image data of component images other than the component images that are frequently used (image data of component images that are not frequently used) is automatically generated from the CGROM 83 to the VRAM 84 based on the drawing instruction in steps S204 and S696. Transferred to and stored in transfer area 155B. That is, when the symbol control CPU 101a instructs to draw image data of a plurality of component images that are not frequently used in steps S204 and S696, the address in the CGROM 83 storing the image data and the address of the frame buffer 156 in the VRAM 84 are stored. Is specified. The VDP 109 sequentially reads the image data at the address designated by the symbol control CPU 101a from the CGROM 83, and stores the read image data at a predetermined address in the automatic transfer area 155B. Immediately, the VDP 109 expands the image data stored in the automatic transfer area 155B in the VRAM 84 to a predetermined position (predetermined address) in the frame buffer 156 specified in the drawing instruction.

  FIG. 101 is an explanatory diagram showing an example of a method of expansion when a component image is expanded from the outside of the display area of the VRAM 84 to the display area. As shown in FIG. 101, the component image of the area specified by the original horizontal coordinate, the original vertical coordinate, the original horizontal size and the original vertical size in the VRAM 84 (stored in a predetermined address in the fixed address area 155A or the automatic transfer area 155B in the VRAM 84). The component image) is developed at a position specified by the development destination horizontal coordinate and the development destination vertical coordinate. The term “development” refers to writing image data at a designated position in the VRAM 84 and is also referred to as drawing. Further, expanding the component image from the display area (also referred to as a drawing area) of the VRAM 84 to the display area specifically means that the source data of the component image stored outside the display area of the VRAM 84 is converted to the display area. Is to write to. The source data is bitmap data, and the encoded part image data is also stored outside the display area of the VRAM 84 as the source data after being decoded.

  FIG. 102 is an explanatory diagram showing an example of how to use the VRAM. As shown in FIG. 100, two display areas (areas 0 and 1) corresponding to the screen of the variable display device 9 are secured in the VRAM 84. The areas 0 and 1 may be called display data storage means or a frame buffer. In areas 0 and 1, a background image (background image is also one of the component images) displayed on the variable display device 9 at a predetermined timing (for example, when the game machine is turned on or when variable display is started). .) Is developed. In addition, component images such as characters and identification information are developed in areas 0 and 1 as appropriate. When the component image is developed in the area 0, an image signal based on the image data of the area 1 is output to the variable display device 9, and when the component image is expanded in the area 1, the image based on the image data of the area 0 is output. A signal is output to the variable display device 9. When the component image is expanded in the area 0, the area 0 is a display area, and when the component image is expanded in the area 1, the area 1 is a display area. Further, when image data is read from the area 0 and an image signal based on the image data is output to the variable display device 9, the area 0 is a display area, and the image data is read from the area 1 and is included in the image data. When the original image signal is output to the variable display device 9, the area 1 is the display area. Thus, the areas 0 and 1 are used as a double buffer.

  In the area other than the areas 0 and 1 in the VRAM 84, as described above, a development area (fixed address area 155A) outside the display area of the VRAM 84 for component images is secured. From the CGROM 83 to the fixed address area 155A, a part image (specifically, source data of the part image) that is likely to be used at that time, that is, that is likely to be developed in the display area of the VRAM 84 is stored. .

  FIG. 103 is a flowchart showing the effect control process (step S777) in the main process shown in FIG. In the effect control process, the symbol control microcomputer 100a executes one of steps S1800 to S1806 according to the value of the effect control process flag. In each process, the following process is executed.

  Ornamental symbol normal processing (step S1800): It is confirmed whether or not a variation pattern command is received. If the variation pattern command has been received, the symbol control microcomputer 100a changes the value of the effect control process flag to a value corresponding to step S1802 (decoration symbol variation start processing).

  Decoration symbol variation start processing (step S1802): Process data predetermined according to the variation pattern is selected, a process timer is started, and display control of the variable display device 9 is started. Thereafter, the value of the effect control process flag is updated to a value according to step S1803.

  Decoration symbol variation processing (step S1803): Controls the switching timing of each variation state (variation speed, etc.) constituting the variation pattern, and monitors the end of the variation time. Thereafter, the value of the effect control process flag is updated to a value according to step S1804.

  Decoration symbol stop process (step S1804): When the variation time elapses, control is performed to stop the variation of the symbol and display the stop symbol (determined symbol). Thereafter, in the case of a big hit, the value of the effect control process flag is updated to a value according to step S1805. Otherwise, the value of the effect control process flag is updated to a value according to step S1800.

  Big hit display process (step S1805): After the end of the fluctuation time, the big hit display is controlled. Thereafter, the value of the effect control process flag is updated to a value according to step S1806.

  Big hit game processing (step S1806): Control during the big hit game is performed. For example, when receiving an effect control command for display before opening the big winning opening or display when opening the big winning opening, display control during the round or interval is performed. In addition, when the big hit game is finished, a predetermined ending display indicating that the big hit game is finished is performed. Thereafter, the value of the effect control process flag is updated to a value corresponding to step S1800.

  FIG. 104 is a flowchart showing the decorative symbol normal process (step S1800) in the effect control process. In the decorative symbol normal process, the symbol control CPU 101a of the symbol control microcomputer 100a checks whether or not the command non-reception timer has timed out (step S1811). The command non-reception timer is a timer that measures a period in which no variation pattern command has been received after the decoration symbol variation ends and the jackpot game ends. The command non-reception timer is started when the decorative symbol fluctuation is stopped and when the big hit game is finished. When the command non-reception timer has timed out (Y in step S1811), the symbol control CPU 101a executes control to display a demonstration screen (demonstration screen) (step S1812).

  Then, the symbol control CPU 101a instructs the VDP 109 to execute processing for clearing (erasing) storage information (image data of frequently used component images) stored in the fixed address area 155A (step S1813). . The VDP 109 clears the image data stored in the fixed address area 155A based on the image data clear instruction from the symbol control CPU 101a. Further, as described in step S772, the symbol control CPU 101a performs pre-transfer command processing (FIG. 97) for instructing transfer of frequently used component image image data from the CGROM 83 to the fixed address area 155A of the VRAM 84. It executes (step S1814). Based on the image data transfer instruction, the VDP 109 reads the image data of the part image frequently used in advance from the CGROM 83, transfers the read image data to the fixed address area 155A of the VRAM 84, and stores it again in the fixed address area 155A. . Then, the symbol control CPU 101a starts a command non-reception timer (step S1815). In this way, when the demo screen is displayed, the image data stored in the fixed address area 155A of the VRAM 84 is cleared and the image data is stored again in the fixed address area 155A. The image data stored in the area 155A can be updated periodically, and even if data corruption occurs due to the image data being stored in the fixed address area 155A for a long time, it is automatically restored. Can do.

  When the command non-reception timer has not timed out (N in Step S1811), the symbol control CPU 101a checks whether the variation pattern reception flag is set (Step S1816). The variation pattern reception flag is set in the command analysis process when a variation pattern command is received.

  If the variation pattern reception flag is set, the symbol control microcomputer 100a resets the variation pattern reception flag (step S1817), and based on the previously determined decorative symbol stop symbol and the content of the variation pattern command. A variation pattern of the decorative design is determined (step S1818). At this time, the current game state is confirmed by confirming the data indicating the game state stored in the predetermined storage area, and the game effect according to the current game state (normal game effect or A decorative pattern variation pattern for executing a special game effect) is determined. For example, in the case of a normal game effect, a decorative pattern is variably displayed by scrolling the decorative symbol horizontally (effect pattern). In the case of a special game effect, the decorative symbol is scrolled vertically. Suppose that it is determined to be a variation pattern (effect pattern) for executing variable display of decorative symbols.

  Then, the value of the effect control process flag is changed to a value corresponding to the decorative symbol variation start process (step S1819).

  FIG. 105 is a flowchart showing a decorative symbol variation start process (step S1802) in the effect control process. In the decorative symbol variation start process, the symbol control CPU 101a of the symbol control microcomputer 100a first selects process data corresponding to the variation pattern of the decorative symbol to be used (step S1821). At this time, based on the effect content command from the sound / lamp control microcomputer 100b, the presence / absence of the notice effect is confirmed. If execution of the notice effect is designated, display control including the notice effect is performed. Process data for executing is selected. Then, the symbol control CPU 101a sets the process timer set value set in the process data selected in step S1821 to the process timer, and starts the process timer (step S1822).

  Thereafter, a variation time timer (a timer corresponding to the variation time of the decorative symbol) is started (step S1823), and the value of the effect control process flag is set to a value corresponding to the processing during the decorative symbol variation (step S1824).

  FIG. 106 is a flowchart showing the decorative symbol variation process (step S1803) in the effect control process. In the decorative symbol changing process, the symbol control CPU 101a of the symbol control microcomputer 100a first loads the contents of the display control execution data set in the process data (step S1840), and the contents of the display control execution data. A predetermined display update command process is executed according to (step S1841). The contents of the display update command process will be described later (see FIG. 108).

  The symbol control CPU 101 a confirms the input of the V blank interrupt signal from the VDP 109. The V blank outputs image data expanded in the frame buffer (display area) of the VRAM 84 to the variable display device 9 and then outputs the image data expanded next to the frame buffer of the VRAM 84 to the variable display device 9. The period until the beginning. The VDP 109 outputs an interrupt signal to the symbol control CPU 101a at the start of the V blank to generate a V blank interrupt. Thus, the V blank interrupt is an interrupt generated by the VDP 109 in the same cycle as the cycle of the vertical synchronization signal supplied to the variable display device 9. For example, when the screen change frequency (frame frequency) of the variable display device 9 is 30 Hz, the generation period of the V blank interrupt is 33.3 ms, and when the frame frequency is 60 Hz, the occurrence of the V blank interrupt is generated. The period is 16.7 ms. The symbol control CPU 101 a includes an interrupt terminal (INT terminal) for receiving an interrupt signal from the VDP 109. When the input level of the interrupt terminal falls to a low level, the symbol control CPU 101a detects the occurrence of a V blank interrupt as an external interrupt. Then, when detecting the occurrence of the V blank interrupt, the symbol control CPU 101a executes a V blank interrupt process (not shown).

  In this embodiment, in the display update command processing described later, the symbol control CPU 101a creates and sets a command for instructing (commanding) image data transfer to the VDP 109, and in the V blank interrupt processing, The CPU 101a is configured to output the set command to the VDP 109. However, in the display update command processing, the symbol control CPU 101a creates a command and when the image display update timing based on the V blank interruption is reached (in addition, whether the image display update timing has come is V blank, for example) This is done by checking a flag that is set when an interrupt occurs), and the created command may be sent to the VDP 109.

  Next, the symbol control CPU 101a decrements the value of the process timer by -1 (step S1842A). When the value of the process timer becomes 0, that is, when the process timer times out (step S1842B), the display control execution data in the process data is switched (step S1843A). Then, the symbol control CPU 101a sets the next process timer set value in the process timer and starts the process timer (step S1843B).

  Then, the symbol control CPU 101a decrements the value of the variable time timer by -1 (step S1848), and checks whether or not the value of the variable time timer is 0 to determine whether or not the variable time timer has timed out. Confirmation is made (step S1849). If the variable time timer has timed out (step S1849), the value of the effect control process flag is set to a value corresponding to the decorative symbol stop process (step S1850).

  FIG. 107 is a flowchart showing the decorative symbol stop process (step S1804) in the effect control process. In the decorative symbol stop process, the symbol control CPU 101a checks whether or not an effect control command (decorative symbol stop command) for instructing stop of the decorative symbol is received (step S1861). If the decorative symbol stop command has been received, control is performed to stop and display the decorative symbol with the stored stop symbol (step S1862).

  If the jackpot symbol is displayed in step S1862 (Y in step S1863), the symbol control CPU 101a sets the value of the effect control process flag to a value corresponding to the jackpot display process (step S1805) (step S1870). ).

  If the big hit symbol is not displayed in step S1862 (if a missing symbol is displayed, N in step S1863), the symbol control CPU 101a checks whether or not the condition mode changing condition is satisfied (step S1864). In this embodiment, a spring mode, a summer mode, an autumn mode, and a winter mode are provided as effect modes. As a change condition for changing (switching) the effect mode, in this embodiment, when a change of a predetermined number of changes (for example, 100 times) is executed after the change of the effect mode and a specific reach (For example, gradation reach) occurs. Each time the symbol control CPU 101a receives a variation pattern command, the symbol control CPU 101a updates the value of a frequency counter that counts the number of variations, and when the value of the frequency counter reaches a value indicating a predetermined variation frequency, Judge that it was established. Further, when the symbol control CPU 101a determines that the variation pattern has a specific reach (for example, reach C having a long variation time; called super-reach) based on the content of the variation pattern command, the change condition of the effect mode is changed. Judge that it was established.

  When the conditions for changing the effect mode are satisfied (Y in step S1864) and the effect mode is switched, the effect mode flag is changed according to the effect mode after the switching (step S1865). When the effect mode is switched, the image data of the part image (especially the background image) that is frequently used is changed. Therefore, the symbol control CPU 101a stores the VDP 109 in the fixed address area 155A. An instruction to execute processing for clearing (erasing) stored information (image data of a part image that is frequently used) is issued (step S1866). Further, the symbol control CPU 101a executes a pre-transfer command process for instructing transfer from the CGROM 83 to the VRAM 84 for the image data of the part image frequently used according to the effect mode (step S1867). As a result, the image data of the part image that is frequently used according to the rendering mode is stored in advance in the fixed address area 155A.

  Then, the symbol control CPU 101a starts a command non-reception timer in order to monitor the time until reception of the next effect control command (step S1868), and sets the value of the effect control process flag as a decorative symbol normal process (step S1800). (Step S1869).

  FIG. 108 is a flowchart illustrating an example of the display update command process executed in step S1841. In the display update command processing, the symbol control CPU 101a first determines whether or not the display mode in the variable symbol display is a reach display period or a notice effect execution period (step S691). For example, in step S691, the symbol control CPU 101a determines whether or not the currently selected process data is process data corresponding to the reach effect, or a variation time timer that measures the variation time of the decorative symbol. It may be determined whether or not it is the reach display period by determining whether or not the value is a predetermined value corresponding to the execution period of the reach effect. Also, the symbol control CPU 101a determines whether or not the currently selected process data is process data corresponding to the notice effect, or starts a timer for measuring the execution timing of the notice effect at the start of fluctuation. It may be determined whether or not it is a notice effect execution period by determining whether or not the timer has measured a predetermined time.

  If it is the reach display period or the notice effect execution period in step S691 (Y in step S691), for example, the variation of the decorative pattern based on the EXT data of the variation pattern stored in the variation pattern data storage area of the RAM. Determine whether the pattern is a variation pattern that performs alpha test processing among the variation patterns that involve reach, and whether or not it is a variation pattern that performs alpha test processing among the variation patterns that involve notice effects (Step S692). In this embodiment, the variation pattern with the display mode reach (for example, reach B) shown in FIGS. 91 and 94 is the variation pattern for executing the alpha test process. At this time, if the variation pattern is to execute the alpha test process (Y in step S692), a predetermined alpha test display command process is executed (step S693).

  If it is not the variation pattern for executing the alpha test process in step S692 (N in step S692), is the variation pattern for the decorative design a variation pattern for executing the alpha synthesis processing among the variation patterns with reach? It is determined whether or not (step S694). In this embodiment, the variation pattern with the reach (for example, reach C) of the display mode shown in FIG. 126 is the variation pattern for executing the alpha synthesis process. At this time, if the variation pattern is to execute the alpha synthesis process (Y in step S694), a predetermined alpha synthesis display command process is executed (step S695).

  If it is not the reach display period in step S691 (N in step S691), or if it is a variation pattern in which neither the alpha test process nor the alpha synthesis process is executed (N in step S692, N in step S694), or steps S693 and S695. After executing any one of the processes, predetermined various update target command processes are executed (step S696).

  FIG. 109 is a flowchart illustrating an example of alpha test display command processing executed in step S693. In the alpha test display command processing, the symbol control CPU 101a first uses a variation pattern in which the variation pattern of the decorative symbol executes the alpha test processing among the variation patterns accompanied by the notice effect based on the EXT data of the variation pattern. It is determined whether or not there is (step S700).

  If it is not a variation pattern with a notice effect (N in step S700), the decorative symbol to be displayed this time is specified (step S701). For example, in step S701, the symbol control CPU 101a starts variable display of the decorative symbol specified based on the content of the process data display control execution data, the final decorative symbol in the current variable display, and the variable time timer value. The decorative symbol to be displayed may be specified at the timing when the process of step S701 is executed based on the elapsed time from the beginning.

  Subsequently, the symbol control CPU 101a compares the ornament symbol specified in step S701 with the ornament symbol that is displayed when the process of step S701 was executed last time (step S702). Then, based on the comparison result at this time, it is determined whether or not the decorative symbol to be displayed has been changed (step S703). In addition, when the process of step S701 is executed for the first time after the decorative display of the decorative design is started, there is no decorative design to be displayed last time, so the decorative design to be displayed is changed. What is necessary is just to make determination that there existed.

  If there is a change in the decorative pattern to be displayed in step S703 (Y in step S703), for example, initial setting of the processing number is performed such as setting the processing number to “0” (step S704). Subsequently, the alpha value distribution setting data associated with the decorative design to be displayed specified in step S701 is specified (step S705). Then, an alpha value distribution setting command for instructing the setting of the alpha value distribution setting data is created based on the decorative design to be displayed specified in step S701 and the alpha value distribution setting data specified in step S705, and the VDP 109 (Step S706). A specific example of the alpha value distribution setting data will be described later (see FIG. 116).

  In step S706, the symbol control CPU 101a says "create a command and send it to the VDP 109". In this embodiment, in step S706, the symbol control CPU 101a command is created and the symbol control CPU 101a internals. In the V blank interrupt process executed when the image display update timing comes, the symbol control CPU 101a transmits the set command to the VDP 109. The same applies to the processing of steps S710, S717, S808, S828, S746, and S750 shown below.

  If there is no change in the decorative pattern to be displayed in step S703 (N in step S703), a setting for returning the number of processes is performed (step S707). For example, in the process of step S707, the number of processes saved in step S711 when the alpha test display command process shown in the flowchart of FIG. 109 was executed last time is restored by reading from a predetermined area of the RAM. Subsequently, the number of processes returned in step S707 is updated by, for example, adding 1 (step S708).

  After executing one of the processes in steps S706 and S708, an alpha reference value and a comparison function are determined as shown in FIG. 110 in accordance with the number of processes (step S709). Based on the alpha reference value thus determined and the comparison function, a test execution command is created and transmitted to the VDP 109 (step S710). Thereafter, the decorative design to be displayed and the number of processes are stored in, for example, a predetermined area of the RAM (step S711), and the alpha test display command process is terminated.

  In step S700, if the variation pattern is accompanied by a notice effect (Y in step S700), the symbol control CPU 101a checks whether or not it is the button valid period (step S712). The button valid period is a period for determining that the chance button 300 is turned on when the chance button 300 is pressed. Although not shown in FIG. 109, whether the button is valid or not is determined when the notice start execution time shown in FIG. Specifically, in the decorative symbol variation start process, a timer that measures the execution timing of the notice effect is started, and when the timer measures a predetermined time), a timer that measures the button effective period is started. Judged by whether or not the timer has timed out. The button valid period is, for example, 5 seconds.

  When the symbol control CPU 101a confirms that the button is valid (Y in step S712), the symbol control CPU 101a confirms whether or not the chance button 300 is outputting an on signal, thereby confirming the on state of the chance button 300. (Step S713). When the chance button 300 is in an on state (Y in step S714), the symbol control CPU 101a updates (changes) an alpha reference value (also referred to as a test value) in response to the chance button 300 being turned on (step S715). . Specifically, the symbol control CPU 101a sets a pre-updated alpha reference value (for example, 1) as a test value after the update. In this way, the symbol control CPU 101a changes the alpha reference value stepwise (gradually) every time it confirms that the chance button 300 is turned on.

  Thereafter, the alpha value distribution setting data associated with the character to be displayed in the notice effect is specified (step S716). Based on the alpha value distribution setting data specified in step S716, an alpha value distribution setting command for instructing the setting of the alpha value distribution setting data is created and transmitted to the VDP 109 (step S717). Since the alpha value distribution setting command is transmitted once at the start of execution of the notice effect, it is not necessary to transmit the alpha value distribution setting command to the VDP 109 thereafter. Skipped.

  Then, the alpha reference value updated in step S715 and a comparison function for executing the notice effect are determined (step S718). Based on the alpha reference value thus determined and the comparison function, a test execution command is created and transmitted to the VDP 109 (step S710). Thereafter, the alpha test display command processing is terminated. At this time, step S711 need not be executed.

  The comparison function shown in FIG. 110 is established (draws) if the alpha value is less than or equal to the alpha reference value (test value), or is established (draws) if the alpha value is greater than or equal to the alpha reference value (test value). ) Is given as an example, but this is not the only case. For example, what happens if the alpha value is equal to the alpha reference value, what happens if the alpha value is not equal to the alpha reference value, what happens if the alpha value is less than the alpha reference value, alpha value Something is drawn if is greater than the alpha reference value. Furthermore, there are some that always hold regardless of the alpha value, and some that do not always hold regardless of the alpha value. The alpha test process may be executed using these comparison functions.

  FIG. 111 is a flowchart illustrating an example of alpha synthesis display command processing executed in step S695. In the alpha synthesis display command process, the symbol control CPU 101a first determines whether or not the synthesis flag provided in a predetermined area of the RAM is on (step S721). Here, the in-combination flag is set to the on state in the process of step S723 described later, while it is cleared to the off state in the process of step S731.

  When the compositing flag is off in step S721 (N in step S721), the elapsed time timer sets the elapsed time timer provided in a predetermined area of the RAM to set the timer initial value “0”. Measurement of the elapsed time from the synthesis start timing is started (step S722). At this time, the compositing flag is set to the on state (step S723). If the combining flag is on in step S721 (Y in step S721), the elapsed time timer value, which is the timer value in the elapsed time timer, is updated by adding, for example, 1 (step S724).

  After executing one of the processes in steps S723 and S724, it is determined whether or not the elapsed time timer value has become larger than the maximum value “200” (step S725). At this time, if the elapsed time timer value is larger than “200” (Y in step S725), the elapsed time timer is reset and set to the timer initial value “0” (step S726). On the other hand, if the elapsed time timer value is “200” or less (step S725; No), the process of step S726 is skipped.

  Thereafter, the symbol control CPU 101a determines whether the alpha synthesis type is the first alpha synthesis or the second alpha synthesis based on the currently selected process data, the elapsed time timer value, or the like (step S727). . Here, in the first alpha composition, the image of the first decorative pattern (for example, the decorative pattern indicating “6”) of the two consecutive decorative patterns is faded out, and the display order is the latter. A composite image is generated by fading in an image of a design (for example, a decorative design indicating “7”). On the other hand, in the second alpha composition, an image of a decorative pattern whose display order is earlier (for example, a decorative pattern indicating “6”) among two consecutive decorative patterns is faded in, and the display order is later. A composite image is generated by fading out an image of a design (for example, a decorative design showing “7”).

  For example, in the process of step S727, the symbol control CPU 101a determines from the display control execution data of the process data based on the variation pattern whether it is an initial synthesis period, a turnover synthesis period, or a final synthesis period. Do. Here, the initial synthesis period is a period from the synthesis start timing to the start timing of turnover synthesis. The turn synthesis period is a period from the start timing of turn synthesis to the start timing of final synthesis. The final synthesis period is a period from the start timing of final synthesis to the synthesis end timing.

  When the symbol control CPU 101a determines that it is the initial synthesis period, it determines whether or not the elapsed time timer value is "100" or less. On the other hand, if the alpha synthesis is greater than “100”, the type of alpha synthesis is the second alpha synthesis. Also, when the symbol control CPU 101a determines that it is the turnover synthesis period, it is determined whether or not the elapsed time timer value is in the range of “20” to “81” or “120” to “181”. judge. If the elapsed time timer value is not within this range, the alpha synthesis type is determined in the same manner as in the initial synthesis period, assuming that it is a period in which the turn synthesis is impossible. On the other hand, if the elapsed time timer value is within the above range, it is determined that the elapsed time timer value is “181”, assuming that it is a period during which turnover synthesis is possible, and “181”. If so, the elapsed time timer value is set to “20”. If the elapsed time timer value is not “181”, it is further determined whether or not the elapsed time timer value is “81”. If it is “81”, the elapsed time timer value is set to “120”. To do. Thereafter, it is determined whether or not the elapsed time timer value is in the range of “20” or more and “80” or less. If it is within this range, the type of alpha composition is set to the first alpha composition, If not, the type of alpha synthesis is the second alpha synthesis.

  Further, when the symbol control CPU 101a determines that it is the final synthesis period, the final symbol in the variable display unit “medium” in the variable display device 9 is displayed in the display order (for example, “7”). It is determined whether it is a decorative pattern to be displayed) or a previous decorative pattern (for example, a decorative pattern indicating “6”) in the display order. When the decorative pattern in the rear order is a confirmed decorative pattern, the type of alpha composition is set to the first alpha composition, while when the decorative pattern in the first order is a finalized decorative pattern, the type of alpha composition is changed. The second alpha composition is assumed.

  If the type of alpha composition is the first alpha composition in step S727 (step S727; first), predetermined first alpha composition command processing is executed (step S728). On the other hand, when the type of alpha synthesis is the second alpha synthesis (step S727; second), predetermined second alpha synthesis command processing is executed (step S729). Thereafter, based on the display control execution data of the process data based on the variation pattern or the like, it is determined whether or not the synthesis end timing has come (step S730). If it is the composition end timing (Y in step S730), the compositing flag is cleared (step S731), and the alpha composition display command processing is terminated. On the other hand, if it is not the synthesis end timing (N in step S730), the process of step S731 is skipped and the alpha synthesis display command process is terminated.

  FIG. 112 is a flowchart illustrating an example of the first alpha synthesis command process executed in step S728. In the first alpha compositing command process, the design control CPU 101a firstly uses a blend rate A table as a table for reading blend rate data to be used for a display design whose display order is earlier (for example, a design showing “6”). Is set, and a blend rate B table is set as a table for reading the blend rate data to be used for a decorative symbol whose display order is later (for example, a decorative symbol indicating “7”) (step S801). In addition, the symbol control CPU 101a sets an enlargement factor A table as a table for reading the enlargement factor data used for the earlier ornament symbol (for example, the ornament symbol indicating “6”). An enlargement ratio B table is set as a table for reading out enlargement ratio data to be used for a later decorative pattern (for example, a decorative pattern indicating “7”) (step S802).

  Here, in this embodiment, a blend rate A table, a blend rate B table, an enlargement rate A table, an enlargement rate B table, and an enlargement rate C table are stored in a predetermined area of the ROM.

  The blend rate A table and the blend rate B table include data indicating the elapsed time TM (M = 1, 2,..., 100) from the start of the generation of the composite image, and the blend rate as data indicating the blend rate. Data is stored in association with each other. The blend rate data stored in the blend rate A table is control data that sequentially decreases the blend rate from “1” to “0” as time passes. The blend rate data stored in the blend rate B table is control data for sequentially increasing the blend rate from “0” to “1” as time passes.

  In the enlargement rate A table, the enlargement rate B table, and the enlargement rate C table, the elapsed time TM and enlargement rate data as data indicating the enlargement rate are stored in association with each other. The enlargement ratio data stored in the enlargement ratio A table is control data for sequentially reducing the enlargement ratio from “1” to “0” as time elapses. The enlargement ratio data stored in the enlargement ratio B table is control data for sequentially increasing the enlargement ratio from “0” to “1” with the passage of time. The enlargement ratio data stored in the enlargement ratio C table is control data that remains “1” without changing the enlargement ratio over time.

  Subsequently, the symbol control CPU 101a determines whether or not the elapsed time timer value is “100” or less (step S803). The blend ratio data and the enlargement ratio data to be read are read out from the blend ratio table and the enlargement ratio table set in steps S801 and S802, respectively (step S804). For example, if the elapsed time timer value is “0”, the blend rate data indicating the blend rate associated with the elapsed time “T0” in the blend rate A table and the blend rate B table, the enlargement rate A table, and the enlargement rate In the rate B table, the magnification rate data indicating the magnification rate associated with the elapsed time “T0” is read.

  If the elapsed time timer value is larger than “100” in step S803 (N in step S803), it is determined whether or not the process up to the previous time is the same in the direction of improvement or reduction in the blend rate and the enlargement rate (step S805). If the directions are the same (Y in Step S805), the blend rate table and the enlargement rate data corresponding to the value obtained by subtracting “100” from the elapsed time timer value are set in Steps S801 and S802. And the enlargement ratio table respectively (step S806). Specifically, when the elapsed time timer value exceeds “100” and becomes “101”, the elapsed time “T1” is associated with the blend rate table and the enlargement rate table set in steps S801 and S802. Data indicating the blend ratio and enlargement ratio being read is read out, and thereafter data indicating the blend ratio and enlargement ratio corresponding to the elapsed times “T2”, “T3”,. As a result, of the two consecutive decorative symbols, the image of the first decorative symbol (for example, the decorative symbol indicating “6”) in the display order completely fades out, and the decorative symbol with the subsequent display symbol (for example, “7”) is displayed. Only the image of the decorative pattern showing) is displayed, the decorative pattern of the later display order is erased, the decorative pattern of the previous display order appears again, and gradually fades out and disappears A composite image is generated so that a decorative pattern whose display order is later fades in.

  When the blend rate and the enlargement rate increase or decrease direction is different from the previous processing in step S805 (N in step S805), blend rate data corresponding to the value obtained by subtracting the elapsed time timer value from “200” The enlargement rate data is read from the blend rate table and the enlargement rate table set in steps S801 and S802, respectively (step S807). Specifically, when the elapsed time timer value exceeds “100” and becomes “101”, the elapsed time “T99” is determined from the blend rate table and the enlargement rate table set in steps S801 and S802. Data indicating the blend rate and the enlargement rate is read, and thereafter data indicating the blend rate and the enlargement rate corresponding to the elapsed times “T98”, “T97”,. As a result, of the two consecutive decorative symbols, the image of the first decorative symbol (for example, the decorative symbol indicating “6”) in the display order completely fades out, and the decorative symbol with the subsequent display symbol (for example, “7”) is displayed. In contrast to the case of step S806, the first decorative pattern fades in the display order while the display order of the subsequent decorative pattern is displayed. A composite image is generated so as to fade out.

  Based on the blend rate data and the enlargement rate data read in any of the processes in steps S804, S806, and S807, an alpha synthesis command is created and transmitted to the VDP 109 (step S808). Thus, the first alpha synthesis command process is completed.

  FIG. 113 is a flowchart illustrating an example of the second alpha synthesis command process executed in step S729. In the second alpha compositing command process, the symbol control CPU 101a firstly uses a blend rate B table as a table for reading blend rate data used for a decorative symbol whose display order is earlier (for example, a decorative symbol indicating “6”). Is set, and a blend rate A table is set as a table for reading out blend rate data used for a decorative symbol whose display order is later (for example, a decorative symbol indicating “7”) (step S821). In addition, the symbol control CPU 101a sets an enlargement factor B table as a table for reading the enlargement factor data used for the earlier ornament symbol (for example, the ornament symbol indicating “6”). An enlargement ratio A table is set as a table for reading out enlargement ratio data to be used for a later decorative pattern (for example, a decorative pattern indicating “7”) (step S822).

  Subsequently, the symbol control CPU 101a determines whether or not the elapsed time timer value is “100” or less (step S823). The blend ratio data and the enlargement ratio data to be read are read out from the blend ratio table and the enlargement ratio table set in steps S821 and S822, respectively (step S824). For example, if the elapsed time timer value is “0”, the blend rate data indicating the blend rate associated with the elapsed time “T0” in the blend rate A table and the blend rate B table, the enlargement rate A table, and the enlargement rate In the rate B table, the magnification rate data indicating the magnification rate associated with the elapsed time “T0” is read.

  If the elapsed time timer value is larger than “100” in step S823 (N in step S823), it is determined whether or not the process up to the previous time is the same in the direction of improving or decreasing the blend rate and the enlargement rate (step S825). If the directions are the same (step S825; Yes), the blend rate table and the enlargement rate data corresponding to the value obtained by subtracting "100" from the elapsed time timer value are set in steps S821 and S822. And the enlargement ratio table are read out (step S826). Specifically, when the elapsed time timer value exceeds “100” and becomes “101”, the elapsed time “T1” is associated with the blend rate table and the enlargement rate table set in steps S821 and S822. Data indicating the blend ratio and enlargement ratio being read is read out, and thereafter data indicating the blend ratio and enlargement ratio corresponding to the elapsed times “T2”, “T3”,. As a result, of two consecutive decorative symbols, the image of the decorative symbol whose display order is later (for example, the decorative symbol indicating “7”) completely fades out, and the decorative symbol whose display order is earlier (for example, “6”). Only the image of the decorative pattern showing) is displayed, and the first decorative pattern is erased, the decorative pattern with the later display order appears again, and it fades out while gradually disappearing. A composite image is generated so that the decorative pattern whose display order is earlier fades in.

  When the blend rate and the enlargement rate increase or decrease direction is different from the previous processing in step S825 (N in step S825), blend rate data corresponding to the value obtained by subtracting the elapsed time timer value from "200" The enlargement rate data is read from the blend rate table and the enlargement rate table set in steps S821 and S822, respectively (step S827). Specifically, when the elapsed time timer value exceeds “100” and becomes “101”, the elapsed time “T99” corresponds to the blend rate table and the enlargement rate table set in steps S821 and S822. Data indicating the blend rate and the enlargement rate is read, and thereafter data indicating the blend rate and the enlargement rate corresponding to the elapsed times “T98”, “T97”,. As a result, of two consecutive decorative symbols, the image of the decorative symbol whose display order is later (for example, the decorative symbol indicating “7”) completely fades out, and the decorative symbol whose display order is earlier (for example, “6”). In contrast to the case of step S826, the display pattern whose display order is earlier is displayed while the subsequent display pattern fades in, contrary to the case of step S826. A composite image is generated so as to fade out.

  Based on the blend rate data and the enlargement rate data read in any of the processes of steps S824, S826, and S827, an alpha synthesis command is created and transmitted to the VDP 109 (step S828). Thus, the second alpha synthesis command process is completed.

  In this embodiment, the first alpha synthesis and the second alpha synthesis are provided as alpha synthesis (alpha blend), but other alpha synthesis may be executed. For example, when an ornamental design image and a background image are alpha-synthesized, the decorative design is faded in or out of the background, or the character image and the background image are alpha-synthesized. This may be the case when the image is faded in or out of the background. Moreover, the structure which changes a blend rate according to ON of the chance button 300 may be sufficient. In this case, instead of the configuration in which the blend rate data is changed with the passage of time (for example, the processing in steps S803 to S807 in FIG. 112 and steps S823 to S827 in FIG. 113), the chance button 300 is confirmed. The blend rate data in the blend rate table may be changed every time the button is turned on.

  FIG. 114 is a flowchart illustrating an example of various update target command processes executed in step S696. In the various update target command processing, the symbol control CPU 101a first specifies a component image whose display is to be updated from, for example, display control execution data of the currently selected process data (step S741). Subsequently, it is determined whether or not the component image identified in step S741 is a component image for which image data is to be transferred in advance to the fixed address area 155A of the VRAM 84 (step S742).

  If it is determined in step S742 that the image is a part image to be pre-transferred (Y in step S742), the image data is read from the fixed address area 155A of the VRAM 84 from, for example, process data display control execution data. An address is specified (step S743). Further, for example, the writing address of the image data in the frame buffer 156 corresponding to the display position (display coordinates) of the component image is specified from the display control execution data of the process data (step S744). Further, the data amount of the image data indicating the component image to be updated is specified (step S745). Thereafter, based on the read address in the fixed address area 155A specified in steps S743 to S745, the write address in the frame buffer 156, and the data amount of the image data, a fixed address designation display command is created and transmitted to the VDP 109 (step S746). ).

  If it is determined in step S742 that the image is not a part image to be pre-transferred (N in step S742), the image data read address in the CGROM 83 is specified from, for example, process data display control execution data (step S742). Step S747). Further, for example, the writing address of the image data in the frame buffer 156 corresponding to the display position (display coordinates) of the component image is specified from the display control execution data of the process data (step S748). Furthermore, the data amount of image data indicating the component image to be updated is specified (step S749). Thereafter, an automatic transfer display command is created and transmitted to the VDP 109 based on the read address in the CGROM 83 specified in steps S747 to S749, the write address in the frame buffer 156, and the data amount of the image data (step S750).

  Thereafter, it is determined whether or not the command for all the part images to be updated is completed (step S751). If the command is not completed (N in step S751), the process returns to step S741. On the other hand, if the command for all the component images to be updated is completed (Y in step S751), the various update target command processing is terminated.

  Note that the VDP 109 performs a process of setting data in a register provided in the drawing control unit 91 based on a command (a fixed address designation display command, an automatic transfer display command, etc.) from the symbol control CPU 101a. Specifically, the storage address (read address) of the image data of the component image in the CGROM 83 is set in the CGROM address register, and the VRAM 84 is stored in the VRAM horizontal coordinate register, VRAM vertical coordinate register, VRAM horizontal size register, and VRAM vertical size register. The information regarding the transfer destination of the source data of the component image is set, and information indicating the data transfer (in the case of a sprite image) or the decoding execution instruction (in the case of movie data) is set in the execution instruction register.

  The VDP 109 also sets the head address of the information storage area indicating the part image in the part image information head address register, and sets the upper left horizontal coordinate and upper left vertical coordinate of the drawing area in the drawing horizontal coordinate register and the drawing vertical coordinate register. Data indicating the horizontal size and vertical size of the drawing area is set in the horizontal size register and the vertical size register, and information indicating a drawing instruction to the frame buffer 156 is set in the execution instruction register Set.

  When the drawing control unit 91 in the VDP 109 recognizes that information indicating data transfer is set in the execution instruction register, the image data (image data of a part image that is not frequently used) is generated from the address of the CGROM 83 set in the CGROM address register. ), And the read image data is stored at a predetermined address in the automatic transfer area 155B of the VRAM 84 specified by the information set in the VRAM horizontal coordinate register, VRAM vertical coordinate register, VRAM horizontal size register, and VRAM vertical size register. To do.

  When the drawing control unit 91 in the VDP 109 recognizes that the information indicating the drawing instruction is set in the execution instruction register, the image data stored in the area other than the frame buffer in the VRAM 84 is drawn (expanded) in the frame buffer. To do.

  Further, the VDP 109 performs a process of setting data in a register provided in the drawing control unit 91 based on commands (alpha value distribution setting command, test execution command, alpha synthesis command, etc.) from the symbol control CPU 101a. . Specifically, information indicating an alpha value is set in the alpha value register, and information indicating a test value (alpha reference value) is set in the test value register (step S205). Based on the alpha value and the test value set in this way, the VDP 109 executes alpha test processing and alpha synthesis processing in the image drawing processing.

  In this embodiment, a command is transmitted to the VDP 109 based on the display control execution data in the process data in the decorative symbol variation processing (step S1803), and the data is stored in the register provided in the drawing control unit 91 of the VDP 109. It is configured to be set. However, the present invention is not limited to such a configuration. In the process based on the V blank interrupt (V blank interrupt process), a command is transmitted to the VDP 109 based on the display control execution data in the process data, and the drawing control unit of the VDP 109 Data may be set in a register provided in 91.

  Next, the alpha value set corresponding to the color data of each pixel constituting the image will be described. FIG. 115 is an explanatory diagram of alpha value distribution setting data. In the CGROM 83, in addition to the color data of each pixel of the image data constituting each component image, data indicating the shape of the component image (image size, angle, deformation mode) and the alpha value of each pixel of the component image are stored. The alpha value distribution setting data shown is stored. The alpha value distribution setting data is stored in the CGROM 83 separately from the color data constituting each component image. The alpha value distribution setting data serves as a filter for setting an alpha value in association with image data (RGB color data). The alpha value distribution setting data is data used to realize, for example, decorative pattern gradation display and character cut-in display as shown in FIGS. 91 to 94, and a plurality of pieces of alpha value distribution setting data are provided depending on the display mode. ing.

  The example shown in FIG. 115 is an example of alpha value distribution setting data indicating an alpha value used for executing variable display of a decorative design with gradation as shown in FIG. 91 by an alpha test process described later. That is, the alpha value distribution setting data that is superimposed (combined) with the image data of the component image of the decorative design “7” is divided into the left region, the middle region, and the right region, and is used as the alpha value α of the adjacent pixels in the left region. 0.3 and 0.4 are alternately set, and 0.4 and 0.5 are alternately set as alpha values α of adjacent pixels in the middle region, and alternately as alpha values of adjacent pixels in the right region. Are set to 0.5 and 0.6. The alpha value distribution setting data in which the α value is set in this way is superimposed on the image data of the component image, so that each pixel (position) of the component image corresponding to each pixel (position) of the alpha value distribution setting data is superimposed. The alpha value α set in the alpha value distribution setting data is set in the image data (color data).

  If the alpha value distribution setting data to be overlaid on the image data of the decorative part image is divided more finely, and a predetermined alpha value is set at a different density for the pixels in the divided area, a finer gradation is added. Display is possible.

  FIG. 115 shows the alpha value distribution setting data when the color of the decorative pattern is changed from left to right as shown in FIG. 91. However, the decoration is shown as shown in FIG. Alpha value distribution setting data for changing the color of the pattern from top to bottom (in the vertical direction) concentrically and in the rotation direction is also provided in the CGROM 83, respectively.

  FIG. 116 is an explanatory diagram showing a data structure of image data of one pixel developed in an area other than the drawing area in the VRAM 84. When the image data is stored in the CGROM 83, it is composed only of color data (R, G, B). As described above, in the color data, R (red), G (green), and B (blue) are each represented by 8 bits. Therefore, each of R, G, and B has 256 gradations, and approximately 16.7 million colors can be displayed.

  The image data is transferred from the CGROM 83 to the fixed address area 155A or automatic transfer area 155B in the VRAM 84, and when the image data stored in the fixed address area 155A or automatic transfer area 155B is temporarily expanded in the temporary expansion area 155C in the VRAM 84. The alpha value (α) is set corresponding to the color data of each pixel. That is, when the VDP 84 is temporarily expanded in the temporary expansion area 155C in the VRAM 84, the VDP 109 selects the alpha value distribution setting data indicating the alpha value according to the information set in the alpha value register by the symbol control CPU 101a, and the selected alpha value Based on the distribution setting data, an alpha value α is set corresponding to the color data of each pixel, and the image data set with the alpha value α is developed in the temporary development region 155C. As shown in FIG. 116, the alpha value α is also represented by 8 bits.

  Next, the operation of the VDP 109 will be described. FIG. 117 is a flowchart illustrating an example of a transfer control process executed by the VDP 109. In the transfer control process, the drawing control unit 91 of the VDP 109 first determines whether or not there is a command serving as a display control command received from the symbol control CPU 101a via the CPU I / F 92 (step S901). If there is no received command from the symbol control CPU 101a (N in step S901), the process of step S901 is repeatedly executed and awaits.

  If there is a reception command in step S901 (Y in step S901), it is determined whether the reception command is a storage area setting command (step S902). If it is a storage area setting command (Y in step S902), a predetermined storage area setting process is executed (step S903), but if it is not a storage area setting command (N in step S902), the received command is pre-transferred. It is determined whether it is a command (step S904).

  If the received command is a pre-transfer command in step S904 (Y in step S904), a predetermined pre-transfer process is executed (step S905), but if it is not a pre-transfer command (N in step S904), the received command is It is determined whether the command is an automatic transfer display command (step S906). If the received command is an automatic transfer display command in step S906 (Y in step S906), a predetermined automatic transfer control process is executed (step S907). If the received command is not an automatic transfer display command in step S906 (N in step S906) or after executing the process in step S907, the process returns to step S901.

  FIG. 118 is a flowchart illustrating an example of the storage area setting process executed in step S903. In the storage area setting process, the drawing control unit 91 of the VDP 109 first clears the VRAM 84 and initializes the stored contents (step S921). Subsequently, the address STADD serving as the start address of the automatic transfer area 155B is specified from the data included in the storage area setting command (step S922). Then, the address STADD specified at this time is set and stored in the internal register of the VDP 109 (step S923). Further, the drawing control unit 91 specifies the address ENADD that is the final address of the automatic transfer area 155B from the data included in the storage area setting command (step S924). Then, the address ENADD specified at this time is set and stored in the internal register of the VDP 109 (step S925), and the storage area setting process is terminated.

  FIG. 119 is a flowchart illustrating an example of the advance transfer process executed in step S905. In the advance transfer process, the drawing control unit 91 of the VDP 109 first specifies a read address of image data in the CGROM 83 from the data included in the advance transfer command (step S941). Subsequently, the write address of the image data in the fixed address area 155A of the VRAM 84 is specified from the data included in the advance transfer command (step S942). Further, the amount of image data to be transferred is specified from the data included in the advance transfer command (step S943). Then, based on the read address, the write address, and the data amount of the image data specified in steps S941 to S943, the data transfer start setting is performed to transfer the image data read from the CGROM 83 to the fixed address area 155A (step). S944). For example, in step S944, the drawing control unit 91 sets the image data amount as the read address of the CGROM 83, the write address of the VRAM 84, and the transfer data amount in a predetermined DMA device, and transfers the image data by DMA transfer. Instruct the start.

  Thereafter, the drawing control unit 91 determines whether or not the transfer of the image data is completed (step S945). If not completed (N in step S945), the drawing control unit 91 repeats the process of step S945 and waits. On the other hand, if it is determined in step S945 that the transfer of image data has been completed based on, for example, the output of a predetermined transfer completion signal from the DMA device (Y in step S945), all the index tables included in the VDP 109 are included. Is registered (step S946), and the pre-transfer processing is terminated. In the process of step S946, the drawing control unit 91 writes data such as “start address” and “horizontal size” that can identify the image data transferred to the fixed address area 155A in the index table, and the corresponding “transfer”. Set “completion flag” to “on”.

  FIG. 120 is a flowchart illustrating an example of the automatic transfer process executed in step S907. In the automatic transfer process, the drawing control unit 91 of the VDP 109 first specifies the read address of the image data in the CGROM 83 from the data included in the automatic transfer display command (step S961). Subsequently, the writing address of the image data in the automatic transfer area 155B of the VRAM 84 is specified (step S962). For example, in the process of step S962, the drawing control unit 91 refers to the index table, and in the automatic transfer area 155B, the “transfer completion flag” is “on” and valid image data is stored. Identify free areas other than areas. Of the vacant areas thus identified, an area for storing the image data to be transferred this time is determined, and the head address thereof is identified as the write address.

  Subsequently, the drawing control unit 91 identifies the amount of image data to be transferred from the data included in the automatic transfer display command (step S963). Then, based on the read address, write address, and data amount of the image data specified in steps S961 to S963, data transfer start setting is performed to transfer the image data read from the CGROM 83 to the automatic transfer area 155B (step). S964). For example, in step S964, the drawing control unit 91 sets the image data amount as the read address of the CGROM 83, the write address of the VRAM 84, and the transfer data amount in a predetermined DMA device, and transfers the image data by DMA transfer. Instruct the start.

  Thereafter, the drawing control unit 91 determines whether or not the transfer of the image data has been completed (step S965). If not completed (N in step S965), the drawing control unit 91 repeats the process of step S965 and waits. On the other hand, if it is determined in step S965 that the transfer of image data has been completed based on, for example, a predetermined transfer completion signal output from the DMA device (Y in step S965), all the index tables provided in the VDP 109 are included. After the completion of the transfer of the image data of the part image is registered (step S966), the automatic transfer process is terminated. In the process of step S966, the drawing control unit 91 writes data such as “start address” and “horizontal size” that can identify the image data transferred to the automatic transfer area 155B in the index table, and the corresponding “transfer”. Set “completion flag” to “on”.

  FIG. 121 is a flowchart illustrating an example of a drawing process executed by the VDP 109. In the drawing process, the drawing control unit 91 of the VDP 109 first determines whether or not there is a command serving as a display control command received from the symbol control CPU 101a via the CPU I / F 92 (step S1001). If there is no received command from the symbol control CPU 101a (N in step S1001), the process of step S1001 is repeatedly executed and awaits.

  If there is a reception command in step S1001 (Y in step S1001), it is determined whether or not the reception command is a fixed address designation display command (step S1002). If it is a fixed address designation display command (Y in step S1002), a predetermined fixed address designation display process is executed (step S1003), but if it is not a fixed address designation display command (N in step S1002), a received command Is an automatic transfer display command (step S1004).

  If the received command is an automatic transfer display command in step S1004 (Y in step S1004), a predetermined automatic transfer display process is executed (step S1005), but if it is not an automatic transfer display command (N in step S1004), It is determined whether or not the received command is an alpha value distribution setting command (step S1006). If the received command is an alpha value distribution setting command in step S1006 (Y in step S1006), a predetermined alpha test drawing process is executed (step S1007), but not an alpha value distribution setting command (in step S1006). N) It is determined whether or not the received command is a test execution command (step S1008).

  If the received command is a test execution command in step S1008 (Y in step S1008), a predetermined alpha test process is executed (step S1009), but if it is not a test execution command (N in step S1008), the received command is It is determined whether the command is an alpha synthesis command (step S1010). If the received command is an alpha synthesis command in step S1010 (Y in step S1010), a predetermined alpha synthesis process is executed (step S1011). If the received command is not an alpha synthesis command in step S1010 (N in step S1010), or after executing the process of step S1111, the process returns to step S1101.

  FIG. 122 is a flowchart showing an example of the fixed address designation display process executed in step S1003. In the fixed address designation display process, the drawing control unit 91 of the VDP 109 first specifies the read address of the image data in the fixed address area 155A of the VRAM 84 from the data included in the fixed address designation display command (step S1021). Subsequently, the index table is referred to based on the read address specified in step S1021, and it is determined whether or not the “transfer completion flag” associated with the image data to be read is “ON” (step S1021). S1022).

  If the “transfer completion flag” is “ON” in step S1022 (Y in step S1022), the writing address of the image data in the frame buffer 156 is specified from the data included in the fixed address designation display command. The image data write address in the temporary development area 155C is specified from the image data write address in the frame buffer 156 (step S1023). At this time, each of the frame buffer 156 and the temporary development area 155C is a display area for one screen in the variable display device 9, and the address is shifted (shifted) by a predetermined position. The area size is the same. Therefore, the drawing control unit 91 can easily specify the image data write address in the temporary development area 155C from the image data write address in the frame buffer 156.

  Thereafter, the drawing control unit 91 reads the image data from the read address specified in step S1021 and writes the image data in the write address specified in step S1023 (step S1024). Then, it is determined whether or not the drawing by writing the image data in the temporary development area 155C is completed (step S1025). If not completed (N in step S1025), the read address and the write address are updated. (Step S1026), the process returns to Step S1024. On the other hand, if the drawing is completed in step S1025 (Y in step S1025), the fixed address designation display process is terminated.

  Although not shown in FIG. 122, when the alpha test process or the alpha synthesis process is not executed, the image data written in the temporary development area 155C in step S1024 is copied from the temporary development area 155C to the frame buffer 156. By doing so, the display data (image data not subjected to alpha test processing or alpha synthesis processing) is updated. Then, the display data copied to the frame buffer 156 is read from the frame buffer 156 by the display signal control unit 87, converted into gradation data, and output to the variable display device 9. As a result, it is displayed on the screen of the variable display device 9. On the other hand, when alpha test processing or alpha synthesis processing is executed, the image data written in the temporary development area 155C in steps S1113 and S1124 described later is displayed by copying it from the temporary development area 155C to the frame buffer 156. Data (image data after execution of alpha test processing and alpha synthesis processing) is updated. When the VRAM 84 is not provided with the temporary development area 155C, or when the alpha test process or the alpha synthesis process is not executed, for example, the image data read from the fixed address area 155A in step S1024 is written into the temporary development area 155C. You may make it write in the frame buffer 156 directly, without performing a process.

  If the “transfer completion flag” is “OFF” in step S1022 (No in step S1022), it is determined whether a predetermined transfer completion waiting time has elapsed (step S1027). At this time, if the transfer completion waiting time has not elapsed (N in step S1027), the process returns to step S1022 and waits. On the other hand, when the transfer completion waiting time has elapsed in step S1027 (Y in step S1027), for example, by transmitting predetermined error information to the symbol control CPU 101a via the CPU I / F 92, etc. After notifying that an error has occurred (step S1028), the fixed address designation display process is terminated. When receiving the error information from the VDP 109, the symbol control CPU 101a performs control for notifying that an error state has occurred, for example, displaying an error screen or sending an error command to the sound / lamp control CPU 101b. Control for lighting a lamp or the like with a predetermined lighting pattern is executed. The same applies to step S1049 described later.

  FIG. 123 is a flowchart illustrating an example of the automatic transfer display process executed in step S1005. In the automatic transfer display process, the drawing control unit 91 first specifies the read address of the image data in the automatic transfer area 155B of the VRAM 84 from the data included in the automatic transfer display command (step S1041). Subsequently, the index table is referred to based on the read address identified in step S1041, and it is determined whether or not the “transfer completion flag” associated with the image data to be read is “ON” (step). S1042).

  If the “transfer completion flag” is “ON” in step S1042 (Y in step S1042), the write address of the image data in the frame buffer 156 is specified from the data included in the automatic transfer display command, and From the image data write address in the frame buffer 156, the image data write address in the temporary development area 155C is specified (step S1043). Thereafter, the drawing control unit 91 reads the image data from the read address specified in step S1041, and writes it to the write address specified in step S1043 (step S1044). Then, it is determined whether or not the drawing by writing the image data in the temporary development area 155C is completed (step S1045). If not completed (N in step S1045), the read address and the write address are updated. (Step S1046), the process returns to Step S1044. On the other hand, if drawing is completed in step S1045 (Y in step S1045), the “transfer completion flag” registered in the index table in association with the image data used for drawing is cleared to “off” ( In step S1047), the automatic transfer display process is terminated.

  Although not shown in FIG. 123, when the alpha test process or the alpha synthesis process is not executed, the image data written in the temporary development area 155C in step S1044 is copied from the temporary development area 155C to the frame buffer 156. By doing so, the display data (image data not subjected to alpha test processing or alpha synthesis processing) is updated. Then, the display data copied to the frame buffer 156 is read from the frame buffer 156 by the display signal control unit 87, converted into gradation data, and output to the variable display device 9. As a result, it is displayed on the screen of the variable display device 9. On the other hand, when alpha test processing or alpha synthesis processing is executed, the image data written in the temporary development area 155C in steps S1113 and S1124 described later is displayed by copying it from the temporary development area 155C to the frame buffer 156. Data (image data after execution of alpha test processing and alpha synthesis processing) is updated. When the VRAM 84 is not provided with the temporary development area 155C, or when the alpha test process or the alpha synthesis process is not executed, a process of writing the image data read from the automatic transfer area 155B in the temporary development area 155C in step S1044. You may make it write in the frame buffer 156 directly, without performing.

  If the “transfer completion flag” is “OFF” in step S1042 (N in step S1042), it is determined whether a predetermined transfer completion waiting time has elapsed (step S1048). At this time, if the transfer completion waiting time has not elapsed (N in Step S1048), the process returns to Step S1042 and waits. On the other hand, when the transfer completion waiting time has elapsed in step S1048 (Y in step S1048), for example, by transmitting predetermined error information to the symbol control CPU 101a via the CPU I / F 92. After notifying that an error has occurred (step S1049), the automatic transfer display process is terminated.

  FIG. 124A is a flowchart illustrating an example of alpha test drawing processing executed in step S1007. In the alpha test drawing process, the drawing control unit 91 specifies a decorative pattern to be displayed from the data included in the alpha value distribution setting command, and reads image data indicating the specified decorative pattern from the fixed address area 155A of the VRAM 84. Is written in the temporary expansion area 155C (step S1101). Subsequently, the drawing control unit 91 specifies the alpha value in each pixel included in the effect image indicating the decorative design from the data included in the alpha value distribution setting command, and the data indicating the specified alpha value is temporarily expanded in the region 155C. The alpha value of each pixel is set by writing to the address corresponding to each pixel in (Step S1102). Thus, the alpha test drawing process ends.

  FIG. 124B is a flowchart showing an example of the alpha test process executed in step S1009. In the alpha test process, the drawing control unit 91 identifies an alpha reference value from the data included in the test execution command, and executes a comparison operation between the identified alpha reference value and the alpha value of each pixel (step S1111). At this time, a pixel that satisfies the display condition “satisfied” by the comparison function specified from the data included in the test execution command is determined as a display target pixel to be displayed on the variable display device 9 (step S1112). . Then, after updating the display data (image data after the alpha test process) by copying the display target pixel determined in step S1112 from the temporary development region 155C to the frame buffer 156 (step S1113), End the alpha test process. The data indicating the pixel value of the display target pixel copied to the frame buffer 156 in this manner is read from the frame buffer 156 as updated display data, converted to grayscale data, and output to the variable display device 9. Is done. As a result, the display target pixel is displayed on the screen of the variable display device 9.

  FIG. 124C is a flowchart showing an example of the alpha synthesis process executed in step S1011. In the alpha compositing process, the drawing control unit 91 specifies a decorative symbol whose display order is earlier (for example, a decorative symbol indicating “6”) from the data included in the alpha combining command, and image data indicating the specified decorative symbol Is read from the fixed address area 155A of the VRAM 84, and then written to the temporary development area 155C at the enlargement ratio indicated by the enlargement ratio data specified from the data included in the alpha synthesis command (step S1121). Subsequently, the drawing control unit 91 blends the blend rate data specified from the data included in the alpha compositing command for the image data indicating the decoration pattern whose display order is written in the temporary development area 155C in step S1121. An alpha value corresponding to the rate is set (step S1122). For example, the blend rate specified based on the data included in the alpha synthesis command is written as an alpha value for each pixel of the effect image showing the decorative design whose display order is earlier in the address corresponding to each pixel in the temporary development region 155C.

  Thereafter, the drawing control unit 91 identifies a decorative symbol whose display order is later (for example, a decorative symbol indicating “7”) from the data included in the alpha synthesis command, and for the image data indicating the specified decorative symbol, After reading from the fixed address area 155A of the VRAM 84, the data included in the alpha compositing command based on the alpha value of each pixel stored in the temporary development area 155C and the blend rate specified from the data included in the alpha compositing command Is written in the temporary development area 155C at the enlargement rate indicated by the enlargement rate data specified from (step S1123). For example, in the processing of step S1123, the drawing control unit 91 sets the alpha value already written in the temporary development area 155C for the effect image A whose display order indicates the previous decorative pattern to α1, and the decorative pattern whose display order is the later. The blend ratio notified by the alpha composition command for the effect image B shown is α2, and the color data of each pixel is calculated as (color data of effect image A) × α1 + (color data of effect image B) × α2. To identify. The drawing control unit 91 synthesizes two consecutive decorative symbols by writing the color data of each pixel specified in this way into the temporary development area 155C, and the like, and displays image data indicating a composite image in which the two decorative symbols overlap. create.

  After executing the processing of step S1123, the display data (image data after the alpha synthesis processing) is updated by copying the storage data of the temporary development area 155C to the frame buffer 156 (step S1124), and then alpha. The synthesis process ends. The data thus copied to the frame buffer 156 is read from the frame buffer 156 as updated display data by the display signal control unit 87, converted into gradation data, and output to the variable display device 9. . As a result, a composite image in which two decorative designs are synthesized and two decorative designs overlap is displayed on the screen of the variable display device 9.

  Next, a specific application example of the alpha test process will be described.

  The image display of the decorative design with gradation shown in FIG. 91 is realized as follows. For example, the alpha value distribution setting data to be superimposed on the image data of the part image of the decorative design “7” is divided into the left region, the middle region, and the right region, and is alternately set to 0. 3 and 0.4 are set, 0.4 and 0.5 are alternately set as the alpha value α of adjacent pixels in the middle region, and 0.5 is alternately set as the alpha value of adjacent pixels in the right region. And 0.6 are set. Further, the alpha value distribution setting data to be superimposed on the image data of the component image of the decorative design “8” is divided into the left region, the middle region, and the right region, and alternately 0. 5 and 0.6 are set, 0.6 and 0.7 are alternately set as the alpha value α of adjacent pixels in the middle region, and 0.7 and 0.7 are alternately set as the alpha value of adjacent pixels in the right region. And 0.8 are set.

  Then, each time the number of processes is updated (see step S708), the symbol control CPU 101a gradually changes the value of the alpha reference value (test value) to be compared with the alpha value (see step S709). . Here, the comparison function for comparing the alpha value α set to the image data of the decorative design “7” and the alpha reference value (test value) is a function that is established if the alpha value α is equal to or greater than the alpha reference value. Yes, the comparison function for comparing the alpha value α set in the image data of the decorative design “8” with the alpha reference value (test value) is a function that is established if the alpha value α is equal to or less than the alpha reference value. Shall.

  When the alpha reference value is 0.3 or less, since the alpha values of the pixels in the entire area “7” are equal to or greater than the alpha reference value, the entire area “7” is displayed. Since the alpha values of the pixels in the entire area are equal to or greater than the alpha reference value, the entire area “8” is erased. When the alpha reference value is a value between 0.3 and 0.4, the alpha value of half the pixels (every other pixel) in the left region of “7” is equal to or less than the alpha reference value. Since the alpha value of the other half of the pixel in the left region of “7” is equal to or greater than the alpha reference value, the left region of “7” is displayed in a light color, and the alpha value of the pixels in the middle region and right region of “7” Is equal to or greater than the alpha reference value, the middle region and the right region of “7” are displayed. Further, since the alpha values of the pixels in the entire area “8” are equal to or greater than the alpha reference value, the entire area “8” is deleted. When the alpha reference value is a value between 0.4 and 0.5, the alpha value of the pixel in the left region of “7” is equal to or less than the alpha reference value, so the left region of “7” is erased. Since the alpha value of the half pixel in the middle region of “7” is less than or equal to the alpha reference value, and the alpha value of the other half pixel of the middle region of “7” is greater than or equal to the alpha reference value, Since the middle region of “7” is displayed in a light color and the alpha value of the pixel in the right region of “7” is greater than or equal to the alpha reference value, the right region of “7” is displayed. Further, since the alpha values of the pixels in the entire area “8” are equal to or greater than the alpha reference value, the entire area “8” is deleted.

  Further, when the alpha reference value is a value between 0.5 and 0.6, the alpha values of the pixels in the left region and the middle region of “7” are less than or equal to the alpha reference value. The area and the middle area will be erased, the alpha value of the half pixel in the right area of “7” is less than or equal to the alpha reference value, and the alpha value of the other half pixel of the right area of “7” is the alpha reference. Since the value is greater than or equal to the value, the right region of “7” is displayed in a light color. Further, since the alpha value of the half pixel in the left region of “8” is equal to or greater than the alpha reference value, and the alpha value of the other half pixel of the left region of “8” is equal to or less than the alpha reference value, The left area will be displayed in a light color, and since the alpha values of the pixels in the middle area and right area of “8” are greater than or equal to the alpha reference value, the middle area and right area of “8” will be erased. become.

  Further, when the alpha reference value is a value between 0.6 and 0.7, the alpha value of the pixels in the entire area “7” is equal to or less than the alpha reference value, and therefore the entire area “7” is erased. Will be. Further, since the alpha value of the pixel in the left region of “8” is less than or equal to the alpha reference value, the left region of “8” is displayed, and the alpha value of the half pixel in the middle region of “8” is Since the alpha value of the other half of the middle region of “8” is equal to or smaller than the alpha reference value, the middle region of “8” is displayed in a light color. Since the alpha value of the pixel in the right region is equal to or greater than the alpha reference value, the right region of “8” is deleted.

  Further, when the alpha reference value is a value between 0.7 and 0.8, the alpha value of the pixels in the entire area “7” is equal to or less than the alpha reference value, and therefore, the entire area “7” is erased. Will be. Further, since the alpha values of the pixels in the left and middle areas of “8” are less than or equal to the alpha reference value, the left and middle areas of “8” are displayed, and half of the right area of “8”. Since the alpha value of the pixel of “8” is equal to or greater than the alpha reference value and the alpha value of the other half of the pixel of “8” is less than the alpha reference value, the right region of “8” is displayed in a light color. become.

  With the above processing, the image display as shown in FIGS. 91C to 91H is realized.

  Further, the image display of the notice effect character shown in FIG. 94 is realized as follows, for example. The symbol control CPU 101a executes the alpha test display command process (step S693) when executing the preview effect for performing the alpha test process (Y in step S692) during the preview effect execution period (Y in step S691). To do. In the alpha test display command processing, the symbol control CPU 101a specifies alpha value distribution setting data for setting an alpha value in the character image to be displayed in the notice effect (step S716), and an alpha value distribution indicating the data A setting command is transmitted to the VDP 109 (step S717). Further, the preset alpha reference value is updated every time the chance button 300 is pressed within the button valid period (steps S712 to S715), and the alpha reference value and the comparison function are determined, Is transmitted to the VDP 109 (steps S718 and S710). In addition, the symbol control CPU 101a specifies a character part image to be displayed in the notice effect in various update target command processes (step S696) (step S741), and automatically instructs to transfer image data of the part image. A transfer display command is transmitted to the VDP 109 (step S750).

  Based on reception of the automatic transfer display command, the VDP 109 transfers character image data from the CGROM 83 to the automatic transfer area 155B of the VRAM 84 in an automatic transfer control process (step S907). Further, based on the reception of the alpha value distribution setting command, the alpha test drawing process (step S1007) is executed on the image data of the character specified by the command (already stored in the automatic transfer area 155B). At this time, the automatic transfer display process (step S1005) is not executed on the character image data. In the alpha test drawing process, the VDP 109 writes the character image data stored in the automatic transfer area 155B to the temporary development area 155C and sets the alpha value of each pixel (steps S1101 and S1102). Subsequently, based on the reception of the test execution command, the VDP 109 executes alpha test processing (step S1009). Specifically, the following processing is performed.

  For example, as an alpha value of each pixel of a human character image, a pixel with an alpha value of 0.2, a pixel with an alpha value of 0.4, and a pixel with an alpha value of 0.6 are arranged in order in the vertical and horizontal directions. Set the alpha value of each pixel to. Then, the symbol control CPU 101a, based on the content of the test execution command, sets an alpha reference value (test value) set to 0.7 in advance every time the chance button 300 is turned on in step S1847. Update from 0.7 to 0.5, update from 0.5 to 0.3, and update from 0.3 to 0.1.

  When the alpha value and the alpha reference value (test value) are compared in step S1111, the test value is 0.7 before the chance button 300 is pressed, so that the alpha value of each pixel of the character image is all alpha. Below the reference value. At this time, if the comparison function is established if the alpha value is equal to or greater than the alpha reference value, it is determined that the color data of all the pixels of the character image is not drawn in the drawing area (not a display target pixel) (step S1112). ). Therefore, no character image is displayed.

  When the chance button 300 is pressed once, the test value is updated from 0.7 to 0.5, so that only one third of the pixels of the character image become the alpha reference value or more. Accordingly, it is determined that the color data of 1/3 of the character image is drawn in the drawing area (step S1112). Therefore, only 1/3 of the character image is displayed (2/3 pixels are thinned out and not displayed). At this time, the character image is slightly displayed on the display screen.

  When the chance button 300 is pressed twice, the test value is updated from 0.5 to 0.3, so that 2/3 of the pixels of the character image are equal to or greater than the alpha reference value. Accordingly, it is determined that the color data of 2/3 of the pixels of the character image is drawn in the drawing area (step S1112). Therefore, 2/3 pixels of the character image are displayed. At this time, the character image is displayed slightly darker on the display screen.

  When the chance button 300 is pressed three times, the test value is updated from 0.3 to 0.1, so that the alpha value of each pixel of the character image is all equal to or greater than the alpha reference value. Therefore, it is determined that the color data of all the pixels of the character image is drawn in the drawing area (step S1112). Therefore, the character image is completely displayed.

  Next, alpha composition (alpha blend processing) will be described. Alpha composition is to compose two images A and B on the VRAM 84 using the following mathematical formula.

  Color data of image A × (1.0−α) + Color data of image B × α

  Here, α is the blend ratio (transparency) of the image B.

  For example, when the color of the image A is yellow, the color data of the image A is (rgb: 1.0, 1.0, 0.0), and the color of the image B is blue with a sky blue color. The color data of the image B is (rgb: 0.0, 0.5, 1.0). When the blend ratio (transparency) of the image B is 0.5, α = 0.5. Substituting these values into the above formula, rgb (1.0, 1.0, 0.0) × (1.0−0.5) + rgb (0.0, 0.5, 1.0) × 0.5 = rgb (0.5, 0.5, 0.0) × (rgb: 0.0, 0.25, 0.5) = rgb (0.5, 0.75, 0.5) Become.

  Translucent (blend rate α = 0.5) image A (yellow (rgb: 1.0, 1.0, 0.0)) and translucent (blend rate α = 0.5) image B (sky blue) (Blue, rgb: 0.0, 0.5, 1.0)) is a superimposed color (yellowish translucent sky blue (0.5, 0.75, 0.5)).

  In the example shown in FIG. 125, the blend rate of the image data of the decorative design “6” at the elapsed time T1 is 0.8, and the blend rate of the image data of the decorative design “7” is 0.2. The enlargement rate of the image data of the decorative design “6” is 1, and the enlargement rate of the image data of the decorative design “7” is 0.8. At this time, the color of the image of the decorative design “6” is green (rgb: 0.0, 1.0, 0.0), and the color of the image of the decorative design “7” is red (rgb: 1.0, 0). .0, 0.0), the composite image is an image in which the image of the full-size decorative pattern “6” and the decorative pattern “7” reduced to one fifth of the size overlap. The color of the overlapped part is a slightly yellowish green (rgb: 0.2, 0.8, or a mixture of green whose transparency is reduced to 0.8 and red whose transparency is reduced to 0.2. 0.0). In addition, the color of the non-overlapping portion of the decorative design “6” is green (rgb: 0.0, 0.8, 0.0) whose transparency is reduced to 0.8, and the decorative design “7” is overlapped. The color of the part which is not is red (rgb: 0.2, 0.0, 0.0) whose transparency is reduced to 0.2. Thus, the blend ratio indicates the transparency α value in alpha synthesis of the image. In this embodiment, each of the R, G, and B signals is expressed in 256 levels of voltage (8 bits). In addition, although the portions other than the decorative symbols “6” and “7” are transparent, an image of a background color specified separately may be displayed.

  As described above, in this embodiment, the random number circuit 503 is initially set (random number circuit setting process) from the start of power-on to the gaming machine until the timer interrupt is set, and the random number circuit In the setting process, a value based on the ID number unique to the game control microcomputer 560 is set as the initial value of the random number. Therefore, the randomness of the random number generated by the random number circuit 503 can be improved. In addition, since randomness of random numbers can be improved, the timing of random number generation can be made difficult to be recognized by a player or a game store, and a capture signal using a radio signal can be generated for a gaming machine. It is possible to prevent the condition for shifting to a specific gaming state such as a big hit state from being illegally established.

  In this embodiment, a software random number is used as a determination random number for determining a jackpot type (a jackpot type determining random number) among the random numbers used in the game control process. Then, only the big hit determination random number for determining whether or not to win is generated using the random number circuit 503. For example, if a random number circuit 503 is used to generate a big hit type determination random number in addition to the big hit determination random number, a random number circuit 503 is used to generate a plurality of types of random numbers. It becomes more complicated than necessary. In this embodiment, since only the big hit determination random number is generated using the random number circuit 503, it is possible to prevent the circuit configuration of the random number circuit 503 from becoming complicated.

  Also, in this embodiment, when the serial communication circuit 505 makes an interrupt request, the interrupt process when a communication error is caused as an interrupt cause is preferentially executed to control the communication to a prohibited state. Therefore, it is possible to prevent communication with the payout control microcomputer 370 of the payout control board 37 mounted on the gaming machine in a state where a communication error has occurred. Therefore, malfunction due to a communication error can be prevented.

  For example, when an overrun occurs in the serial communication circuit 505, the next received data is stored in the receiving shift register 713 before the received data in the received data register 711 is read. It is overwritten and the CPU 56 cannot read the received data correctly. For this reason, communication with the microcomputer mounted on each control board cannot be performed correctly, causing the game control microcomputer 560 to malfunction. In this embodiment, when an overrun occurs, the serial communication circuit 505 makes an interrupt request at the time of a communication error, and the CPU 56 controls the communication to a prohibited state. Therefore, it is possible to prevent the gaming control microcomputer 560 from malfunctioning due to the occurrence of overrun.

  Further, for example, when a noise error occurs in the serial communication circuit 505, there is a high possibility that correct received data cannot be received due to the noise, which causes the CPU 56 to malfunction. In this embodiment, when a noise error occurs, the serial communication circuit 505 issues an interrupt request at the time of a communication error, and the CPU 56 controls the communication to a prohibited state. Therefore, it is possible to prevent the CPU 56 from malfunctioning due to the occurrence of a noise error.

  Further, for example, when a framing error occurs in the serial communication circuit 505, it is in a state where the stop bit of the received data has not been correctly received. . In this embodiment, when a framing error occurs, the serial communication circuit 505 issues an interrupt request at the time of a communication error, and the CPU 56 controls the communication to a prohibited state. Therefore, it is possible to prevent the CPU 56 from malfunctioning due to the occurrence of a framing error.

  Further, for example, when a parity error occurs in the serial communication circuit 505, it is in a state where each data bit or parity bit of the received data has not been correctly received, so there is a high possibility that correct received data cannot be received, and the CPU 56 malfunctions. Cause. In this embodiment, when a parity error occurs, the serial communication circuit 505 makes an interrupt request at the time of a communication error, and the CPU 56 controls the communication to a prohibited state. Therefore, it is possible to prevent the CPU 56 from malfunctioning due to the occurrence of a parity error.

  In this embodiment, when a communication error occurs in the serial communication circuit 505, a prize ball number command is transmitted to the payout control microcomputer 370 mounted on the payout control board 37, and the payout control microcomputer 370 receives the command. Control is performed to prohibit the reception of a prize ball ACK command. For example, if a prize ball number command is transmitted to the payout control microcomputer 370 mounted on the payout control board 37 when a communication error occurs, an incorrect prize ball number command may be transmitted. Therefore, an incorrect number of game balls may be paid out based on the number of prize balls indicated in the wrong prize ball number command, which may affect the game result. In this embodiment, when a communication error occurs, control is performed so as to prohibit transmission of a prize ball number command to the payout control microcomputer 370 mounted on the payout control board 37, so that it is based on an erroneous prize ball command. It is possible to prevent an incorrect number of game balls from being paid out and affecting the game result.

  Note that when a communication error occurs in the serial communication circuit 505, only reception of data from a microcomputer mounted on each control board may be prevented. For example, consider a case where serial communication is performed between the game control means and the effect control means. In this case, the communication performed between the game control microcomputer 560 and the effect control microcomputer is only the transmission of the effect control command from the game control microcomputer 560 to the effect control microcomputer. No command is transmitted from the microcomputer to the game control microcomputer 560. That is, communication in only one direction is performed between the game control microcomputer 560 and the effect control microcomputer. Further, even if an erroneous effect control command is transmitted from the game control microcomputer 560 to the sound / lamp control board 80b, an erroneous effect display is only performed on the variable display device 9, and an incorrect payout process is performed. Compared with the case where the game is executed, the influence on the game result is small.

  In this embodiment, the inverting circuit 532 of the random number circuit 503 generates the inverted clock signal SI2 (or the delayed clock signal delayed by the delay circuit) whose polarity is inverted, and is synchronized with the inverted clock signal SI2. A latch signal for instructing random number storage is output. Therefore, the timing for updating the random number and the timing for storing the random number in the random value storage circuit 531 can be shifted, and the generated random number can be stored stably and reliably.

  In this embodiment, the expression “the serial communication circuit 505 issues an interrupt request to the CPU 56” is used. Specifically, when an interrupt factor such as transmission / reception of data or occurrence of a communication error occurs. In addition, the interrupt control circuit 714 of the serial communication circuit 505 sets a set value to a corresponding bit (bit corresponding to an interrupt factor) of the status register A 705 and outputs an interrupt signal (internal IRQ) to the CPU 56. An interrupt request is made by the serial communication circuit 505. For example, when a communication error occurs, the interrupt control circuit 714 of the serial communication circuit 505 sets a set value in a corresponding bit (bits 0 to 3 corresponding to the communication error) of the status register A 705 and also sends an interrupt signal to the CPU 56. Is output, the serial communication circuit 505 issues an interrupt request when a communication error occurs.

  Further, the CPU 56 is configured to check the power-off signal in the main processing, and when the power-off signal is not in the OFF state, the CPU 56 is configured to check the power-off signal again after a predetermined time (timeout time). The state of the power-off signal can be monitored while the target voltage is stable. Since the power-off signal is monitored after a predetermined period without specially providing software processing or hardware circuitry, the program capacity is not increased and the cost of providing special circuitry is also provided. A configuration for monitoring a power-off signal after a predetermined period can be realized without applying the above.

  Further, when the power-off signal is turned on, a power-off process (power supply stop process) is executed, and in the power supply stop process, the data stored in the RAM 55 is used as data for restoring the control state. The check data is created and stored in the RAM 55. Then, when the power supply is resumed, it is determined whether or not the storage content of the RAM 55 is normal based on the check data stored in the RAM 55. On the condition that it is determined that the power is normal, Based on the stored contents of the RAM 55, a recovery process for restoring the control state to the state before stopping the power supply is executed. Therefore, the control state can be restored based on the normal stored contents stored in the RAM 55.

  Further, since the software delay process is executed in a part of the main process when the power supply is started, the microcomputer on the control board other than the main board 31 can be controlled earlier. Can be. As a result, it is possible to prevent a situation in which a microcomputer other than the game control microcomputer 560 misses a command from the game control microcomputer 560. Therefore, the effect control microcomputer (such as the symbol control CPU 101a) can reliably receive the restoration command and the effect control command, and can reliably execute the game effect from the game state when the power supply is stopped. In addition, since the payout control microcomputer 370 can reliably receive the prize ball command, the prize ball to be paid out can be surely paid out.

  In addition, since the process of confirming the power-off signal is performed during the software delay process, it is possible to prevent the stored contents of the RAM 55 from being destroyed and the control state from being restored to the state when the power supply is stopped. it can. In other words, if the power supply is started and VSL rises to + 22V or higher before or during execution of the software delay process, and the power supply is stopped during the software delay process, the power supply is interrupted during the software delay process. If the signal is not confirmed, a checksum is generated in the power-off process (step S18; the power-off process executed in the timer interrupt process) executed after the software delay process. Thus, it may happen that the power supply is completely stopped before (or without saving) the process of saving the data in the RAM 55. However, if the configuration that performs the process of checking the power-off signal during the software delay process, it can recognize that the power-off signal has been turned on in response to a decrease in the power-supply voltage, and the power-off signal can be turned on. When the state is confirmed, the state is shifted to a standby state (infinite loop). At this time, since the RAM 55 is not yet set to be accessible (see step S6), even if the power supply is completely stopped in the standby state, the stored contents of the RAM 55 are not destroyed. Therefore, the data in the RAM 55 can be reliably protected.

  In addition, when the number of changes after the transition to the probable change state reaches 100, it is configured to control the game state as a high probability latent state, so whether or not the player continues the high probability state You can be interested in how. In addition, when the power supply is recovered from the power failure state, the game control microcomputer 560 is connected to the production microcomputer (the sound / lamp control microcomputer 100b and the symbol control microcomputer 100a) in the main process. The normal display command, special display command, and high-probability latent display command are transmitted as a recovery command for restoring the control state, and the production microcomputer performs a game production according to the game state based on the restoration command. Since it is comprised so that it may perform, the game production according to the game state before a power failure can be performed by the production | presentation microcomputer, and it can avoid giving distrust to a player. Further, even if an illegal act that intentionally stops the power supply is performed, the high-latency state is not realized by an unauthorized person when the power supply is restored.

  The production microcomputer determines the game state based on the variation pattern command and stores the current game state as a result of the determination in a predetermined storage area. However, when a power failure occurs, the production microcomputer Since the RAM in the computer is not backed up, it is necessary for the game control microcomputer 560 to transmit a recovery command to the production microcomputer when the power supply is restored. In the above embodiment, the production microcomputer determines the gaming state based on the variation pattern command. However, the present invention is not limited to such a configuration. For example, the gaming state is changed (transferred). The game control microcomputer 560 may transmit a command indicating a change in the game state to the effect microcomputer each time.

  In addition, when two big prize openings are provided and a big hit game is executed, one of the two big prize openings is opened, and before the big prize opening is opened, The player is informed of whether or not the special prize opening is to be opened by a special prize opening indicator light, and is also informed to the player by using an effect device such as the variable display device 9. Therefore, it is possible to prevent the player from receiving a disadvantage because he / she cannot recognize which of the big winning openings is opened.

  Also, the symbol control CPU 101a instructs to transfer image data (image data that is not frequently used) from the CGROM 83 to the automatic transfer area 155B of the VRAM 84, and to transfer image data from the automatic transfer area 155B of the VRAM 84 to the frame buffer 156. If the VDP 109 is configured so that the symbol control CPU 101a has to instruct the VDP 109 twice, the control burden increases. However, in this embodiment, for image data that is infrequently used, the symbol control CPU 101a automatically designates the read address of the CGROM 83 and the write address of the frame buffer 156 once, and the VDP 109 automatically changes from the CGROM 83. Since image data is transferred to the VRAM 84 and image data is transferred (written) from the automatic transfer area 155B of the VRAM 84 to the frame buffer 156, the control burden on the symbol control CPU 101a is reduced. Further, when all image data is configured to be automatically transferred as described above, the control load on the symbol control CPU 101a is reduced, but frequently used image data is transferred from the CGROM 83 to the VRAM 84. It is transferred frequently and wasteful processing increases. However, according to this embodiment, since frequently used image data does not need to be transferred from the CGROM 83 to the VRAM 84, it is possible to reduce the control burden on the symbol control CPU 101a and prevent unnecessary processing from being executed. it can.

  Note that the timing for notifying which jackpot opening will be opened by the jackpot indicator light is the timing at which the jackpot symbol is stopped, but this is not the only configuration, and the jackpot opening is open. It may be just before being played or after the grand prize opening is opened (during opening). Also, which winning prize opening is opened by the presentation microcomputer notifying the type of jackpot using the presentation device (variable display device 9, lamp / LED, speaker 27) based on the fanfare command. However, it may be configured to notify which winning prize opening is opened based on an effect control command other than the fanfare command. For example, a decoration symbol stop designation command that can specify the type of jackpot (divided according to the type of jackpot), a display command during opening of the big prize opening, or a display command after opening the big prize opening is transmitted, and a micro for directing The computer may notify which jackpot is to be opened by notifying the type of jackpot immediately before opening the jackpot or after opening based on those effect control commands. In addition, the notification of which of the big winning openings is opened in correspondence with the type of the big hit is made, but the type of the big winning and the opening position of the big winning opening may not be made to correspond. In this case, the player is notified of the opening position of the big winning opening by a method such as displaying on the screen of the variable display device 9 which opening will be opened.

  Also, in the above embodiment, the big winning opening to be opened in advance is determined according to the type of the big hit, but every time a big hit occurs, the big winning opening to be opened is determined by a method such as using a random number. It may be configured. In addition, a different prize winning opening may be opened for each round, and in this case, the winning prize opening to be opened is determined by a method such as using a random number.

  In the above embodiment, the watchdog timer 60 is built in the game control microcomputer 560, but may be externally attached to the game control microcomputer 560. In this case, in the process of clearing the count value of the watchdog timer 60, a clear signal is output from the output port to the external watchdog timer instead of setting predetermined data in the WDT clear register 62. Just do it.

  In this embodiment, during the variable display of the decorative design, the decorative design is divided into a plurality of regions (for example, the left region, the middle region, and the right region), and the image data (color data) of the pixels in the divided regions The test value to be compared with the alpha value is changed in stages, the alpha value and the test value are compared, and each pixel is set according to the comparison result. It is configured to determine whether or not to draw, and to draw the image data of the pixel determined to be drawn in the frame buffer. Therefore, in the variable display of the decorative design, the decorative design image can be changed step by step with gradation, and the effect in the variable display of the decorative design can be improved.

  Also, as shown in FIG. 91, when a reach occurs, the expectation for the big hit can be enhanced by changing the image of the decorative symbol of the final stop symbol step by step with gradation, and the interest of the game can be enhanced. Can be improved.

  Also, as shown in FIGS. 91 to 93, when the decorative design displayed on the front is erased step by step, the next decorative design is displayed step by step from the erased location. As a result, the production effect can be improved, and the expectation for the specific game state can be enhanced particularly in the reach state.

  Also, as shown in FIG. 92, when a reach occurs, the decorative image of the final stop symbol is changed in stages with gradation, and the decorative image is enlarged / reduced, thereby producing a production effect. As well as improving, the expectation for jackpot can be further increased.

  In addition, a chance button 300 that can be operated by the player is provided, and a preview image is displayed step by step as shown in FIG. 94 each time the chance button 300 is pressed when the notice effect is executed. Therefore, the notice image is not displayed before the chance button 300 is pressed, and the notice image can be displayed so as to be cut in step by step each time the chance button 300 is pressed. Thus, the effect of the notice effect can be improved. In addition, since the cut-in display of such a preview image is realized by the alpha test process, it can be realized without requiring complicated control.

  In the above embodiment, when the image data stored in the fixed address area 155A or the automatic transfer area 155B of the VRAM 84 is temporarily expanded in the temporary expansion area 155C, an alpha value is set for each pixel of the image data. However, when the process of transferring the image data (the pre-transfer process of FIG. 119 and the automatic transfer control process of FIG. 120) is executed (when the image data is read from the CGROM 83 and transferred to the VRAM 84), each pixel of the image data Alternatively, an alpha value may be set to be expanded in the fixed address area 155A or the automatic transfer area 155B of the VRAM 84. In this case, since an alpha value has already been set for each pixel of the image data stored in the fixed address area 155A and the automatic transfer area 155B, the image data is stored in the frame buffer without temporarily expanding the image data in the temporary expansion area 155C. The image data may be directly developed. Such a configuration can be realized by specifying the write address of the frame buffer 156 in steps S1023 and S1043 and directly writing the image data in the frame buffer 156 in steps S1024 and S1044.

  Further, the alpha value is set in the image data (RGB color data) using the alpha value distribution setting data indicating the alpha value of each pixel of the component image stored in the CGROM 83. However, the symbol control CPU 101a designates the alpha value of each pixel of the component image, and the VDP 109 sets the alpha value of each pixel designated by the symbol control CPU 101a in the image data (RGB color data). Also good. Further, image data in which an alpha value is set in advance corresponding to the color data of each pixel may be stored in the CGROM 83. In this case, it is necessary to store a plurality of pieces of image data having different alpha values for image data of component images having the same color data for each pixel.

  In the above embodiment, the symbol control CPU 101a determines whether or not the part image to be updated is a part image for which image data is to be transferred in advance to the fixed address area 155A of the VRAM 84 in various target command processes. Is determined (step S742), and if it is a part image to be pre-transferred (Y in step S742), the readout address of the image data of the part image to be updated in the fixed address area 155A of the VRAM 84 is specified. The VDP 109 is designated (steps S743 and S746). However, the present invention is not limited to such a configuration, and regardless of whether or not the part image to be updated is a part image to be pre-transferred. CGRO is performed on the image data of all the update target component images (without executing step S742). Identify the read address of the image data of the update target part image in 83 specifies the VDP109 (step S747, S750) may be configured so. In this case, for example, when the image data is read from the CGROM 83 and stored in the fixed address area 155A in the advance transfer process, the VDP 109 associates the read address of the CGROM 83 with the write address of the fixed address area 155A. Remember it. In the automatic transfer control process, when the read address of the CGROM 83 is specified (step S961), it is determined whether or not there is a write address of the fixed address area 155A stored in association with the specified read address. If the write address exists, the image data is read from the write address in the fixed address area 155A and written in the temporary development area 155C in the automatic transfer display process (step S1044). In this case, the fixed address designation display process is not necessary. Therefore, the processing burden on the symbol control CPU 101a can be reduced.

  Further, when the image data is read from the CGROM 83 and stored in the automatic transfer area 155B in the automatic transfer control process, the VDP 109 stores the read address of the CGROM 83 and the write address of the automatic transfer area 155B in association with each other in the index table. In the subsequent automatic transfer control process, when the read address of CGROM 83 is specified (step S961), is there a write address of automatic transfer area 155B stored in association with the specified read address? If there is a write address, image data may be read from the write address in the automatic transfer area 155B and written in the temporary development area 155C in the automatic transfer display process (step S1044). . According to such a configuration, it is possible to reduce the burden of the transfer process from the CGROM 83 to the VRAM 84 for the low-frequency image data.

  In the above-described embodiment, the frame buffer 156 is provided as a predetermined storage area of the VRAM 84. However, a storage unit different from the VRAM 84 may be used. When the frame buffer 156 is a storage unit different from the VRAM 84, the temporary development area 155C provided as a predetermined storage area of the VRAM 84 is also provided in another storage unit provided with the frame buffer 156. May be.

  Note that the automatic transfer area 155B setting process of the VRAM 84 (storage area setting command process of step S772) is also performed before the execution of the preliminary transfer process (pre-transfer process based on steps S1814 and S1867) other than when the symbol control CPU 101a is activated. May be configured to execute. According to such a configuration, even when the register value indicating the start address or the end address of the automatic transfer area 155B is changed due to garbled data or the like, the register value can be restored. As a result, it is possible to prevent data that should be transferred to the automatic transfer area 155B from being transferred to the fixed address area 155A or the like.

  Further, it may be configured such that the types of decorative symbols are different between the normal gaming state (including the latent probability changing state) and the probability changing state. For example, in the normal gaming state, it may be a number symbol of “1” to “9”, and in the probability variation state, it may be an alphabetic symbol of “A” to “I”. In such a configuration, the symbol control CPU 101a confirms the gaming state at the time of the power failure based on the recovery command received when recovering from the power failure, and displays the image data of the decorative symbol corresponding to the confirmed gaming state. Perform pre-transfer control. Also, the symbol control CPU 101a receives the signal when the game state is restored from a power failure even when the background image is different between the normal gaming state (including the latent probability changing state) and the probability changing state. Based on the recovery command to be executed, a game state at the time of the occurrence of a power failure is confirmed, and control for pre-transferring background image data corresponding to the confirmed game state is executed.

Embodiment 2. FIG.
In the first embodiment, a sound / lamp control board 80b and a symbol control board 80a are provided as control boards on which a microcomputer for controlling the effect device is mounted, and the game control microcomputer 560 on the main board 31 performs sound / lamp control. An effect control command is transmitted to the sound / lamp control microcomputer 100b mounted on the substrate 80b, and the sound / lamp control microcomputer 100b controls the effect on the symbol control microcomputer 100a mounted on the symbol control board 80a. It was configured to send a command according to the command. However, in the second embodiment, the game control microcomputer 560 transmits an effect control command to the symbol control microcomputer 100a, and the symbol control microcomputer 100a uses the effect control command to the sound / lamp control microcomputer 100b. The corresponding command is transmitted.

  FIG. 126 is a block diagram showing another circuit configuration example of the relay board 77, the sound / lamp control board 80b, and the symbol control board 80a. When the circuit configuration shown in FIG. 126 is used, for example, the symbol control microcomputer 100a mounted on the symbol control board 80a follows the process similar to steps S1851 to S1856 based on the variation pattern command. Whether or not to perform, and the type of notice effect). Then, the symbol controlling microcomputer 100a causes the VDP 109 to perform a notice effect using the variable display device 9 in accordance with the determined effect contents. Further, the symbol control microcomputer 100a may generate an effect content designation command indicating the determined effect content and transmit it to the sound / lamp control board 80b. The sound / lamp control microcomputer 100b mounted on the sound / lamp control board 80b performs display control of the lamps 25, 28a, 28b, 28c in accordance with the contents of the effect indicated by the received effect content designation command. Sound output control of the sound output device 27 may be performed.

  Moreover, in this embodiment, the case where the sound / lamp control board 80b and the symbol control board 80a are used as the case where each effector is controlled using separate control boards has been described. Each effect device may be controlled using. For example, each rendering device may be controlled using a sound control board that controls the sound output device 27, a lamp control board that controls each lamp, and a symbol control board that controls the variable display device 9. In this case, for example, the effect control command from the main board 31 is first received by the sound control board, and the sound control microcomputer mounted on the sound control board receives the effect contents (notice effect) based on the received variation pattern command. Or the type of the notice effect) may be determined (a process having the same contents as the process shown in FIG. 88). Then, the sound control microcomputer may transmit a command indicating the determined production contents to the lamp control board and the symbol control board (configuration to transmit to the symbol control board via the lamp control board or the symbol control board) Including a configuration of transmitting to the lamp control board via Further, each effect device may be controlled using a sound / symbol control board for controlling the sound output device 27 and the variable display device 9 and a lamp control board for controlling each lamp. In this case, for example, an effect control command from the main board 31 is received by the sound / symbol control board, and the sound / symbol control microcomputer mounted on the sound / symbol control board is based on the received variation pattern command. The contents of the effect may be determined (a process having the same contents as the process shown in FIG. 88). Then, the sound / symbol control microcomputer may transmit a command indicating the determined effect to the lamp control board. Note that the present invention is not limited to the combination of the above control boards, and a configuration in which an effect control command is transmitted from the main board 31 to the lamp control board, and a command is transmitted from the lamp control board to the sound / symbol control board. Also good.

  In addition, the sound control microcomputer specifies the number of decorative symbol shifts based on the display result designation command, and the decorative symbol variation time based on the basic time indicated by the variation pattern command and the decorative symbol shift number. May be specified. Then, the sound control microcomputer may generate a command including the determined content of the effect and the variation time (or add it to the effect control command) and transmit it to the lamp control board or the symbol control board. The production control command from the main board 31 is first received by the lamp control board or the design control board, and the microcomputer mounted on the lamp control board or the design control board determines the production contents or specifies the variation time. Also good.

Embodiment 3 FIG.
In each of the embodiments described above, the case where the CPU 56 executes the interrupt process at the time of a communication error with priority over other interrupt processes has been described. However, interrupt processes other than the interrupt process at the time of a communication error ( For example, priority may be given to interrupt processing at the time of reception. Hereinafter, a third embodiment in which interrupt processing at the time of reception is preferentially executed will be described.

  In the present embodiment, detailed description of the parts having the same configuration and processing as those in the first embodiment will be omitted, and parts different from those in the first embodiment will be mainly described.

  In this embodiment, the CPU 56 executes the main process according to the same process as in FIG. 46 and FIG. In the main process, the processes from Step S1 to Step S15b (including the processes from Steps S81 to S90 and S91 to S93) are the same as those shown in the first embodiment. Further, the processes from step S16 to step S20 are the same as those shown in the first embodiment.

  When the serial communication circuit setting process in step S15b is executed and the serial communication circuit 505 is initialized, the CPU 56 initializes the priority of the interrupt process to be executed in response to the interrupt request from the serial communication circuit 505 (step S15c). . In this embodiment, an interrupt process that causes an interruption cause that the serial communication circuit 505 has received the received data is specified in advance in the specification information. Then, based on the designation information, the CPU 56 performs an initial setting so as to preferentially execute an interrupt process whose cause is the reception of received data. In other words, in this embodiment, in the interrupt processing priority table shown in FIG. 48, by default, interrupt processing that causes the occurrence of a communication error in the serial communication circuit 505 is preferentially executed. Although set, the CPU 56 sets the priority order of the interrupt processing so that the interrupt processing whose cause is the reception of the received data is preferentially executed based on the designation information set by the user. change. In this case, for example, the CPU 56 sets a reception-time interrupt priority execution flag indicating that priority is given to interrupt processing that causes reception of received data.

  In the loop process from step S17 to step S20 in the main process, if there is an interrupt request from the serial communication circuit 505 during the interrupt enabled state, the CPU 56 of the game control microcomputer 560 follows the process shown in FIG. The serial communication circuit 505 executes interrupt processing according to the interrupt cause for which an interrupt request has been made.

  The CPU 56 determines whether or not any interrupt process is preferentially executed. For example, the CPU 56 determines whether or not any interrupt process is preferentially executed. In this embodiment, the CPU 56 preferentially executes an interrupt process in which the reception data is received based on the fact that the reception interrupt priority execution flag is set.

  When there is an interrupt request from the serial communication circuit 505, the CPU 56 checks each bit of the status register A 705 of the serial communication circuit 505 to identify the cause of the interrupt. In this embodiment, the CPU 56 preferentially confirms bit 5 of the status register A705 to identify the cause of the interrupt. That is, the CPU 56 determines whether or not the serial communication circuit 505 has made an interrupt request due to the fact that the received data has been received as an interrupt cause in preference to other interrupt causes (the occurrence of a communication error or the completion of transmission of transmission data). . When determining that the bit 5 of the status register A is “1”, the CPU 56 specifies that the cause of the interruption is that the serial communication circuit 505 has received the reception data.

  If it is determined that the cause of the interruption is that the serial communication circuit 505 has received the reception data, the CPU 56 preferentially executes the reception interrupt process shown in FIG. 77 (b). In this case, the CPU 56 sets a reception interrupt flag indicating that the serial communication circuit 505 is receiving reception data (step S42).

  As described above, in this embodiment, the game control microcomputer 560 initializes the priority of interrupt processing before setting the interrupt-permitted state in the main processing. For this reason, it is possible to reliably execute an interrupt process to be preferentially executed among interrupt processes corresponding to a plurality of types of interrupt causes. In addition, since the interrupt process to be executed with priority can be initialized, the degree of freedom of the program executed by the game control microcomputer 560 can be improved.

  For example, in the reception process in the prize ball process (for example, the prize ball ACK waiting process in step S1234), each bit of the status register A705 is checked to determine whether or not a communication error has occurred in the serial communication circuit 505. If a simple program is built, control can be performed so that a command is not received when a communication error occurs without executing an interrupt process that causes the occurrence of a communication error. Therefore, when a program that confirms the occurrence of a communication error in the reception process is built, priority is given to the interrupt process that causes the reception of data to cause a game control micro The degree of freedom of the program executed by the CPU 56 of the computer 560 can be improved.

  In this embodiment, the expression “the serial communication circuit 505 issues an interrupt request to the CPU 56 during reception” is used. Specifically, when an interrupt factor (data reception in this example) occurs. In addition, the interrupt control circuit 714 of the serial communication circuit 505 sets a setting value in a corresponding bit of the status register A 705 (bit 5 corresponding to data reception) and outputs an interrupt signal to the CPU 56, whereby the serial communication circuit 505 An interrupt request is received at the time of reception.

Embodiment 4 FIG.
In each of the embodiments described above, the case has been described in which the CPU 56 sets or changes which interrupt process has priority over the interrupt process corresponding to the interrupt request from the serial communication circuit 505. However, when a timer interrupt and an interrupt request from the serial communication circuit 505 are generated at the same time, it may be possible to set or change which interrupt processing is to be preferentially executed. Hereinafter, a description will be given of a fourth embodiment for setting or changing which of the timer interrupt and the interrupt request from the serial communication circuit 505 has priority.

  In the present embodiment, detailed description of the parts having the same configuration and processing as those in the first embodiment will be omitted, and parts different from those in the first embodiment will be mainly described.

  First, the main processing in the fourth embodiment will be described with reference to FIGS. 46 and 47 of the first embodiment.

  When the serial communication circuit setting process in step S15b is executed and the serial communication circuit 505 is initialized, the CPU 56 executes the timer interrupt process executed when a timer interrupt occurs and the interrupt request of the serial communication circuit 505. The priority of interrupt processing is initially set (step S15c).

  For example, the CPU 56 initializes the priority of each interrupt process according to a predetermined interrupt process priority table including the default priority of each interrupt process. FIG. 127 is an explanatory diagram illustrating an example of an interrupt processing priority table according to the fourth embodiment. In this embodiment, the CPU 56 is initially configured to preferentially execute an interrupt process whose cause is a communication error in the serial communication circuit 505 according to the interrupt process priority table shown in FIG. Set. That is, the CPU 56 sets by default so that an interrupt process (in this example, a communication error interrupt process) by an interrupt request from the serial communication circuit 505 is executed in preference to the timer interrupt process. In this case, for example, the CPU 56 sets an interrupt priority execution flag at the time of communication error indicating that priority is given to an interrupt process whose cause is an interrupt.

  In this embodiment, in step S15c, the interrupt processing priority is initially set in accordance with the interrupt processing priority table shown in FIG. 127, whereby the timer interrupt and the interrupt request from the serial communication circuit 505 are performed. Occur at the same time, priority is given to interrupt processing for an interrupt request from the serial communication circuit 505.

  In addition, the default priority of each interrupt process can be changed by the user. For example, the game control microcomputer 560 stores specification information for specifying an interrupt process set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 sets the priority of interrupt processing according to the designation information stored in a predetermined storage area of the ROM 54.

  For example, a case where a timer interrupt process is designated in designated information stored in advance will be described. In this case, based on the designation information, the CPU 56 performs timer interrupt processing for each interrupt processing for the interrupt request from the serial communication circuit 505 (communication error interrupt processing, reception interrupt processing, and transmission completion interrupt processing). ) To be executed in preference to (). That is, in the interrupt processing priority table shown in FIG. 127, the interrupt processing is set by default so as to preferentially execute the interrupt processing that causes the occurrence of a communication error in the serial communication circuit 505. Based on the designation information set by the user, the CPU 56 changes the priority of the interrupt process so that the timer interrupt process is executed with priority. In this case, for example, the CPU 56 sets a timer interrupt priority execution flag indicating that timer interrupt processing is executed with priority.

  Further, the processes from step S16 to step S20 are the same as those shown in the first embodiment. When the interrupt enabled state is set in step S20, the timer interrupt or the interrupt request from the serial communication circuit 505 is permitted until the processing in step S17 is executed and the interrupt disabled state is set next time. . When a timer interrupt occurs while the interrupt permission state is set, the game control microcomputer 560 executes a timer interrupt process to be described later. In addition, when an interrupt request is generated from the serial communication circuit 505 while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 causes each interrupt process (communication error interrupt process and reception) to be described later. Execute time interruption processing and transmission completion interruption processing). Further, in the present embodiment, by executing step S15c before the loop processing from step S17 to step S20, before the timer interrupt or interrupt request is set to be permitted, the timer interrupt processing and Processing for setting or changing the priority of interrupt processing in response to an interrupt request from the serial communication circuit 505 is performed.

  In the loop process from step S17 to step S20 in the main process, if there is an interrupt request from the serial communication circuit 505 during the interrupt enabled state, the CPU 56 of the game control microcomputer 560 follows the process shown in FIG. The serial communication circuit 505 executes interrupt processing according to the interrupt cause for which an interrupt request has been made. Further, when a timer interrupt occurs in the loop process from step S17 to step S20 in the main process, the CPU 56 executes the timer interrupt process according to the process shown in FIG.

  In this embodiment, when a timer interrupt and an interrupt request from the serial communication circuit 505 occur at the same time, the CPU 56 determines whether or not an interrupt process is preferentially executed. . For example, the CPU 56 determines whether or not any interrupt process is preferentially executed. For example, the CPU 56 preferentially executes timer interrupt processing based on the setting of the timer interrupt priority execution flag.

  As described above, in this embodiment, the CPU 56 sets each interrupt corresponding to the interrupt request from the timer interrupt process and the serial communication circuit 505 before setting the interrupt enabled state in the main process. Initialize processing priority. Therefore, among the interrupt processing corresponding to the timer interrupt processing and the plurality of types of interrupt causes, the interrupt processing to be executed with priority can be surely executed. Further, since the interrupt process to be executed with priority can be initially set, the degree of freedom of the program executed by the CPU 56 of the game control microcomputer 560 can be improved.

  In each of the above-described embodiments, as the types of big hits, 2 rounds probable big hits, 2 rounds short hits, 7 rounds normal big hits, 15 rounds normal big hits, 15 rounds probable big hits, and 15 rounds short hits are provided. The type is not limited to this. For example, it may be a big hit with different opening times of the big winning opening, or a big winning with a different number of winning balls for one winning winning opening during the big winning. Such a jackpot is also determined based on the jackpot type determination random number.

  In the configuration of the power supply substrate 910 shown in FIG. 39, the following characteristic configuration is also disclosed. The operable voltage value of the microcomputer mounted on each board and the watchdog timer 60 is +5 V, and the voltage value at which the reset signal is turned off (system reset is applied) when the power supply voltage decreases. Is + 9V, and the voltage value at which the power-off signal is turned on when the power supply voltage decreases is + 22V. Here, when the AC voltage of AC + 24V is normally supplied, the rectifying / smoothing circuit 915 continues to output VSL + 30V. Then, the power supply monitoring circuit 920 monitors VSL + 30V, and turns on (outputs) the power-off signal when the voltage value becomes + 22V. When a voltage of VSL + 30V is supplied from the rectifying / smoothing circuit 915, the switching regulator 924B continues to output VCC + 5V, which is a driving voltage for a microcomputer or the like. The switching regulator 924B continues to output VCC + 5V when + 30V to + 7V is supplied as the voltage value of VSL. Therefore, at this time, the microcomputer or the like is in a driveable state. Since the system is reset at + 9V before VSl drops to + 5V, the microcomputer will not run out of control and the data in the RAM will not be destroyed. Further, since the creation of the checksum in the power-off process can be completed between VSL + 22V and + 9V, a situation in which the data in the RAM is destroyed and cannot be recovered does not occur.

  In each of the above-described embodiments, a plurality of types of effect devices (such as the variable display device 9 and the speaker 27) are replaced with a plurality of effect microcomputers (in the example shown in FIG. 3, the sound / lamp control microcomputer 100b). The design control microcomputer 100a) is configured to control, but may be configured to control all the production devices by one production microcomputer (for example, production control microcomputer).

  In the above-described embodiment, characteristic configurations of gaming machines as shown in the following (1) to (6) are also shown.

  (1) The game control microcomputer includes a plurality of random number circuits (for example, a 12-bit random number circuit 503a and a 16-bit random number circuit 503b) having different predetermined ranges of numerical data that can be updated by the numerical value updating means. In the initial setting, the setting means sets a usable random number circuit from among a plurality of random number circuits built in the game control microcomputer (for example, the game control microcomputer 560 executes step S151), and the random number circuit Random number stopping means for stopping the function of the random number circuit other than the random number circuit set to be usable by the initial setting means (for example, when the game control microcomputer 560 sets the random number circuit 503 used in step S151, it is not used. The counter 521 of the random number circuit that has been set to updates the count value C It may be configured to include a portion) of odd controlled. According to such a configuration, it is configured to set whether or not each of a plurality of random number circuits having different predetermined ranges of numerical data that can be updated can be used. By setting, the range of the value of the random number to be generated can be appropriately set, and the random number need not be updated unnecessarily.

  (2) The random number circuit initial setting means stores a numerical value in a numerical maximum value register (for example, the random number maximum value setting register 535) in which a value as a maximum value in a predetermined range in which numerical data is updated is set in the initial setting. Maximum value setting means for setting a predetermined maximum value (for example, a random number maximum value) within the range of numerical data that can be updated by the updating means (for example, a part for executing step S152 in the game control microcomputer 560), Setting value determining means for determining whether or not the predetermined maximum value set by the value setting means is equal to or less than a predetermined lower limit value (for example, “256” when the 12-bit random number circuit 503a is set) The portion for executing step S153b in the gaming control microcomputer 560) and the maximum value by the set value determination means When it is determined that the predetermined maximum value set in the register is less than or equal to the predetermined lower limit value, a predetermined value (for example, 12 bits) within the range of numerical data that can be updated by the numerical value updating means is stored in the numerical maximum value register. Maximum value resetting means for resetting “4095” when the random number circuit 503a is set (for example, a part for executing step S153c in the game control microcomputer 560) may be included. According to such a configuration, the value as the maximum value of the predetermined range in which the numerical data is updated is set in advance, so that a value larger than the range of random numbers used during the execution of the timer interrupt process Can be prevented from being generated, and the processing load on the random number circuit and the game control microcomputer can be reduced. In addition, when the set maximum value is less than or equal to the predetermined lower limit value, the predetermined maximum value is reset, so that malfunction of the game control microcomputer or radio signal is used. It is possible to prevent an excessively small value from being set as the maximum value of the random number due to an action such as generating a captured signal to the gaming machine.

  (3) The gaming machine includes clock signal generation means (for example, a clock circuit 501) that generates a clock signal having a predetermined period and outputs the clock signal to a random number circuit, and the numerical value update means is provided on the condition that the clock signal is input a predetermined number of times The numerical data is updated (for example, when the clock signal output circuit 524 inputs the random number generating clock signal SI obtained by dividing the reference clock signal CLK by 16), the counter 521 updates the count value C). The setting means may be configured to set the number of clock signal inputs, which is a condition for the numerical value updating means to update the numerical data (for example, the game control microcomputer 560 executes step S156). According to such a configuration, the numerical value updating means is configured to preset the number of times of input of the clock signal, which is a condition for updating the numerical data, so that the randomness of the random number generated by the random number circuit is further improved. be able to.

  (4) The game control microcomputer uses a microcomputer identification information to calculate a predetermined initial value of the numerical data set by the random number circuit initial setting means (for example, in step S154b in the game microcomputer) When the process is executed, it includes the calculation of the ID number of the game control microcomputer 560 and a predetermined value (for example, a portion for calculating the calculated value by adding the predetermined value to the ID number), and the random number circuit initial setting The means sets an initial value based on the value calculated by the calculation by the numerical value calculation means (for example, when the gaming microcomputer executes the process of step S154b, the calculated calculated value is used as the initial value of the count value. Set). According to such a configuration, since the initial value is set based on the value calculated by the calculation using the microcomputer identification information, the randomness of the random number generated by the random number circuit is further improved. Can do. For this reason, it is possible to make it difficult to recognize the initial value of the random number simply by looking at the microcomputer identification information, and the security can be improved.

  (5) The gaming machine detects that the game medium has won a prize area in the game area (for example, winning a game ball to the special variable winning ball apparatus 20) and receives a winning detection signal (for example, count switches 231 and 232). And a random number circuit that is updated by the numerical value updating means based on the input of the winning detection signal from the winning detection means. Including a latch signal output means (for example, a latch signal generation circuit 533) for outputting a latch signal for storing data in the random number storage means. The latch signal output means continuously receives a winning detection signal from the winning detection means for a predetermined period. When the condition is input (for example, when the timer circuit 534 measures a predetermined period (for example, 3 ms), the random value read signal output circuit 526 The latch signal generation circuit 533 outputs the random value read signal output from the random value read signal output circuit 526 to the inversion circuit 532. (The portion that is output to the random value storage circuit 531 as the latch signal SL) in synchronization with the rising edge of the inverted clock signal SI2 output from the According to such a configuration, when the random number storage means stores the random number based on the output of the latch signal, the latch signal is set on condition that the winning detection signal is continuously input for a predetermined period. Since it is configured to output, it is possible to prevent the occurrence of noise from being erroneously recognized as the input of the input detection signal, outputting the latch signal, and storing the generated random number. In addition, it is possible to reduce the possibility that a random number generated by an illegal latch signal is stored due to an output of a latch signal by an action such as generating a capture signal using a radio signal to the gaming machine. .

  (6) The random number reading means continues on the condition that the winning detection signal is input from the winning detection means (for example, for game control) while the timer interrupt processing execution means is executed a predetermined number of times. When the microcomputer 560 executes the process of step S3202, the random number storage means stores the number of times the timer interrupt process indicated by the interrupt counter has reached a predetermined number (for example, 3 times). (For example, the CPU 56 reads the random R value stored as the random number value from the random value storage circuit 531 of the random number circuit 503), and a predetermined period of time (for example, 3 ms) It may be configured to be shorter than a period (for example, 6 ms) in which the loading process is executed. According to such a configuration, when reading a random number from the random number storage unit, the random number is read from the random number storage unit on condition that the winning detection signal is continuously input while the timer interruption process is executed a predetermined number of times. Therefore, it is possible to prevent the random number from being read again after the random number is read and before the value of the random number stored in the random number storage unit is updated. Therefore, it is possible to prevent a random number having the same value as the random number read from the previous random number storage unit from being read again.

  Further, in the above-described embodiment, characteristic configurations of gaming machines as shown in the following (1) to (6) are also shown.

  (1) A game equipped with a game control microcomputer (for example, a game control microcomputer 560) for executing a game control process (for example, the processes of steps S21 to S36 based on a timer interrupt) for controlling the progress of the game A first electric component that controls a control board (for example, game control board 31) and a first electric part (for example, at least one of the variable display device 9, speaker 27, lamp, etc.) used for the game effect. A first electric component control board (eg, sound / lamp control board 80b or symbol control board 80a) on which a control microcomputer (eg, sound / lamp control microcomputer 100b or symbol control microcomputer 100a) is mounted; Second electrical components used for production (for example, variable display device 9, speaker 27, A second electric component control board on which a second electric component control microcomputer (e.g., a symbol control microcomputer 100a or a sound / lamp control microcomputer 100b) that controls at least one of the amplifier and the like is mounted. (For example, the symbol control board 80a or the sound / lamp control board 80b), and the game control microcomputer uses the display result of the variable display of the identification information as the specific display result when the variable display start condition is satisfied. Display result determination means (for example, the part that executes step S56B in the game control microcomputer 560) and a variation pattern of variable display of the identification information based on the determination result of the display result determination means. Select a variation pattern command to select and identify the selected variation pattern 1 game control side command transmission means for transmitting to the electrical component control microcomputer (for example, the part for executing step S373 in the game control microcomputer 560), and the first electrical component control microcomputer is a game control microcomputer. Based on the variation pattern command received from the game, the production content determination means for determining the content of the game production (for example, the part for executing steps S1853 to S1855 in the sound / lamp control microcomputer 100b) and the production content determination means are determined. A command transmission means (for example, in the sound / lamp control microcomputer 100b) that transmits a command (for example, an effect content command) that can specify the content of the played game effect to the second electrical component control microcomputer. The second electric component control microcomputer includes the second electric component control microcomputer based on the content of the game effect indicated by the command transmitted from the first electric component control side command transmission means. This is a gaming machine that controls a game effect using electric parts (for example, the design control microcomputer 100a executes the effect control process of step S777 based on the effect content command). According to such a configuration, it is not necessary for the game control microcomputer to determine the contents of the effect, so that the processing load of the game control microcomputer can be reduced.

  (2) Whether or not the effect content determining means executes a notice effect for notifying that the display result of the variable display of the identification information becomes a specific display result based on the variation pattern command received from the game control microcomputer. (For example, the processing of steps S1852 to S1855 is executed based on the variation pattern command), and the first electric component control side command transmitting means sends a command corresponding to the determination result by the effect content determining means to the second electric You may be comprised so that it may transmit to a components control microcomputer (for example, the process of step S1856, S1857 is performed). According to such a configuration, the control burden on the game control microcomputer can be reduced.

  (3) The first electrical component control microcomputer uses command generation means (for example, sound / lamp control) to generate an effect content command that can specify the content of the game effect determined by the effect content determination means based on the variation pattern command. The first microcomputer 100b includes a part for executing a process for generating an effect content command in step S1856, or a part for executing a process for generating an effect content command by the design / sound control microcomputer). The side command transmission means transmits the effect content command generated by the command generation means (for example, the sound / lamp control microcomputer 100b transmits the effect content command in step S1856, or the symbol / sound control microcomputer Send the production contents command), the second electric part The microcomputer controls the game effect using the second electrical component based on the content of the game effect indicated by the effect content command transmitted by the first electrical component control side command transmission means (for example, for symbol control) The microcomputer 100a may execute the process of step S777 based on the effect content command, or the lamp control microcomputer may execute the process of step S777 based on the effect content command. According to such a configuration, the control burden on the game control microcomputer can be reduced.

  (4) The first electric component control microcomputer adds the content of the game effect determined by the effect content determination means to the variation pattern command (for example, the sound / lamp control microcomputer 100b uses the variation pattern command). The first electric component control side command transmission means includes a variation in which the contents of the game effect are added by the effect content adding means. The pattern command is transmitted (for example, the sound / lamp control microcomputer 100b executes the same processing as in step S1856), and the second electrical component control microcomputer is transmitted by the first electrical component control side command transmission means. Based on the contents of the game effect shown in the variation pattern command, the second electricity Controlling game effects with goods (for example, executes the processing of step S777 based on the symbol control microcomputer 100a Produce contents command) may be configured so. According to such a configuration, the control burden on the game control microcomputer can be reduced, and the number of commands transmitted by the first electric component control microcomputer can be reduced.

  In addition, the pachinko gaming machine of the above embodiment can be given a predetermined game value to a player mainly when the stop symbol of the special symbol variably displayed on the variable display unit based on the start winning becomes the predetermined symbol. A pachinko machine that can be given a predetermined gaming value to a player when there is a prize in a predetermined area of an electric game that is released based on a start prize, or a start prize The present invention can be applied even to a pachinko gaming machine in which a predetermined right is generated or continued when a winning is given to a predetermined electric combination that is released when a stop symbol of a variably displayed symbol becomes a predetermined symbol combination . Furthermore, the present invention can be applied to a slot machine that inserts game medals and sets a bet number and plays a game, or a game machine that inserts game balls instead of game medals and sets a bet number and plays a game.

  The present invention is applicable to gaming machines such as pachinko gaming machines and slot machines, and in particular, gaming machines that perform variable display of decorative symbols and game effects on variable display devices based on variation pattern commands and display result designation commands. It can be suitably applied to.

1 Pachinko machine 9 Variable display device 14 Start winning opening 15 Variable winning ball device 31 Game control board (main board)
37 Dispensing control board 38, 39 Big prize opening indicator light 56 CPU
80a design control board 80b sound / lamp control board 83 CGROM
84 VRAM
100a Symbol control microcomputer 100b Sound / lamp control microcomputer 101a Symbol control CPU
101b Sound / lamp control CPU
109 VDP
503a 12-bit random number circuit 503b 16-bit random number circuit 505 Serial communication circuit 560 Microcomputer for game control

Claims (1)

Image display of a plurality of types of effect images including a plurality of types of identification information that can identify each of them, and after a predetermined variable display execution condition is satisfied, identification is performed based on the satisfaction of the variable display start condition A gaming machine comprising variable display means for performing variable display of information, and transitioning to a specific gaming state advantageous to a player when the display result of variable display of identification information becomes a specific display result,
A game control microcomputer for executing a game control process for controlling the progress of the game after executing a predetermined initial setting process according to the control program;
An electric component control microcomputer for giving a command for controlling the display operation of the variable display means;
Power monitoring means for monitoring the state of a predetermined power source used in the gaming machine and outputting a detection signal based on the detection condition relating to the stop of power supply to the gaming machine being satisfied;
Timer means for measuring a predetermined monitoring time;
A reset means for resetting the gaming control microcomputer when the timer means measures that the monitoring time has elapsed;
In response to a command from the electrical component control microcomputer, image display control means for controlling the image display of the effect image in the variable display means,
The game control microcomputer is:
An initialization processing means for periodically executing an initialization process for initializing the time measured by the timer means in a period shorter than the monitoring time in the game control process;
Even if the power supply to the gaming machine is stopped, it is possible to retain the stored contents for a predetermined period, and the fluctuation data storage means for storing the fluctuation data that fluctuates according to the progress of the game,
Power supply stop processing for executing power supply stop processing for saving data necessary for restoring the control state in the fluctuation data storage device based on the detection signal output from the power monitoring means Execution means;
After the power supply stop process is terminated, a stop standby state transition means for transitioning to a standby state in which the initialization process is not performed,
Detection signal determination means for determining whether or not a detection signal is output from the power supply monitoring means when the predetermined initial setting process is executed;
Standby state transition means for transitioning to a standby state in which the initialization process is not executed when it is determined that the detection signal is output by the detection signal determination means;
An initial setting process starting means for starting the predetermined initial setting process from the standby state based on the reset made by the reset means when transitioning to the standby state;
When it is determined by the detection signal determination means that a detection signal is not output, the control state is determined based on the stored contents stored in the fluctuation data storage means on condition that a predetermined recovery condition is satisfied. Power supply start time processing means for executing power supply start time processing to restore the state before the supply stop time processing is executed;
Pre-determining means for determining whether or not the display result of the variable display of identification information is the specific display result according to the establishment of the variable display start condition,
The electric component control microcomputer is:
Display content determining means for determining the display content of the variable display means based on the determination result of the prior determination means,
The image display control means includes
Image data storage means for storing a plurality of types of image data including image data corresponding to the effect image;
Temporary storage means for temporarily storing image data read from the image data storage means;
Corresponding to the activation of the electrical component control microcomputer, storage area setting means for setting the storage area in the temporary storage means to a plurality of areas including a specific storage area;
Transfer control means for controlling transfer of image data read from the image data storage means to the temporary storage means;
Display data creation means for creating presentation image display data in the variable display means based on the image data temporarily stored in the temporary storage means;
Display data storage means for storing display data created by the display data creation means;
Display data output means for outputting display data read from the display data storage means to the variable display means,
The display content determination means includes
After the storage area is set by the storage area setting means, it is necessary to execute an image display frequency with the effect image corresponding to the image data among a plurality of types of image data stored in the image data storage means. Start-up data transfer instruction means for instructing transfer of high-frequency image data to a region other than the specific storage area in the temporary storage means compared to the execution frequency of the image display by the effect image corresponding to the image data;
Display image update command means for notifying the image display control means of the reading position of the image data and the writing position in the display data storage means and instructing update of the display image in the variable display means,
The transfer control means includes
In response to a command from the startup data transfer command means, the startup data transfer means for reading the high-frequency image data from the image data storage means and transferring it to an area other than the specific storage area;
When the read position of the image data notified from the display image update command means is included in the image data storage means, the image data is read from the read position in the image data storage means and stored in the specific storage area in the temporary storage means. Normal data transfer means for transferring;
Image data reading means for reading image data including display color data of each pixel constituting the effect image of the identification information among the image data stored in the image data storage means;
Control data setting means for setting control data for controlling the display operation of the identification information corresponding to the image data read by the image data reading means,
The display data creation means includes:
After the image data is transferred to the specific storage area by the normal data transfer means, the image data is read from the specific storage area, and the writing position in the display data storage means notified from the display image update command means A first image display control means for writing and storing
When the read position of the image data notified by the display image update command means is included in the temporary storage means, the image data is read from the read position in the temporary storage means and notified from the display image update command means Second image display control means for writing and storing at a writing position in the display data storage means,
The first image display control means or the second image display control means is executing variable display based on the image data read by the image data reading means and the control data set by the control data setting means. A game machine comprising: stage display updating means for updating display data so that the effect image of the identification information is displayed or erased stepwise over time.

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