JP2011238766A - Dielectric structure and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a dielectric structure formed on a heat-resisting substrate for forming a dielectric on a non-heat resisting substrate, and a peeling transition process to the non-heat resisting substrate of a dielectric film.SOLUTION: The dielectric structure 1 has a first substrate 5, an oxide film 4 and a first electrode layer 3 formed on the first substrate 5, and a dielectric layer 2 formed on the first electrode layer 3. Between the first substrate 5 and the first electrode layer 3, a coupling layer 6 formed by Ti and the like so as to cover at least a part of the first substrate 5 is provided. By optimizing the mechanical characteristics of an interface according to residual stress in the dielectric after forming, the peeling characteristics of the interface in which the dielectric layer 2 and the electrode layer 3 is not peeled from the heat-resisting substrate in a forming process and peeled in a transition process can be obtained.

Description

The present invention relates to an electronic material structure for an exfoliation and transfer process of an electronic material film used in electronic devices, MEMS (Micro Electro Mechanical System) and other electronic circuit structures, and an exfoliation and transfer process thereof.
More specifically, the present invention relates to a dielectric structure formed on a heat-resistant substrate and a process of peeling the dielectric film onto the non-heat-resistant substrate for forming a dielectric on the heat-resistant substrate. It is about.

Dielectrics have useful properties such as ferroelectricity, dielectricity, pyroelectricity, piezoelectricity, electro-optical properties, photovoltaic properties, electrostriction, and photostriction. Electronic devices such as capacitors and memories It is used for optical devices such as drive and detection devices such as sensors and actuators, optical switches, SHG (second harmonic) elements, and optical waveguides.
In application to such a small device, in order to facilitate integration and mounting on a substrate or the like, it is desirable to use it as a film structure formed on a substrate instead of a bulk single crystal or ceramics. In particular, the ferroelectric structure has a high electromechanical coupling constant, and the linearity of the input / output characteristics makes it possible to realize a drive / detection method suitable for miniaturization because of low power consumption and low thermal influence. There are many advantages of applying these materials as components of small devices such as MEMS.

  Conventionally, such a dielectric film has been produced by, for example, a sol-gel method, an MOD method, a sputtering method, an electron beam evaporation method, a laser evaporation method, an MOCVD method, a CVD method, or the like. At this time, what has been mainly used as a film-forming substrate has been silicon or silicon having an oxide film or a base electrode formed thereon, or a heat-resistant substrate material such as magnesium oxide or sapphire. In particular, a dielectric film having electrical / mechanical characteristics has been formed on such a heat-resistant substrate.

However, the relative dielectric constant of the organic / inorganic oxide mixed thin film obtained in Patent Document 1 is about 50 at most. Further, in this method of obtaining a thin film, the volume shrinkage during the formation process is large, and it is difficult to control the dimensions such as the film thickness, and the surface unevenness is large compared to other thin film forming techniques.
Further, in the circuit board obtained in Patent Document 2, it is necessary to develop a technique for stably maintaining the film formation, and additionally, it is necessary to cope with the problem of particulate contamination. Furthermore, problems remain with respect to damage to the substrate due to anchoring of fine particles, and in the method of obtaining this circuit board, the dielectric film to be formed becomes a random alignment film because the fine particles are baked, and the highest level is obtained. It is difficult to achieve dielectric performance.
Moreover, the dielectric constant of the dielectric obtained by the method of Patent Document 3 is also about 50, and it has not been realized to produce a film having a high dielectric constant. In addition, similar to the technique of Patent Document 1, problems remain regarding dimensional control and generation of surface irregularities. Furthermore, the transfer method by this method is a method using a dielectric paste, and can only realize a dielectric constant that is smaller by one digit or less than that produced by a method using thin film technology.
Further, the method of Non-Patent Document 1 requires a high-temperature process of about 1200 ° C. at the time of firing, and a special laser device and technology are required, so that simpler technical development is required.

On the other hand, in order to secure advantages such as cost reduction, weight reduction, and high moldability in the technological innovation competition for miniaturization of small electronic devices typified by mobile phones, it will be made of resin in addition to silicon substrates in the future. The printed circuit board material is expected to be widely used.
Generally, 40 to 50% of the area occupied on the printed circuit board is occupied by passive elements such as capacitors and resistors. Accordingly, as the semiconductor LSI technology is miniaturized, a reduction in the area occupied by these passive elements on the printed circuit board is required.

Accordingly, a component-embedded substrate technology has been developed in which electronic components are not mounted on the substrate surface but are three-dimensionally embedded and mounted in the substrate. With this technique, passive elements such as capacitors formed on the substrate surface can be eliminated, and in addition, a substantial occupied area of passive elements on the printed circuit board can be reduced.
However, in general, heat treatment at 600 ° C. or higher is necessary for crystallization of the dielectric thin film. Epoxy resins and the like used for printed circuit boards are so-called low melting point materials, and their heat resistance temperature is about 400 ° C. Stay. Therefore, it has been difficult to monolithically form a good dielectric thin film on a printed circuit board such as an epoxy resin.

  Therefore, in order to form a dielectric film having high electrical / mechanical characteristics on a printed circuit board or a resin substrate, in Patent Document 4, the dielectric film 12 is first formed on the heat-resistant substrate 14 and then the dielectric film is formed. A technique for transferring the body film 12 onto the non-heat resistant substrate 16 has been proposed (FIG. 1). Here, a highly peelable laminated structure 13 is introduced into a base electrode on a heat resistant substrate 14 on which a dielectric film is to be formed and transferred, so that it has a high dielectric constant at a low cost and has a required level. A dielectric structure 11, a dielectric structure manufacturing method, a pressure-transfer transfer method, and a holding structure that can be formed without waste are proposed. (Patent Document 4)

  Among dielectrics, PZT is a material that has been researched and developed as the most promising dielectric so far. However, with increasing awareness of international environmental issues and the promotion of regulatory policies, replacement of lead-containing materials, such as PZT, with non-lead-containing (lead-free) materials has been required.

JP 2005-56935 A JP 2005-5645 A JP 2001-160672 A JP 2009-147238 A

B. Xu et al. Appl. Phys. Lett. 87 (2005) 192902.

  However, when using materials other than materials with advanced technological development such as PZT, the film formation conditions such as thickness and crystallization temperature are different, and the volume expansion / reduction ratio of the dielectric material in the film formation process may increase. . Then, the residual stress in the dielectric material after the film formation process increases due to a difference in thermal expansion coefficient from the substrate. At this time, in the conventional technique, if the adhesive force between the dielectric film and the donor substrate is low, the dielectric film peels off from the donor substrate in the process of generating the dielectric film before the transfer process. there were.

  The present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a bonding layer using a material having a high adhesive force at the interface between the electrode layer and the heat-resistant substrate. It is to provide a technique in which a layer does not peel in the formation process.

  On the other hand, if the adhesive strength between the dielectric film and the donor substrate is increased too much, the adhesive strength is the strength required for peeling during the transfer process, even if it can avoid peeling and produce a good dielectric film. If it is higher, the dielectric film transfer process may be hindered.

  Therefore, a further object of the present invention is to optimize the formation area of the above-mentioned bonding layer, thereby controlling the adhesive force between the transferred dielectric film and the substrate to an appropriate level, and forming the formed dielectric film. It is intended to provide a technique for transferring to a different substrate by peeling off at the interface between the electrode layer and the substrate.

In order to solve the above problems, the present invention includes a first substrate, a first electrode layer formed on the first substrate, and a dielectric layer formed on the first electrode layer. A dielectric structure comprising a coupling layer formed so as to cover at least a part of the first substrate between the first substrate and the first electrode layer. I will provide a.
Further, the present invention provides a first step of forming a bonding layer on the first substrate so as to cover at least a part of the first substrate, the first substrate, and the bonding layer. Provided is a method for manufacturing a dielectric structure, which includes a step of forming an electrode layer and a step of forming a dielectric layer on the first electrode layer.
Furthermore, the present invention includes a step of bonding a second substrate to the formed dielectric structure, and then a step of peeling the first electrode layer from the first substrate. A method of manufacturing a dielectric structure is provided.
Still further, the present invention provides a step of forming a bonding layer on the first substrate so as to cover at least a part of the first substrate, the first substrate, and the bonding layer. A step of forming a first electrode layer; and a step of forming a dielectric layer on the first electrode layer, wherein the first electrode layer is formed on the first substrate during the step of forming the dielectric layer. A dielectric produced by: a step characterized by not peeling off from the substrate; a step of bonding a second substrate to the dielectric structure; and a step of peeling off the first electrode layer from the first substrate. A body structure is provided.

  According to the present invention, by optimizing the mechanical properties of the interface according to the residual stress in the dielectric after formation, the dielectric and the electrode layer do not peel from the heat-resistant substrate in the formation process, and in the transition process It is possible to obtain the peeling characteristics of the interface to be peeled, and to produce a dielectric having a desired characteristic on a predetermined heat-resistant substrate and to transfer to a predetermined non-heat-resistant substrate. Is.

1 illustrates a conventional thin film transfer process. The relationship between the film thickness and peeling of a Pt electrode layer and a PZT dielectric layer according to the first embodiment of the present invention will be described. The relationship with the residual stress in a Pt electrode layer concerning the 1st Embodiment of this invention is shown. It is sectional drawing of the dielectric material structure concerning the 1st Embodiment of this invention. FIG. 4 shows a coupling layer formation pattern when the dielectric structure of FIG. 3 is viewed from above. The XRD measurement result of the BTO dielectric material concerning the 1st Embodiment of this invention is shown. The in-film residual stress of PZT for comparison with BTO according to the first embodiment of the present invention is shown. The conceptual diagram of the transfer process of the dielectric material layer and electrode layer from the dielectric material structure of 1st Embodiment concerning the 2nd Embodiment of this invention is shown. The formation pattern of the coupling layer concerning the 3rd Embodiment of this invention is shown. 1 is a cross-sectional view of a component built-in substrate according to an application embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described in detail.

A first embodiment of the present invention will be described with reference to FIGS.
In the present embodiment, a dielectric layer using BaTiO ₃ (hereinafter referred to as BTO) as a lead-free dielectric, an electrode layer using Pt, and a bonding layer using Ti are formed by forming an oxide film. Formed on a substrate.

1) Thickness of electrode layer by Pt As one aspect of the present invention, the optimization of the thickness of the electrode layer when forming an electrode layer by sputtering Pt on a Si substrate on which SiO ₂ is formed will be described. To do.
In the present embodiment, the Pt electrode layer and the oxide film layer on the Si substrate are in direct contact with each other in the portion where the bonding layer on the substrate does not exist. Accordingly, the absence of the bonding layer results in a lower adhesive force than the portion where the bonding layer exists. However, in the dielectric formation process, the dielectric layer or electrode layer does not peel from the substrate, and It is required that peeling is possible after the body layer is formed.

Therefore, when a PZT dielectric was formed, the influence of the film pressure of the Pt electrode layer and the PZT film thickness on the peeling characteristics was examined by a tape peeling test.
On a Si substrate having an oxide film formed on the surface, Pt was formed by sputter deposition after appropriate cleaning, and then PZT was formed by a MOD (Molecular Organic Deposition) method. Specifically, first, the surface is washed with pure water, acetone, and IPA, and the MOD solution is spin-coated at a maximum of 2500 rpm, and then RTA (Rapid Thermal Annealing) at 120 ° C. (solvent volatilization temperature) for 2 minutes, 250 Heat treatment was performed at 4 ° C. (precursor formation temperature) for 4 minutes and at 700 ° C. (crystallization temperature) for 2 minutes. In order to obtain a sufficient PZT film thickness that does not cause leakage, the MOD process including coating and baking was repeated 10 times.
FIG. 2 shows the result of a tape peel test performed on this dielectric structure. ○ indicates that peeling was possible, × indicates that peeling was not possible, and Δ indicates that peeling was partially possible. This experimental result indicates that peeling is easier as Pt is thicker and PZT is thinner.

The reason why peeling was not possible when Pt was thin was as follows. First, after the PZT solution was applied onto the Pt film, part of it penetrated the Pt layer and reached the interface between Pt and the substrate. It is assumed that This phenomenon can be understood from the fact that when PZT solution is directly dropped onto SiO ₂ and heat treatment is performed, PZT adheres and cannot be removed from SiO ₂ , and Pt and PZT cannot be removed in the same manner. it can.
Therefore, when the Pt electrode layer is thin, the Pt layer formed by sputter deposition is not completely dense, and there is a possibility that a minute gap is formed. Therefore, the SiO ₂ / Pt interface of the spin coating solution of PZT As a result, it is thought that peeling was impossible.
When the thickness of the Pt layer is about 100 to 500 nm, that is, when it is thin, the amount of the PZT solution penetrating the Pt layer increases while the PZT is laminated by a plurality of coatings, which may be a factor that makes peeling impossible. . However, when the thickness of the Pt layer is about 1000 nm, that is, when it is thick, it is considered that even if PZT is laminated, it hardly penetrates to the interface.

Next, when Pt is thin, the influence of residual stress inside the Pt layer is considered as a second factor that could not be peeled off.
FIG. 3 shows the relationship between the internal stress and the thickness of the Pt layer when PZT is not applied. The internal stress was obtained by measuring the deflection of the substrate after the Pt electrode layer was formed on the Si substrate, and calculating the internal stress using the Stoney equation (Equation 1).
It can be seen that the thinner the Pt layer, the more rapidly the compressive stress in the Pt layer increases. It is considered that the compressive stress was superior to the tensile force in the tape peeling test and could not be peeled off in a very thin region having a film thickness of about 100 nm.

From the above results, it was found that when the Pt electrode layer is formed by sputter deposition, the thickness of the Pt electrode layer must be at least 100 nm in order to enable the Pt electrode layer to be peeled off from SiO ₂ .

2) Pattern formation of bonding layer using Ti As one aspect of this embodiment, a method of partially forming a bonding layer using Ti on a Si substrate will be described below.
First, the silicon substrate is cleaned by O ₂ RIE (Reactive Ion Etching), and then Ti (5 nm) is deposited by sputtering. Then, a resist is attached on Ti, patterning is performed, and Ti is partially removed by ECR etching. Next, the remaining resist is removed.
As another aspect, Ti may be removed by lift-off.

3) Formation of Pt Electrode Layer and BTO Dielectric Layer FIG. 4 shows a cross-sectional view of the dielectric structure 1 in which the coupling layer is formed according to the first embodiment. FIG. 5 shows the formation pattern of the coupling layer when the dielectric structure is viewed from above.
First, on the Si 20 mm square chip 5 provided with the oxide film 4, Ti was deposited as a bonding layer 6 with a thickness of 5 nm, and then Pt was deposited as a lower electrode 3 with a thickness of 50 nm. After sputter deposition, the chip with the lower electrode was subjected to ultrasonic cleaning in pure water and subsequently in acetone. Next, the chip was immersed in 2-propanol and washed with pure water. For the production of the dielectric layer 2, BTO was laminated using the MOD method. First, the BTO solution was thinly applied with a spin coater (2500 RPM 20s). The wafer coated with BTO was crystallized by RTA (rapid thermal annealing) under the conditions of 120 degrees 2 minutes, 250 degrees 5 minutes, and 700 degrees 2 minutes. The dielectric layer 2 was produced by repeating BTO coating and crystallization by RTA 15 times.

During the formation of the dielectric film, the crystallinity of growth during the film formation process was examined using XRD (X-ray diffraction). As shown in FIG. 6, it can be seen that peaks corresponding to each crystal plane of the perovskite structure have grown by repeating the coating and crystallization processes.
Although not shown, the IV characteristic indicates the insulation property of the generated dielectric film, and in the P (E) hysteresis measurement, a hysteresis with a residual polarization value of 3 μC / cm 2 and a coercive electric field of 37 kV / cm was observed.
From the above, it was experimentally verified that a desired BTO can be formed on the Si substrate.

4) Film formation process Next, when the other processes were performed in the same manner as described above on a substrate (peelable substrate) on which no Ti bonding layer was formed, peeling of the BTO film was observed.
Therefore, for comparison, one layer of each dielectric film was laminated on a 4-inch wafer using a solution of BTO 6% and PZT 20% on a substrate using a Ti bonding layer. Then, the residual stress in the formed film was calculated based on the Stoney equation (Equation 1) by measuring the warpage of the chip.
In FIG. 7, the horizontal axis indicates the measurement position in the diameter direction on a 4-inch wafer, and the vertical axis indicates the residual internal stress. It was found that the internal stress of BTO was around 3000 MPa, reaching almost three times the internal stress of PZT of about 1000 MPa. Compared to the stress measurement in the case of single layer lamination, the residual internal stress should increase further in the case of thicker film formation.
Therefore, it is considered that the BTO peeling observed on a peelable substrate that does not form a Ti bonding layer is caused by a high internal stress.

5) Shape of Bonding Layer Accordingly, as one aspect of the present embodiment, the bonding layer is configured as follows.
That is, as shown in FIG. 5, in a 20 mm square chip, Ti having a thickness of 5 nm was first formed as a bonding layer along the edge, and a structure having no Ti at the center was formed. From the experimental results described above, the thickness of Pt serving as the electrode layer must exceed 100 nm from the substrate surface. In this embodiment, Pt having a thickness of 1000 nm was formed by sputtering deposition on a substrate on which a Ti bonding layer was formed.
For comparison, by changing the width of Ti, the ratio of the area of the portion with Ti and the area of the portion without Ti was changed, and the influence of the ratio on the peeling at the time of thin film formation was examined. At this time, the wafer cleaning method and the Ti selective formation method were changed and examined.
In order to generate Ti at the edge and not Ti at the central part, it is removed by lift-off or ECR after generation, and SiO ₂ is washed with O ₂ RIE (Reactive Ion Etching) before Ti formation Grown up.
Table 1 summarizes whether or not BTO delamination during the BTO film formation was observed under the above conditions.
From this result, it was found that if the portion with Ti is made an area ratio of 50% or more, peeling does not occur at the BTO film formation stage.

A second embodiment of the present invention will be described.
<Transition process>
A method for transferring the electrode layer and the dielectric layer from the dielectric structure formed in the first embodiment to the non-heat-resistant substrate will be described with reference to FIG.

FIG. 8A shows the dielectric structure 1 according to the embodiment shown in FIG. 4 turned upside down in the drawing. Another electrode layer 8 is formed on the non-heat resistant substrate 7 at the transfer destination. Then, the electrode layer 8 of the non-heat-resistant substrate 7 and the dielectric layer 2 formed on the heat-resistant substrate 5 are bonded to each other, and if necessary, pressed to obtain sufficient bonding strength (B). The electrode layer 3 is peeled from the heat-resistant substrate 5 along the vicinity of the bonding layer 6 (C). As described above, the well-formed dielectric layer 2 was formed by transfer on the non-heat-resistant substrate in a configuration sandwiched between the two upper electrodes 3 ′ and the lower electrode 8.
In the present embodiment, the electrode layer to be the lower electrode is formed on the non-heat resistant substrate that is the transition destination, but is not limited thereto. For example, the electrode layer serving as the lower electrode may be formed on the dielectric layer before the transfer process, or may be formed on both the non-heat-resistant substrate and the dielectric layer.

<About other embodiments>
As a third embodiment of the present invention, FIG. 9 shows a bonding layer formation pattern when the structure of the first embodiment is repeated to cover the entire wafer surface and viewed from the upper surface. In this case, the bonding layer 96 is configured to include a portion without a plurality of bonding layers.

Further, the shape of the portion without Ti is not limited to the square shown in the first and second embodiments, but may be other shapes such as a rectangle or a circle.
Moreover, one period may not be 20 mm of the said embodiment. The periodicity is not limited to the second embodiment, and can be designed as appropriate.

  As another embodiment, for example, a plurality of Ti-free portions may be formed apart from each other, or conversely, a Ti-containing portion may be formed separately in a Ti-free portion.

  Moreover, the threshold of the area ratio that the area of a part with Ti is about 50%, which is necessary for preventing peeling, is only what is shown in the above embodiment.

  Furthermore, in the above embodiment, BTO is used as the dielectric, Pt is used as the electrode layer, Pt is used as the bonding layer, and Si is used as the heat resistant substrate. However, the present invention is not limited to this. It will be understood by those skilled in the art that the material can be optimally modified and designed according to the physical properties, specifications, or technology used, such as the material used for the dielectric layer, electrode layer, or substrate, and the thickness and formation method thereof. is there.

Moreover, in the said embodiment, although Ti was used for the coupling layer, it is not limited to this, Other metals or materials other than a metal, for example, resin, an oxide, nitride, etc. can be selected suitably.
As for the separation for transfer, the embodiment described above shows the mechanical separation, but the injection of energy necessary for the separation from the outside does not need to be mechanical. For example, by using a predetermined material and applying heat or passing an electric current through the electrode layer, the bonding layer can be dissolved or stress can be applied to the vicinity of the peeling interface due to thermal expansion. Alternatively, an electric method such as generating a repulsive force of charge inside by applying static electricity may be used.
Further, the term “peeling” used in the present invention should not be understood in a limited sense, but generally means that a dielectric layer or the like is separated from the substrate in the vicinity of the bonding layer. It should be.

<Application embodiment>
FIG. 10 shows an example of a component-embedded board manufactured according to the above embodiment of the present invention. A capacitor 109 having a dielectric 102 is mounted in the substrate interior 110 and is electrically connected by a wiring 103. Thus, according to the invention of the present application, elements such as capacitors are three-dimensionally mounted inside the board, and the substantial area of the printed board can be reduced.

11: Dielectric structure (prior art)
12: Dielectric layer (prior art)
13: Electrode layer (prior art)
14: Substrate (prior art)
1: Dielectric structure 2: Dielectric layer 3: Electrode layer 4: Oxide film 5: Heat resistant substrate 6: Bonding layer 7: Non-heat resistant substrate 3 ′: Upper electrode 8 ′: Lower electrode 102: Dielectric 103: Wiring 109: capacitor 110: component built-in substrate

Claims (11)

A first substrate;
A first electrode layer formed on the first substrate;
A dielectric layer formed on the first electrode layer;
In a dielectric structure having
A dielectric structure having a coupling layer formed to cover at least a part of the first substrate between the first substrate and the first electrode layer. A plurality of the at least part on the first substrate on which the bonding layer is formed; or
The dielectric structure according to claim 1, wherein there are a plurality of portions on the first substrate where the bonding layer is not formed. The first substrate is a Si substrate having an oxide film formed on a surface thereof,
The material of the first electrode layer is Pt formed by sputter deposition,
The thickness of the first electrode layer is 100 nm or more.
The dielectric structure according to claim 1 or 2, wherein The dielectric structure according to any one of claims 1 to ₃ , wherein a material of the dielectric layer is BaTiO ₃ . The dielectric structure according to claim 1, wherein the material of the bonding layer is Ti. 6. The dielectric structure according to claim 1, wherein the at least part of the first substrate on which the bonding layer is formed occupies 50% or more of the area of the first substrate. . Forming a bonding layer on the first substrate so as to cover at least a part of the first substrate;
Forming a first electrode layer on the first substrate and on the coupling layer;
Forming a dielectric layer on the first electrode layer;
A method of manufacturing a dielectric structure having Bonding the second substrate to the dielectric structure formed by the manufacturing method according to claim 7;
Thereafter, peeling the first electrode layer from the first substrate;
A method of manufacturing a dielectric structure on the second substrate. Before the step of peeling the first electrode layer from the first substrate,
9. The manufacturing method according to claim 8, further comprising a step of forming a second electrode layer on the dielectric layer or on the second substrate. Forming a bonding layer on the first substrate so as to cover at least a part of the first substrate;
Forming a first electrode layer on the first substrate and the coupling layer;
Forming a dielectric layer on the first electrode layer, wherein the first electrode layer is not separated from the first substrate during the step of forming the dielectric layer; ,
Bonding a second substrate to the dielectric structure;
Thereafter, peeling the first electrode layer from the first substrate;
A dielectric structure manufactured by a method comprising: Before the step of peeling the first electrode layer from the first substrate,
The dielectric structure according to claim 10, further comprising a step of forming a second electrode layer on the dielectric layer or on the second substrate.