JP2011222699A - Wiring for semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring material which does not lose conductivity even under an oxidation process at 500°C, which has a work function of TiN or higher, and which is less expensive than precious metals.SOLUTION: A wiring material which is a NiTi mixture film and has a Ti content, represented by Ti/(Ni+Ti), with a composition ratio of 60-80 at.% is used and transformed into a mixture film containing Ni and TiOthrough a high-temperature oxidation process at 500°C or higher.

Description

  The present invention relates to a wiring material used for a semiconductor device, and more particularly to a semiconductor wiring that does not lose conductivity even when exposed to a high-temperature oxidation process. The present invention also relates to a capacitor using the wiring as a lower electrode and a semiconductor device including the capacitor.

  Normally, the wiring is oxidized by a high temperature oxidation process to become an insulator. As a wiring subjected to such a process, there is a lower electrode of a capacitor.

Conventionally used lower electrode material is TiN, which has relatively high oxidation resistance. FIG. 8 shows XRD measurement results when this TiN film is annealed with oxygen (furnace 10 minutes). (M) is TiN during film formation, (n) is TiN after 300 ° C. annealing, and (o) to (t) are TiN when the annealing temperature is further increased every 50 ° C. As shown in the figure, the crystal peak of TiN is at 2θ = 22.6 °, and TiO ₂ is at 2θ = 25.3 ° (anatase crystal) and 27.4 ° (rutile crystal). A large peak around 2θ = 32.8 ° is a peak of the substrate Si.

Referring to FIG. 8, the oxygen annealing up to 400 ° C. ((m), (n), (o), (p)) has no change in the TiN peak intensity, but becomes 450 ° C. oxygen annealing ((q)). It begins to become a little smaller and disappears completely by oxygen annealing ((r), (s), (t)) at 500 ° C. or higher, and a TiO ₂ crystal peak can be seen instead. That is, the oxygen annealing temperature is limited to around 400 ° C. Therefore, it cannot be used for an oxide insulating film that crystallizes at higher temperatures.

  Further, when used as an electrode of a capacitor element, the higher the work function, the larger the offset between the Fermi level and the insulator conduction band, and there is an advantage that current leakage can be suppressed. In this case, an electrode material having a work function higher than that of the TiN electrode (work function 4.8 eV) is still desirable.

  Precious metals such as Pt (work function 5.4 eV) have a high work function. In addition, since these noble metals have extremely high oxidation resistance or do not lose their conductivity even when they become oxides oxidized at high temperatures (for example, ruthenium oxide and iridium oxide), these noble metals can be used as capacitor electrode materials. Many have been proposed. However, these noble metals are very expensive compared to other metal materials.

  Ni is cheap and has a work function of 5.05 eV, which is promising higher than TiN electrodes. Thus, when this material was examined, it was found that Ni is much easier to oxidize than TiN, and the oxidized NiO crystal is almost an insulator.

  As represented by stainless steel, a method for improving oxidation resistance by adding another metal element to a metal that is easily oxidized is known. For example, in the case of stainless steel, Cr is added to improve the oxidation resistance of iron (Fe), the main component, and a protective film of chromium oxide is formed on the surface to prevent internal metal corrosion. is doing.

  It is also known that the oxidation resistance of Ni is improved by alloying. For example, Patent Document 1 discloses an optical element that includes a protective film formed of a Ni-based alloy as an outermost layer. An alloy containing Ni, Cr, Ti, Cu, Al, Co, Fe, or the like can reliably prevent the optical element from being eroded by moisture or oxygen, and the reflectance of the optical element gradually decreases with erosion. It can be prevented. As a specific example, an alloy of Ni 50 wt% and Ti 50 wt% is shown.

  However, in these, a protective film having low oxygen permeability is formed on the surface of the alloy to prevent corrosion of the internal metal, and the conductivity of the material is not taken into consideration. In addition, when exposed to a high temperature oxidation process, such as the lower electrode of a capacitor, it is predicted that the protective film will become thicker. Since such a protective film is a metal oxide, it is generally an insulator. is there. The wiring material used for the semiconductor device is a very thin film (several tens to several hundreds of nanometers) due to the miniaturization of the semiconductor device, and the thinner the film material, the higher the probability that the entire film thickness is oxidized. Furthermore, the capacitive insulating film formed on the lower electrode has a thinner film thickness and easily transmits oxygen in the high temperature oxidation process. In addition, the surface of the lower electrode may be oxidized and the capacitance value may deviate from the intended design value.

JP 2006-173502 A

  The present invention provides a wiring material that does not lose electrical conductivity even at an oxidation treatment of 500 ° C., has a work function equal to or higher than TiN, and is cheaper than a noble metal.

  According to an embodiment of the present invention, the NiTi mixed film has a Ti content represented by Ti / (Ni + Ti) of 60-80 at. A semiconductor wiring having a composition ratio of% is provided.

Also, according to another embodiment of the present invention,
A capacitor comprising a lower electrode, a capacitive insulating film on the lower electrode, and an upper electrode on the capacitive insulating film,
The lower electrode is a NiTi mixed film, and the Ti content represented by Ti / (Ni + Ti) is 60-80 at. % Of the composition ratio,
There is provided a capacitor in which the capacitive insulating film is a film crystallized by an oxidation process at 500 ° C. or higher.

According to yet another embodiment of the invention,
A capacitor comprising a switching element formed on a semiconductor substrate, a lower electrode electrically connected to the switching element, a capacitive insulating film on the lower electrode, and an upper electrode on the capacitive insulating film;
A semiconductor device comprising:
The lower electrode of the capacitor is a NiTi mixed film, and has a Ti content expressed by Ti / (Ni + Ti) of 60-80 at. % Of a wiring material having a composition ratio of
A semiconductor device is provided in which the capacitor insulating film of the capacitor is a film crystallized by an oxidation process at 500 ° C. or higher.

  The conductivity is maintained even at a temperature higher than the oxygen annealing temperature at which TiN becomes an insulator, and the work function exceeds that of TiN.

It is a graph which shows the resistivity change (at the time of film-forming and after oxygen annealing) by Ti content in the NiTi mixed film which concerns on this invention. It is a figure which shows the inplane XRD measurement result of the NiTi mixed film after the oxygen annealing which concerns on this invention. It is a figure which shows the result of having measured the work function of Pt used as a prior art example. It is a figure which shows the result of having measured the work function of TiN used as a prior art example. It is a figure which shows the result of having measured the work function of Ni used as a prior art example. It is a figure which shows the result of having measured the work function of amorphous NiO. It is a figure which shows the result of having measured the work function of the NiTi mixed film after the oxygen annealing which concerns on this invention. It is an XRD measurement result when the TiN film is annealed (furnace 10 minutes). It is typical sectional drawing which shows the example which applied the NiTi mixed film which concerns on this invention to the capacitor. It is a figure which shows an example of the plane layout of the DRAM memory cell which applies the NiTi mixed film which concerns on this invention as a lower electrode material of a capacitor. FIG. 11 is a diagram showing a cross-sectional structure of a DRAM memory cell, and is a vertical cross-sectional view taken along line A-A ′ of FIG. 10. FIG. 12 is a process cross-sectional view illustrating a manufacturing process of the capacitor portion illustrated in FIG. 11. FIG. 12 is a process cross-sectional view illustrating a manufacturing process of the capacitor portion illustrated in FIG. 11. FIG. 12 is a process cross-sectional view illustrating a manufacturing process of the capacitor portion illustrated in FIG. 11.

  Embodiments of the present invention will be described below, but the present invention is not limited to these examples.

The semiconductor wiring according to the present invention is an electrode wiring mainly used for a lower electrode of a capacitor element, is a NiTi mixed film, and has a Ti content represented by Ti / (Ni + Ti) of 60-80 at. % Composition ratio. In the present invention, “NiTi mixed film” means both a NiTi alloy film at the time of film formation and a mixed film containing Ni and TiO ₂ after oxygen annealing unless otherwise specified. When there is a reference such as “after”, the latter means a mixed film containing Ni and TiO ₂ .

(Experimental example)
The following experiment was conducted on the semiconductor wiring according to the present invention.
As a sample, a NiTi alloy film was formed on SiO ₂ by multi-source sputtering. The target Ni and Ti are simultaneously sputtered and alloyed. The substrate temperature was 300 ° C., Ar gas was 100 sccm, and the total pressure was 5 Pa. Each of the Ni and Ti targets was RF-discharged and the RF power was changed to control the amount of each adhesion, thereby changing the composition ratio of the film from the amount of Ti (Ni) from 0 to 100%.

  FIG. 1 shows a NiTi alloy film produced in this way, measured for resistance by four-terminal resistance measurement, and converted into resistivity. The black (（) in the figure is the resistivity at the time of film formation. Thereafter, oxygen annealing was performed at 500 ° C. for 10 minutes, and 4-terminal resistance measurement was performed again. In the figure (black square) is the resistivity after annealing. Looking at the results, the Ti content represented by Ti / (Ni + Ti) is 60-80 at. %, The conductivity of the film remained, otherwise it became an insulator. Especially 60-75 at. %, The resistivity decreases from 400 μΩ · cm or more before oxygen annealing to around 100 μΩ · cm, which is the same level as that of the TiN electrode before oxygen annealing.

  FIG. 2 shows in-plane XRD measurement of the sample after oxygen annealing, and shows XRD measurement results for each Ti content (Ti / (Ti + Ni) × 100 (at.%: Hereinafter referred to as “%”)). is there. (A) Ti = 0%, (b) Ti = 10%, (c) Ti = 20%, (d) Ti = 40%, (e) Ti = 70%.

When the Ti content was 40% or less ((a), (b), (c), (d)), NiO (peak black Δ mark) was clearly generated, and therefore it was made into an insulator. In contrast, the 70% Ti content sample ((e)), which was a conductor, is completely different, and the crystal peaks are Ni (black square) and rutile TiO ₂ (black circle) crystals. Ni is not oxidized and only Ti is preferentially oxidized. In this process, Ni and Ti are separated, and it is considered that conductivity remains as a mixed film of Ni metal having good conductivity and TiO ₂ that is an insulator. A slight NiO broad peak (black Δ mark position) is seen, and amorphous NiO is generated. However, although NiO crystal is an insulator, it has been confirmed that amorphous NiO is a slightly high-resistance conductor, so that the conductivity is not lost.

  3 to 7 show the results of measuring the photoelectron intensity of various wiring materials related to the present invention by XPS. For the sake of accuracy, these are measured by the same XPS apparatus, and differences due to different apparatuses are not included. The vertical axis is a log scale, and the kinetic energy position at the boundary where photoelectrons start to be counted (more than noise) is approximately the work function value. Ultimately, an accurate work function value can be obtained by obtaining a photoelectron intensity measurement value by curve fitting using a Fowler function. 3 is Pt, FIG. 4 is TiN, FIG. 5 is Ni, FIG. 6 is amorphous NiO, and FIG. 7 is a NiTi mixed film of the present invention (NiTi alloy film with 70% Ti content is oxygen annealed at 500 ° C. for 10 minutes. ) Result. The NiTi mixed film of the present invention had a work function of 5.17 eV, which was higher than TiN (4.8 eV). This numerical value is higher than 5.05 eV for Ni and lower than 5.24 eV for amorphous NiO. The reason seems to be that the surface is a mixture of Ni and amorphous NiO.

  As described above, the semiconductor wiring according to the present invention is a material having a work function higher than that of TiN without losing conductivity even after high-temperature oxidation annealing.

  Next, an example in which the wiring material of the present invention is applied to a lower electrode of a capacitor will be shown. FIG. 9 is a longitudinal sectional view schematically showing the structure of the capacitor.

  The capacitor according to the present invention has a structure in which a capacitive insulating film 2 is sandwiched between a lower electrode 1 and an upper electrode 3. The upper electrode 3 is formed of a metal film, and a metal film such as Ru, Pt, Ir, Ti, W, Ta, or a nitride thereof (TiN, WN, TaN, etc.) can be used. In the present invention, the NiTi mixed film of the present invention is used as the lower electrode 1. That is, the capacitor according to the present invention is a MIM (Metal-Insulator-Metal) capacitor.

A known material can be used for the capacitor insulating film 2, but a material having a high relative dielectric constant is particularly preferable. An example of an insulating material for a capacitor having a high dielectric constant is TiO ₂ (titanium oxide). TiO ₂ has _two well-known crystal structures, anatase type and rutile type. Anatase crystals are a low-temperature phase that is easily formed at low temperatures and have a low relative dielectric constant of about 40. On the other hand, a rutile crystal is a high-temperature phase usually formed at a high temperature, and has a high relative dielectric constant of 80 or more. Particularly when used as an insulating material for a capacitor, a high-capacity capacitor can be manufactured.

The TiO ₂ film can be formed by various methods such as sputtering, CVD (Chemical Vapor Deposition), and ALD (Atomic Layer Deposition). When used in semiconductor devices, the ALD method is currently the mainstream from the viewpoint of miniaturization. However, when forming a TiO ₂ film used in a semiconductor device, it is difficult to form a high dielectric constant rutile crystal at a low temperature of 400 ° C. or lower by any method including the ALD method.

Thus, in the manufacturing process of the TiO ₂ film having a rutile crystal structure, a high-temperature oxidation process of 400 ° C. or higher, preferably 500 ° C. or higher is required. Further, the TiO ₂ film is excellent in relative dielectric constant, but has a narrow band gap width and inferior to other materials in terms of breakdown voltage leakage. Since the NiTi mixed film after oxygen annealing according to the present invention is a material having a work function superior to that of TiN, the breakdown voltage leakage can be improved as compared with the case where TiN is used as the lower electrode.

  Next, as a specific example to which the present invention is applied, a case where the present invention is used for a lower electrode of a capacitor element (capacitance element) constituting a memory cell of a DRAM element will be described.

  FIG. 10 is a conceptual diagram showing a planar layout of a memory cell portion in a DRAM which is a semiconductor device to which the present invention is applied. The right-hand side of FIG. 10 is shown as a transmission cross-sectional view with reference to a plane that cuts the gate electrode 5 and the side wall 5b, which will be described later, as the word wiring W. For simplification, the description of the capacitor is omitted in FIG.

  FIG. 11 is a schematic cross-sectional view corresponding to the line A-A ′ of the memory cell portion (FIG. 10). Note that these drawings are for explaining the structure of the semiconductor device, and the sizes, dimensions, and the like of the respective parts shown in the drawings are different from the dimensional relationship of an actual semiconductor device.

  As shown in FIG. 11, the memory cell section is schematically configured from a switching element such as a MOS transistor Tr1 for a memory cell and a capacitor Cap connected to the MOS transistor Tr1 through a plurality of contact plugs.

10 and 11, the semiconductor substrate 101 is formed of silicon (Si) containing a P-type impurity having a predetermined concentration. An element isolation region 103 is formed on the semiconductor substrate 101. The element isolation region 103 is formed in a portion other than the active region K by embedding an insulating film such as a silicon oxide film (SiO ₂ ) by a STI (Shallow Trench Isolation) method on the surface of the semiconductor substrate 101 and adjacent to the active region K. The area K is insulated and separated. In this embodiment, an example in which the present invention is applied to a cell structure in which 2-bit memory cells are arranged in one active region K is shown.

In the present embodiment, as in the planar structure shown in FIG. 10, a plurality of elongate strip-like active regions K are arranged in a diagonally downward right direction with a predetermined interval, and are generally called 6F type ² memory cells. Arranged along the layout.

  Impurity diffusion layers are individually formed at both ends and the center of each active region K and function as source / drain regions of the MOS transistor Tr1. The positions of the substrate contact portions 205a, 205b, and 205c are defined so as to be disposed immediately above the source / drain regions (impurity diffusion layers).

  In the horizontal (X) direction of FIG. 10, bit lines 106 are extended in a polygonal line shape (curved shape), and a plurality of bit lines 106 are arranged at predetermined intervals in the vertical (Y) direction of FIG. In addition, linear word lines W extending in the vertical (Y) direction of FIG. 10 are arranged. A plurality of individual word lines W are arranged at predetermined intervals in the horizontal (X) direction of FIG. 10, and the word lines W are configured to include the gate electrode 105 shown in FIG. Has been. In the present embodiment, the MOS transistor Tr1 includes a groove-type gate electrode.

  As shown in the cross-sectional structure of FIG. 11, an impurity diffusion layer 108 functioning as a source / drain region is formed in the active region K partitioned in the element isolation region 103 in the semiconductor substrate 101 so as to be separated from each other. Between these, a trench-type gate electrode 105 is formed.

  The gate electrode 105 is formed so as to protrude above the semiconductor substrate 101 by a multilayer film of a polycrystalline silicon film and a metal film, and the polycrystalline silicon film contains impurities such as phosphorus at the time of film formation by the CVD method. Can be formed. As the metal film for the gate electrode, a refractory metal such as tungsten (W), tungsten nitride (WN), tungsten silicide (WSi), or the like can be used.

Further, as shown in FIG. 11, a gate insulating film 105 a is formed between the gate electrode 105 and the semiconductor substrate 101. Further, a sidewall 105 b made of an insulating film such as silicon nitride (Si ₃ N ₄ ) is formed on the sidewall of the gate electrode 105. An insulating film 105 c such as silicon nitride is also formed on the gate electrode 105 to protect the upper surface of the gate electrode 105.

  The impurity diffusion layer 108 is formed by introducing, for example, phosphorus as an N-type impurity into the semiconductor substrate 101. A substrate contact plug 109 is formed so as to be in contact with the impurity diffusion layer 108. The substrate contact plugs 109 are respectively disposed at the positions of the substrate contact portions 205c, 205a, and 205b shown in FIG. 10, and are formed of, for example, polycrystalline silicon containing phosphorus. The width of the substrate contact plug 109 in the lateral (X) direction has a self-aligned structure defined by the sidewall 105b provided in the adjacent gate wiring W.

  As shown in FIG. 11, a first interlayer insulating film 104 is formed so as to cover the insulating film 105 c on the gate electrode and the substrate contact plug 109, and the bit line contact plug penetrates the first interlayer insulating film 104. 104A is formed. The bit line contact plug 104A is disposed at the position of the substrate contact portion 205a and is electrically connected to the substrate contact plug 109. The bit line contact plug 104A is formed by stacking tungsten (W) or the like on a barrier film (TiN / Ti) made of a stacked film of titanium (Ti) and titanium nitride (TiN). Bit wiring 106 is formed so as to be connected to bit line contact plug 104A. The bit wiring 106 is composed of a laminated film made of tungsten nitride (WN) and tungsten (W).

  A second interlayer insulating film 107 is formed so as to cover the bit wiring 106. A capacitor contact plug 107A is formed so as to penetrate the first interlayer insulating film 104 and the second interlayer insulating film 107 and connect to the substrate contact plug 109. The capacitor contact plug 107A is disposed at the position of the substrate contact portions 205b and 205c.

  On the second interlayer insulating film 107, a third interlayer insulating film 111 using silicon nitride and a fourth interlayer insulating film 112 using a silicon oxide film are formed.

  A capacitor Cap is formed through the third interlayer insulating film 111 and the fourth interlayer insulating film 112 so as to be connected to the capacitor contact plug 107A.

  The capacitor Cap has a structure in which a capacitive insulating film 114 is sandwiched between a lower electrode 113 and an upper electrode 115 to which the wiring material of the present invention is applied, and the lower electrode 113 is electrically connected to the capacitive contact plug 107A.

  A fifth interlayer insulating film 120 formed of silicon oxide or the like, an upper wiring layer 121 formed of aluminum (Al), copper (Cu), or the like, and a surface protective film 122 are formed on the upper electrode 115.

  A predetermined potential is applied to the upper electrode 115 of the capacitor Cap, and it functions as a DRAM element that performs an information storage operation by determining the presence or absence of electric charge held in the capacitor Cap.

Next, a specific method for forming the capacitor Cap will be described.
12-14, only the upper part from the 3rd interlayer insulation film 111 was described as sectional drawing.

  First, as shown in FIG. 12, after the third interlayer insulating film 111 and the fourth interlayer insulating film 112 are deposited with a predetermined film thickness, a capacitor Cap is formed by using a photolithography technique. An opening 112A is formed.

  As the lower electrode 113, a NiTi alloy film was formed by multi-source sputtering as shown in the above experimental example. Using a dry etching technique or a CMP (Chemical Mechanical Polishing) technique, the lower electrode 113 is formed so as to remain only on the inner wall portion of the opening 112A.

  Here, a NiTi alloy film containing 70% Ti is used as the lower electrode 113.

Next, as shown in FIG. 13, a TiO ₂ film having an anatase crystal structure is deposited to a thickness of 6 to 10 nm using the ALD method as the capacitor insulating film 114. Thereafter, annealing treatment was performed in an oxygen atmosphere set to 500 ° C. to obtain a TiO ₂ film having a rutile crystal structure. The oxygen atmosphere need not be 100% oxygen, and air was used here. Further, since the third interlayer insulating film 111 is formed of a silicon nitride film having oxidation resistance, the wiring material and the element under the capacitor are prevented from being oxidized.

  The lower electrode using the wiring material of the present invention is converted into a NiTi mixed film having a resistivity lower than that of the NiTi alloy film at the time of film formation, as shown in FIG. The

  Next, as shown in FIG. 14, the upper electrode 115 is formed by depositing a metal film so as to cover the surface of the capacitor insulating film 114 and fill the opening (112A). Here, an Ru film was deposited and patterned to form the upper electrode 115. Moreover, you may use the material inferior in oxidation resistance. Examples of other materials for forming the upper electrode 115 include metal films such as Pt, Ti, Ir, W, and Ta, and nitrides thereof. Further, the upper electrode may be formed as a laminated film of a plurality of materials. Thereby, the capacitor element Cap is completed.

  In this embodiment, the capacitor Cap is a cylinder type that uses only the inner wall of the lower electrode as an electrode, but is a crown type that uses both the outer wall and the inner wall of the lower electrode as an electrode, or only the outer wall of the lower electrode is used as an electrode. It is also possible to form a pedestal capacitor.

As the capacitor insulating film, a TiO ₂ film to which another element, for example, a lanthanoid element or the like is added may be used. Other examples include Al ₂ O ₃ , Ta ₂ O ₅ , LaO ₂ , and HfO ₂ films.

DESCRIPTION OF SYMBOLS 1 Lower electrode 2 Capacitance insulating film 3 Upper electrode 101 Semiconductor substrate 103 Element isolation region 104 1st interlayer insulation film 104A Bit line contact plug 105 Gate electrode 106 Bit wiring 107 2nd interlayer insulation film 107A Capacity contact plug 108 Impurity diffusion layer 109 substrate contact plug 111 third interlayer insulating film 112 fourth interlayer insulating film 113 lower electrode 114 capacitive insulating film 115 upper electrode 120 fifth interlayer insulating film 121 metal wiring layer 122 surface protection layer Tr MOS transistor Cap capacitor

Claims (16)

  A TiTi mixed film having a Ti content represented by Ti / (Ni + Ti) of 60-80 at. Semiconductor wiring with a composition ratio of%.   The Ti content is 60-75 at. The semiconductor wiring according to claim 1, wherein the composition ratio is%. The semiconductor wiring according to claim 1, wherein the NiTi mixed film is a mixed film containing Ni and TiO ₂ . 4. The semiconductor wiring according to claim 3, wherein the mixed film containing Ni and TiO ₂ is obtained by oxidizing the NiTi alloy film having the Ti content at 500 ° C. or more.   The semiconductor wiring according to claim 3 or 4, further comprising amorphous NiO. Ti content represented by Ti / (Ni + Ti) is 60-80 at. %, A manufacturing method of a semiconductor wiring comprising a NiTi mixed film having a composition ratio of
The manufacturing method which oxidizes the NiTi alloy film of said Ti content at 500 degreeC or more.   The Ti content is 60-75 at. The method for manufacturing a semiconductor wiring according to claim 6, wherein the composition ratio is%.   8. The method of manufacturing a semiconductor wiring according to claim 6, wherein the oxidation is performed by forming an oxide film that is crystallized by an oxidation process at 500 [deg.] C. or more on the NiTi alloy film. A capacitor comprising a lower electrode, a capacitive insulating film on the lower electrode, and an upper electrode on the capacitive insulating film,
The lower electrode is a NiTi mixed film, and the Ti content represented by Ti / (Ni + Ti) is 60-80 at. % Of the composition ratio,
A capacitor in which the capacitive insulating film is a film crystallized by an oxidation process at 500 ° C. or higher.   The Ti content is 60-75 at. The capacitor according to claim 9, wherein the composition ratio is%. The capacitor according to claim 9 or 10, wherein the lower electrode after the formation of the capacitive insulating film is a mixed film containing Ni and TiO ₂ .   The capacitor according to claim 11, wherein the mixed film further includes amorphous NiO. A capacitor comprising a switching element formed on a semiconductor substrate, a lower electrode electrically connected to the switching element, a capacitive insulating film on the lower electrode, and an upper electrode on the capacitive insulating film;
A semiconductor device comprising:
The lower electrode of the capacitor is a NiTi mixed film, and has a Ti content expressed by Ti / (Ni + Ti) of 60-80 at. % Of a wiring material having a composition ratio of
A semiconductor device, wherein the capacitor insulating film of the capacitor is a film crystallized by an oxidation process at 500 ° C. or higher.   The Ti content is 60-75 at. The semiconductor device according to claim 13, wherein the composition ratio is%. The capacitor lower electrode after the insulating film formation, a semiconductor device according to claim 13 or 14 which is a mixed film comprising Ni and TiO _2.   The semiconductor device according to claim 15, wherein the mixed film further includes amorphous NiO.