JP2005064466A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a disconnection of an electrode caused by performing a heat treatment of comparatively high temperature to dielectrics. <P>SOLUTION: A capacitive element 26 is provided with: a lower electrode 23 comprising polycrystals of oxide, nitride or oxynitride of a noble metal formed on a bottom face and a wall surface of an opening 22a provided on a third insulating film 22 on a semiconductor substrate 10; a capacitive insulating film 24 comprising the dielectrics formed on the lower electrode 23; and an upper electrode 25 comprising polycrystals of oxide, nitride or oxynitride of a noble metal formed on the capacitance insulating film 24. According to this configuration, it is possible to prevent disconnections of the lower electrode 23 and the upper electrode 25 and a diffusion of atoms constituting the capacitive insulating film 24, which are caused at the time of a heat treatment for crystallization of the dielectrics to the capacitive insulating film 24. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a so-called three-dimensional capacitor having a three-dimensional structure, and more particularly to a semiconductor device using a noble metal as a conductive film constituting an electrode of a three-dimensional capacitor and a method for manufacturing the same.

  A capacitive insulating film made of a high dielectric material or a ferroelectric material having a perovskite crystal structure, which is used in a semiconductor memory device such as a dynamic random access memory (DRAM) or a ferroelectric random access memory (FeRAM), is a crystal. It is necessary to perform heat treatment in a relatively high-temperature oxygen atmosphere in order to improve the quality and improve the film quality. During this heat treatment, if the composition ratio of the capacitive insulating film deviates from the design value due to, for example, the reaction between the capacitive insulating film and the electrode material, deterioration of characteristics such as a decrease in the amount of polarization and an increase in leakage current in the capacitive insulating film cause. Therefore, the conductive film material for forming the lower electrode or the upper electrode in contact with such a capacitive insulating film is platinum that has oxidation resistance and extremely low chemical reactivity so as to prevent the compositional deviation of the capacitive insulating film. (Pt) and ruthenium (Ru) are generally used.

  Further, along with miniaturization and high integration of semiconductor integrated circuits, miniaturization is also required for memory cells in DRAM devices and FeRAM devices. As a result, the capacitor element constituting the memory cell is about to have a three-dimensional shape, that is, a three-dimensional shape, in order to increase the capacitance per unit area.

  For example, in Patent Document 1 below, a lower electrode containing platinum or iridium is formed by a metal organic chemical vapor deposition (MOCVD) method on a base substrate having an uneven cross-sectional shape, and a dielectric is formed on the formed lower electrode. In this example, a capacitor is formed by sequentially forming a film and an upper electrode. By this method, the lower electrode can be formed with a uniform film thickness with good coverage even for a groove (concave portion) having a large aspect ratio.

  The following Patent Document 2 is an example of a capacitive element including a high dielectric film or a ferroelectric film having a three-dimensional shape, for example, a concave shape. After forming the lower conductive film along the recess by sputtering, an upper conductive film is formed on the formed lower conductive film by CVD to form an electrode film composed of the lower conductive film and the upper conductive film This prevents the electrode film from being interrupted (disconnected) at the bottom corner of the formed electrode film. As described above, the morphology of the lower conductive film is improved by using the sputtering method, and the film thickness of the upper conductive film becomes uniform by using the CVD method thereafter, so that the heat treatment for crystallization of the dielectric film is performed. Also in the process, since the lower conductive film and the upper conductive film are less likely to aggregate, it is possible to prevent discontinuity (disconnection) occurring at the bottom corner of the electrode film.

In Patent Document 3 below, film peeling of the lower electrode that occurs in the heat treatment process for crystallization of the dielectric film is prevented by forming an adhesive layer on the side wall portion of the lower electrode having a concave cross section. Here, the adhesive layer is an oxide using any one of titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), or a mixture of these oxides and other metals. Consists of. Further, a structure is disclosed in which a compound made of ruthenium barium strontium oxide ((Ba, Sr) RuO ₃ ) or an amorphous material containing ruthenium (Ru) or oxygen (O) is used for the adhesive layer. The composition of the lower electrode is ruthenium (Ru), ruthenium oxide (RuO ₂ ), or a mixture thereof.

In Patent Document 4 below, peeling of a metal film that occurs at the interface between a metal film made of a platinum group that constitutes a lower electrode of a capacitor element and an insulating film made of silicon oxide is nitrided between the metal film and the insulating film. This is prevented by providing an adhesive layer made of tantalum (TaN). Further, here, the upper end portion of the adhesive layer is removed so that the upper end portion of the adhesive layer is covered with the lower electrode, thereby preventing the adhesive layer from being oxidized.
JP 2001-160616 A JP 2002-231905 A JP 2001-223345 A JP 2002-76306 A

  A problem that arises when a ferroelectric nonvolatile memory (FeRAM) device having a capacitor having a concave structure obtained by the inventors of the present application is manufactured by a conventional method will be described.

  When a platinum (Pt) film, which is a metal film, is used for the lower electrode or the upper electrode of the capacitor, the platinum film is migrated or removed by high-temperature heat treatment in an oxygen atmosphere for subsequent crystallization of the ferroelectric film. Volume shrinkage occurs, and the platinum film breaks. Thus, when a disconnection occurs in the electrode film, the electrode area is reduced and the capacitance value of the memory is reduced. In addition, the stress at the time of migration deteriorates the quality of the ferroelectric film and causes characteristics such as leakage.

  In addition, when the platinum film is broken, a chemically very stable film other than platinum comes into contact with the ferroelectric film, or components of the film other than the platinum film diffuse into the ferroelectric film. Conversely, the ferroelectric film components diffuse into the film other than the platinum film, and the film quality of the ferroelectric film changes, resulting in a decrease in the amount of polarization and an increase in leakage due to a shift in the composition of the dielectric film. Will cause.

  The dielectric film grows and is oriented according to the crystallinity of the underlying platinum film, but if the underlying platinum film is broken, the dielectric film crystals located on the broken portion are crystallized. Sex will also be different from other parts.

  Hereinafter, a method for manufacturing the capacitor portion of the FeRAM device whose disconnection has been confirmed by the present inventors will be briefly described.

First, a recess having a depth of 300 nm to 500 nm and a taper angle of 70 ° to 80 ° is formed in the base insulating film by lithography and dry etching. Next, a platinum film having a film thickness of 50 nm is formed by sputtering to form the lower electrode of the capacitor along the recess on the base insulating film. Here, when the platinum film is formed directly on the base insulating film, the platinum film is peeled off at the time of film formation or heat treatment. Therefore, titanium nitride (TiN) or iridium oxide ( An adhesion layer made of IrO _x ) or the like is formed with a thickness of 10 nm. Next, the platinum film deposited on the portion other than the inner wall surface of the recess and the adhesion layer are removed by a chemical mechanical polishing (CMP) method using a strongly basic slurry until the base insulating film is exposed. Next, a strontium barium tantalate (SBT) film is formed on the platinum film by a metal organic vapor phase deposition (MOCVD) method so that the coverage is good with a thickness of 100 nm or less. Next, a platinum film having a thickness of 20 nm is formed on the SBT film by sputtering. Next, the upper electrode and the SBT film are patterned by lithography and dry etching. Next, an insulating film made of silicon oxide such as ozone-non-silicate glass (O ₃ -NSG) is formed to a thickness of 100 nm by a CVD method. Next, heat treatment is performed for 60 seconds in an oxygen atmosphere at a temperature of 750 ° C. by a rapid heating oxidation (RTO) method. It has been confirmed that when the SBT film, which is a ferroelectric film, is crystallized by this rapid thermal oxidation treatment, a disconnection occurs in the platinum film constituting the lower electrode and the upper electrode. At this time, the disconnection of the upper electrode was severer than that of the lower electrode, and the disconnection portion occurred irregularly (randomly) on the inner wall surface of the recess. Note that no peeling of the platinum film was observed. Due to this disconnection, it has been confirmed that the amount of polarization of the three-dimensional capacitor becomes about two-thirds or less, and the amount of leakage increases.

  Hereinafter, differences from the above-described patent documents will be described.

  The purpose of Patent Document 1 is to form the lower electrode uniformly with good coverage by the MOCVD method, and disconnection of the lower electrode is not listed as a problem.

  Patent Document 2 raises the problem that a wire breakage occurs at the corner of the bottom of the three-dimensional electrode during a relatively high-temperature heat treatment performed on the dielectric film, which is a capacitive film, by the electrode film formation method. . As a solution to this, Patent Document 2 prevents the disconnection of the electrode film by improving the morphology and the uniformity of the film thickness of the conductive electrode film, and no further prevention method is disclosed. Moreover, it is described that the disconnection which arises in an electrode film generate | occur | produces in the corner | angular part of the bottom part of this electrode film.

  On the other hand, patent document 3 makes the peeling of an electrode film a subject, and the disconnection which arises in this electrode film is not mentioned as a subject.

  In addition, Patent Document 4 mentions a configuration in which an adhesive layer is provided between an insulating film (underlayer film) and an electrode film, as in Patent Document 3, in order to prevent peeling of the electrode film. Covering with a film prevents oxidation of the adhesive layer.

  An object of the present invention is to solve the above-described problems and prevent disconnection of a conductive film provided in the vicinity of a dielectric even when a relatively high temperature heat treatment is performed on the dielectric. .

  In order to achieve the above object, a first semiconductor device according to the present invention includes a first conductive film formed on a bottom surface and a wall surface of an opening provided in an insulating film on a substrate, and a first conductive film. A capacitor element including a dielectric film formed on the film and a second conductive film formed on the dielectric film, wherein the dielectric film in the capacitor element is crystallized; The conductive film and the second conductive film are characterized by being made of a noble metal oxide, nitride, or oxynitride polycrystal.

  According to the first semiconductor device, the noble metal oxide, nitride, or oxynitride is used for the conductive film to be the electrode of the capacitor element, and the noble metal oxide, nitride, or oxynitride is made of only the noble metal. Since the migration resistance is higher than that of the conductive film and the volume shrinkage is small, disconnection of the conductive film caused by heat treatment for crystallization of the dielectric film can be prevented. In addition, since noble metal oxide, nitride, or oxynitride films are generally chemically stable, diffusion of atoms constituting the dielectric film can be prevented during heat treatment of the dielectric film. For this reason, since the decrease in the polarization amount of the dielectric can be suppressed, the reliability of the dielectric can be maintained, and as a result, a stable electrode can be realized.

  In the first semiconductor device, it is preferable that at least one of the first conductive film and the second conductive film has a grain size constituting a polycrystal of one third or less of the thickness of the conductive film. In this case, resistance to migration of the conductive film is improved, so that disconnection that occurs in the conductive film can be more reliably prevented.

  In the first semiconductor device, it is preferable that at least one of the first conductive film and the second conductive film contains a refractory metal. As described above, when a refractory metal is added to a conductive film, resistance to migration is higher than that of a conductive film to which no refractory metal is added, and the volume shrinkage rate is also reduced. The disconnection of the conductive film caused by can be prevented.

  Here, the refractory metal is preferably made of a metal different from the noble metal constituting the conductive film.

  The second semiconductor device according to the present invention is formed on the insulating film on the substrate in the shape of an island or along the uneven shape of the insulating film having the uneven shape of the cross section. A film, a dielectric film formed on the first conductive film, and a second conductive film formed on the dielectric film, wherein the first conductive film and the second conductive film are: It is made of a noble metal oxide, nitride, or oxynitride, and at least one of the first conductive film and the second conductive film contains a refractory metal.

  According to the second semiconductor device, the conductive film to which the refractory metal is added has higher resistance to migration and the volume shrinkage ratio is smaller than that of the conductive film to which the refractory metal is not added. The disconnection of the conductive film caused by the heat treatment performed on can be prevented.

  The first or second semiconductor device preferably further includes an adhesion layer between the insulating film and the first conductive film for improving the adhesion of the first conductive film to the insulating film. In this way, the resistance to migration of the first conductive film is further improved.

  In this case, the adhesion layer is preferably made of a conductive material that is not easily oxidized by the film quality improvement process performed on the dielectric film. In this way, even if the film is subjected to a heat treatment for improving the film quality of the dielectric film after the adhesion layer is formed, film peeling due to oxidation of the adhesion layer can be prevented.

  In the first or second semiconductor device, the amount of the refractory metal added to the conductive film is preferably 0.5% by mass or more and 30% by mass or less. Here, the refractory metal is preferably made of a metal different from the noble metal constituting the conductive film.

  In the first or second semiconductor device, the noble metal preferably contains iridium as a main component.

  In the first or second semiconductor device, the dielectric film is preferably a ferroelectric film made of a perovskite oxide.

  In this case, the ferroelectric film preferably contains bismuth as a main component.

  In the first method of manufacturing a semiconductor device according to the present invention, after forming an opening in an insulating film on a substrate, an oxide, nitride, or oxynitride of a noble metal is formed on the bottom surface and wall surface of the formed opening. A step (a) of forming a first conductive film comprising: a step (b) of forming a dielectric film on the first conductive film; and a noble metal oxide or nitride on the dielectric film. Or a step (c) of forming a second conductive film made of oxynitride, and a step (d) of crystallizing the formed dielectric film after the step (c). In the step (c), each of the first conductive film and the second conductive film has a polycrystalline structure.

  According to the first method for manufacturing a semiconductor device, the noble metal oxide, nitride, or oxynitride is used for the conductive film. Therefore, the noble metal oxide, nitride, or oxynitride migrates compared to the noble metal. Since the resistance is high and the volume shrinkage rate is small, disconnection of the conductive film caused by the heat treatment for crystallization of the dielectric film can be prevented. In addition, since noble metal oxide, nitride or oxynitride films are generally chemically stable, diffusion of atoms constituting the dielectric film is prevented during heat treatment of the dielectric film. For this reason, since the decrease in the polarization amount of the dielectric can be suppressed, the reliability of the dielectric film can be maintained, and as a result, a stable electrode can be obtained from the conductive film.

  In the second method for manufacturing a semiconductor device according to the present invention, the first conductive film is formed in an island shape on the insulating film on the substrate, or the upper portion of the insulating film is formed in a concavo-convex shape and then formed. A step (a) of forming a first conductive film along the uneven shape, a step (b) of forming a dielectric film on the first conductive film, and a second step on the dielectric film. A step (c) of forming a conductive film, and a step (d) of crystallizing the formed dielectric film after the step (c), wherein the first conductive film and the second conductive film are: It is made of a noble metal oxide, nitride, or oxynitride, and at least one of the first conductive film and the second conductive film contains a refractory metal.

  According to the second method for manufacturing a semiconductor device, since the refractory metal is added to at least one of the first conductive film and the second conductive film, the refractory metal is not added to the conductive film to which the refractory metal is added. Compared to the conductive film, the resistance to migration is high and the volume shrinkage rate is small, so that disconnection of the conductive film caused by, for example, heat treatment for crystallizing the dielectric film can be prevented.

  In the manufacturing method of the first or second semiconductor device, in the step (a) and the step (c), the first conductive film or the second conductive film is formed at a temperature of 300 ° C. or more and 600 ° C. or less. Is preferred. Thus, since the first conductive film or the second conductive film is formed at a relatively high temperature of 300 ° C. or more and 600 ° C. or less as the film formation temperature, the conductive film is formed on the dielectric film. Since the conductive film has already received a relatively high thermal history during the heat treatment for improving the film quality of the dielectric film performed at a temperature higher than the film formation temperature, the amount of heat shrinkage of the conductive film due to the heat treatment on the dielectric film As a result, disconnection occurring in the conductive film can be prevented.

  In the manufacturing method of the first or second semiconductor device, in the step (d), the dielectric film is preferably heat-treated at a temperature of 500 ° C. or higher and 800 ° C. or lower.

  In the first or second method for manufacturing a semiconductor device, the difference between the heating temperature for crystallization of the dielectric film and the formation temperature for forming the first conductive film and the second conductive film is It is preferably within 200 ° C. In this way, during the heat treatment for improving the film quality of the dielectric film, each conductive film has already received a thermal history within 200 ° C. with respect to the heat treatment temperature applied to the dielectric film. Since the amount of thermal contraction of the conductive film due to heat treatment is reduced, disconnection generated in the conductive film can be prevented.

  In the manufacturing method of the first or second semiconductor device, the temperature higher than the formation temperature of the first conductive film and the second conductive film and the temperature at which the dielectric film crystallizes before the step (d). It is preferable to further include a step (e) of performing a heat treatment on the first conductive film and the second conductive film at a low temperature. In this case, the conductive film is already higher than the formation temperature of the conductive film during the heat treatment for crystallization of the dielectric film performed on the dielectric film at a temperature higher than the film formation temperature of the conductive film. Is subjected to a heat treatment at a temperature lower than the temperature at which the dielectric film is crystallized, so that the amount of thermal contraction of the conductive film is reduced during the heat treatment for crystallizing the dielectric film, so that disconnection occurring in the conductive film can be prevented. .

  In the first or second method for manufacturing a semiconductor device, a step (f) of forming a protective insulating film so as to cover the second conductive film after the step (c) and before the step (d). Is preferably further provided. Thus, during the heat treatment for improving the film quality of the dielectric film, the second conductive film is not directly exposed to the high temperature atmosphere by the protective insulating film thereon, and the thermal contraction amount of the second conductive film is reduced. Therefore, disconnection that occurs in the second conductive film can be prevented.

  In the method for manufacturing the first or second semiconductor device, the step (a) includes the step of forming the insulating film and the first conductive film on the insulating film before forming the first conductive film. It is preferable to include the process of forming the contact | adherence layer which improves adhesiveness. In this way, resistance to migration with respect to the first conductive film is further improved.

  In the method for manufacturing the first semiconductor device, it is preferable that at least one of the first conductive film and the second conductive film contains a refractory metal.

  In the first or second method for manufacturing a semiconductor device, the noble metal preferably contains iridium as a main component.

  In the first or second method for manufacturing a semiconductor device, the dielectric film is preferably a ferroelectric film made of a perovskite oxide.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, it is possible to prevent the conductive film from being disconnected by a heat treatment applied to the dielectric film that is the capacitive film after the conductive film to be the electrode of the capacitive element is formed. it can.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a cross-sectional configuration of a semiconductor memory device according to a first embodiment of the present invention.

  As shown in FIG. 1, for example, each element formation region partitioned by a shallow trench isolation (STI) region 11 formed on an upper part of a semiconductor substrate 10 made of silicon (Si) includes a gate. A plurality of transistors 15 each including a gate electrode 13 with an insulating film 12 interposed therebetween and an impurity diffusion layer 14 formed on both sides of the gate electrode 13 are formed.

On the semiconductor substrate 10, a first interlayer insulating film 16 made of silicon oxide having a film thickness of about 0.4 μm to 0.8 μm is formed so as to cover each transistor 15. Here, so-called BPSG (Boro-Phospho-Silicate Glass) to which boron (B) and phosphorus (P) are added to silicon oxide, or so-called HDP-NSG which is formed by high-density plasma and does not contain boron or phosphorus. (High Density Plasma-Non Silicate Glass) or O ₃ —NSG using ozone (O ₃ ) in an oxidizing atmosphere may be used.

  A first contact plug 17 electrically connected to the impurity diffusion layer 14 is formed on one impurity diffusion layer 14 of the transistor 15 in the first interlayer insulating film 16. As a material of the first contact plug, tungsten (W), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), or tantalum nitride (TaN) is used. Further, titanium (Ti), nickel (Ni) or cobalt (Co) metal silicide, copper (Cu), or polycrystalline silicon doped with impurities may be used.

  A plurality of bit wirings 18 made of tungsten or polycrystalline silicon are selectively formed on the first interlayer insulating film 16 whose upper surface is planarized and electrically connected to the first contact plug 17. Yes.

  A second interlayer insulating film 19 is formed on the first interlayer insulating film 16 so as to cover each bit line 18. The second interlayer insulating film 19 needs to be thick enough to prevent oxidation of each bit wiring 18.

  A second contact plug 20 electrically connected to the impurity diffusion layer 14 is formed on the other impurity diffusion layer 14 of the transistor 15 in the first interlayer insulating film 16 and the second interlayer insulating film 19. Has been. The second contact plug 20 may be made of a material equivalent to the material used for the first contact plug 17.

The second contact plug 20 is electrically connected to the second interlayer insulating film 19 whose upper surface is planarized, and the periphery of the second contact plug 20 on the second interlayer insulating film 19 A plurality of oxygen barrier films 21 that also covers the portions are formed. Examples of the material of the oxygen barrier film 21 include titanium aluminum nitride (TiAlN), titanium aluminum oxynitride (TiAlON), titanium nitride (TiN), iridium oxide (IrO _x ), iridium (Ir), ruthenium oxide (RuO _x ), Alternatively, ruthenium (Ru) may be used, and a stacked structure including at least two of them may be used. Here, x in the general formulas of iridium oxide and ruthenium oxide is a positive real number.

  On the second interlayer insulating film 19, a third interlayer insulating film 22 having an opening exposing each oxygen barrier film 21 and having a film thickness on the oxygen barrier film 21 of about 300 nm to 700 nm is formed. Yes. The film thickness of the third interlayer insulating film 22 is a parameter that determines the capacitance value of a capacitive element to be described later.

Each opening in the third interlayer insulating film 22 has a lower electrode 23 and an upper electrode 25 made of, for example, a noble metal oxide, nitride, or oxynitride, and a capacitive insulating film 24 along the wall surface and bottom surface thereof. A capacitive element 26 is formed. Specific materials of the lower electrode 23 and the upper electrode 25 are platinum (Pt), iridium (Ir), ruthenium (Ru), gold (Au), silver (Ag), palladium (Pd), rhodium (Rh), or osmium. There are oxides, nitrides or oxynitrides of (Os). For example, when an oxide is used, it is iridium oxide (IrO ₂ ), ruthenium oxide (RuO ₂ ), silver oxide (Ag ₂ O), or the like.

Further, as the capacitor insulating film 24, a barium strontium titanate (Ba _x Sr _1-x TiO ₃ ) (provided that x is 0 ≦ x ≦ 1, hereinafter referred to as BST) -based dielectric. Or lead zirconium titanate (Pb (Zr _x T _1-x ) O ₃ ) (where x is 0 ≦ x ≦ 1, hereinafter referred to as PZT) or lead lanthanum zirconium titanate (Pb _y La _{1 -y} (Zr _x Ti _1-x ) O 3) (where x and y are 0 ≦ x, y ≦ 1) or the like, or a perovskite-based dielectric material containing strontium bismuth tantalate (Sr _1-y Bi _{2 + x} Ta ₂ O ₉ ) (where x and y are 0 ≦ x and y ≦ 1, hereinafter referred to as SBT) or bismuth lanthanum titanate (Bi _4−x La _x Ti ₃ O ₁₂ ) (Where x is 0 ≦ x ≦ 1), etc., a perovskite-based dielectric containing bismuth Can be used to manufacture a nonvolatile memory device.

For the ferroelectric film, a compound having a perovskite structure represented by a general formula ABO ₃ (however, A and B are different elements) can be used. Here, the element A is, for example, lead (Pb), barium (Ba), strontium (Sr), calcium (Ca), lanthanum (La), lithium (Li), sodium (Na), potassium (K), magnesium. (Mg) and at least one selected from the group consisting of bismuth (Bi), and the element B is, for example, titanium (Ti), zirconium (Zr), niobium (Nb), tantalum (Ta), tungsten (W ), Iron (Fe), nickel (Ni), scandium (Sc), cobalt (Co), hafnium (Hf), magnesium (Mg), and molybdenum (Mo).

  The capacitor insulating film 24 is not limited to a single-layer ferroelectric film, and a plurality of ferroelectric films having different compositions may be used. Further, the composition is inclined by changing different compositions continuously. A configuration may be adopted.

Needless to say, the capacitor insulating film 24 according to the present invention is not limited to a ferroelectric substance, and silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), niobium pentoxide (Nb ₂ O _5). ), Tantalum pentoxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), or the like may be used.

  A fourth interlayer insulating film 27 is formed on the third interlayer insulating film 22 so as to fill the concave portion of the capacitive element 26. The first contact plug 17 and the bit wiring 18 are electrically connected on the first contact 17 in the second interlayer insulating film 19, the third interlayer insulating film 22, and the fourth interlayer insulating film 27. A third contact plug 28 is formed. Again, the third contact plug 28 may be made of a material equivalent to the material used for the first contact plug 17 and the second contact plug 20.

  Hereinafter, a method of manufacturing the semiconductor memory device configured as described above will be described with reference to the drawings.

  2 (a) to 2 (d) to 6 (a) to 6 (c) show cross-sectional structures in the order of steps of the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention. .

First, as shown in FIG. 2A, the STI region 11 is selectively formed on the semiconductor substrate 10, and the semiconductor substrate 10 is partitioned into a plurality of element formation regions by the formed STI region 11. Subsequently, each element formation region includes, for example, a gate insulating film 12 made of silicon oxide or silicon oxynitride and having a thickness of about 3 nm, and a gate electrode 13 having a thickness of about 200 nm including polycrystalline silicon, metal, or metal silicide. And the impurity diffusion layer 14 is formed by ion implantation of impurity ions using the gate electrode 13 as a mask, thereby forming the transistors 15. Subsequently, an insulating film such as BPSG, HDP-NSG, or O ₃ -NSG is formed by CVD to a thickness of about 0.6 μm to 1.2 μm, and then chemical mechanical polishing (Chemical Mechanical Polishing). The first interlayer insulating film 16 having a thickness of about 0.4 μm to 0.8 μm is formed by planarizing the surface of the formed insulating film by using the CMP method.

  Next, as shown in FIG. 2B, a first contact hole 16a exposing one impurity diffusion layer 14 of each transistor 15 is formed in the first interlayer insulating film 16 by lithography and dry etching. To do.

  Next, as shown in FIG. 2C, the first contact is formed so that the first contact hole 16a is filled on the first interlayer insulating film 16 by sputtering, CVD, or plating. A plug forming film 17A is formed. Here, as described above, the first contact plug forming film 17A uses a metal such as tungsten, a metal nitride such as titanium nitride, a metal silicide such as titanium silicide, copper, or polycrystalline silicon. Further, before forming the first contact plug formation film 17A, an adhesion layer made of, for example, titanium and titanium nitride, or a laminated film of tantalum and tantalum nitride, which are sequentially laminated from the substrate side, may be formed.

  Next, as shown in FIG. 2D, the first contact plug formation film 17A that has been formed is etched back or subjected to CMP until the first interlayer insulating film 16 is exposed. The first contact plug 17 electrically connected to one impurity diffusion layer 14 of each transistor 15 is formed from the contact plug formation film 17A.

  Next, as shown in FIG. 3A, a conductive film made of, for example, tungsten or polycrystalline silicon is formed on the first interlayer insulating film 16 by a sputtering method, a CVD method, or a furnace, A plurality of bit lines 18 are formed from the conductive film by patterning the conductive film so as to be connected to the first contact plug 17 by lithography and etching. At this time, when the wiring material is tungsten, for example, an etching gas obtained by mixing a chlorine-based gas and a fluorine-based gas may be used, and when polycrystalline silicon is used, a fluorine-based gas may be used. Further, when tungsten is used for the bit wiring 18, an adhesion layer made of a laminated film of, for example, titanium and titanium nitride sequentially laminated from the substrate side may be formed before the tungsten film is formed. The thickness of each bit wiring 18 is determined by wiring resistance and design rules, and is preferably about 20 nm to 150 nm. Further, when forming a stack type contact plug with the wiring above the capacitor element, a bit wiring pattern is formed in advance so as to cover one of the first contact plugs 17. May be.

  Next, as shown in FIG. 3B, a second interlayer insulating film 19 made of BPSG or the like having a thickness of about 200 nm to 800 nm is formed on each bit on the first interlayer insulating film 16 by CVD. A film is formed so as to cover the wiring 18. Subsequently, the formed second interlayer insulating film 19 is planarized by performing CMP, etch back or reflow processing. By this planarization treatment, it is easy to form a capacitor element provided on the second interlayer insulating film 19. In particular, when the CMP method is used, the stepped portion caused by each bit wiring 18 on the second interlayer insulating film 19 can be further flattened. The film thickness X of the upper portion of each bit wiring 18 in the second interlayer insulating film 19 is preferably set to 50 nm to 500 nm, which is a film thickness that can prevent the oxidation of each bit wiring 18.

  Next, as shown in FIG. 3C, the other impurity diffusion layer 14 of each transistor 15 is exposed to the first interlayer insulating film 16 and the second interlayer insulating film 19 by lithography and dry etching. A second contact hole 19a is formed.

  Next, as shown in FIG. 3D, the second contact hole 19a is filled on the second interlayer insulating film 19 by sputtering, CVD, or plating. A plug forming film (not shown) is formed. Here, the material of the second contact plug formation film may be the same as that of the first contact plug 17. Also in this case, an adhesive layer made of a laminated film of titanium nitride and titanium or tantalum nitride and tantalum may be formed before the second contact plug formation film is formed. Thereafter, etch back or CMP treatment is performed on the formed second contact plug formation film until the second interlayer insulating film 19 is exposed. From the second contact plug formation film, the other of the transistors 15 is removed. A second contact plug 20 electrically connected to the impurity diffusion layer 14 is formed.

  Next, as shown in FIG. 4A, on the second interlayer insulating film 19, for example, by sputtering, CVD, or metal organic chemical vapor deposition (MOCVD), An oxygen barrier formation film 21A having a thickness of 50 nm to 250 nm and preventing the second contact plug 20 from being oxidized is formed on the entire surface of the second interlayer insulating film 19. As described above, titanium nitride, titanium aluminum nitride, titanium aluminum oxynitride, iridium or an oxide thereof, or ruthenium or an oxide thereof is used as the material of the oxygen barrier formation film 21A.

  Next, as shown in FIG. 4B, the second contact plugs 20 and their peripheral portions are respectively covered by a lithography method and a dry etching method using a mixed gas of a chlorine-based gas and a fluorine-based gas. By patterning in this manner, a plurality of oxygen barrier films 21 are formed from the oxygen barrier forming film 21A. Although not shown, when the second contact plug formation film is removed from the second interlayer insulating film 19, a concave portion (recessed portion) generated on the upper end surface of each second contact plug 20 is formed. The oxygen barrier film 21 may be embedded.

  Next, as shown in FIG. 4C, a third interlayer insulating film 22 made of BPSG or the like having a thickness of about 900 nm to 1400 nm is formed on the second interlayer insulating film 19 by the CVD method. A film is formed so as to cover the barrier film 21. Subsequently, a planarization process is performed on the formed third interlayer insulating film 22 by a CMP method. At this time, the thickness of the third interlayer insulating film 22 on each oxygen barrier film 21 is a parameter that determines the capacitance value of the capacitor, and is preferably about 300 nm to 700 nm.

  Next, as shown in FIG. 4D, the central portion of each oxygen barrier film 21, that is, the upper portion of the second contact plug 20 is formed with respect to the third interlayer insulating film 22 by lithography and etching. A plurality of exposed openings 22a are formed. Here, the etching for forming the opening 22a may be dry etching or wet etching.

  The opening 22a has a shape in which the opening widens from the bottom surface toward the top surface, that is, the wall surface of the opening portion is tapered in the cross-sectional view shown in FIG.

  Next, as shown in FIG. 5A, the wall surface of each opening 22a and the third interlayer insulating film 22 are formed on the third interlayer insulating film 22 at a temperature of about 200 ° C. to 500 ° C. by sputtering, CVD, or MOCVD. A lower electrode formation film 23A made of a noble metal oxide such as platinum or iridium, nitride or oxynitride and having a thickness of about 20 nm to 60 nm is formed over the entire surface including the bottom surface.

Here, film forming conditions when iridium oxide (IrO ₂ ) is used for the lower electrode forming film 23A will be described.

  First, film forming conditions for forming the lower electrode forming film 23A made of iridium oxide by sputtering are shown below.

Target material: Iridium (Ir)
Substrate temperature: 300 ° C to 500 ° C
Pressure: 0.5 Pa to 0.8 Pa
Power: 0.8kW to 3.5kW
Sputtering gas: Argon (Ar)
Oxidizing gas: Oxygen (O ₂ )
Gas ratio: O ₂ / Ar = 1-3
Next, film forming conditions for forming the lower electrode forming film 23A made of iridium oxide by MOCVD instead of sputtering will be shown.

Organometallic raw material (precursor) containing iridium
: Dimethyliridium cyclooctadiene
Solvent: Tetrahydrafuran Temperature of vaporizer: 60 ° C to 120 ° C
Oxidizing gas: oxygen (O ₂ ) [flow rate: 50 to 150 ml / min]
Carrier gas: Argon (Ar) [flow rate: 150 to 250 ml / min]
Pressure: 133Pa-266Pa
Temperature: 250 ° C-450 ° C
Here, the noble metal nitride film is formed using nitrogen gas in the case of sputtering, and the noble metal oxynitride film is formed using nitrogen gas and oxygen gas. In the case of MOCVD, film formation is performed by appropriately using a raw material containing nitrogen or oxygen. As a result, the lower electrode formation film 23A has a polycrystalline structure in both the sputtering method and the MOCVD method.

  Thus, by forming the lower electrode formation film 23A using the MOCVD method, the coverage on the wall surface and the bottom surface of the opening 22a of the third interlayer insulating film 22 in the lower electrode formation film 23A is improved. In addition, by using a noble metal oxide or nitride for the lower electrode formation film 23A, the contraction rate of the electrode formation film is reduced, so that disconnection of the electrode formation film can be prevented.

  Next, as shown in FIG. 5B, the lower electrode formation film 23A deposited on the third interlayer insulating film 22 is removed by CMP so that the third interlayer insulating film 22 is exposed. The lower electrode 23 is formed from the lower electrode forming film 23A on the wall surface and the bottom surface of the opening 22a of the third interlayer insulating film 22.

  Here, instead of using the CMP method, an insulating film (sacrificial film, not shown) is deposited so as to fill the recess of the lower electrode 23 formed in the opening 22 a of the third interlayer insulating film 22. Etching back the entire surface of the insulating film by dry etching may remove portions other than the lower electrode 23 in the lower electrode forming film 23A until the third interlayer insulating film 22 is exposed. Thereafter, the sacrificial film on the lower electrode 23 is removed by wet etching using hydrofluoric acid (HF) or the like.

  Next, as shown in FIG. 5C, the entire surface including the lower electrodes 23 having a concave cross section on the third interlayer insulating film 22 is formed on the third interlayer insulating film 22 by a sputtering method or an MOCVD method. A capacitive insulating film forming film 24A having a thickness of 40 nm to 100 nm is formed. As described above, a ferroelectric material such as BST, PZT, or SBT is used for the capacitor insulating film forming film 24A.

  Subsequently, an oxide, nitride or acid of noble metal such as platinum or iridium is formed on the capacitor insulating film forming film 24A by sputtering, CVD or MOCVD under the same film forming conditions as the lower electrode forming film 23A. An upper electrode formation film 25A made of nitride polycrystal and having a thickness of 20 nm is formed. In the first embodiment, the underlying layer of the lower electrode formation film 23A and the upper electrode formation film 25A is the third interlayer insulating film 22 having an opening 22a.

  Next, as shown in FIG. 5D, the capacitive insulating film formation film 24A and the upper electrode formation film 25A are formed by a lithography method and a dry etching method using a mixed gas of a chlorine-based gas and a fluorine-based gas. By patterning so as to cover the lower electrode 23, the capacitive insulating film 24 is formed from the capacitive insulating film forming film 24A, and the upper electrode 25 is formed from the upper electrode forming film 25A. As a result, a capacitive element 26 having a concave cross section composed of the lower electrode 23, the capacitive insulating film 24 and the upper electrode 25 is formed.

  Next, as shown in FIG. 6A, a fourth interlayer insulating film 27 made of BPSG or the like is formed on the third interlayer insulating film 22 so as to cover the capacitive element 26 by the CVD method. . Thereafter, the surface of the formed fourth interlayer insulating film 27 is planarized by CMP. The film thickness above the upper end of the capacitor 26 in the fourth interlayer insulating film 27 after planarization is preferably 100 nm to 300 nm. Subsequently, heat treatment is performed at a high temperature and in an oxygen atmosphere for improving the film quality of the capacitor insulating film 24, such as crystallization of a ferroelectric forming the capacitor insulating film 24. This heat treatment may be annealing using a furnace, or rapid thermal annealing (RTA). The heating temperature is preferably 500 ° C. or higher and 800 ° C. or lower. Furthermore, it is preferable that the difference between the heat treatment temperature for the capacitor insulating film 24 and the temperature at which the lower electrode 23 and the upper electrode 25 are formed is within 200 ° C. For example, when the heating temperature for improving the film quality of the capacitive insulating film 24 is 700 ° C., the lower electrode 23 and the upper electrode 25 are preferably formed at a temperature of 500 ° C. or higher.

  The heat treatment for improving the film quality of the capacitor insulating film 24 may be performed before the formation of the fourth interlayer insulating film 27. However, the inventors of the present application have made the upper electrode 25 covered with the insulating film. It has been found that the thermal contraction of the upper electrode 25 is smaller when the heat treatment is performed than when the upper electrode 25 is exposed to a thermal atmosphere. Therefore, the film quality of the capacitive insulating film 24 is improved also here. The heat treatment to be performed is preferably performed after the fourth interlayer insulating film 27 is formed.

  Further, after the formation of the upper electrode 25 and before the heat treatment for improving the film quality of the capacitor insulating film 24, the capacitor insulating film 24 is formed with respect to the upper electrode 25 at a temperature higher than the formation temperature of the upper electrode 25. It is preferable to perform the heat treatment at a temperature lower than the temperature at which the ferroelectric crystallizes. Here, for example, after the formation of the upper electrode formation film 25A, heat treatment may be performed at about 600 ° C. for about 60 seconds. Furthermore, since the stress due to shrinkage during the heat treatment increases as the area of the upper electrode formation film 25A increases, it is more preferable after patterning. Thereby, before the heat treatment for improving the film quality of the capacitor insulating film 24, the lower electrode 23 and the upper electrode 25 are crystallized by a ferroelectric material that is higher than the formation temperature of these electrodes and that constitutes the capacitor insulating film 24. A heat treatment is previously performed at a temperature lower than the temperature. For this reason, since the rapid thermal contraction of the electrodes 23 and 25 during the heat treatment for crystallization of the capacitive insulating film 24 is suppressed, disconnection of the electrodes 23 and 25 can be reduced.

  Next, as shown in FIG. 6B, the bit wiring 18 is exposed to the fourth interlayer insulating film 27, the third interlayer insulating film 22, and the second interlayer insulating film 19 by lithography and dry etching. A third contact hole 27a is formed.

  Next, as shown in FIG. 6C, the third contact is made so that the third contact hole 27a is filled on the fourth interlayer insulating film 27 by sputtering, CVD, or plating. A plug forming film (not shown) is formed. Here, the material of the third contact plug formation film may be the same as that of the first contact plug 17. Also in this case, an adhesion layer made of a laminated film of titanium nitride and titanium or tantalum nitride and tantalum may be formed before forming the third contact plug formation film. Thereafter, etch back or CMP processing is performed on the formed third contact plug formation film until the fourth interlayer insulating film 27 is exposed, and each bit wiring 18 and the third contact plug formation film are formed from the third contact plug formation film. A third contact plug 28 to be electrically connected is formed. Thus, a so-called stack contact is formed by the first contact plug 17, the bit line 18 and the third contact plug 28.

The disconnection rate of the electrode (conductive film) in the capacitor thus formed will be described with reference to FIG. FIG. 7 shows the thickness ratio of each electrode when iridium (Ir), iridium oxide (IrO _x ), iridium nitride (IrN), and iridium oxynitride (IrON) are used as electrode materials, and the heat treatment of the capacitive insulating film. It shows the relationship with the probability of occurrence of disconnection.

  As shown in FIG. 7, when iridium is used as an electrode material, the disconnection occurrence rate when the value of the film thickness ratio between the thinnest part and the thickest part of the electrode is 0.8 or less. Was 100%, and even when the film thickness ratio was 1.0 when the film thickness was uniform, the disconnection occurrence rate was 30%. On the other hand, when iridium oxide was used for the electrode, the disconnection rate was 0% when the film thickness ratio was 0.8 or more and 1.0 or less. When iridium nitride is used for the electrode, the disconnection rate is 10% or less when the film thickness ratio is 0.6 or more and 1.0 or less, and 0% when the film thickness ratio is 0.7 or more and 1.0 or less. It was. When iridium oxynitride is used for the electrode, the disconnection rate is 10% or less at a film thickness ratio of 0.5 or more and 1.0 or less, and 0% at 0.7 or more and 1.0 or less. Met. That is, when a noble metal oxide, nitride or oxynitride is used as the electrode material and the film is formed such that the ratio of the minimum value to the maximum value in the film thickness is 0.8 or more and 1.0 or less In addition, disconnection of the capacitor element can be prevented.

  Further, if the thickness of the thinnest portion of the electrode is about 15 nm, the original role as the electrode is not deteriorated and disconnection hardly occurs.

  Therefore, the occurrence of disconnection of the electrode can be reduced when a noble metal oxide, nitride, or oxynitride is used rather than when a noble metal is used for the electrode of the capacitor. Further, when noble metal nitride is used for the electrode, the disconnection can be most effectively reduced.

  As described above, according to the first embodiment, only the noble metal oxide, nitride, or oxynitride is used for the lower electrode 23 and the upper electrode 25 of the so-called concave capacitor 26 having a concave cross section. Therefore, it is possible to prevent a situation in which the lower electrode 23 and the upper electrode 25, in particular the upper electrode 25, are disconnected during the crystallization heat treatment of the capacitive insulating film 24 and a leak occurs.

  The crystallization of the ferroelectric requires a relatively high temperature heat treatment of 500 ° C. or higher and 800 ° C. or lower, so that the effect of the present invention is great.

Further, when a ferroelectric made of a perovskite oxide is used for the capacitor insulating film 24, a heat treatment at a higher temperature is required as compared with a paraelectric such as tantalum pentoxide (Ta ₂ O ₅ ). The effect of the present invention is great.

  Further, when a perovskite-based oxide containing bismuth is used for the capacitor insulating film 24, a heat treatment at a higher temperature is required as compared with a perovskite-based oxide containing lead, and thus the effect of the present invention is further increased.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 8 shows a cross-sectional structure of a semiconductor memory device according to the second embodiment of the present invention. In FIG. 8, the same components as those shown in FIG.

  As shown in FIG. 8, in the second embodiment, a lower electrode 23 </ b> B made of, for example, iridium oxide constituting the capacitive element 26 is a relatively large film of 300 nm to 700 nm on the second interlayer insulating film 19. It is thick and formed in an island shape. In other words, the lower electrode 23B is formed so as to have a convex shape in the cross-sectional view shown in FIG.

  Thus, the capacitive insulating film 24 made of a ferroelectric material such as BST and the upper electrode 25 made of, for example, iridium oxide are formed so as to cover the island-like lower electrode 23B. Each cross-sectional shape is convex upward.

  Even if the capacitive element 26 having such a configuration is exposed to a heat treatment in a high temperature and oxygen atmosphere for improving the film quality of the capacitive insulating film 24, the upper part made of a noble metal oxide such as iridium oxide is used. Since the thermal contraction rate of the electrode 25 is smaller than the thermal contraction rate of the upper electrode made of iridium, the volume of the upper electrode 25 contracts, so that, for example, the bent portion or the like in the convex shape does not break. Similarly, when the upper electrode 25 made of a noble metal nitride or oxynitride such as iridium is used, disconnection due to thermal contraction of the upper electrode can be suppressed.

  Hereinafter, a method of manufacturing the semiconductor memory device configured as described above will be described with reference to the drawings.

  9 (a) to 9 (d) and FIGS. 10 (a) to 10 (c) show cross-sectional structures in the order of steps of the method of manufacturing a semiconductor memory device according to the second embodiment of the present invention. . Here, the same steps as those of the first embodiment are omitted, and the process of forming the island-shaped lower electrode 23B, which is a feature of the second embodiment, will be described.

  As shown in FIG. 9 (a), a noble metal oxide such as platinum or iridium, nitride or oxynitride is formed on the entire surface of the second interlayer insulating film 19 by sputtering, CVD or MOCVD. Thus, a lower electrode formation film 23A having a thickness of about 500 nm is formed.

  Next, as shown in FIG. 9B, the second contact plug 20 and its peripheral portion are respectively covered with the lower electrode formation film 23A formed by lithography and dry etching. By patterning, a plurality of lower electrodes 23B are formed from the lower electrode formation film 23A.

  Next, as shown in FIG. 9C, the entire surface of the second interlayer insulating film 19 is covered with, for example, a ferroelectric so as to cover each lower electrode 23 by sputtering or MOCVD. A capacitor insulating film formation film 24A having a thickness of 50 nm to 100 nm is formed. Here, a ferroelectric material such as BST, PZT, or SBT is used for the capacitor insulating film forming film 24A. Subsequently, from a noble metal oxide such as platinum or iridium, nitride or oxynitride on the capacitor insulating film formation film 24A by sputtering or MOCVD under the same film formation conditions as the lower electrode formation film 23A. Thus, an upper electrode formation film 25A having a thickness of 20 nm is formed. In the second embodiment, the base layer of the upper electrode formation film 25A is the third interlayer insulating film 22 in a state where the island-shaped lower electrode 23B is formed.

  Next, as shown in FIG. 9 (d), the capacitive insulating film forming film 24A and the upper electrode forming film 25A are patterned by the lithography method and the dry etching method so as to cover the lower electrode 23B. The capacitor insulating film 24 is formed from the film forming film 24A, and the upper electrode 25 is formed from the upper electrode forming film 25A. As a result, a capacitive element 26 having a convex cross section composed of the lower electrode 23B, the capacitive insulating film 24, and the upper electrode 25 is formed.

  Next, as shown in FIG. 10A, a third interlayer insulating film 22 made of BPSG or the like is formed on the second interlayer insulating film 19 so as to cover the capacitive element 26 by the CVD method. . Thereafter, the surface of the formed third interlayer insulating film 22 is planarized by CMP. The film thickness on the upper side of the capacitive element 26 in the third interlayer insulating film 22 after planarization is preferably 100 nm to 300 nm. Subsequently, heat treatment is performed at a high temperature and in an oxygen atmosphere for improving the film quality of the capacitor insulating film 24, such as crystallization of a ferroelectric forming the capacitor insulating film 24. This heat treatment may be annealing using a furnace or rapid heat treatment (RTA). The heating temperature is preferably 500 ° C. or higher and 800 ° C. or lower. Furthermore, the difference between the heat treatment temperature for the capacitive insulating film 24 and the temperature when forming the lower electrode 23 and the upper electrode 25 is preferably within 200 ° C. That is, when the heating temperature for improving the film quality of the capacitive insulating film 24 is 700 ° C., the lower electrode 23B and the upper electrode 25 are preferably formed at 500 ° C.

  The heat treatment for improving the film quality of the capacitor insulating film 24 may be performed before the third interlayer insulating film 22 is formed. However, as described in the first embodiment, the film quality of the capacitor insulating film 24 is improved. The heat treatment for achieving the above is preferably performed after the formation of the third interlayer insulating film 22.

  Also in the second embodiment, for example, after the upper electrode formation film 25A is formed, it is preferable to perform a heat treatment at a temperature of about 600 ° C. for about 60 seconds. Furthermore, since the stress due to shrinkage during the heat treatment increases as the area of the upper electrode formation film 25A increases, it is more preferable after patterning.

  Next, as shown in FIG. 10B, a third contact hole 27a that exposes the bit wiring 18 in the third interlayer insulating film 22 and the second interlayer insulating film 19 is formed by lithography and dry etching. Form.

  Next, as shown in FIG. 10C, the third contact is made so that the third contact hole 27a is filled on the third interlayer insulating film 22 by sputtering, CVD, or plating. A plug forming film (not shown) is formed. Here, the material of the third contact plug formation film may be the same as that of the first contact plug 17. Further, an adhesion layer made of a laminated film of titanium nitride and titanium or tantalum nitride and tantalum may be formed before forming the third contact plug formation film. Thereafter, etch back or CMP treatment is performed on the formed third contact plug formation film until the third interlayer insulating film 22 is exposed, and each bit wiring 18 and the third contact plug formation film are formed from the third contact plug formation film. A third contact plug 28 to be electrically connected is formed. Thus, a so-called stack contact is formed by the first contact plug 17, the bit line 18 and the third contact plug 28.

  As described above, according to the second embodiment, since the noble metal oxide is used for the upper electrode 25 having the bent portion constituting the capacitive element 26 having a convex cross section, the crystallization of the capacitive insulating film 24 is performed. During the heat treatment, it is possible to prevent a situation in which the upper electrode 25 is disconnected due to volume shrinkage or the like, or leakage occurs in the capacitor insulating film 24.

(One Modification of Second Embodiment)
Hereinafter, a modification of the second embodiment of the present invention will be described with reference to the drawings.

  FIG. 11 shows a cross-sectional configuration of a semiconductor memory device according to a modification of the second embodiment of the present invention. In FIG. 11, the same components as those shown in FIG.

  As shown in FIG. 11, in this modification, a lower electrode 23B made of iridium oxide constituting the capacitive element 26 is embedded in the lateral region with a third interlayer insulating film 22, and the capacitive insulating film 24B and The upper electrode 25B is formed on the lower electrode 23B and the third interlayer insulating film 22 whose surfaces are planarized.

  Therefore, in the present modification, the base layer of the upper electrode formation film 25A is the third interlayer insulating film 22 and the capacitor insulating film 24B.

  Also in this modified example having such a configuration, since the noble metal oxide is used for the upper electrode 25B having the bent portion constituting the capacitive element 26 having a convex cross section, the capacitor insulating film 24 is subjected to the heat treatment for crystallization. Thus, it is possible to prevent a situation in which the lower electrode 23B or the upper electrode 25B is disconnected or a leak occurs in the capacitor insulating film 24.

  In the first embodiment, the second embodiment, and the modifications thereof, the electrode of the capacitive element 26 is taken as an example of the conductive film that can prevent disconnection, but the present invention is not limited to the electrode of the capacitive element. . For example, the conductive film has a concave section or a convex section, that is, a bent portion, and after the conductive film having the bent portion is formed, a heat treatment at a temperature higher than the film formation temperature of the conductive film is performed. It is extremely effective for such semiconductor processes.

  The transistor 15 is not necessarily formed directly on the semiconductor substrate 10, and may be formed, for example, in a partial region of a semiconductor layer that is epitaxially grown on the substrate.

  In addition, a hydrogen permeable barrier film for preventing reduction of the capacitive insulating film 24, which is a ferroelectric film, by a hydrogen atmosphere covers the upper or lower portion of the capacitive element or the capacitive element, and further completely surrounds the capacitive element. You may form in.

(Knowledge by the present inventors)
Hereinafter, as a result of repeated examinations by various experiments on the cause of the disconnection that occurs when the conductive film having a bent portion is subjected to heat treatment at a temperature higher than the film forming temperature, the inventors have found the following knowledge. Have gained.

  First, the inventors of the present application are considered to cause disconnection when forming a conductive film having a concave section or a convex section, that is, a bent section, by a precious metal such as platinum (Pt) that is generally used because of its oxidation resistance. It has been determined that platinum has low resistance to migration, and it has been confirmed that disconnection is easily caused by heat treatment at a temperature higher than the film formation temperature of platinum.

  Therefore, the first finding is that when a noble metal oxide or nitride is used as the material of the conductive film, disconnection due to heat treatment does not occur in the conductive film having a bent portion. Since noble metal oxides or nitrides have higher migration resistance and smaller volume shrinkage than the noble metal, the conductive film can be prevented from being disconnected during heat treatment of other members such as a dielectric film. This is because noble metals are generally chemically stable, so that, for example, diffusion of atoms constituting the ferroelectric can be prevented during heat treatment of the ferroelectric. For this reason, since the decrease in the polarization amount of the ferroelectric can be suppressed, the reliability of the ferroelectric can be maintained, and a stable electrode can be formed.

The second finding is that the film thickness of the conductive film made of noble metal oxide, nitride or oxynitride is such that the value of the ratio between the smallest part and the largest part is 0.8 or more. This is because disconnection due to heat treatment does not occur in the conductive film having a bent portion. Again, the composition of the conductive film is not limited. When a thick part and a thin part are mixed in the conductive film, atoms (molecules) in the thin part tend to move (migrate) to the thick part, so the thin part breaks. Will end up. In particular, when the conductive film is formed along the uneven shape of the base layer, the formed conductive film tends to be thin at the stepped portion, and the change in the film thickness of the conductive film is large at the corner or corner. In this case, disconnection is likely to occur. As an example, preferable materials having a ratio of the smallest part to the largest part of the conductive film of 0.8 or more include titanium nitride (TiN), iridium oxide (IrO _x ), titanium aluminum nitride (TiAlN), There is titanium aluminum oxynitride (TiAlON). FIG. 12 shows the relationship between the value of the ratio between the smallest part and the largest part when titanium nitride is used for the conductive film and the probability of occurrence of disconnection. As shown in FIG. 12, when the ratio value between the smallest part and the largest part of the conductive film is set to 0.8 or more, it is understood that no disconnection occurs in the conductive film.

  The third finding is that when the volume contraction rate of the conductive film by the heat treatment during the formation of the dielectric film or after the film formation is set to 30% or less, the conductive film having the bent portion is not disconnected by the heat treatment. Is. Note that the conductive film only needs to have conductivity, and is not limited to a metal, an oxide or a nitride of the metal, or a mixture thereof. As an example, an iridium (Ir) oxide is a material in which the volume shrinkage of the conductive film during heat treatment of the dielectric film is 30% or less. FIG. 13 shows the relationship between the volume shrinkage due to heat treatment and the probability of occurrence of disconnection when platinum (Pt) is used for the conductive film. As shown in FIG. 13, when the volume shrinkage ratio of the conductive film exceeds 30%, it is found that the conductive film is disconnected.

  A fourth finding is that when the reduction rate of the lattice constant of the conductive film by the heat treatment after the dielectric film is formed is set to 25% or less, the conductive film having a bent portion is disconnected by the heat treatment. Does not occur. Again, the composition of the conductive film is not limited. As an example, an iridium (Ir) oxide is a material in which the reduction rate of the lattice constant of the conductive film during the heat treatment of the dielectric film is 25% or less. FIG. 14 shows the relationship between the lattice constant reduction rate due to heat treatment and the probability of disconnection when platinum (Pt) is used for the conductive film. As shown in FIG. 14, when the rate of decrease of the lattice constant of platinum exceeds 25%, it can be seen that the conductive film is disconnected.

  The fifth finding is that when a refractory metal is added to the conductive film, disconnection due to heat treatment is prevented in the conductive film having a bent portion. This is because a conductive film containing a refractory metal has a smaller volume shrinkage ratio than a conductive film that does not contain a refractory metal, and therefore prevents disconnection that occurs in the conductive film during heat treatment of the dielectric film. Can do. Again, the composition of the conductive film is not limited. The refractory metal is preferably tungsten (W), tantalum (Ta), niobium (Nb), molybdenum (Mo), vanadium (V), or chromium (Cr). Note that the metal used for the refractory metal is a metal different from the noble metal used for the conductive film. FIG. 15 shows the relationship between the addition amount and the disconnection rate when a refractory metal is added to the conductive film. As shown in FIG. 15, when adding niobium to a conductive film made of iridium oxide, for example, if the amount of niobium added is 35% by mass or more, the conductive film is difficult to dissolve, so addition of niobium added to the conductive film The amount is preferably 0.5% by mass to 30% by mass. Furthermore, 5 mass%-30 mass% are preferable.

  The sixth finding is that the value of the ratio between the film thickness (in nanometers) of the conductive film and the shrinkage rate (percentage) of the conductive film by the heat treatment when the dielectric film is formed or after the film formation is determined. If it is 1.5 or more, disconnection due to heat treatment does not occur in the conductive film having a bent portion. FIG. 16 shows the relationship between the ratio of the absolute value of the film thickness and the absolute value of the shrinkage rate and the probability of occurrence of disconnection when platinum (Pt) is used for the conductive film. As shown in FIG. 16, when the value of the ratio of the film thickness (in nanometers) of the conductive film to the shrinkage rate (percentage) of the conductive film is 1.5 or more, disconnection that occurs in the conductive film can be prevented. I understand. Note that the maximum value of the thickness of the conductive film is such that the capacitor can be formed in the concave portion of the base layer. For example, if the film thickness is such that the recess is filled with the conductive film, the capacitive element cannot be formed.

  The seventh finding is that when the size of the grains constituting the polycrystalline conductive film is set to one third or less of the film thickness of the conductive film, the conductive film having a bent portion is not disconnected by heat treatment. Is. According to the experiments by the inventors of the present application, the disconnection generated in the conductive film having the bent portion, that is, the concave section or the convex section is caused by the fact that the grain grain boundaries are arranged in the film thickness direction and are weak against tensile stress. Make sure you do. Therefore, if the size of the grain is set to one third or less of the film thickness of the conductive film, the number of grains in the film thickness direction becomes relatively large, and the stress applied to the conductive film is easily relaxed. Disconnection is less likely to occur in the conductive film having

  The eighth finding is that if the aspect ratio (depth / opening diameter) of the concave portion provided in the insulating film serving as the base layer of the capacitive element is 2 or less, the conductive film having the bent portion is not disconnected by heat treatment. Is. FIG. 17 shows the relationship between the aspect ratio value of the recess and the probability of occurrence of disconnection. As shown in FIG. 17, it is understood that disconnection can be prevented by setting the aspect ratio value to 2 or less. When the value of the aspect ratio is larger than 2, the coverage of the conductive film to the concave portion of the underlying layer is extremely deteriorated, so that disconnection is likely to occur.

  The ninth finding is that when the wall surface of the concave portion or the side surface of the convex portion in the underlayer is formed so as to form an angle (taper angle) of 0 ° or more and 80 ° or less with respect to the main surface of the underlayer. The disconnection due to heat treatment does not occur in the conductive film. FIG. 18 shows the relationship between the taper angle and the probability of occurrence of disconnection. As shown in FIG. 18, when the taper angle is set to 80 ° or less, coverage to a concave portion or a convex portion of the base layer in the conductive film is improved, so that disconnection generated in the conductive film can be prevented.

  A tenth finding is that when a conductive film is formed on a dielectric film at a temperature of 300 ° C. or higher and 600 ° C. or lower, disconnection due to heat treatment does not occur in the conductive film having a bent portion. As in the first and second embodiments, when the conductive film is formed at a relatively high temperature of 300 ° C. or higher, the conductive film for improving the film quality of the dielectric film is formed. In the heat treatment performed at a temperature higher than the film formation temperature, since the conductive film has already received a relatively high thermal history, the amount of thermal contraction of the conductive film due to the heat treatment on the dielectric film is reduced. Disconnection can be prevented. On the other hand, when the conductive film is formed at 600 ° C. or higher, the film formation process is changed from supply rate control to reaction rate control, so that the coverage to the concave or convex portions of the underlayer is reduced, contact plugs, bit wirings, etc. It will also oxidize other members.

  The eleventh finding is that if the difference between the temperature at the time of heat treatment for the dielectric film and the temperature at the time of forming the conductive film is set within 200 ° C., the conductive film having a bent portion is not disconnected by the heat treatment. is there. This knowledge is also applied to the dielectric film in the heat treatment performed at a temperature higher than the film formation temperature for improving the film quality of the dielectric film as in the first and second embodiments. Since the thermal history within 200 ° C. has already been received with respect to the heat treatment temperature, the amount of thermal contraction of the conductive film due to the heat treatment on the dielectric film is reduced, and as a result, disconnection occurring in the conductive film can be prevented. Note that the heat treatment temperature for the dielectric film is not necessarily higher than the formation temperature of the conductive film, and depending on the material of the dielectric film and the conductive film, the heat treatment temperature for the dielectric film is lower than the formation temperature of the conductive film. There may be cases.

  The twelfth finding is that, after the conductive film is formed and before the heat treatment of the dielectric film, the temperature is higher than the temperature at which the conductive film is formed and lower than the temperature at which the dielectric crystallizes. When the heat treatment is performed, the disconnection due to the heat treatment does not occur in the conductive film having the bent portion. As this knowledge was also obtained in the first and second embodiments, by giving the conductive film a thermal history by heat treatment at a temperature higher than the formation temperature of the conductive film and lower than the temperature at which the dielectric crystallizes, Since the conductive film can be prevented from rapidly shrinking during the heat treatment of the dielectric, disconnection generated in the conductive film can be prevented.

  A thirteenth finding is that when a dielectric film is subjected to heat treatment in a state where a protective insulating film is formed on the conductive film, disconnection due to the heat treatment does not occur in the conductive film having a bent portion. As in the first and second embodiments, when this heat treatment is performed on the dielectric film with the conductive film (upper electrode) covered with the protective insulating film (interlayer insulating film), the surface of the conductive film is also obtained. Since the morphology can be improved and shrinkage of the conductive film can be suppressed, disconnection generated in the conductive film can be prevented.

  According to a fourteenth finding, when an adhesive layer that improves the adhesion of the conductive film to the base layer is provided between the base layer having a recess or a protrusion on the upper surface and the conductive film, the conductive film having a bent portion is disconnected by heat treatment. Does not occur. This makes it difficult for migration to occur in the conductive film (lower electrode) during the heat treatment for improving the film quality of the dielectric, so that disconnection occurring in the conductive film can be prevented.

  According to the fifteenth finding, when an adhesion layer that enhances adhesion with the upper electrode is formed on the upper electrode using a gas that does not contain hydrogen atoms, disconnection due to heat treatment does not occur in the upper electrode having a bent portion. Is. This is because when the adhesion layer is formed using a gas containing hydrogen atoms, the dielectric film is deteriorated by the hydrogen atoms. Therefore, when the dielectric film is made of a ferroelectric material, the amount of polarization of the dielectric film is reduced, so that it is desirable to form the film without containing hydrogen atoms.

  In addition, as a specific example of the electrically conductive film in each knowledge demonstrated above, the upper electrode and lower electrode which concern on 1st Embodiment, 2nd Embodiment, and its modification are mentioned.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings. In the third embodiment, a configuration based on the above-described fourteenth knowledge of the present invention will be described.

  FIG. 19 shows a cross-sectional structure of a semiconductor memory device according to the third embodiment of the present invention. 19, the description of the same components as shown in FIG. 1 is omitted by retaining the same reference numerals.

  As shown in FIG. 19, an adhesion layer 30 having a thickness of about 10 nm is formed between the third interlayer insulating film 22 and the lower electrode 23.

  The adhesion layer 30 is preferably made of a material that is difficult to oxidize because when it is oxidized by heat treatment for improving the film quality of the capacitive insulating film 24, it causes thermal expansion or increases contact resistance. In particular, when a metal oxide, nitride, or oxynitride is used, adhesion can be improved and oxidation of the adhesion layer 30 can be reliably prevented.

Here, as specific examples of the adhesion layer 30, tantalum (Ta), titanium aluminum nitride (TiAlN), titanium aluminum (TiAl), titanium aluminum oxynitride (TiAlON), iridium oxide (IrO ₂ ), ruthenium oxide (RuO) ₂ ), tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride silicide (AlSiN), or tantalum nitride silicide (TaSiN) is preferred.

Note that the lower electrode 23 and the upper electrode 25 constituting the capacitive element 26 according to the third embodiment need not necessarily use a noble metal oxide such as iridium oxide (IrO ₂ ) as in the first embodiment. Alternatively, a conventional main component of a noble metal such as platinum or iridium may be used.

  The semiconductor device and the manufacturing method thereof according to the present invention have an effect of preventing the conductive film from being disconnected during the heat treatment performed on the dielectric film after the formation of the conductive film. This is useful for a semiconductor device having a capacitive film made of a ferroelectric material so as to be in contact with a certain conductive film, a manufacturing method thereof, and the like.

1 shows a cross-sectional configuration of a semiconductor device according to a first embodiment of the present invention. (A)-(d) is the structure sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(d) is the structure sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(d) is the structure sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(d) is the structure sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(c) is the structure sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a graph which shows the relationship between the film thickness ratio of the electrically conductive film in the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention, and the generation | occurrence | production probability of a disconnection. 3 shows a cross-sectional configuration of a semiconductor device according to a second embodiment of the present invention. (A)-(d) is the structure sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(c) is the structure sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. 8 shows a cross-sectional configuration of a semiconductor device according to a modification of the second embodiment of the present invention. It is a graph which shows the relationship between the value of the ratio of the smallest part in a conductive film of this invention, and the largest part, and the generation probability of a disconnection. It is a graph which shows the relationship between the volume shrinkage rate at the time of using platinum for the electrically conductive film of this invention, and the generation probability of a disconnection. It is a graph which shows the relationship between the decreasing rate of the lattice constant at the time of using platinum for the electrically conductive film of this invention, and the generation | occurrence | production probability of a disconnection. is there. It is a graph which shows the relationship between the addition amount of a refractory metal of this invention, and the occurrence probability of a disconnection. It is a graph which shows the relationship between the value of the ratio of the film thickness (nanometer unit) of an electrically conductive film of this invention, and shrinkage | contraction rate (percentage), and the occurrence probability of a disconnection. It is a graph which shows the relationship between the value of an aspect-ratio of this invention, and the occurrence probability of a disconnection. It is a graph which shows the relationship between the taper angle of the wall surface of a recessed part in the base layer of this invention, or the side surface of a convex part, and the occurrence probability of a disconnection. 4 shows a cross-sectional configuration of a semiconductor device according to a third embodiment of the present invention.

Explanation of symbols

10 semiconductor substrate 11 shallow trench isolation region 12 gate insulating film 13 gate electrode 14 impurity diffusion layer 15 transistor 16 first interlayer insulating film 16a first contact hole 17 first contact plug 17A first contact plug forming film 18 bit Wiring 19 Second interlayer insulating film 19a Second contact hole 20 Second contact plug 21 Oxygen barrier film 21A Oxygen barrier forming film 22 Third interlayer insulating film 22a Opening 23 Lower electrode 23A Lower electrode forming film 23B Lower electrode 24 capacitive insulating film 24A capacitive insulating film forming film 24B capacitive insulating film 25 upper electrode 25A upper electrode forming film 25B upper electrode 26 capacitive element 27 fourth interlayer insulating film 27a third contact hole 28 third contact plug 30 adhesion layer

Claims (20)

A first conductive film formed on a bottom surface and a wall surface of an opening provided in an insulating film on the substrate; a dielectric film formed on the first conductive film; and A capacitor element made of a second conductive film formed on
The dielectric film in the capacitive element is crystallized,
The semiconductor device, wherein the first conductive film and the second conductive film are made of a noble metal oxide, nitride, or oxynitride polycrystal.   2. The grain size constituting at least one of the first conductive film and the second conductive film is less than one third of the film thickness of the conductive film. The semiconductor device described.   The semiconductor device according to claim 1, wherein at least one of the first conductive film and the second conductive film contains a refractory metal. A first conductive film formed on the insulating film on the substrate in an island shape or along the concave-convex shape of the insulating film having a cross-sectional concave-convex shape;
A dielectric film formed on the first conductive film;
A second conductive film formed on the dielectric film,
The first conductive film and the second conductive film are made of a noble metal oxide, nitride, or oxynitride, and at least one of the first conductive film and the second conductive film is a refractory metal. A semiconductor device comprising:   5. The adhesive layer according to claim 1, further comprising an adhesion layer that enhances adhesion of the first conductive film to the insulating film between the insulating film and the first conductive film. Semiconductor device.   The semiconductor device according to claim 5, wherein the adhesion layer is made of a conductive material that is not easily oxidized by a film quality improvement process performed on the dielectric film.   The ratio of the refractory metal contained in the first conductive film or the second conductive film is 0.5% by mass or more and 30% by mass or less. Semiconductor device.   The semiconductor device according to claim 1, wherein the noble metal contains iridium as a main component.   5. The semiconductor device according to claim 1, wherein the dielectric film is a ferroelectric film made of a perovskite oxide. Forming an opening in the insulating film on the substrate and then forming a first conductive film made of a noble metal oxide, nitride, or oxynitride on the bottom surface and wall surface of the formed opening (a )When,
Forming a dielectric film on the first conductive film (b);
Forming a second conductive film made of a noble metal oxide, nitride or oxynitride on the dielectric film (c);
A step (d) of crystallizing the formed dielectric film after the step (c);
In the step (a) and the step (c), each of the first conductive film and the second conductive film has a polycrystalline structure. The first conductive film is formed in an island shape on the insulating film on the substrate, or the upper part of the insulating film is formed in a concavo-convex shape, and then the first conductive film is formed along the formed concavo-convex shape. Forming (a);
Forming a dielectric film on the first conductive film (b);
A step (c) of forming a second conductive film on the dielectric film;
A step (d) of crystallizing the formed dielectric film after the step (c);
The first conductive film and the second conductive film are made of a noble metal oxide, nitride, or oxynitride, and at least one of the first conductive film and the second conductive film is a refractory metal. A method for manufacturing a semiconductor device, comprising:   The said 1st electrically conductive film and said 2nd electrically conductive film are formed in the said process (a) and the said process (c) at the temperature of 300 degreeC or more and 600 degrees C or less, It is characterized by the above-mentioned. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.   12. The method of manufacturing a semiconductor device according to claim 10, wherein in the step (d), the dielectric film is subjected to heat treatment at a temperature of 500 ° C. or higher and 800 ° C. or lower.   The difference between the heating temperature for crystallizing the dielectric film and the forming temperature for forming the first conductive film and the second conductive film is within 200 ° C. A method for manufacturing a semiconductor device according to 10 or 11. Prior to step (d),
With respect to the first conductive film and the second conductive film, the temperature is higher than the formation temperature of the first conductive film and the second conductive film and lower than the temperature at which the dielectric film is crystallized. The method of manufacturing a semiconductor device according to claim 10, further comprising a step (e) of performing a heat treatment. After step (c) and before step (d),
12. The method for manufacturing a semiconductor device according to claim 10, further comprising a step (f) of forming a protective insulating film so as to cover the second conductive film.   The step (a) includes a step of forming an adhesion layer for improving adhesion between the insulating film and the first conductive film on the insulating film before forming the first conductive film. 12. The method of manufacturing a semiconductor device according to claim 10, further comprising:   The method for manufacturing a semiconductor device according to claim 10, wherein at least one of the first conductive film and the second conductive film contains a refractory metal.   The method of manufacturing a semiconductor device according to claim 10, wherein the noble metal contains iridium as a main component. 12. The method of manufacturing a semiconductor device according to claim 10, wherein the dielectric film is a ferroelectric film made of a perovskite oxide.

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