JP2013038279A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with excellent reliability.SOLUTION: A resistance-change-type nonvolatile memory device 100 includes a semiconductor substrate, a metal layer, a lower electrode, a resistance change layer, an upper electrode, and a spacer part. The metal layer (metal adhesion layer 142) is provided above the semiconductor substrate 102. The lower electrode 144 is provided on the metal adhesion layer 142 and is connected to the metal adhesion layer 142. The upper electrode 148 is located above the lower electrode 144 and is provided at a position facing the lower electrode 144. The resistor change layer 146 is provided between the lower electrode 144 and the upper electrode 148, and extends closer to an outside than to a region in which the lower electrode 144 and the upper electrode 148 are overlapped. The spacer part 150 is provided between the portion extending toward the outside of the resistor change layer 146 and the metal adhesion layer 142.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

In the field of non-volatile memories, researches such as ferroelectric memories (FeRAM), MRAMs (magnetic RAMs), OUMs (Ovonic Unified Memory), etc. are actively conducted with flash memories at the top.

Recently, a resistance variable nonvolatile memory (resistance variable nonvolatile memory element: resistance RAM) different from these conventional nonvolatile memories has been proposed (Non-patent Document 1). This variable resistance nonvolatile memory is a nonvolatile memory in which information can be written and non-destructive reading of information can be performed by setting the resistance value of the variable resistance layer of the memory cell by applying a voltage pulse. . In addition, since the resistance change type nonvolatile memory has a small cell area and can be multi-valued, it has a possibility of surpassing existing nonvolatile memories. PCMO (Pr _0.7 Ca _0.3 MnO ₃ ) and YBCO (YBa ₂ Cu ₃ O _y ) are used as the resistance change layer of Non-Patent Document 1. Other proposals have been made for variable resistance nonvolatile memories (Non-Patent Document 2 and Non-Patent Document 3). In Non-Patent Document 2, approximately 50 nm of polycrystalline NiOx (x = 1 to 1.5) is used as the resistance change layer. By applying a positive voltage to the upper electrode, the low resistance state or the high resistance state is applied. It is stated that it changes. In Non-Patent Document 3, 80 nm microcrystalline TiO ₂ is used for the variable resistance layer.
Non-Patent Document 4 and Non-Patent Document 5 describe the switching principle of a variable resistance nonvolatile memory element.

  Further, FIG. 2 of Patent Document 1 and FIG. 27 of Patent Document 2 describe the structure of a conventional nonvolatile memory. This nonvolatile memory has a structure in which a lower electrode layer, a resistance change layer, and an upper electrode layer are laminated in this order. It is described that the side walls of these layers constitute one surface.

  The technique of Patent Document 1 aims to simplify the manufacturing process of a conventional nonvolatile memory by integrating a wiring and a lower electrode. That is, the technique of this document uses this wiring as a lower electrode of a nonvolatile memory by forming a resistance change layer on the surface of the wiring layer. It is described that such a resistance change layer is formed by oxidizing the surface of the wiring layer.

  Further, in Patent Document 2, since the transition metal oxide film (resistance change layer) can be thinned at the side wall portion of the groove by a method described later, variations in characteristics of the conventional nonvolatile memory can be suppressed. It is described. Here, the resistance change layer is thinned by the following steps. That is, first, a trench is formed in the interlayer insulating film. Next, a barrier metal film, a lower electrode, a resistance change layer, and an upper electrode are formed on the wiring and in the trench. At this time, the lower electrode and the upper electrode are formed by sputtering from the oblique upper side with respect to the upper surface of the substrate, thereby forming a film while forming a shadow portion that is not formed in the groove.

JP 2009-117668 A JP 2009-295842 A

W. W. Zhuang et al. , Novell Colossal Magnetosensitive Thin Film Nonvolatile Resilience Random Access Memory (RRAM), IEDM, Paper No. 7.5, pp. 193-196, 2002. G. -S. Park et. al. , Observation of electric-field induced Ni filament channels in polycrystalline NiOx film, APL, Vol. 91, pp. 222103, 2007 C. Yoshida et. al. , High speed reactive switching in Pt / TiO2 / TiN film for non-volatile memory application, APL, Vol. 91, pp. 223510, 2007 J. et al. F. Gibbons et. al. , Switching properties of thin NiO Films, Solid State Electronics, vol. 7, pp. 785-797, 1964 K. Kinoshita et. al. , Bias polarity dependent data retention of resistive random access memory coordinating of binary transition metal oxide, APL, vol. 89, pp. 103509, 2006

However, in the technique of Patent Document 1, the side wall end portion of the resistance change layer is an effective region. There is a concern that the characteristics of the memory element may vary due to the end portion of the side wall.
In the technique of Patent Document 2, the resistance change layer and the barrier metal film underlying the lower electrode are in contact with each other. For this reason, there is a possibility that unintended deterioration of switching characteristics may occur at the interface between the resistance change layer and the barrier metal film.

According to the present invention,
A substrate,
A metal layer provided on the substrate;
A lower electrode provided on the metal layer;
A resistance change layer provided on the lower electrode, a part of which is opposed to the metal layer;
A spacer portion located at a portion where the metal layer and the resistance change layer face each other;
An upper electrode provided on the variable resistance layer;
A semiconductor device is provided.

  In the present invention, the variable resistance layer is provided on the lower electrode, and a part of the variable resistance layer faces the metal film, so that the lower electrode and the upper electrode are positioned outside the effective region facing each other. . For this reason, it is possible to suppress the deterioration of the memory element characteristics due to the damage of the end portion of the resistance change layer. In addition, the spacer portion is disposed at a portion where the metal layer and the resistance change layer face each other. For this reason, it can suppress that degradation of the unintended switching characteristic generate | occur | produces when a resistance change layer and metal layers other than a lower electrode contact. Therefore, according to the present invention, it is possible to achieve both suppression of deterioration of memory element characteristics and suppression of unintended switching characteristics.

Moreover, according to the present invention,
A substrate,
An underlayer provided on the substrate;
A metal layer provided on the underlayer;
A lower electrode provided on the metal layer;
Provided on the lower electrode, a part of which faces the metal layer, is located on and around the lower electrode, and a portion located on the circumference is in contact with the base layer A resistance change layer;
A spacer portion, which is located in a portion where the metal layer and the resistance change layer face each other, and is formed on a peripheral portion of the metal layer;
An upper electrode provided on the variable resistance layer;
Comprising
A semiconductor device is provided.

Moreover, according to the present invention,
A substrate,
An interlayer insulating layer provided on the substrate;
A metal layer located on the bottom of the recess formed in the interlayer insulating layer and on a part of the side wall;
A spacer portion located on the upper end surface of the metal layer;
A lower electrode located on the metal layer and on the inner wall and on the inner wall of the spacer portion;
A resistance change layer located on the lower electrode and the spacer portion;
An upper electrode located on the variable resistance layer;
Comprising
A semiconductor device is provided.

Moreover, according to the present invention,
A substrate,
A first interlayer insulating layer and a second interlayer insulating layer stacked on the substrate;
A metal layer located on the bottom of the first recess formed on the first interlayer insulating layer and on a part of the side wall;
A spacer portion located on the upper end surface of the metal layer;
A lower electrode embedded inside the metal layer;
A resistance change layer located along a part of the bottom and side wall of the second recess formed in the second interlayer insulating layer, and located on the spacer part and the lower electrode;
An upper electrode located on the inner wall of the variable resistance layer;
Comprising
A semiconductor device is provided.

Moreover, according to the present invention,
A method of manufacturing a semiconductor device comprising a lower electrode, a resistance change layer, and an upper electrode,
Forming a metal layer on the substrate;
Forming the lower electrode on a portion of the metal layer;
Forming a spacer portion on the exposed portion of the metal layer;
Forming the variable resistance layer in contact with the lower electrode and the spacer portion;
Forming the upper electrode on the variable resistance layer;
A method for manufacturing a semiconductor device is provided.

  In the present invention, since the variable resistance layer is in contact with the lower electrode and the spacer portion, the variable resistance layer is positioned outside the effective region where the lower electrode and the upper electrode face each other. For this reason, it is possible to suppress the deterioration of the memory element characteristics due to the damage of the end portion of the resistance change layer. In addition, a spacer portion is disposed between the resistance change layer and the metal layer. For this reason, it can suppress that degradation of the unintended switching characteristic generate | occur | produces when a resistance change layer and metal layers other than a lower electrode contact. Therefore, according to the present invention, it is possible to achieve both suppression of deterioration of memory element characteristics and suppression of unintended switching characteristics.

  According to the present invention, a semiconductor device having excellent reliability is provided.

It is sectional drawing of the resistance change type non-volatile memory device (1T1R cell) for demonstrating a subject. It is a figure for demonstrating the switching principle of a resistance variable nonvolatile memory element. It is sectional drawing of the resistance change type non-volatile memory device for demonstrating a subject. It is sectional drawing of the resistance change type non-volatile memory device for demonstrating a subject. It is sectional drawing of the resistance change type non-volatile memory device for demonstrating a subject. FIG. 6A is a plan view of the variable resistance nonvolatile memory device according to the first embodiment, and FIG. 6B is a cross-sectional view taken along the line aa ′ in FIG. FIG. 7 is a part of a cross-sectional view taken along the line bb ′ of FIG. It is process sectional drawing which shows the procedure of the manufacturing process of the resistance variable nonvolatile memory device of 1st Embodiment. FIG. 9A is a plan view of the variable resistance nonvolatile memory device according to the second embodiment, and FIG. 9B is a cross-sectional view taken along the line aa ′ in FIG. 9A. It is a part of aa 'sectional view of Drawing 9 (a). It is process sectional drawing which shows the procedure of the manufacturing process of the variable resistance nonvolatile memory device of 2nd Embodiment. 12A is a plan view of the variable resistance nonvolatile memory device according to the third embodiment, and FIG. 12B is a cross-sectional view taken along the line aa ′ in FIG. It is a part of aa 'sectional view of Drawing 12 (a). It is process sectional drawing which shows the procedure of the manufacturing process of the variable resistance nonvolatile memory device of 3rd Embodiment.

  First, in describing this embodiment, the above-described problem will be described in detail with reference to FIGS. 1 to 5 are diagrams created by the inventors themselves to explain the problem.

  FIG. 1 is a cross-sectional view of a general 1T1R variable resistance nonvolatile memory device 10. The variable resistance nonvolatile memory element is generally used in the configuration of one control transistor and one resistance change element per memory cell. In the 1T1R variable resistance nonvolatile memory device 10, a gate insulating film 24, a gate electrode 26, a source / drain diffusion layer (a source diffusion layer 18, a drain diffusion) are formed in an element region partitioned by the element isolation layer 14 from the semiconductor substrate 12. A control transistor consisting of layer 16) is formed. A contact 22 is formed so as to be connected to the source diffusion layer 18 or the drain diffusion layer 16. The contact 22 is formed on the first interlayer insulating layer 20. A first wiring 34 made of barrier metal (barrier metal film 36) and Cu is formed so as to be connected to the contact 22. The first wiring 34 is formed in the second interlayer insulating layer 32. An MIM (Metal / Insulator / Metal) structure comprising a metal adhesion layer 52, a lower electrode 54, a resistance change layer 56, and an upper electrode 58 so as to be connected to the first wiring 34 through the opening of the second cap insulating layer 40. The variable resistance nonvolatile memory element 50 having the above is formed. A barrier metal (barrier metal film 48), a via 46 made of Cu, and a second wiring 60 are formed so as to be connected to the upper electrode 58. The via 46 is formed through the third interlayer insulating layer 42 and the third cap insulating layer 44. As shown in FIG. 1, a general variable resistance nonvolatile memory element 50 is formed between wiring layers (that is, the first wiring 34 and the second wiring 60). The variable resistance nonvolatile memory element 50 has an MIM capacitor structure isolated between adjacent cells.

Next, an operation method of a general variable resistance nonvolatile memory element 50 will be described.
First, a positive voltage is applied to the upper electrode 58 via the second wiring 60 to lower the resistance change layer 56 (Forming). At this time, the voltage applied to the gate electrode 26 is adjusted so that the current is limited by the saturation current value of the control transistor, so that the resistance change layer 56 has a desired resistance value. In forming, a positive voltage may be applied to the lower electrode 54 instead of the upper electrode 58. When switching from the low resistance state to the high resistance state, a positive voltage is applied to the drain diffusion layer 16 and the gate electrode 26. For switching from the high resistance state to the low resistance state, a positive voltage is applied to the upper electrode 58 and the gate electrode 26. At this time, a voltage higher than that at the time of switching to the high resistance state is applied to the first wiring 34. Further, the voltage applied to the gate electrode 26 is adjusted so that the current is limited by the saturation current value of the control transistor, so that the resistance change layer 56 has a desired resistance value. It should be noted that the switching operation can be performed even when a positive voltage is applied to the upper electrode 58 instead of the drain diffusion layer 16 in switching from the high resistance state to the low resistance state and from the low resistance state to the high resistance state. it can.

However, as a result of investigations by the inventors, such a variable resistance nonvolatile memory element 50 has the following problems due to etching damage applied to the side wall portion during MIM processing and accumulation of etching residues. There was found.
Hereinafter, this point will be described in detail.

  FIG. 2 illustrates the switching principle of the general variable resistance nonvolatile memory element 50 described above (Non-patent Documents 4 and 5). As shown in FIG. 2, in the variable resistance nonvolatile memory element 50, a voltage is applied to the upper electrode 58 to reduce the resistance (Forming), and then a current path (current path 70) due to oxygen vacancies in the variable resistance layer 56. Is formed. When a voltage is applied between the upper and lower electrodes in a state where this current path is formed, an oxidation-reduction reaction occurs in the current path, and the resistance value changes. It is considered that the resistance change of the current path is caused by oxidation-reduction near the interface between the upper and lower electrodes of this current path.

  However, as shown in FIG. 3, not only one current path is actually formed by applying a voltage to the upper electrode 58 but also one incomplete current path (incomplete current path 72). Thus, it is formed at various locations in the resistance change layer 56. In particular, the incomplete current path 72 is likely to be formed by the side wall portion 74 deteriorated due to etching damage or residue accumulation. In the switching operation after forming, when these incomplete current paths are conducted, the resistance value is abruptly lowered, causing a malfunction. In other words, the incomplete current path 72 causes a malfunction. In addition, the switching characteristics of the current path in the resistance change layer near the sidewall 74 that has undergone process damage differ from the current path in the resistance change layer near the electrode center that is not damaged, resulting in increased variations in memory element performance. There is a risk that the reliability is greatly deteriorated. FIG. 3 corresponds to a dashed box shown in FIG.

  Therefore, the inventors have further studied and the problem caused by the side wall damage of the resistance change layer as described above by forming the side wall portion of the resistance change layer outside the effective region functioning as a nonvolatile memory element. I thought it was possible to avoid. As this type of structure, for example, the structures shown in FIGS. 4 and 5 are conceivable. In the variable resistance nonvolatile memory element shown in FIG. 4A, the variable resistance layer 56 and the upper electrode 58 are deposited so as to cover the laminated structure of the metal adhesion layer 52 and the lower electrode 54. The upper electrode 58 and the resistance change layer 56 are etched outside the lower electrode 54.

  In the structure shown in FIG. 4A, the effective region 80 sandwiched between the upper electrode and the lower electrode is separated from the side wall portion 82 that has been subjected to etching damage. For this reason, it is possible to improve variation and characteristic deterioration due to side etching damage. However, as shown in FIG. 4B, the metal adhesion layer 52 and the resistance change layer 56 are in contact with each other at the outer peripheral portion of the lower electrode 54. As a result, switching characteristics deteriorate at the interface 84 between the metal adhesion layer 52 and the resistance change layer 54.

  In the variable resistance nonvolatile memory element shown in FIG. 5A, the metal adhesion layer 52 and the lower part are formed in the recess formed in the interlayer insulating film (for example, the third interlayer insulating layer 42 in FIG. 1). A laminate of the electrodes 54 is formed. A resistance change layer 56 and an upper electrode 58 are deposited so as to cover the stacked body in the recess. In the peripheral region above the opening of the recess, the upper electrode 58 and the resistance change layer 56 are etched. Therefore, in the structure shown in FIG. 5A, the effective region 80 sandwiched between the upper electrode 58 and the lower electrode 52 is separated from the side wall portion 82 of the resistance change layer 56 that has been damaged by etching. For this reason, it is possible to improve variation and characteristic deterioration due to side etching damage. However, as shown in FIG. 5B, the metal adhesion layer 52 and the resistance change layer 56 are in contact with each other at the outer peripheral portion of the lower electrode 54. For this reason, as in FIG. 4B, the switching characteristics deteriorate at the interface 84 between the metal adhesion layer 52 and the resistance change layer 54.

  As described above, even if the resistance change layer 56 is extended outside the effective region sandwiched between the upper electrode 58 and the lower electrode 54, the extended portion is a metal layer other than the lower electrode 54 (for example, the first layer There is a possibility that the first metal 34 and the lower electrode 54 are in contact with the metal adhesion layer 52). When the resistance change layer 56 is in contact with a metal layer other than the lower electrode 54, there is a possibility that unintended deterioration of switching characteristics or the like occurs.

As a result of examination in view of the above problems, the present inventors have found that the following configuration is suitable.
That is, the semiconductor device (resistance change type nonvolatile memory device 100) of the present embodiment includes a substrate, a metal layer, a lower electrode, a resistance change layer, an upper electrode, and a spacer portion. The metal layer (metal adhesion layer 142) is provided on the semiconductor substrate 102. The lower electrode 144 is provided on the metal adhesion layer 142 and is connected to the metal adhesion layer 142. The upper electrode 148 is provided on the lower electrode 144 at a position facing the lower electrode 144. The resistance change layer 146 is provided between the lower electrode 144 and the upper electrode 148 and extends outward from a region where the lower electrode 144 and the upper electrode 148 overlap. The spacer portion 150 is provided between a portion of the resistance change layer 146 that extends outward and the metal adhesion layer 142.
Specifically, the configuration is as follows. The metal adhesion layer 142 is located on the semiconductor substrate 102. The lower electrode 144 is located on the metal adhesion layer 142. The resistance change layer 146 is located on the lower electrode 144, and a part thereof faces the metal adhesion layer 142. The spacer portion 150 is located at a portion where the metal adhesion layer 142 and the resistance change layer 146 face each other. The upper electrode 148 is located on the resistance change layer 146.

  In the present embodiment, the end portion of the resistance change layer 146 is located outside the effective region where the lower electrode 144 and the upper electrode 148 overlap. For this reason, it is possible to suppress the deterioration of the memory element characteristics due to the damage of the end portion of the resistance change layer 146. In addition, a spacer portion 150 is disposed between the resistance change layer 146 and the metal adhesion layer 142 extending outward from the effective region. For this reason, it can suppress that the deterioration of the unintended switching characteristic generate | occur | produces when the resistance change layer 146 and metal adhesion layers 142 other than the lower electrode 144 contact. Therefore, according to the present embodiment, it is possible to achieve both suppression of deterioration in memory element characteristics and suppression of unintended switching characteristics.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 6A is a plan view of the variable resistance nonvolatile memory device according to the first embodiment. The variable resistance nonvolatile memory device 100 shown in FIG. 6A is applied with a variable resistance nonvolatile memory array of 1T1R type. FIG. 6B is a cross-sectional view along the line aa ′ in FIG. FIG. 7 is a part of the bb ′ cross-sectional view of FIG.

  As shown in FIG. 6A, the variable resistance nonvolatile memory device 100 includes a gate electrode 116 (word line), a first wiring 124a, a first wiring 124b, a second wiring 138, and a variable resistance nonvolatile memory element 140. Is provided. The gate electrode 116 is formed on the semiconductor substrate 102. A plurality of second wirings 138 are formed to be orthogonal to the gate electrode 116. The variable resistance nonvolatile memory element 140 includes a region where the first wiring 124 a and the second wiring 138 overlap, and is electrically connected to the first wiring 124 a and the second wiring 138. The first wiring 124 a is connected to the source diffusion layer 108 formed in the semiconductor substrate 102. In the present embodiment, the first wiring 124b (common line) is formed in parallel to the gate electrode 116 (word line), but may be formed to be orthogonal to the gate (word line). In plan view, for example, the first wirings 124a are preferably separated from each other between adjacent elements and have a rectangular shape, and the first wirings 124b and the second wirings 138 preferably extend in the in-plane direction. FIG. 6A shows a 1T1R type configuration, but this embodiment is not limited to this mode.

  As illustrated in FIG. 6B, the element isolation layer 104 is formed on the semiconductor substrate 102. The element isolation layer 104 forms an element region in the semiconductor substrate 102 and separates the element region from other regions. A transistor is formed on the semiconductor substrate 102 in the element region. The transistor includes a gate insulating film 114, a gate electrode 116, and a diffusion layer including a source diffusion layer 108 and a drain diffusion layer 106. Side wall portions 118 are formed on both side walls of the gate electrode 116. Note that the source diffusion layer 108 and the drain diffusion layer 106 may be either an N-type impurity diffusion layer or a P-type impurity diffusion layer.

  On the surface of the diffusion layer, an alloy of metal such as cobalt, nickel, platinum, etc., generally called silicide, and silicon is formed. As the gate electrode of the transistor, a commonly used polysilicon electrode, a polysilicon electrode partially metal-silicided, or a metal gate electrode may be used. Furthermore, as a method for forming a metal gate electrode, a gate first method, a gate last method, and the like are known, but either can be applied.

  A first interlayer insulating layer 110 is formed on the semiconductor substrate 102. A contact 112 is formed on the first interlayer insulating layer 110. The contact 112 is embedded in the first interlayer insulating layer 110 and is connected to the source diffusion layer 108 or the drain diffusion layer 106. As the contact 112, various metals such as W and Al are used.

  A first cap insulating layer 120 is formed on the first interlayer insulating layer 110. A second interlayer insulating layer 122 is formed on the first cap insulating layer 120. A first wiring 124 including a first wiring 124 a and a first wiring 124 b is formed in the second interlayer insulating layer 122. The first wiring 124 is connected to the contact 112. The first wiring 124 includes a barrier metal film 126 and a metal layer embedded in the wiring trench. Examples of the metal layer include an alloy containing an additive such as W or Al in addition to Cu, an alloy containing 90% by mass or more of Cu, and a metal composed of Cu alone. In the present embodiment, the first wiring 124 and the contact 112 are formed of separate members, but may have a single damascene structure or a dual damascene structure.

  A second cap insulating layer 128 and a third interlayer insulating layer 130 are formed on the second interlayer insulating layer 122. The variable resistance nonvolatile memory element 140 is formed in the third interlayer insulating layer 130, and a part thereof is disposed in the opening of the second cap insulating layer 128. The variable resistance nonvolatile memory element 140 is connected to the lower first wiring 124 a in the opening of the second cap insulating layer 128. On the other hand, the variable resistance nonvolatile memory element 140 is connected to the upper via 134. The via 134 electrically connects the upper electrode 148 of the variable resistance nonvolatile memory element 140 and the second wiring 138. The second wiring 138 is formed on the third cap insulating layer 132 formed on the first cap insulating layer 120. In addition, a barrier metal film 136 is continuously formed on at least the lower surface of the second wiring 138 and around the via 134. Further, in the present embodiment, the second wiring 138 and the via 134 may be integrally configured as in the present embodiment (in other words, may be formed in the same process), but are separate members. It may be constituted by. The via 134 is covered with the upper electrode 148 at the bottom and part of the side wall.

Here, the variable resistance nonvolatile memory element 140 according to the first embodiment will be described in detail.
The variable resistance nonvolatile memory element 140 has a stacked structure in which a metal adhesion layer 142, a lower electrode 144, a variable resistance layer 146, and an upper electrode 148 are stacked in this order. The resistance change layer 146 extends outward from a region (effective region 160) where the lower electrode 144 and the upper electrode 148 overlap in plan view. In the present embodiment, the resistance change layer 146 covers the upper surface and side surfaces of the stacked body of the metal adhesion layer 142 and the lower electrode 144. Furthermore, the resistance change layer 146 has a side wall portion located outside the effective region 160 having a portion where the lower electrode 144 and the upper electrode 148 face each other in plan view. In the present embodiment, the effective region 160 is a region in which the lower electrode 144 and the upper electrode 148 face each other in both the film thickness direction and / or the in-plane direction (in other words, the horizontal direction and the vertical direction). However, it may be a region where both electrodes face each other only in the film thickness direction as in a second embodiment described later. In the present embodiment, since the variable resistance nonvolatile memory element 140 has a stack structure, the film thickness direction can be compared with a case where the variable resistance nonvolatile memory element 140 is embedded in a recess formed in the third interlayer insulating layer 130. Is reduced in thickness.

  The metal adhesion layer 142 and the lower electrode 144 are positioned on the base layer (for example, the first wiring 124a and / or the second cap insulating layer 128) in this order. That is, the metal adhesion layer 142 is located on the base layer. The lower electrode 144 is located on the metal adhesion layer 142. Further, the resistance change layer 146 is located on and around the lower electrode 144, and the portion located around the lower electrode 144 is in contact with the base layer. That is, the resistance change layer 146 is in contact with the lower electrode 144 and is located on the upper surface and the side wall of the lower electrode 144. The resistance change layer 146 faces the side wall of the metal adhesion layer 142 and is in contact with the spacer portion 150. A portion of the resistance change layer 146 that faces the metal adhesion layer 142 is in contact with the base layer. The upper electrode 148 is located on the resistance change layer 146.

  The spacer portion 150 prevents the resistance change layer 146 extending from the effective region 160 from contacting the lower electrode 144. In the present embodiment, the spacer portion 150 is preferably formed in the same layer as the metal adhesion layer 142, and is preferably formed, for example, on the entire peripheral portion of the metal adhesion layer 142 in a plan view.

  Further, each layer constituting the variable resistance nonvolatile memory element 140 has, for example, a rectangular shape in plan view. In the present embodiment, the metal adhesion layer 142 having the spacer portion 150 around the entire periphery and the lower electrode 144 may have the same area. Further, the resistance change layer 146 has a larger area than the lower electrode 144 and may have the same area as the upper electrode 148. In other words, the position of the side wall part of the spacer part 150 and the side wall part of the lower electrode 144 may coincide with each other in a sectional view. Further, the side wall portion of the resistance change layer 146 and the position of the side wall portion of the upper electrode 148 may coincide with each other in a sectional view (in the present embodiment, the term “coincidence” means variation according to the manufacturing process). Means that). The resistance change layer 146 is not limited to such an aspect of the present embodiment as long as the resistance change layer 146 extends outside the region (effective region 160) where the lower electrode 144 and the upper electrode 148 overlap in plan view.

As shown in FIGS. 6B and 7, the metal adhesion layer 142 may be provided over the upper surface of the first wiring 124a and the upper surface of the second cap insulating layer 128, but the first wiring 124a. It may be provided only on the upper surface.
Further, in the cross-sectional view, the variable resistance nonvolatile memory elements 140 are separated from each other, and a groove other than a wiring groove (for example, a dummy groove in which a side wall portion of a variable resistance film shown in Patent Document 2 is located) therebetween. Is preferably not formed. As a result, the semiconductor device can be miniaturized in the in-plane direction.

  The spacer 150 is preferably an insulating layer, and more preferably an oxide of the metal adhesion layer 142. For example, the metal adhesion layer 142 is preferably made of a material larger than the oxide generation energy of the lower electrode 144. In addition, as described above, the spacer portion 150 may be formed of a separate member having an insulating property, but the lower electrode 144 extends to a region where the metal adhesion layer 142 and the resistance change layer 146 face each other. It may be composed of parts. Thereby, it is possible to prevent an unintended switching phenomenon from occurring at the interface between the resistance change layer 146 and the metal adhesion layer 142 due to the resistance change layer 146 being in direct contact with the metal adhesion layer 142.

  The metal adhesion layer 142 (metal layer) can improve the adhesion between the second cap insulating layer 128 and / or the first wiring 124 a and the lower electrode 144. The metal adhesion layer 142 preferably has a function of preventing diffusion of the metal constituting the first wiring 124a. By forming the metal adhesion layer 142 from the first wiring 124a to the second cap insulating layer 128, it is possible to reliably prevent the metal constituting the first wiring 124a from diffusing into the resistance change element. . As a constituent material of the metal adhesion layer, for example, it is desirable to use Ta, TaN, Ti, TiN and their laminated structure. In this embodiment, as the metal adhesion layer 142, for example, a laminated film of TiN and Ti is used.

  As the lower electrode 144, it is desirable to use a material having an oxide film generation energy lower than that of the metal adhesion layer 142. For example, W, Ru, Pt, or the like is desirable. In the present embodiment, for example, W is used as the lower electrode 144.

  As the upper electrode 148, for example, Ti, TiN, Al, Ni, Cu, CuAl, Ta, TaN, Zr, Hf, Mo, Ru, Pt, or the like is preferably used. Moreover, the laminated body of these materials may be sufficient. In the present embodiment, for example, Ru is used as the upper electrode 148.

As the resistance change layer 146, it is desirable to use a single layer film or a multilayer film including at least TiO ₂ , FeO, NiO, ZrO ₂ , CuO, HfO ₂ , Ta ₂ O ₅ , WO, and nitrides and silicates thereof. . In the present embodiment, for example, Ta ₂ O ₅ is used as the resistance change layer 146.

  Next, a manufacturing process of the semiconductor device (resistance variable nonvolatile memory device 100) according to the first embodiment will be described. FIG. 8 is a process cross-sectional view illustrating the procedure of the manufacturing process of the variable resistance nonvolatile memory device according to the first embodiment. FIG. 8 is a process sectional view in a part of the bb ′ sectional view of FIG.

A method of manufacturing the resistance change type nonvolatile memory device 100 according to the present embodiment (hereinafter also referred to as this process) is a method of manufacturing a semiconductor device including a lower electrode 144, a resistance change layer 146, and an upper electrode 148. And having the following steps. That is, first, a metal layer (metal adhesion layer 142) is formed on a substrate (semiconductor substrate 102). Next, on part of the metal adhesion layer 142 (in this embodiment, “on part of the metal adhesion layer 142” includes part of the upper surface and / or part of the side surface of the metal adhesion layer 142). The lower electrode 144 is formed. Next, the spacer portion 150 is formed on the exposed portion of the metal adhesion layer 142. Next, a resistance change layer 146 in contact with the lower electrode 144 and the spacer portion 150 is formed. Next, the upper electrode 148 is formed on the resistance change layer 146.
Details will be described below.

  First, a transistor is formed over the semiconductor substrate 102 over an element region separated from other regions by the element isolation layer 104 and the element isolation layer 104 by a commonly used method. A contact 112 connected to the first interlayer insulating layer 110 and the diffusion layer of the transistor is formed thereon. In the present embodiment, the steps up to the formation of the contact 112 may be performed by a commonly used method for manufacturing a semiconductor device. For example, although not shown, after the first interlayer insulating layer 110 is deposited after the formation of the transistor, an opening serving as a cell contact is opened by a photolithography method, and then a contact material is embedded by a CVD (Chemical Vapor Deposition) method. The contact 112 is formed by removing the surplus contact material by a (chemical mechanical polishing) method. Thereafter, a first cap insulating layer 120 and a second interlayer insulating layer 122 are deposited and planarized by CMP.

  Next, a wiring groove (a recess corresponding to each of the first wiring 124a and the first wiring 124b) is formed in the first cap insulating layer 120 and the second interlayer insulating layer 122, and the barrier metal film 126 and the wiring material are formed in the wiring groove. Buried. Next, the first wiring 124 (the first wiring 124a and the first wiring 124b) is formed by removing excess metal by CMP. Next, a second cap insulating layer 128 is formed on the first wiring 124 and the second interlayer insulating layer 122. Then, using an photolithography method and an etching method, an opening is formed on the upper surface of the first wiring 124a, and the upper surface of the first wiring 124a is exposed.

  Next, as shown in FIG. 8A, a metal adhesion layer 142 and a lower electrode 144 are deposited on the lower wiring layer (first wiring 124 a) and the second cap insulating layer 128. For example, the metal adhesion layer 142 is formed by a DC sputtering method using TiN and Ti as a target of Ti, and a sputtering gas is switched from Ar to nitrogen to continuously form a laminated film of TiN and Ti. Thereafter, W (lower electrode 144) is formed using a CVD (Chemical Vapor Deposition) method. Next, a lower electrode pattern is formed by using a photolithography process and a dry etching process. In the present embodiment, for example, a silicon nitride film is used as the second cap insulating layer 128, a laminated film of TiN and Ti is used as the metal adhesion layer material, and W is used as the lower electrode material. In this step, the metal adhesion layer 142 and the lower electrode 144 may be formed and then patterned simultaneously. However, after the metal adhesion layer 142 is formed and patterned, the lower electrode 144 is formed thereon and patterned. By doing so, you may pattern individually.

Next, as shown in FIG. 8B, after the lower electrode 144 is laminated on the metal adhesion layer 142, the exposed portion of the metal adhesion layer 142 is selectively oxidized. Thereby, the spacer part 150 can be formed. For example, by heating the structure shown in FIG. 8A in an oxygen atmosphere, the side wall end portion where the metal adhesion layer 142 is exposed can be oxidized. In this step, the metal adhesion layer 142 is made of a material having oxide generation energy larger than that of the lower electrode 144. For this reason, the metal adhesion layer 142 is easily oxidized at a lower temperature than the lower electrode 144. By using a temperature at which the metal adhesion layer 142 is selectively oxidized, the spacer portion 150 can be formed only at the end of the metal adhesion layer 142. That is, the spacer portion 150 is composed of an oxide of the metal adhesion layer 142. In this step, for example, by using an oxidation temperature of 300 ° C., a spacer portion made of TiO ₂ can be formed at the end of the spacer portion 150.

Next, as illustrated in FIG. 8C, the resistance change layer 146 and the upper electrode 148 are deposited so as to cover the metal adhesion layer 142 in which the spacer portion 150 is formed and the lower electrode 144. In this step, for example, Ta ₂ O ₅ is used as the resistance change layer, and Ru is used as the upper electrode metal. Ta ₂ O ₅ is deposited by RF sputtering using a Ta ₂ O ₅ target. On the other hand, Ru is deposited by a DC sputtering method using a Ru target.

  Next, as shown in FIG. 8D, the upper electrode and the resistance change layer are processed using a photolithography process and a dry etching process. For example, the upper electrode and the resistance change layer between adjacent non-volatile memory element formation regions can be removed. Thereby, the variable resistance nonvolatile memory element 140 of the present embodiment can be formed. In this step, the variable resistance layer 146 and the upper electrode 148 may be formed and then patterned simultaneously. However, after the variable resistance layer 146 is formed and patterned, the upper electrode 148 is formed thereon and patterned. By doing so, you may pattern individually.

Thereafter, a third interlayer insulating layer 130 is formed on the variable resistance nonvolatile memory element 140. A third cap insulating layer 132 and a fourth interlayer insulating layer (not shown) are formed on the third interlayer insulating layer 130. Next, a via hole penetrating through the fourth interlayer insulating layer and the third interlayer insulating layer 130 and reaching the upper surface of the upper electrode 148 is formed. Then, a wiring groove continuing to the via hole is formed in the fourth interlayer insulating layer. Next, the third cap insulating layer 132 and a metal film are embedded in the via hole and the wiring groove. By removing the excess metal film by CMP, the via 134 and the second wiring 138 are formed. Thereafter, a normal semiconductor device manufacturing process may be performed.
As described above, the variable resistance nonvolatile memory device 100 according to the first embodiment can be formed.

Next, the effect of this Embodiment is demonstrated.
In the first variable resistance nonvolatile memory element, since the spacer portion is formed between the metal adhesion layer and the resistance change layer, an unintended switching phenomenon at the interface between the metal adhesion layer and the resistance change layer, or the metal adhesion layer Therefore, it is possible to avoid the deterioration of the switching characteristics due to the reaction between the resistance change layer and the resistance change layer, and to realize a variable resistance nonvolatile memory element having high reliability. In particular, when the spacer portion is made of an insulating film material, the effect is ensured.

Moreover, since the oxide formation energy of the metal adhesion layer material is larger than the oxide formation energy of the lower electrode material, it is possible to selectively oxidize only the edge of the metal adhesion layer, as shown in the manufacturing method. The spacer portion made of the oxide of the metal adhesion layer can be formed by self-alignment advantageous for miniaturization. For this reason, cost reduction can be realized. As an example, when Ti or TiN / Ti laminated structure is used for the metal adhesion layer and W or Ru is used for the lower electrode, the above effect can be obtained because the oxide formation energy of the metal adhesion layer is low. Further, for example, W, Ru, and Pt are suitable as the lower electrode material of the variable resistance nonvolatile memory element, and therefore excellent nonvolatile memory characteristics can be obtained.
As described above, a highly reliable variable resistance nonvolatile memory element can be realized at low cost.

(Second Embodiment)
Next, the variable resistance nonvolatile memory device 100 according to the second embodiment will be described.
In the variable resistance nonvolatile memory device 100 according to the second embodiment, a variable resistance nonvolatile memory element 140 is disposed in a recess 152 formed in an interlayer insulating layer (third interlayer insulating layer 130). Except for this, it is the same as in the first embodiment.
Hereinafter, differences from the first embodiment will be described in detail.

  FIG. 9A is a plan view of the variable resistance nonvolatile memory device according to the second embodiment. A variable resistance nonvolatile memory array of 1T1R type is applied to the variable resistance nonvolatile memory device 100 shown in FIG. FIG. 9B is a cross-sectional view taken along the line aa ′ in FIG. FIG. 10 is a part of an aa ′ cross-sectional view of FIG.

  As shown in FIG. 9B, the second cap insulating layer 128 and the third interlayer insulating layer 130 are stacked on the second interlayer insulating layer 122 on the semiconductor substrate 102. A first wiring 124 a is formed in the second interlayer insulating layer 122. On the other hand, in the second cap insulating layer 128 and the third interlayer insulating layer 130, a recess 152 connected to the first wiring 124a is formed. In plan view, the recess 152 is preferably formed inside a region partitioned by the outer edge of the first wiring 124a. In addition, for example, the recess 152 may have various shapes such as a rectangular shape, a circular shape, and an elliptical shape in a plan view, but has a circular shape in the present embodiment.

  A part or all of the variable resistance nonvolatile memory element 140 is formed in the recess 152. As an example, as shown in FIG. 9B, the entire metal adhesion layer 142, the spacer portion 150, and the lower electrode 144 are embedded in the recess 152. On the other hand, a part of the resistance change layer 146 and the upper electrode 148 is embedded in the recess 152 and the rest is formed outside the opening of the recess 152. As described above, the variable resistance nonvolatile memory element 140 is formed along the recess 152.

  As shown in FIG. 9A, the variable resistance nonvolatile memory element 140 is preferably formed inside the formation region of the first wiring 124a in plan view. Further, as shown in FIG. 9B, the variable resistance nonvolatile memory element 140 is compared with the width of the first wiring 124a in the direction orthogonal to the extending direction of the lower layer wiring (first wiring 124a). It is preferable that the width is equal or less. Thereby, it becomes possible to achieve miniaturization in the in-plane direction.

  Specifically, the metal adhesion layer 142 is formed on the upper surface of the first wiring 124 a and a part of the side wall of the recess 152. The cross-sectional shape of the metal adhesion layer 142 may be a U shape or may be a plate shape. The lower electrode 144 is laminated on the upper surface or the upper surface of the metal adhesion layer 142 embedded in the recess 152 and along the inner wall. The spacer portion 150 is formed on the outer edge portion of the metal adhesion layer 142. As shown in FIG. 10, the end portion of the spacer portion 150 may form the same surface as the lower electrode 144 (in this embodiment, the same surface can allow variations in the manufacturing process).

  Further, the resistance change layer 146 is formed on the upper surfaces of the lower electrode 144 and the spacer portion 150 embedded in the recess 152, on the inner wall of the recess 152, and around the opening of the recess 152. In other words, the lower electrode 144 and the spacer portion 150 are disposed between the resistance change layer 146 and the metal adhesion layer 142. The upper electrode 148 is formed along the upper surface of the resistance change layer 146. Further, as shown in FIG. 9A, the upper electrode 148 may be separated without being continuous between the adjacent recesses 152.

  In the present embodiment, as shown in FIG. 10, the effective region 160 where the upper electrode 148 and the lower electrode 144 face each other is formed in the recess 152. The side wall portion of the resistance change layer 146 is formed outside the opening of the recess 152 and is formed away from the effective region 160. In addition, in the recess 152, the lower electrode 144 and the spacer portion 150 are disposed between the resistance change layer 146 and the metal adhesion layer 142.

Further, as shown in FIG. 10, the metal adhesion layer 142 is located along the bottom of the recess 152 and a part of the side wall formed in the third interlayer insulating layer 130. For example, the metal adhesion layer 142 has a U-shape when viewed in cross section. The spacer portion 150 is located on the upper end surface of the metal adhesion layer 142. That is, the spacer portion 150 is formed along the periphery of the inner wall of the recess 152. For example, the spacer portion 150 has a ring shape in a plan view. The lower electrode 144 is located on the metal adhesion layer 142, on the inner wall, and on the inner wall of the spacer unit 150. The lower electrode 144 may have a U-shape as illustrated, but may be embedded in an inner hole formed by the metal adhesion layer 142 and the spacer portion 150. The resistance change layer 146 is located on the lower electrode 144 and the spacer portion 150. The resistance change layer 146 is located on the remaining portion of the side wall of the recess 152. Further, the upper electrode 148 is located on the resistance change layer 146, specifically, located on the resistance change layer 146 and on the inner wall. In the present embodiment, the via 134 only needs to be positioned on the upper electrode 148, and may be embedded in an inner hole formed by the upper electrode 148, for example.
As described above, the second embodiment can obtain the same effects as those of the first embodiment.

  Next, a manufacturing process of the semiconductor device (resistance variable nonvolatile memory device 100) according to the second embodiment will be described. FIG. 11 is a process cross-sectional view illustrating the procedure of the manufacturing process of the variable resistance nonvolatile memory device according to the second embodiment. FIG. 11 is a process cross-sectional view in a part of the cross-sectional view along the line aa ′ in FIG.

The method for manufacturing variable resistance nonvolatile memory device 100 according to the present embodiment (hereinafter sometimes referred to as “this step”) includes the following steps. First, an interlayer insulating layer (third interlayer insulating layer 130a) is formed over a substrate (semiconductor substrate 102). Next, a recess (recess 152) is formed in the third interlayer insulating layer 130a. Next, the metal adhesion layer 142 and the lower electrode 144 are formed inside the recess 152. Next, the spacer portion 150 is formed on the exposed portion of the metal adhesion layer 142 inside the recess 152. Next, a resistance change layer 146 is formed on the lower electrode 144 and the spacer portion 150 and outside the opening of the recess 152. Thereafter, the upper electrode 148 is formed on the resistance change layer 146.
Hereinafter, differences from the first embodiment will be described in detail.

  First, as in the first embodiment, a second interlayer insulating layer 122 (lower wiring layer) having a first wiring 124 is formed on the semiconductor substrate 102. Next, a second cap insulating layer 128 and a third interlayer insulating layer 130 a are deposited on the second interlayer insulating layer 122.

  Next, as illustrated in FIG. 11A, a recess 152 is formed in the third interlayer insulating layer 130 a and the second cap insulating layer 128. For example, the recess 152 can be formed using a photolithography process and a dry etching process. At least a part of the upper surface of the first wiring 124 a is exposed on the bottom surface of the recess 152.

  Next, as shown in FIG. 11B, a metal adhesion layer 142 and a lower electrode 144 are deposited inside the recess 152 and outside the opening. The deposition method can be the same as in the first embodiment. The metal adhesion layer 142 and the lower electrode 144 are formed along the shape of the recess 152. Next, as illustrated in FIG. 11C, the metal adhesion layer 142 and the lower electrode 144 formed at least outside the opening of the recess 152 are selectively formed in a state where a resist (not illustrated) is embedded in the recess 152. Remove. In the present embodiment, part of the metal adhesion layer 142 and the lower electrode 144 formed on the inner wall of the recess 152 may also be removed. In other words, the metal adhesion layer 142 and the lower electrode 144 can be selectively left at least at the bottom of the recess 152. For example, a dry etching process can be used for this process. Thereafter, the resist (not shown) is removed.

  Next, as illustrated in FIG. 11D, the spacer portion 150 is formed in the exposed portion of the metal adhesion layer 142, in other words, the portion not covered with the lower electrode 144. In this step, as in the first embodiment, the exposed end of the metal adhesion layer can be oxidized by heating in an oxygen atmosphere.

  Next, as illustrated in FIG. 11E, the resistance change layer 146 and the upper electrode 148 are provided inside the recess 152 and outside the opening so as to cover the lower electrode 144 and the spacer portion 150 embedded in the bottom of the recess 152. accumulate. At this time, the resistance change layer 146 is not in contact with the metal adhesion layer 142 but is in contact with the upper surface of the lower electrode 144 and the upper surface of the spacer portion 150. Further, the deposition method can be the same as in the first embodiment. As a result, the resistance change layer 146 and the upper electrode 148 can be uniformly deposited inside the recess 152.

  Next, as shown in FIG. 11F, the resistance change layer 146 and the upper electrode 148 can be patterned by selectively removing the resistance change layer 146 and the upper electrode 148. Thereby, at least the sidewall portion of the resistance change layer 146 can be left outside the opening of the recess 152. In this step, for example, a photolithography step and a dry etching step can be used in the same manner as in the first embodiment.

  Next, an interlayer insulating layer (not shown) is deposited on the upper electrode 148 and the third interlayer insulating layer 130a. Thereby, the third interlayer insulating layer 130 is formed. Thereafter, the variable resistance nonvolatile memory device 100 of the second embodiment can be obtained in the same manner as in the first embodiment.

(Third embodiment)
Next, a variable resistance nonvolatile memory device 100 according to a third embodiment will be described.
In the variable resistance nonvolatile memory device 100 according to the third embodiment, the metal adhesion layer 142, the lower electrode 144, and the spacer portion 150 are embedded in the first recess (recess 154) formed in the first interlayer insulating layer 110. The second embodiment is the same as the first embodiment except that the resistance change layer 146 and the upper electrode 148 in the second recess (recess 156) formed in the second interlayer insulating layer 122 are embedded. . The variable resistance nonvolatile memory element 140 according to the third embodiment is configured such that each configuration is formed in two or more recesses including a first recess and a second recess formed continuously. This is different from the second embodiment in which each component is formed in one recess.
Hereinafter, differences from the first embodiment will be described in detail.

  FIG. 12A is a plan view of the variable resistance nonvolatile memory device according to the third embodiment. A variable resistance nonvolatile memory array of 1T1R type is applied to the variable resistance nonvolatile memory device 100 shown in FIG. FIG. 12B is a cross-sectional view taken along the line aa ′ in FIG. FIG. 13 is a part of the cross-sectional view taken along the line aa ′ in FIG.

  As shown in FIG. 12B, the variable resistance nonvolatile memory element 140 according to the present embodiment can form a contact 162 and a first via 164. The contact 162 is connected to the source diffusion layer 108 of the transistor. The contact 162 electrically connects the first via 164 and the source diffusion layer 108. On the other hand, a contact 112 is formed in the same layer as the contact 162. The contact 112 includes a buried metal layer 112a and a barrier metal film 112b. This contact 112 is connected to the drain diffusion layer 106. The contact 112 electrically connects the first wiring 124 b and the drain diffusion layer 106. The contacts 162 and 112 are buried in the first interlayer insulating layer 110 formed on the transistor.

  The first via 164 electrically connects the contact 162 and the second via 166. The first via 164 is formed in the same layer as the first wiring 124b. In other words, the first via 164 and the first wiring 124 b are embedded in the second interlayer insulating layer 122 formed on the first interlayer insulating layer 110.

  The second via 166 is composed of a buried metal layer 166a and a barrier metal film 166b. The second via 166 electrically connects the first via 164 and the second wiring 138. Note that the second via 166 may be formed of the same member as the second wiring 138, as in the first embodiment.

Next, the variable resistance nonvolatile memory element 140 will be described in detail.
The contact 162 includes a metal adhesion layer 142, a lower electrode 144, and a spacer part 150. The metal adhesion layer 142 is formed on the bottom surface and the inner wall of the recess 154 and covers the lower surface and the side wall surface of the lower electrode 144. The lower electrode 144 is formed at the center inside the recess 154. The spacer 150 is formed on the inner wall of the recess 154 and is formed at the end of the lower electrode 144. The spacer 150 is formed at the end of the first via 164 together with the lower electrode 144 and is formed so as to cover the periphery of the lower electrode 144.

  The first via 164 only needs to be composed of at least the resistance change layer 146 and the upper electrode 148, and may further include a buried metal portion 158 as shown in FIG. The upper electrode 148 is formed on the bottom and inner wall of the recess 156, and is in contact with the lower electrode 144 and the spacer portion 150 which are lower layers. The upper electrode 148 is formed on the inner side of the resistance change layer 146. The upper electrode 148 may be formed along the resistance change layer 146 and may have a cross-sectional shape similar to that of the resistance change layer 146. The embedded metal portion 158 embeds the remainder of the recess 156 where the variable resistance layer 146 and the upper electrode 148 are formed.

  As shown in FIG. 13, the resistance change layer 146 extends outside the effective region 160 where the upper electrode 148 embedded in the recess 156 and the lower electrode 144 embedded in the recess 154 face each other. The resistance change layer 146 extending outward from the effective region 160 is in contact with the spacer portion 150. In the present embodiment, the width of the upper electrode 148 and the width of the lower electrode 144 can be the same in a cross-sectional view (the same means that variations in the manufacturing process are allowed).

  Further, as shown in FIG. 12A, the variable resistance nonvolatile memory element 140 may have a circular shape, an elliptical shape, or a rectangular shape in plan view. Further, the contact 162 and the first via 164 may have the same hole diameter. Further, the variable resistance nonvolatile memory element 140 may have the same hole diameter as the second via 166 or the contact 112. In plan view, the contact 162 and the first via 164 can have the same or smaller hole diameter compared to the wiring width of the first wiring 124b.

  Further, as shown in FIG. 13, the metal adhesion layer 142 is located on the bottom of the recess 154 formed in the first interlayer insulating layer 110 and on a part of the side wall. For example, the metal adhesion layer 142 has a U-shape when viewed in cross section. The spacer portion 150 is located on the upper end surface of the metal adhesion layer 142. That is, the spacer portion 150 is formed along the periphery of the inner wall of the recess 154. For example, the spacer portion 150 has a ring shape in a plan view. The lower electrode 144 is located on the metal adhesion layer 142, on the inner wall, and on the inner wall of the spacer unit 150. The lower electrode 144 is embedded in an inner hole composed of the metal adhesion layer 142 and the spacer portion 150 as shown in the figure. In addition, the resistance change layer 146 is positioned along the bottom of the recess 156 formed in the second interlayer insulating layer 122 and along a part of the side wall. For example, the resistance change layer 146 has a U shape in a cross-sectional view. The resistance change layer 146 is located on the lower electrode 144 and the spacer portion 150. Further, the upper electrode 148 is located on the resistance change layer 146, specifically, located on the resistance change layer 146 and on the inner wall. In the present embodiment, the embedded metal portion 158 may be positioned on the upper electrode 148, and may be embedded in an inner hole formed by the upper electrode 148, for example.

  In the third embodiment, since the variable resistance nonvolatile memory element 140 is embedded in the contacts and vias, the in-plane direction is compared with the first and second embodiments. Further miniaturization can be realized. In addition, the third embodiment can obtain the same effect as the first embodiment.

  Next, a manufacturing process of the semiconductor device (resistance variable nonvolatile memory device 100) of the third embodiment will be described. FIG. 14 is a process cross-sectional view illustrating the procedure of the manufacturing process of the variable resistance nonvolatile memory device according to the second embodiment. FIG. 14 is a process cross-sectional view in a part of the cross-sectional view along the line aa ′ in FIG.

The method for manufacturing variable resistance nonvolatile memory device 100 according to the present embodiment (hereinafter sometimes referred to as “this step”) includes the following steps. First, the first interlayer insulating layer 110 is formed on the semiconductor substrate 102. Next, a first recess (recess 154) is formed in the first interlayer insulating layer 110. Next, the metal adhesion layer 142 and the lower electrode 144 are embedded in the recess 154. Next, the spacer portion 150 is formed on the exposed portion of the metal adhesion layer 142. Next, a second interlayer insulating layer 122 is formed on the first interlayer insulating layer 110. A second recess (recess 156) is formed in the second interlayer insulating layer 122. Thereafter, the resistance change layer 146 and the upper electrode 148 are embedded in the recess 156.
Hereinafter, differences from the first and second embodiments will be described in detail.

First, in the same manner as in the first embodiment, a transistor is formed in an element region on the semiconductor substrate 102, and a first interlayer insulating layer 110 is formed thereon.
As shown in FIG. 14A, a recess (contact hole) reaching the diffusion layer of the semiconductor substrate 102 is formed in the first interlayer insulating layer 110 by using a photolithography method and a dry etching method. In one contact hole, a barrier metal film 112b and a buried metal layer 112a are formed.
As shown in FIG. 14B, a metal adhesion layer 142 and a lower electrode 144 are embedded in the other contact hole (recess 154). For example, the metal adhesion layer 142 and the lower electrode 144 are deposited inside the recess 154 and outside the opening, and the excess portion is ground using CMP. The same deposition method as that in the first embodiment can be used.

  Next, as shown in FIG. 14C, the exposed metal adhesion layer 142 is oxidized in the opening of the recess 154. Thereby, the spacer part 150 can be formed in the exposed part of the metal adhesion layer 142.

  The first wiring 124b can be formed by forming a metal layer on the first interlayer insulating layer 110 and patterning the metal layer. Note that the first wiring 124b may be formed by a damascene method. In this case, the first wiring 124b may be formed before or after the first via 164.

  Next, as shown in FIG. 14D, a second interlayer insulating layer 122 is formed on the first interlayer insulating layer 110 so as to cover the first wiring 124b. A recess 156 is formed in the second interlayer insulating layer 122. For example, a photolithography method and a dry etching method can be used.

Thereafter, as shown in FIG. 14E, the resistance change layer 146 and the upper electrode 148 are deposited in the recess 156. The deposition method can be the same as in the first embodiment.
Then, as shown in FIG. 14F, the resistance change layer 146 and the upper electrode 148 formed outside the opening are selectively removed in a state where a resist mask (not shown) is buried in the center of the recess 156. . For example, a dry etching method can be used. Thereafter, the resist mask (not shown) is removed. Thereby, the resistance change layer 146 and the upper electrode 148 can be selectively formed on the bottom and the inner wall of the recess 156. However, the present invention is not limited to this aspect, and the entire inside of the recess 156 is formed in the resistance change layer 146 and the upper electrode 148. It may be buried with.

  Next, the remaining space of the recess 156 is embedded with the embedded metal portion 158. For example, it is possible to form a predetermined metal layer on the upper electrode 148 inside the recess 156 and form the buried metal portion 158 by CMP on the surplus portion of this metal layer. The embedded metal portion 158 is not particularly limited, and for example, various metals or alloys used for vias and wiring such as Cu, Al, and W can be used.

Next, a third interlayer insulating layer 130 is formed on the variable resistance nonvolatile memory element 140 and the second interlayer insulating layer 122. A via hole is formed in the third interlayer insulating layer 130, and a barrier metal film 166b and an embedded metal layer 166a are embedded in the via hole. Thereafter, a third cap insulating layer 132 and a fourth interlayer insulating layer (not shown) are formed on the third interlayer insulating layer 130. Next, an opening that penetrates the fourth interlayer insulating layer and the third cap insulating layer 132 and reaches the upper surface of the second via 166 is formed. Then, a wiring groove continuing to the opening is formed in the fourth interlayer insulating layer. Next, a barrier metal film 136 and a metal film are embedded in the opening and the wiring groove. The second wiring 138 is formed by removing the excess metal film by CMP. Thereafter, a normal semiconductor device manufacturing process may be performed.
As described above, the variable resistance nonvolatile memory device 100 according to the third embodiment can be formed.

  Needless to say, the above-described embodiments can be combined within a range in which the contents do not conflict with each other. In the above-described embodiment, the structure of each part has been specifically described. However, the structure and the like can be variously changed within a range that satisfies the present invention.

10 resistance variable nonvolatile memory device 12 semiconductor substrate 14 element isolation layer 16 drain diffusion layer 18 source diffusion layer 20 first interlayer insulating layer 22 contact 24 gate insulating film 26 gate electrode 28 sidewall 30 first cap insulating layer 32 second interlayer Insulating layer 34 First wiring 36 Barrier metal film 40 Second cap insulating layer 42 Third interlayer insulating layer 44 Third cap insulating layer 46 Via 48 Barrier metal film 50 Variable resistance nonvolatile memory element 52 Metal adhesion layer 54 Lower electrode 56 Resistance change layer 58 Upper electrode 60 Second wiring 70 Current path 72 Incomplete current path 74 Side wall 76 Incomplete current path 80 Effective area 82 Side wall 84 Interface 100 Resistance change nonvolatile memory device 102 Semiconductor substrate 104 Element isolation layer 106 Drain diffusion layer 108 Source diffusion layer 110 First interlayer insulating layer 112 Tact 112a Buried metal layer 112b Barrier metal film 114 Gate insulating film 116 Gate electrode 118 Side wall 120 First cap insulating layer 122 Second interlayer insulating layers 124, 124a, 124b First wiring 126 Barrier metal film 128 Second cap insulating layer 130 , 130a Third interlayer insulating layer 132 Third cap insulating layer 134 Via 136 Barrier metal film 138 Second wiring 140 Variable resistance nonvolatile memory element 142 Metal adhesion layer 144 Lower electrode 146 Resistance change layer 148 Upper electrode 150 Spacer portion 152 Recess 154 Recess 156 Recess 158 Embedded metal portion 160 Effective region 162 Contact 164 First via 166 Second via 166a Embedded metal layer 166b Barrier metal film

Claims (16)

A substrate,
A metal layer provided on the substrate;
A lower electrode provided on the metal layer;
A resistance change layer provided on the lower electrode, a part of which is opposed to the metal layer;
A spacer portion located at a portion where the metal layer and the resistance change layer face each other;
An upper electrode provided on the variable resistance layer;
A semiconductor device comprising: The semiconductor device according to claim 1,
The semiconductor device, wherein the spacer portion is an insulating layer. The semiconductor device according to claim 1 or 2,
The said spacer part is a semiconductor device comprised with the oxide of the said metal layer. The semiconductor device according to any one of claims 1 to 3,
The semiconductor device, wherein the metal layer is made of a material having a larger oxide film generation energy than the lower electrode. The semiconductor device according to any one of claims 1 to 4,
The semiconductor device, wherein the metal layer includes at least one selected from the group consisting of Ta, TaN, Ti, and TiN. The semiconductor device according to any one of claims 1 to 5,
The lower electrode includes a semiconductor device including at least one selected from the group consisting of W, Ru, and Pt. A substrate,
An underlayer provided on the substrate;
A metal layer provided on the underlayer;
A lower electrode provided on the metal layer;
Provided on the lower electrode, a part of which faces the metal layer, is located on and around the lower electrode, and a portion located on the circumference is in contact with the base layer A resistance change layer;
A spacer portion, which is located in a portion where the metal layer and the resistance change layer face each other, and is formed on a peripheral portion of the metal layer;
An upper electrode provided on the variable resistance layer;
Comprising
Semiconductor device. A substrate,
An interlayer insulating layer provided on the substrate;
A metal layer located on the bottom of the recess formed in the interlayer insulating layer and on a part of the side wall;
A spacer portion located on the upper end surface of the metal layer;
A lower electrode located on the metal layer and on the inner wall and on the inner wall of the spacer portion;
A resistance change layer located on the lower electrode and the spacer portion;
An upper electrode located on the variable resistance layer;
Comprising
Semiconductor device. A substrate,
A first interlayer insulating layer and a second interlayer insulating layer stacked on the substrate;
A metal layer located on the bottom of the first recess formed on the first interlayer insulating layer and on a part of the side wall;
A spacer portion located on the upper end surface of the metal layer;
A lower electrode embedded inside the metal layer;
A resistance change layer located along a part of the bottom and side wall of the second recess formed in the second interlayer insulating layer, and located on the spacer part and the lower electrode;
An upper electrode located on the inner wall of the variable resistance layer;
Comprising
Semiconductor device. A method of manufacturing a semiconductor device comprising a lower electrode, a resistance change layer, and an upper electrode,
Forming a metal layer on the substrate;
Forming the lower electrode on a portion of the metal layer;
Forming a spacer portion on the exposed portion of the metal layer;
Forming the variable resistance layer in contact with the lower electrode and the spacer portion;
Forming the upper electrode on the variable resistance layer;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 10,
Forming an interlayer insulating layer on the substrate;
Forming a recess in the interlayer insulating layer,
The step of forming the metal layer includes the step of forming the metal layer in the recess,
The step of forming the variable resistance layer includes a step of forming the variable resistance layer on the lower electrode, on the spacer portion, and outside the opening of the concave portion.
A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 10,
Forming a first interlayer insulating layer on the substrate;
Forming a first recess in the first interlayer insulating layer;
Forming a second interlayer insulating layer on the first interlayer insulating layer;
Forming a second recess in the second interlayer insulating layer,
The step of forming the metal layer and the step of forming the lower electrode include a step of burying the metal layer and the lower electrode in the first recess,
The step of forming the variable resistance layer and the step of forming the upper electrode include a step of burying the variable resistance layer and the upper electrode in the second recess.
A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to any one of claims 10 to 12,
The method of manufacturing a semiconductor device, wherein the step of forming the spacer portion includes a step of selectively oxidizing an exposed portion of the metal layer. In the manufacturing method of the semiconductor device according to any one of claims 10 to 13,
The method for manufacturing a semiconductor device, wherein the metal layer is made of a material having an oxide film generation energy larger than that of the lower electrode. In the manufacturing method of the semiconductor device according to any one of claims 10 to 14,
The method for manufacturing a semiconductor device, wherein the metal layer includes at least one selected from the group consisting of Ta, TaN, Ti, and TiN. In the manufacturing method of the semiconductor device according to any one of claims 10 to 15,
The method for manufacturing a semiconductor device, wherein the lower electrode includes at least one selected from the group consisting of W, Ru, and Pt.

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