JP2012064631A - Method of manufacturing capacitor, and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a capacitor which can form a capacitive insulating film having a high-temperature phase crystal structure on an electrode directly.SOLUTION: A method of manufacturing a capacitor Cap includes: a step of forming a first electrode 3; a step of forming a metal oxide made of an amorphous phase on the first electrode 3 at a first temperature lower than a film formation temperature of a low-temperature phase crystal structure, the metal oxide being capable of forming the amorphous phase, the low-temperature phase crystal structure, and a high-temperature phase crystal structure in an ascending order of the film formation temperature; a step of depositing the high-temperature phase crystal structure on the metal oxide to obtain a capacitive insulating film 4 by rising the temperature from the first temperature to a second temperature equal to a film formation temperature of the high-temperature phase crystal structure at a temperature rising speed of 10°C/second or more and annealing the metal oxide at the second temperature; and a step of forming a second electrode 5 on the capacitive insulating film 4.

Description

  The present invention relates to a capacitor manufacturing method and a semiconductor device manufacturing method.

In recent years, with the high integration of semiconductor devices such as DRAMs, it has been important to increase the capacitance of capacitors constituting the DRAMs. Further, as a capacitor having a large capacitance, an element having an MIM (Metal-Insulator-Metal) structure in which a dielectric film is sandwiched between two electrodes made of a metal thin film is employed.
Besides the MIM structure of the capacitor, there are a method of three-dimensionalizing the lower electrode, a method of increasing the surface area by increasing the aspect ratio of the lower electrode, and a method of reducing the thickness of the dielectric film. It is adopted as a method for increasing the electric capacity. However, in order to stably secure a high capacitance in a small space, the above method is not sufficient. Therefore, in recent years, a method of using a crystalline dielectric film having a high dielectric constant has been adopted as a capacitor insulating film of a capacitor.

  Further, since the capacitor is required to have a high aspect ratio and a large surface area, a method for forming a dielectric film on an electrode having a high aspect ratio with good coverage is required. As described above, an ALD (Atomic Layer Deposition) method is generally used as a method for forming a dielectric film on a fine electrode.

  In the ALD method, a volatile metal precursor is ideally adsorbed one by one at the monoatomic level and then reacted with an oxygen precursor to form a predetermined dielectric oxide film by appropriately selecting the deposition temperature. It is a method to do. The precursor is supplied into the reaction chamber at a high concentration to be saturated and adsorbed on the reaction surface. Excess precursor that did not contribute to the adsorption is purged from the reaction chamber before sending the oxygen precursor. At this time, reaction by-products are also purged. The same supply and purging are performed for the oxygen precursor. A thin film can be formed with good controllability by sequentially repeating the adsorption and purging of the metal precursor and the oxidation and purging with the oxygen precursor.

As a material for the dielectric film, TiO ₂ (titanium oxide) is generally used. As the crystal structure of TiO ₂ , two types of anatase structure and rutile structure are well known. The crystal structure of TiO ₂ depends on the temperature setting during film formation.
For example, the anatase structure is a crystal structure that is easily formed at a low temperature (a so-called low-temperature phase crystal structure). More specifically, it is known that an anatase structure is formed when a film of TiO ₂ is formed under a low temperature (330 to 465 ° C.) condition.
Further, TiO ₂ having an anatase structure has a low relative dielectric constant of about 40-50, and thus is not desirable as a dielectric film constituting a capacitor.

On the other hand, TiO _{2 having} a rutile structure is usually a crystal structure formed at a high temperature (a so-called high-temperature phase crystal structure) and has a high relative dielectric constant of about 70-100. For this reason, the dielectric film constituting the capacitor of the DRAM is preferably made of TiO _{2 having} a rutile structure.
The rutile structure is a crystal structure that is easily formed at a high temperature (a so-called high-temperature phase crystal structure). Specifically, when a film is formed at a high temperature (660 ° C. or higher), only the rutile structure is obtained. In addition, when the film is formed under a medium temperature (550 ° C.) condition, TiO ₂ is in a mixed state of an anatase structure and a rutile structure.
In addition, once anatase structure crystals are deposited at the time of TiO ₂ film formation, the anatase structure crystals can be converted to a rutile structure even if annealing is performed under conditions higher than those at the time of film formation. Is considered difficult (Non-Patent Document 1).

In addition, as a method of forming a dielectric film made of rutile TiO ₂ , for example, after irradiating ions on the surface of an anatase TiO ₂ film, annealing is performed under a temperature condition of 500 ° C. to 700 ° C. Known (Patent Document 1). In addition, a method is known in which a metal oxide having a rutile structure is formed under a temperature condition of 500 ° C. by a laser vapor deposition method, and then heat treatment is performed under a temperature condition of 750 ° C. to 950 ° C. (Patent Document 2). Further, as a method for forming the TiO ₂ of the rutile structure in low temperature conditions, after forming the TiO ₂ film at a temperature of 400 ° C. or less on the pretreatment layer of the rutile structure, 500 ° C. or less temperature condition A method of performing a heat treatment under is known (Patent Document 3).
As mentioned in Patent Documents 1, 2 and 3, by performing the post-annealing after the film formation or TiO ₂ film formation of the TiO ₂ film under high temperature conditions, the TiO ₂ film is rutile structure crystallizes It becomes. Further, when the TiO ₂ film formation, impurities contained in the TiO ₂ film (C, H, N, etc.) is removed by heat.

JP 2000-254519 A JP 2003-63892 A JP 2007-110111 A

IBM Journal of Research and Development, volume 43, number3, MAY1999, pp383-392

  However, if a capacitive insulating film is formed on an electrode under temperature conditions for forming a metal oxide having a high-temperature phase crystal structure such as a rutile structure, for example, an electrode or an already formed element (such as a transistor) Heat burden increases. For this reason, damage due to a heat burden occurs, and problems such as a decrease in manufacturing yield and deterioration of electrical characteristics are likely to occur. For this reason, it is said that it is difficult to form a capacitive insulating film made of a metal oxide having a high-temperature crystal structure on an electrode provided in a semiconductor device. Therefore, there is a demand for a method of forming a capacitive insulating film made of a metal oxide having a crystal structure in a high temperature phase on an electrode under conditions as low as possible.

  In order to solve the above problems, the present invention employs the following configuration. That is, the method for manufacturing a capacitor according to the present invention is a method for manufacturing a capacitor using a film made of a metal oxide having a crystal structure of a low-temperature phase stable at a low temperature and a crystal structure of a high-temperature phase stable at a high temperature as a capacitor insulating film. A step of forming a first electrode, and forming an amorphous film of the metal oxide on the first electrode at a temperature lower by 100 ° C. or more than a temperature at which the crystal structure of the low-temperature phase is obtained. And the step of forming and maintaining the temperature at which the crystal structure of the high-temperature phase is obtained after increasing the temperature at a temperature rising rate of 10 ° C./second or more to a temperature at which the crystal structure of the high-temperature phase is obtained. The method includes: annealing the crystalline film to form a crystal film of the metal oxide; and forming a second electrode on the crystal film.

  According to the method for manufacturing a capacitor of the present invention, the metal oxide amorphous film is formed on the first electrode at a temperature lower by 100 ° C. or more than the temperature at which the crystal structure of the low-temperature phase of the metal oxide film is obtained. After that, the temperature is rapidly increased to a temperature at which a high-temperature crystal structure of the metal oxide is obtained at a rate of temperature increase of 10 ° C./second or more, thereby preventing precipitation of the crystal structure of the low-temperature phase during the temperature-raising process. be able to. In addition, by annealing the amorphous film while maintaining the temperature at which the high-temperature phase crystal structure is obtained after raising the temperature of the metal oxide, the high-temperature phase crystal structure can be obtained without precipitating the low-temperature phase crystal structure. It can be deposited. This eliminates the need for high-temperature annealing for changing the crystal structure of the low-temperature phase to the crystal structure of the high-temperature phase. Therefore, a capacitive insulating film made of a metal oxide having a crystal structure in a high temperature phase can be formed on the electrode without applying a heat burden. In addition, since a thermal burden on the semiconductor device including the electrode is reduced, a capacitor can be formed while suppressing a decrease in manufacturing yield and electrical characteristics. As described above, a highly integrated and low power consumption semiconductor device can be realized.

FIG. 1 is a longitudinal sectional view schematically showing a method for manufacturing a capacitor in the first embodiment. FIG. 2 is a longitudinal sectional view schematically showing the method for manufacturing the capacitor in the first embodiment. FIG. 3 is a flowchart showing a part of the process of the capacitor manufacturing method according to the first embodiment. FIG. 4 is a longitudinal sectional view schematically showing the method for manufacturing the capacitor in the first embodiment. FIG. 5 is a plan view showing an example of some elements such as a wiring structure of a memory cell including the capacitor formed according to the first embodiment. FIG. 6 is a cross-sectional view showing a cross-sectional structure of the semiconductor device corresponding to the A-A ′ line of FIG. 5. FIG. 7 is a longitudinal sectional view schematically showing a method for manufacturing a semiconductor device, and is a sectional view showing a part of FIG. FIG. 8 is a diagram showing a step subsequent to FIG. 7, and is a cross-sectional view showing a part of FIG. FIG. 9 is a view showing a step subsequent to FIG. 8, and is a cross-sectional view showing a part of FIG.

  Hereinafter, an example of a method for manufacturing a capacitor according to the first embodiment of the present invention will be described. Note that the drawings referred to in the following description may show the features that are enlarged for convenience in order to make the features easier to understand, and the dimensional ratios of the respective components are not always the same as the actual ones. Absent. In addition, the raw materials, dimensions, and the like exemplified in the following description are merely examples, and the present invention is not limited to these, and can be appropriately modified and implemented without changing the gist thereof.

  The method for manufacturing the capacitor Cap of the present embodiment includes a step of forming the first electrode 3, a step of forming the capacitive insulating film 4 on the first electrode 3, and the second electrode 5 on the capacitive insulating film 4. The process is generally composed of: Details of each step will be described below.

First, as shown in FIG. 1, an interlayer insulating film 2 made of silicon oxide (SiO ₂ ) or the like is formed on a semiconductor substrate 1.

Next, the first electrode 3 is formed.
First, a metal film made of a laminated film of, for example, a titanium film and a titanium nitride film is deposited on the interlayer insulating film 2 by, for example, a CVD (chemical vapor deposition) method or an ALD (atomic layer deposition) method. At this time, the structure of the metal film may be either a single metal film or a laminated film in which a plurality of metal films are deposited. Further, the material of the metal film is not limited to the titanium film and the titanium nitride film, and other metals may be used. Other examples of the material of the first electrode 3 include platinum (Pt), ruthenium (Ru), iridium (Ir), and tungsten (W).
Next, dry etching is performed using the photoresist film as a mask to pattern the metal film into a predetermined shape. By this patterning, a first electrode 3 made of a metal film having a predetermined shape is formed on the interlayer insulating film 2.

Next, as shown in FIG. 2, a capacitive insulating film 4 made of a metal oxide is formed on the first electrode 3. As the metal oxide for the capacitive insulating film 4 in the present embodiment, an oxide capable of forming an amorphous phase, a low-temperature phase crystal structure, and a high-temperature phase crystal structure in descending order of film formation temperature is used. As such a material, any one of titanium oxide, niobium oxide (Nb ₂ O ₅ ), and zirconium oxide (ZrO ₂ ) can be selected and used. Alternatively, a laminated film in which at least two kinds of titanium oxide, niobium oxide, or zirconium oxide are selected and laminated may be formed.
Hereinafter, an example in which titanium oxide (TiO ₂ ) is used as the metal oxide for the capacitive insulating film 4 will be described.

  First, a film forming apparatus (not shown) is prepared. This film forming apparatus includes a reaction chamber in which a metal oxide can be deposited by an ALD method, and a gas supply system capable of introducing an oxidizing agent and a source gas. Next, a substrate formed up to the first electrode 3 for the capacitor Cap is prepared and placed in the reaction chamber of the film forming apparatus. At this time, the temperature in the reaction chamber of the film forming apparatus is set in advance to the first temperature before the substrate is installed.

The first temperature is set to be 100 ° C. or more lower than the temperature at which the crystal structure (anatase structure) of the low-temperature phase of the metal oxide (titanium oxide) for the capacitive insulating film 4 is obtained. Specifically, the temperature is set to 230 ° C. or lower.
Also, when niobium oxide is used as the metal oxide material, the temperature is 100 ° C. or more lower than the temperature at which a low-temperature phase crystal structure (hexagonal crystal structure) is obtained. Also when zirconium oxide is used, the temperature is set to be 100 ° C. or more lower than the temperature at which a low-temperature phase crystal structure (tetragonal structure) is obtained.

  Note that the crystal structure of the low temperature phase described here is a temperature range (for example, a range of temperatures Tn-1 to Tn) in a relationship of Tn> Tn-1> .. T2> T1 (n is an integer of 2 or more). ), A high-dielectric material (metal oxide for the capacitive insulating film 4) having n kinds of crystal structures Sn (n is an integer of 2 or more) each stably present can be stably obtained at the lowest temperature. The crystal structure of S1 is shown. In the case of titanium oxide, n = 2.

  Next, an amorphous film (capacitive insulating film 4) made of a metal oxide having an amorphous crystal structure is formed on the first electrode 3. Note that in this specification, a film made of a metal oxide having an amorphous crystal structure is referred to as an amorphous film 4.

FIG. 3 shows a flowchart of a process for forming the amorphous film 4 of titanium oxide. In forming the amorphous film 4, an ALD method using a Ti raw material (Ti precursor) as a raw material gas can be used. Examples of the Ti precursor include organometallic complexes such as TDMAT (tetrakisdimethylaminotitanium: Ti [N (CH ₃ ) ₂ ] ₄ ), but the Ti precursor is not limited to TDMAT. A thing may be used.

First, Ti source gas (Ti precursor) is supplied into the reaction chamber, and a titanium film is deposited on the surface of the first electrode 3. At this time, at least one element from the group of Y (yttrium), Zr (zirconium), La (lanthanum), Al (aluminum) or Sr (strontium) may be added together with the source gas. When adding such another element, a cycle for supplying a gas containing the additive element is provided separately from the cycle for supplying the Ti raw material gas in the ALD method, and the number of each cycle is set independently. By doing so, it is possible to deposit a titanium film containing an additive element at a predetermined concentration. By adding these additive elements, an effect of controlling the band gap of the finally formed titanium oxide film can be obtained, and a dielectric film having an optimum leakage withstand voltage can be formed.
In addition, when forming niobium oxide or zirconium oxide, it is possible to add these additional elements (excluding zirconium as an additional element in the case of zirconium oxide).

Next, N ₂ gas for purge is supplied into the reaction chamber, and excess Ti source gas is discharged. Next, by supplying an oxidizing agent into the reaction chamber, the titanium film is oxidized to form a titanium oxide film. At this time, as the oxidizing agent, oxygen (O ₂ ), ozone (O ₃ ), water vapor (H ₂ O), a mixed gas of these gases, or a mixed gas of these gases and nitrogen gas, etc. Can be used.
Thereafter, N ₂ gas is supplied into the reaction chamber and the oxidant is discharged.

  Thus, an atomic layer of titanium oxide is formed so as to cover the surface of the first electrode 3. Thereafter, a series of steps from the introduction of the source gas to the discharge of the oxidizing agent is repeated an arbitrary number of times, thereby forming a thin film of the amorphous film 4 composed of a laminated film of titanium oxide atomic layers.

In the formation of the amorphous film 4, at least two kinds of titanium oxide, niobium oxide or zirconium oxide are selected without stacking the same atomic layer of the same metal, and a stacked film (amorphous film 4) may be laminated.
At this time, depending on the temperature setting conditions of the film forming apparatus, a part may have a low-temperature phase crystal structure, but the amorphous film 4 preferably does not contain a low-temperature phase crystal structure.

  Next, from the first temperature to the temperature (second temperature) at which a high-temperature stable crystal structure such as a rutile structure in titanium oxide is obtained (second temperature), the reaction chamber is heated at a rate of 10 ° C./second or more. Increase temperature. In the case of titanium oxide, the second temperature is 600 ° C.

  The second temperature when niobium oxide is used as the metal oxide (amorphous film 4) is 700 ° C. Further, by annealing the amorphous film 4 made of niobium oxide, the orthorhombic crystal structure is precipitated as a high-temperature phase crystal structure. Similarly, the second temperature when zirconium oxide is used as the amorphous film 4 is 450 ° C., and the amorphous film 4 is annealed to precipitate a hexagonal crystal structure as a high-temperature phase crystal structure. .

  Further, in the case of using a laminated film (amorphous film 4) in which at least two kinds of titanium oxide, niobium oxide, or zirconium oxide are selected and laminated as the metal oxide, each metal used in the laminated film is used. The temperature is raised to the highest temperature among the second temperatures.

The crystal structure of the high-temperature phase described here is a temperature range (for example, a range of temperatures Tn-1 to Tn) having a relationship of Tn>Tn-1> .. T2> T1 (n is an integer of 2 or more). ) In a high-dielectric material (metal oxide for the capacitive insulating film 4) having n kinds of crystal structures Sn (n is an integer of 2 or more) that exist stably, at a k-th temperature from the lowest. The crystal structure Sk (k is an integer of 2 or more and n or less) is obtained. In the case of the high-temperature phase of titanium oxide, k = 2.
That is, in the present invention, the temperature in the reaction chamber is set to a second temperature (Tk at which the k-th crystal structure Sk is formed from a first temperature that is 100 ° C. lower than the temperature T1 at which the first crystal structure S1 is formed. The temperature is increased at a temperature increase rate of 10 ° C./second or more until the temperature is less than Tk + 1. The present invention can also be applied to a high dielectric material having three or more types of crystal structures depending on the temperature.

  Next, the amorphous film 4 is annealed (post-annealing) in a nitrogen atmosphere while the temperature in the reaction chamber is maintained at the second temperature. By this annealing, a high-temperature phase crystal structure is deposited, and a capacitive insulating film 4 made of a metal oxide (titanium oxide) having a high-temperature phase crystal structure is formed.

Next, a second electrode 5 is formed as shown in FIG. First, a metal oxide made of, for example, a laminated film of a titanium film and a titanium nitride film is deposited so as to cover the capacitor insulating film 4. Next, the metal oxide is patterned into a predetermined shape. By this patterning, the second electrode 5 having a predetermined shape is formed on the capacitive insulating film 4.
Thus, the MIM structure Cap is formed.

According to the manufacturing method of the capacitor Cap of the present embodiment, the amorphous metal oxide is formed on the first electrode 3 at a temperature lower by 100 ° C. or more than the temperature at which the crystal structure of the low-temperature phase of the metal oxide film is obtained. By forming the film, the amorphous film 4 can be formed without precipitating the crystal structure of the low temperature phase. In addition, after the amorphous film 4 is formed, the temperature is rapidly increased at a temperature increase rate of 10 ° C./second or more to a temperature at which a high-temperature crystal structure of the metal oxide is obtained. Precipitation of the crystal structure of the low temperature phase can be prevented.
Also, by annealing the amorphous film while maintaining the temperature at which the high-temperature phase crystal structure is obtained after rapidly raising the temperature of the metal oxide, the high-temperature phase crystal can be obtained without precipitating the low-temperature phase crystal structure. The structure can be deposited.

  Further, since precipitation of the crystal structure of the low-temperature phase in the amorphous film 4 is prevented, high-temperature annealing for changing the crystal structure of the low-temperature phase to the crystal structure of the high-temperature phase becomes unnecessary, and the first The thermal burden on the electrode 3 can be reduced. For this reason, the capacitor insulating film 4 made of a metal oxide having a crystal structure of a high temperature phase can be directly formed on the first electrode 3 under conditions lower than that of the prior art. Further, annealing may be performed at a lower limit temperature at which a high-temperature phase crystal structure is obtained, and the capacitor insulating film 4 having a desired crystal structure (high-temperature phase crystal structure) can be efficiently obtained.

In addition, since the heat burden on the first electrode 3 material is reduced, it is possible to prevent the first electrode 3 from being defective and the operating characteristics from being deteriorated. Therefore, a highly integrated and low power consumption capacitor Cap can be realized. Further, since the capacitor insulating film 4 having a high-temperature phase crystal structure can be easily formed on the first electrode 3, the process is compared with the conventional method of manufacturing a capacitor Cap having the capacitor insulating film 4 having a high-temperature phase crystal structure. It can be simplified.
As described above, a highly integrated and low power consumption capacitor Cap can be realized.

Further, by selecting and using any one of titanium oxide, niobium oxide, and zirconium oxide as the metal oxide for the capacitive insulating film 4, a capacitor Cap having a large capacitance can be formed.
In addition, a capacitor Cap having a large capacitance can be formed by forming a laminated film in which at least two kinds of titanium oxide, niobium oxide or zirconium oxide are selected and laminated as a metal oxide film.

  In addition, when forming a film made of titanium oxide and / or niobium oxide as a film made of metal oxide, together with the source gas, Y (yttrium), Zr (zirconium), La (lanthanum), Al (aluminum) or By forming a film using a gas containing at least one element from the group of Sr (strontium), the capacitor insulating film 4 to which the element is added is formed, and a capacitor Cap having excellent leakage characteristics is obtained. Can be formed. When a film made of zirconium oxide is formed as a film made of metal oxide, a gas containing at least one element from the group of Y, La, Al, or Sr is used together with the source gas. Similar effects can be obtained by forming a film.

Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described. First, an example of the configuration of the semiconductor device 110 formed by the manufacturing method of this embodiment will be described with reference to FIGS.
FIG. 5 is a conceptual diagram showing a planar layout of a memory cell portion in a DRAM to which the capacitive insulating film 114 of the present invention shown in FIG. 6 is applied. Further, the right-hand side of FIG. 5 is a transmission cross-sectional view with reference to a plane that cuts a gate electrode 105 and a side wall 105b to be a word wiring W to be described later.
6 is a cross-sectional view showing a cross-sectional structure of the semiconductor device 110 corresponding to the line AA ′ of FIG. Note that the description of the capacitor Cap is omitted in FIG. 5 and only shown in FIG.

  First, the memory cell portion of the semiconductor device 110 will be described with reference to FIG. The memory cell portion is roughly composed of a bit wiring 106 extending in the X direction, a word wiring W extending in the Y direction, an elongated strip-shaped active region K, and an impurity diffusion layer 108. Details of each configuration will be described below.

The bit wiring 106 extends in a polygonal line shape (curved shape) in the X direction, and a plurality of bit wirings 106 are arranged at predetermined intervals in the Y direction.
Further, the word lines W are linearly extended in the Y direction, and a plurality of word lines W are arranged at a predetermined interval in the X direction. Further, the portion where the word line W and each active region K intersect each other includes a gate electrode 105 described later in the intersecting region. Further, sidewalls 105b are formed on both sides of the word wiring W along the line direction (Y direction).

The active region K is formed on one surface of the semiconductor substrate 101. The active region K has a long and narrow strip shape, and is arranged in an obliquely downward right direction with a predetermined interval. This is an arrangement along a layout generally called a 6F2 type memory cell.
Impurity diffusion layers 108 are individually formed in the central portion and both end sides of the active region K, and function as source / drain regions of a MOS transistor Tr1 described later. Circular substrate contact portions 205a, 205b, and 205c are formed so as to be disposed immediately above the source / drain regions (impurity diffusion layers), respectively.
The semiconductor substrate 101 has a plurality of element isolation regions 103 extending linearly in the Y direction. The element isolation regions 103 are arranged at predetermined intervals in the X direction.

Further, the substrate contact portions 205a, 205b, and 205c are arranged so that their centers are between the word lines W, respectively. The central substrate contact portion 205 a is arranged so as to overlap the bit wiring 106.
Further, the substrate contact portions 205a, 205b and 205c are provided at positions where a substrate contact plug 109 described later is disposed. Further, the positions where the substrate contact portions 205 a, 205 b and 205 c are formed are in contact with the semiconductor substrate 101.

  Next, a cross-sectional structure of the semiconductor device 110 will be described with reference to FIG. FIG. 6 is a schematic cross-sectional view corresponding to the A-A ′ line of the memory cell portion (FIG. 5). The semiconductor device 110 according to the present embodiment is generally configured by a semiconductor substrate 101, a MOS transistor Tr1, a substrate contact plug 109 and a capacitor contact plug 107A connected to the MOS transistor Tr1, and a capacitor Cap. Details of each will be described below.

The semiconductor substrate 101 is formed of a semiconductor containing a P-type impurity having a predetermined concentration, for example, silicon (Si). An element isolation region 103 is formed on the semiconductor substrate 101. The element isolation region 103 is formed by embedding an insulating film such as a silicon oxide film (SiO ₂ ) on the surface of the semiconductor substrate 101 by an STI (Shallow Trench Isolation) method. With such a configuration, adjacent active regions K are isolated from each other by the element isolation region 103. In the present embodiment, an example in which the present invention is applied to a cell structure in which 2-bit memory cells are arranged in one active region K is shown.

  The MOS transistor Tr1 includes a gate electrode 105 and an impurity diffusion layer 108. The gate electrode 105 is a groove-type gate electrode, and is embedded in a groove provided on one surface of the semiconductor substrate 101 and is formed so as to protrude from the groove through the impurity diffusion layer 108 to the upper portion of the semiconductor substrate 101. Yes.

  The gate electrode 105 is composed of a multilayer film of a polycrystalline silicon film containing impurities and a metal film. The polycrystalline silicon film can be formed by containing an N-type impurity such as phosphorus (P) during film formation by CVD (Chemical Vapor Deposition). The metal film may be made of a refractory metal such as tungsten (W), tungsten nitride (WN), tungsten silicide (WSi), or the like. With such a configuration, the gate electrode 105 functions as the gate electrode of the MOS transistor Tr1.

A gate insulating film 105 a is formed between the gate electrode 105 and the semiconductor substrate 101. A side wall 105b made of an insulating film such as silicon nitride (Si ₃ N ₄ ) is formed on the side wall of the gate electrode 105 protruding from the semiconductor substrate 101. An insulating film 105 c made of silicon nitride or the like is formed on the gate electrode 105 to protect the upper surface of the gate electrode 105.

  In the active region K of the semiconductor substrate 1, an impurity diffusion layer 108 that functions as a source / drain region of the MOS transistor Tr1 is formed. The impurity diffusion layer 108 is formed by introducing, for example, phosphorus as an N-type impurity into the semiconductor substrate 101. A groove-type gate electrode 105 is formed between the individual impurity diffusion layers 108, and the individual impurity diffusion layers 108 are separated from each other.

  The substrate contact plug 109 is formed so as to be in contact with the impurity diffusion layer 108. The substrate contact plug 109 is disposed at the position of each of the substrate contact portions 205c, 205a, and 205b shown in FIG. 5, and is made of, for example, polycrystalline silicon containing phosphorus (P). Further, the width in the horizontal (X) direction of the substrate contact plug 109 is defined by the sidewall 105 b provided in the adjacent gate wiring W. That is, the substrate contact plug 109 has a self-aligned structure defined by the sidewall 105b.

  The first interlayer insulating film 104 is formed so as to cover the insulating film 105 c on the gate electrode 105 and the substrate contact plug 109. The bit line contact plug 104A is disposed at a position corresponding to the substrate contact portion 205a of FIG. Further, the bit line contact plug 104A is formed so as to penetrate the first interlayer insulating film 104 and to be electrically connected to the substrate contact plug 109. The bit line contact plug 104A has a structure in which, for example, tungsten (W) or the like is sequentially laminated on a barrier film (TiN / Ti) made of a laminated film of titanium (Ti) and titanium nitride (TiN).

  The bit line 106 is formed so as to be connected to the bit line contact plug 104A. The bit wiring 106 is formed of a laminated film made of tungsten nitride (WN) and tungsten (W).

  The second interlayer insulating film 107 is formed so as to cover the bit wiring 106 and the first interlayer insulating film 104. Further, the capacitor contact plug 107A is formed so as to penetrate the second interlayer insulating film 107 and the first interlayer insulating film 104 and to be connected to the substrate contact plug 109. The capacitor contact plug 107A is disposed at the position of the substrate contact portions 205b and 205c shown in FIG.

  The third interlayer insulating film 111 made of silicon nitride is formed so as to cover the second interlayer insulating film 107, and the fourth interlayer insulating film 112 made of a silicon oxide film is formed by the third interlayer insulating film 111. It is formed so as to cover.

  The capacitor Cap is disposed inside the third interlayer insulating film 111 and the fourth interlayer insulating film 112. The capacitor Cap passes through the third interlayer insulating film 111 and the fourth interlayer insulating film 112, and the portion of the first electrode 113 is connected to the capacitor contact plug 107A. The first electrode 113 and the capacitor contact plug 107A may not be directly connected, and a pad formed of a conductive film may be interposed between the first electrode 113 and the contact plug 107A. The first electrode 113 is connected to the MOS transistor Tr1 via the capacitive contact plug 107A.

The capacitor Cap includes a first electrode 113, a capacitor insulating film 114 formed to cover the side surface of the first electrode 113, and a second electrode 115 formed to cover the capacitor insulating film 114. It is configured. That is, the capacitor Cap has a structure in which the capacitor insulating film 114 is sandwiched between the first electrode 113 and the second electrode 115.
A predetermined potential is applied to the second electrode 115 of the capacitor Cap. Therefore, by determining the presence or absence of electric charge held in the capacitor Cap, it can function as a DRAM that performs an information storage operation.

The capacitor insulating film 114 is formed of a metal oxide having a crystal structure in a high temperature phase. The capacitor insulating film 114 is preferably formed of titanium oxide, niobium oxide (Nb ₂ O ₅ ), or ZrO ₂ (zirconium oxide). _{Also, TiO 2, Nb 2 O 5} , from the ZrO ₂ may be composed of a laminated film of laminated layers by selecting at least two or more types. By using such a metal oxide as the material of the capacitor insulating film 114, a capacitor Cap having a large capacitance can be formed.
Further, the capacitor insulating film 114 may contain (add) at least one element from the group of yttrium, zirconium, lanthanum, aluminum, or strontium. This is because the leakage withstand voltage of the capacitor Cap is improved.

  A fifth interlayer insulating film 120 made of silicon oxide or the like is formed on the second electrode 115. On the fifth interlayer insulating film 120, a wiring 121 made of aluminum (Al), copper (Cu), or the like is formed. A surface protective film 122 is formed so as to cover the fifth interlayer insulating film 120 and the wiring 121.

  Next, an example of a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. In addition, the raw material, dimension, etc. which are illustrated in the following description are an example, Comprising: This invention is not limited to them, It is possible to change suitably in the range which does not change the summary.

  The manufacturing method of the semiconductor device of this embodiment is roughly configured from a step of forming a transistor (MOS transistor Tr1) and a step of forming a capacitor Cap. Details of each step will be described below.

  First, a semiconductor substrate 101 containing a predetermined concentration of P-type impurities is prepared. Next, an element isolation region 103 is formed on the surface of the semiconductor substrate 101 by STI (Shallow Trench Isolation). Thus, the region partitioned by the element isolation region 103 becomes the active region K shown in FIG. Next, a plurality of trenches 102 are formed adjacent to one surface of the semiconductor substrate 101 using a mask (not shown). The trench 102 is used for a trench-type gate electrode of the MOS transistor Tr1.

Next, the surface of the semiconductor substrate 101 is oxidized by a thermal oxidation method, and a gate insulating film 105 a made of silicon oxide (SiO ₂ ) is formed on the inner wall of the trench 102. Note that the silicon oxide film formed on the main surface of the semiconductor substrate 101 may be removed in a later manufacturing process of the MOS transistor.
Next, a polycrystalline silicon film containing an N-type impurity such as phosphorus is deposited on the gate insulating film 105a to completely fill the trench 102 with the polycrystalline silicon film. Next, a refractory metal such as tungsten, tungsten nitride, or tungsten silicide is deposited on the polycrystalline silicon film to a thickness of about 50 nm by sputtering, thereby forming a metal film. The polycrystalline silicon film and the metal film formed in this manner are used as the gate electrode 105 through a process described later.

  Next, an insulating film 105c made of, for example, silicon nitride is deposited to a thickness of about 70 nm on the metal film by plasma CVD. Next, a photoresist pattern (resist mask) for forming a gate electrode is formed on the insulating film 5c by photolithography, and then the insulating film 105c is anisotropically etched using the resist mask. After removing the resist mask, the gate electrode 105 is formed by etching the metal film and the polycrystalline silicon film using the insulating film 105c as a hard mask. Note that the gate electrode 105 functions as the word line W shown in FIG.

  Next, an impurity diffusion layer 108 is formed by performing ion implantation of phosphorus as an N-type impurity on one surface of the semiconductor substrate 101 not covered with the gate electrode 105 in the active region. The impurity diffusion layer 108 functions as a source / drain region of the MOS transistor Tr1. Thus, the MOS transistor Tr1 including the gate electrode 105 and the impurity diffusion layer 108 is formed.

  Next, a silicon nitride film having a thickness of about 20 to 50 nm is deposited by CVD to cover one surface of the semiconductor substrate 101, the gate electrode 105, and the insulating film 105c. Next, the silicon nitride film is etched back until the insulating film 105c is exposed. As a result, a sidewall 105 b is formed on the side wall of the gate electrode 105.

  Next, using a photolithography method, a photoresist pattern (resist mask) is formed on the insulating film 105c so as to form openings at the positions of the substrate contact portions 205a, 205b, and 205c shown in FIG. Next, anisotropic dry etching is performed using the resist mask. Thus, an opening can be provided between the gate electrodes 105 by self-alignment using the insulating film 105c and the sidewall 105b made of silicon nitride.

Next, a polycrystalline silicon film containing phosphorus is deposited by CVD. Next, the surface of the polycrystalline silicon film is polished by CMP until the insulating film 105c is exposed. As a result, a substrate contact plug 109 having a structure filled in the opening is formed on the impurity diffusion layer 108.
Next, a first interlayer insulating film 104 made of silicon oxide or the like is formed so as to cover the insulating film 105c on the gate electrode and the substrate contact plug 109 by using the CVD method. Next, the surface of the first interlayer insulating film 104 is polished and planarized using a CMP method.

Next, an opening (contact hole) is formed in the first interlayer insulating film 104 at the position of the substrate contact portion 205a shown in FIG. 5 so that the surface of the substrate contact plug 109 is exposed.
Next, after depositing a film in which tungsten (W) is laminated on a barrier film such as TiN / Ti so as to fill the opening, the first interlayer insulating film 104 is exposed by CMP. The surface is polished until the bit line contact plug 104A is formed.

  Next, after the bit wiring 106 is formed on the first first interlayer insulating film 104 so as to be connected to the bit line contact 104A, the bit wiring 106 and the first first interlayer insulating film 104 are covered. Then, a second interlayer insulating film 107 made of silicon oxide or the like is formed.

Next, the first first interlayer insulating film 104 and the second second interlayer insulating film 107 are exposed so as to expose the surface of the substrate contact plug 109 at the positions of the substrate contact portions 205b and 205c shown in FIG. An opening (contact hole) penetrating through is formed.
Next, after depositing a film in which tungsten (W) is laminated on a barrier film such as TiN / Ti so as to fill the opening, the first interlayer insulating film 4 is exposed by CMP. The surface is polished until the capacitor contact plug 107A is formed. As described above, the capacitor contact plug 107A and the MOS transistor Tr1 are connected via the substrate contact plug 109.

  Next, the capacitor Cap is formed. In FIG. 7 to FIG. 9, the description of the portion below the first third interlayer insulating film 111 is omitted.

  First, the first electrode 113 is formed as shown in FIG. First, a first third interlayer insulating film 111 made of silicon nitride is formed to a thickness of about 60 nm so as to cover the second second interlayer insulating film 107. Next, a second fourth interlayer insulating film 112 made of silicon oxide or the like is deposited to a thickness of about 2 μm so as to cover the first third interlayer insulating film 111, and then anisotropic dry etching is used. Then, a hole 112A is formed in the second fourth interlayer insulating film 112 so as to expose the surface of the capacitor contact plug 107A. The inner wall of the hole 112A is a region where the capacitor Cap is formed.

  Next, a titanium film and a titanium nitride film are sequentially deposited so as to cover the inner wall side surface and the bottom surface of the hole 112A and not to completely fill the inside of the hole 112A. Next, the titanium film and the titanium nitride film on the fourth interlayer insulating film 112 are removed by a dry etching method or a CMP method, and a cylindrical first electrode 113 made of the titanium film and the titanium nitride film is formed. Note that here, a titanium film and a titanium nitride film are cited as materials for the first electrode 113, but the materials are not limited to these, and other metal films may be used.

Next, as shown in FIG. 8, a capacitive insulating film 114 made of a metal oxide is formed. As the metal oxide in this embodiment, an oxide capable of forming an amorphous phase, a low-temperature phase crystal structure, and a high-temperature phase crystal structure in descending order of film formation temperature is used. As such a material, any one of titanium oxide, niobium oxide, and zirconium oxide can be selected and used. Alternatively, a laminated film in which at least two kinds of titanium oxide, niobium oxide, or zirconium oxide are selected and laminated may be formed.
Hereinafter, an example in which titanium oxide (TiO ₂ ) is used as the metal oxide for the capacitive insulating film 4 will be described.

  First, the semiconductor substrate 101 on which up to the first electrode 113 is formed is placed in a reaction chamber of a film forming apparatus (not shown). At this time, the temperature in the reaction chamber of the film forming apparatus is set to the first temperature.

The first temperature is set to be 100 ° C. or more lower than the temperature at which the crystal structure (anatase structure) of the low-temperature phase of the metal oxide (titanium oxide) for the capacitive insulating film 4 is obtained.
Also, when niobium oxide is used as the metal oxide material, the temperature is 100 ° C. or more lower than the temperature at which a low-temperature phase crystal structure (hexagonal crystal structure) is obtained. Also when zirconium oxide is used, the temperature is set to be 100 ° C. or more lower than the temperature at which a low-temperature phase crystal structure (tetragonal structure) is obtained.

  Next, an amorphous film (capacitive insulating film 114) made of a metal oxide having an amorphous crystal structure is formed on the first electrode 113 by ALD. Note that in this specification, a film made of a metal oxide having an amorphous crystal structure is referred to as an amorphous film 114.

  First, Ti source gas (Ti precursor) is supplied into the reaction chamber, and a titanium film is deposited on the surface of the first electrode 3. At this time, in addition to the film formation with the source gas, at least one element from the group of Y (yttrium), Zr (zirconium), La (lanthanum), Al (aluminum) or Sr (strontium) is added. Then, the film may be formed. In this embodiment, an example using titanium oxide will be described. However, when zirconium oxide is formed as a metal oxide film, at least one or more kinds of Y, La, Al, or Sr are added as additives. Elements may be used.

Next, purge N ₂ gas is supplied into the reaction chamber, and Ti source gas is discharged. Next, the titanium film is oxidized by supplying an oxidizing agent into the reaction chamber. At this time, as the oxidizing agent, oxygen (O ₂ ), ozone (O ₃ ), water vapor (H ₂ O), a mixed gas of these gases, or a mixed gas of these gases and nitrogen gas, etc. Can be used.
Thereafter, N ₂ gas is supplied into the reaction chamber and the oxidant is discharged.

  Thus, an atomic layer of titanium oxide is formed so as to cover the inner wall surface and the bottom surface of the first electrode 113. Thereafter, the thin film of the amorphous film 114 made of an atomic layer of titanium oxide is formed by repeating a series of steps from introduction of the source gas to purging of the oxidant any number of times. Here, for example, the amorphous film 114 is formed with a film thickness of 6 nm to 10 nm.

  In the formation of the amorphous film 114, at least two types of titanium oxide, niobium oxide, or zirconium oxide are selected without stacking the same metal atomic layer, and a stacked film (amorphous film) is selected. 114) may be laminated.

  Next, from the first temperature to the temperature (second temperature) at which a high-temperature stable crystal structure such as a rutile structure in titanium oxide is obtained (second temperature), the reaction chamber is heated at a rate of 10 ° C./second or more. Increase temperature.

  At this time, the second temperature when niobium oxide is used as the metal oxide (amorphous film 4) is 700 ° C. Further, the annealing of the amorphous film 4 made of niobium oxide precipitates the orthorhombic crystal structure as a high-temperature phase crystal structure. In order to form a high-temperature phase (orthorhombic structure) crystal film using niobium oxide, an amorphous film is formed at a temperature of 400 ° C. or lower, and then a temperature increase rate of 10 ° C./second or higher is 700. Annealing may be performed by raising the temperature to ° C.

  Similarly, the second temperature when zirconium oxide is used as the amorphous film 4 is 450 ° C., and the amorphous film 4 is annealed to precipitate a hexagonal crystal structure as a high-temperature phase crystal structure. . In order to form a high-temperature phase (hexagonal crystal) crystal film using zirconium oxide, an amorphous film is formed at a temperature of 200 ° C. or lower, and then a temperature rise rate of 10 ° C./second or higher is 450 ° C. The temperature may be increased up to annealing.

  Further, in the case of using a laminated film (amorphous film 114) in which at least two kinds of titanium oxide, niobium oxide, or zirconium oxide are selected and laminated as the metal oxide, each metal used in the laminated film is used. The temperature is raised to the highest temperature among the second temperatures.

  Next, the amorphous film 114 is annealed in a nitrogen atmosphere while maintaining the temperature in the reaction chamber at the second temperature. By this annealing, a high-temperature phase crystal structure is deposited, and a capacitive insulating film 114 made of a metal oxide having a high-temperature phase crystal structure is formed.

Next, as shown in FIG. 9, the second electrode 115 is formed.
First, a laminated film of, for example, a titanium film and a titanium nitride film is deposited so as to cover the inner wall surface of the capacitor insulating film 114 and the second fourth interlayer insulating film 112. Next, the stacked film is patterned to form the second electrode 115.
As described above, the cylindrical first electrode 113, the capacitor insulating film 114 formed so as to cover the inner wall surface and the bottom surface of the first electrode 113, and the second electrode formed so as to cover the capacitor insulating film 114. A capacitor Cap having the electrode 115 is formed.

  In addition, although the capacitor Cap in the present embodiment has been shown as an example of a cylinder type that uses only the inner wall of the first electrode 113 as an electrode, a crown type that uses both the outer wall and the inner wall of the first electrode 113 as an electrode. Alternatively, a pedestal capacitor that uses only the outer wall of the first electrode 113 as an electrode can be used.

Thereafter, as shown in FIG. 6, a fifth interlayer insulating film 120 made of silicon oxide or the like is formed so as to cover the second electrode 115.
Next, a lead-out contact plug (not shown) for applying a potential to the second electrode 115 of the capacitor Cap is formed so as to penetrate the fifth interlayer insulating film 120.
Next, a wiring 121 made of aluminum (Al), copper (Cu), or the like is formed on the fifth interlayer insulating film 120 so as to be connected to the lead contact plug. Next, a surface protective film 122 made of silicon oxynitride (SiON) or the like is formed so as to cover the wiring 121 and the fifth interlayer insulating film 120.
Through the above steps, the semiconductor device 110 according to the embodiment of the present invention is manufactured.

  According to the method for manufacturing the semiconductor device 110 of this embodiment, the amorphous metal oxide is formed on the first electrode 113 at a temperature that is 100 ° C. or more lower than the temperature at which the low-temperature crystal structure of the metal oxide film is obtained. By forming the material film, the amorphous film 114 can be formed without precipitating the crystal structure of the low temperature phase. Further, after the amorphous film 114 is formed, the temperature is rapidly increased at a temperature increase rate of 10 ° C./second or more to a temperature at which a crystal structure of a high-temperature phase of the metal oxide can be obtained. Precipitation of the crystal structure of the phase can be prevented.

  In addition, since precipitation of the crystal structure of the low temperature phase in the amorphous film 114 is prevented, high temperature annealing for changing the crystal structure of the low temperature phase to the crystal structure of the high temperature phase is not necessary, The heat burden on the electrode 113 and the MOS transistor can be reduced. Therefore, the capacitor insulating film 114 made of a metal oxide having a crystal structure in a high temperature phase can be formed on the first electrode 113 without damaging the semiconductor device under a condition lower than that in the past. Further, since annealing at a lower limit temperature for obtaining a high-temperature phase crystal structure may be performed, the semiconductor device 110 including the capacitor insulating film 114 having a desired crystal structure (high-temperature phase crystal structure) can be easily formed.

  In addition, since a capacitor using a dielectric film having a crystal structure with a high dielectric constant can be easily formed, it is possible to realize a semiconductor device 110 having excellent refresh characteristics (data retention characteristics), high integration, and low power consumption. Become.

Further, by selecting and using any one of titanium oxide, niobium oxide, and zirconium oxide as the metal oxide for the capacitor insulating film 114, the semiconductor device 110 having the capacitor Cap having a large capacitance can be formed. .
Further, a semiconductor device 110 having a capacitor Cap having a large capacitance is formed by forming a laminated film in which at least two or more of titanium oxide, niobium oxide and zirconium oxide are laminated as a metal oxide film. Can be formed.

  In addition, when forming a film made of titanium oxide and / or niobium oxide as a film made of metal oxide, together with the source gas, Y (yttrium), Zr (zirconium), La (lanthanum), Al (aluminum) or By forming a film using a gas containing at least one kind of element from the group of Sr (strontium), the semiconductor device 110 having the capacitor Cap with a large leakage withstand voltage can be formed. In addition, when forming a film made of zirconium oxide as a film made of metal oxide, a film containing at least one element from the group of Y, La, Al, or Sr is formed together with the source gas. The same effect can be obtained by forming a film.

Hereinafter, an example of the manufacturing method of the capacitor Cap of the present invention will be specifically described based on examples. However, the present invention is not limited only to these examples.
Example 1

As Example 1, a process of finally forming a capacitor Cap having a capacitive insulating film 4 made of titanium oxide (TiO ₂ ) using the ALD method will be described.
First, as shown in FIG. 1, an interlayer insulating film 2 made of silicon oxide (SiO ₂ ) was formed on a semiconductor substrate 1 made of Si. Next, a first electrode 3 made of Pt was formed on the interlayer insulating film 2. Here, the reason why Pt is used as the material of the first electrode 3 is that Pt is excellent in heat resistance and easy to evaluate characteristics.

  Next, the semiconductor substrate 1 formed up to the first electrode 3 was placed in the reaction chamber of the ALD film forming apparatus. Next, an amorphous film 4 having an amorphous crystal structure was formed on the first electrode 3 by an ALD method using TDMAT as a source gas. At this time, the temperature (first temperature) in the reaction chamber was set to 200 ° C., which is 100 ° C. lower than the lowest temperature (330 ° C.) at which titanium oxide having a low-temperature phase crystal structure (anatase structure) is stably formed. As a result, an amorphous film 4 made of titanium oxide in an amorphous state (amorphous state) having a thickness of 9 nm was formed.

In addition, when the TiO ₂ film is formed at a high temperature (660 ° C. or higher), only the rutile structure is formed from the beginning. When the TiO ₂ film is formed at an intermediate temperature (550 ° C.), a mixed state of the anatase structure and the rutile structure. It is supposed to be. The second temperature at which the annealing of the present invention is performed is a temperature for forming a film formed in an amorphous state into a predetermined crystal structure. It does not necessarily match the film temperature. In the present invention, the second temperature for forming the rutile-structured titanium oxide is 600 ° C.

Next, the temperature in the reaction chamber was increased from the first temperature (200 ° C.) to the second temperature (600 ° C.) at a rate of temperature increase of 10 ° C./second. At this time, the reaction chamber was filled with nitrogen.
Next, with the temperature in the reaction chamber maintained at the second temperature (600 ° C.), the amorphous film 4 was annealed (post-annealed) to form the capacitive insulating film 4. After the annealing treatment, the crystal structure of the capacitive insulating film 4 (titanium oxide) was examined by XRD (X-ray diffracation). As a result, the rutile structure (crystal structure of the high temperature phase) was the main crystal structure.

Similarly, the first temperature was changed to 250 ° C. and 300 ° C., and the second temperature was changed to 400 ° C., 500 ° C., 600 ° C. and 700 ° C., and the amorphous film 4 was formed under each condition. . Further, as a comparative example, the amorphous film 4 was formed without performing the post-annealing process.
Table 1 shows each crystal structure when the capacitor insulating film 4 is formed by changing the first temperature and the second temperature, respectively. In addition, what is underlined has shown that the structure is main. In addition, an underlined “anatase structure + rutile structure” indicates that titanium oxides having two types of crystal structures are contained to the same extent.

As shown in Table 1, when the first temperature was 200 ° C., an amorphous (amorphous) amorphous film 4 having a thickness of 9 nm was formed. Thereafter, post-annealing was performed at a second temperature of 600 ° C., and the amorphous film 4 became a capacitive insulating film 4 mainly composed of titanium oxide having a rutile structure. Further, no anatase structure was generated in the capacitive insulating film 4. The same result was obtained when the second temperature was 500 ° C.
On the other hand, when the first temperature is 200 ° C. and the second temperature is 400 ° C., the amorphous film 4 does not have a rutile structure, and the crystal structure of the capacitive insulating film 4 is amorphous (amorphous state). It remained.

In addition, when the first temperature was 250 ° C., an amorphous film 4 having a film thickness of 9 nm was formed. Thereafter, post-annealing was performed at a second temperature of 700 ° C. As a result, the amorphous film 4 became a capacitive insulating film 4 having a crystal structure mainly including a rutile structure and including an anatase structure.
Further, when the first temperature was 250 ° C. and the second temperature was 600 ° C., the capacitive insulating film 4 had a crystal structure including both the rutile structure and the anatase structure.
Further, when the first temperature is 250 ° C. and the second temperature is 500 ° C., titanium oxide having a rutile structure does not precipitate in the capacitor insulating film 4, and the crystal structure of the capacitor insulating film 4 is amorphous ( (Amorphous state).

Further, when the first temperature was set to 300 ° C., the capacitive insulating film 4 having an anatase structure with a film thickness of 20 nm was formed. Thereafter, post-annealing was performed at a second temperature of 700 ° C., and the capacitive insulating film 4 had a crystal structure mainly including a rutile structure and including an anatase structure.
Similarly, when the first temperature is 300 ° C. and the second temperature is 600 ° C., the capacitive insulating film 4 has a crystal structure mainly including a rutile structure and including an anatase structure.
When the first temperature was 300 ° C. and the second temperature was 500 ° C., the capacitive insulating film 4 had a crystal structure mainly including an anatase structure and including a rutile structure.
When the first temperature was 300 ° C. and the second temperature was 400 ° C., the capacitive insulating film 4 remained in a crystal structure mainly composed of an anatase structure.

When the first temperature is 200 ° C. or 250 ° C., the capacitive insulating film 4 is formed with a thickness of 9 nm, whereas when the first temperature is 300 ° C., the capacitive insulating film 4 is The film was formed with a thickness of 20 nm.
The reason for the difference in film thickness due to the temperature during film formation is that when the first temperature is set to 300 ° C., the film formation temperature at the first temperature is high in addition to the high temperature during film formation. Sometimes it is already anatase structure, and it is presumed that this is because it is easier to crystallize compared to the amorphous state.

As described above, the capacitive insulating film 4 is formed at the first temperature (200 ° C.) that is 100 ° C. or more lower than the lowest temperature (330 ° C.) at which the titanium oxide having the anatase structure as the low temperature phase is stably formed. By setting the temperature increase rate of post-annealing to 10 ° C./second or more, the capacitive insulating film 4 having a rutile structure as a desired crystal structure could be obtained by a low temperature process.
Further, when the first temperature is 300 ° C., an anatase structure is deposited. However, when the first temperature is 200 ° C., the capacitive insulating film 4 having the rutile structure can be obtained without generating the anatase structure. It was.

  Examples of utilization of the present invention include semiconductor devices including DRAMs, capacitors, or MOS transistors.

Tr1 ... MOS transistor, W ... word wiring, Cap ... capacitor, 1 ... semiconductor substrate, 2 ... interlayer insulating film, 3 ... first electrode, 4 ... capacitive insulating film (amorphous film), 5 ... second electrode 101 ... Semiconductor substrate, 102 ... Trench, 103 ... Element isolation region, 104 ... First interlayer insulating film, 104A ... Bit line contact plug, 105 ... Gate electrode, 105a ... Gate insulating film, 105b ... Side wall, 105c ... Insulating film, 106 bit wiring, 107 second interlayer insulating film, 107A capacitor contact plug, 108 impurity diffusion layer, 109 substrate contact plug, 110 semiconductor device, 111 third interlayer insulating film, 112 ... fourth interlayer insulating film, 113 ... first electrode, 114 ... capacitive insulating film (amorphous film), 115 ... second electrode

Claims (9)

A method for manufacturing a capacitor using a film made of a metal oxide having a crystal structure of a low-temperature phase stable at a low temperature and a crystal structure of a high-temperature phase stable at a high temperature as a capacitor insulating film,
Forming a first electrode;
Forming an amorphous film of the metal oxide on the first electrode at a temperature 100 ° C. or more lower than a temperature at which the crystal structure of the low-temperature phase is obtained;
After the temperature is increased at a temperature rising rate of 10 ° C./second or more to a temperature at which the high-temperature phase crystal structure is obtained, the amorphous film is annealed while maintaining the temperature at which the high-temperature phase crystal structure is obtained. And a step of forming a crystal film of the metal oxide,
And a step of forming a second electrode on the crystal film.   The method for manufacturing a capacitor according to claim 1, wherein the metal oxide is made of any one of titanium oxide, niobium oxide, and zirconium oxide.   2. The method of manufacturing a capacitor according to claim 1, wherein the film made of the metal oxide is a laminated film in which at least two kinds of films selected from titanium oxide, niobium oxide, and zirconium oxide are laminated.   The film made of the metal oxide contains at least one element from the group of Y (yttrium), Zr (zirconium), La (lanthanum), Al (aluminum), or Sr (strontium). The method for manufacturing a capacitor according to claim 2, wherein: A method of manufacturing a semiconductor device including a capacitor using a metal oxide as a capacitor insulating film,
Forming a MOS transistor on a semiconductor substrate;
Forming a first electrode for the capacitor connected to any one of the source and drain electrodes of the MOS transistor;
Forming an amorphous film of the metal oxide on the first electrode at a temperature lower by 100 ° C. or more than a temperature at which a crystal structure of a low-temperature phase of the metal oxide is obtained;
After the temperature is increased at a rate of temperature increase of 10 ° C./second or more to a temperature at which the crystal structure of the high-temperature phase of the metal oxide is obtained, the temperature at which the crystal structure of the high-temperature phase is obtained is maintained and the amorphous Annealing the material film to form a crystal film of the metal oxide;
A method of manufacturing a semiconductor device, comprising: forming a second electrode for the capacitor on the crystal film.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the metal oxide is formed so as to include any one of titanium oxide, niobium oxide, and zirconium oxide. Forming the amorphous metal oxide film includes depositing a metal film mainly composed of a metal contained in the metal oxide;
The method for manufacturing a semiconductor device according to claim 5, further comprising: oxidizing the metal film with an oxidizing agent to change the metal film into a metal oxide film. The metal film contains any one of Ti (titanium), Nb (niobium), and Zr (zirconium) as a main component,
Furthermore, it contains at least one element from the group of Y (yttrium), Zr (zirconium), La (lanthanum), Al (aluminum) or Sr (strontium). Item 8. A method for manufacturing a semiconductor device according to Item 7. The metal oxide is titanium oxide,
Forming the amorphous film at a temperature of 230 ° C. or lower;
The method of manufacturing a semiconductor device according to claim 5, wherein the annealing is performed at a temperature of 600 ° C. or more.

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