JP2011213082A - Light emitting device, electronic device, and driving method of the light emitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the transfer rate of light emission control signals from being increased in a light emitting device employing a multiplex exposure system.SOLUTION: A control circuit 20 is configured to, in a writing period TW, make the gate of a first drive transistor Td1 and the gate of a second drive transistor Td2 in a non-conductive state, and thereafter, supply a data potential Vd[1] to the gate of the first drive transistor Td1, and in the following transfer period, make the gate of the first drive transistor Td1 and the gate of the second drive transistor Td2 in a conductive state, and transfer the data potential Vd[1] held by a first holding capacitance C1 to a second holding capacitance C2. That is, the control circuit 20 can control light emission of each of the first and second light emitting elements E11 and E21 by supplying the data potential Vd[1] to a data line 23[1] only once in each unit period (T1 to T3).

Description

  The present invention relates to a light emitting device, an electronic apparatus, and a driving method of the light emitting device.

  2. Description of the Related Art Conventionally, an electrophotographic image forming apparatus using a light emitting device in which a plurality of light emitting elements are arranged for exposure of an image carrier such as a photosensitive drum has been proposed. For example, in Patent Document 1, two rows of light emitting lines in which a plurality of light emitting elements are arranged along the main scanning direction are provided, and light emitted from each light emitting element (first light emitting element) belonging to one light emitting line and the other are provided. Discloses a technique for performing multiple exposure on an exposed surface of an image carrier with light emitted from each light emitting element (second light emitting element) belonging to the light emitting line.

  The light emitting device (exposure head) disclosed in Patent Document 1 includes a plurality of processing units for driving each of a plurality of sets each composed of a first light emitting element and a second light emitting element, And a control circuit for controlling the processing unit. A light emission control signal for controlling light emission of each light emitting element is supplied to the control circuit from the outside. The control circuit supplies (transfers) a light emission control signal supplied from the outside to each processing unit. Each processing unit generates a drive current according to the light emission control signal supplied from the control circuit.

JP 2008-80608 A

The above-described control circuit supplies, to each processing unit, the light emission control signal of the first light emitting element belonging to the group corresponding to the processing unit and the light emission control signal of the second light emitting element belonging to the group. . That is, the control circuit supplies (transfers) twice as many light emission control signals as compared with a configuration in which multiple exposure is not performed, which causes a problem that the transfer rate of the light emission control signals increases.
The present invention has been made in view of such circumstances, and an object of the present invention is to prevent an increase in the transfer rate of the light emission control signal in a light emitting device employing a multiple exposure method.

  In order to solve the above-described problems, a light-emitting device according to the present invention includes first and second light-emitting elements, first and second drive transistors that each output a drive current according to a gate potential, A first storage capacitor for holding the gate potential of the first drive transistor, a second storage capacitor for holding the gate potential of the second drive transistor, and between the gate of the first drive transistor and the data line Provided between a first switching element for switching between conduction and non-conduction between the gate of the first drive transistor and the data line, and between the gate of the second drive transistor and the gate of the first drive transistor, A second switching element for switching between conduction and non-conduction between the gate of the drive transistor and the gate of the first drive transistor; The switching element is set to the on state, the second switching element is set to the off state, a data potential corresponding to the image data is supplied to the data line, and the first switching element is turned off in the transfer period after the writing period. And a control unit that sets the second switching element to an ON state.

  In the writing period, the control circuit of the present invention sets the gate of the first drive transistor and the gate of the second drive transistor in a non-conducting state and sets the data potential corresponding to the image data to the gate of the first drive transistor. In the subsequent transfer period, the gate of the first drive transistor and the gate of the second drive transistor are made conductive to transfer the data potential held in the first storage capacitor to the second storage capacitor. That is, the control circuit can control the light emission of each of the first light-emitting element and the second light-emitting element by supplying the data potential (light emission control signal) to the data line only once. There is an advantage that an increase in the signal transfer rate can be prevented.

  As a mode of the light-emitting device according to the present invention, the light-emitting device further includes a reset transistor for switching conduction and non-conduction between one electrode of the second storage capacitor and the other electrode, and the control unit includes a period after the writing period In the initialization period immediately before the transfer period, the second switching element is set to the off state and the reset transistor is set to the on state. In this aspect, the charge held in the second storage capacitor is completely removed (reset) by setting the reset transistor to the ON state in the initialization period. As a result, in the subsequent transfer period, the gate potential of the second drive transistor can be set to a desired value with high accuracy.

  The light-emitting device according to the present invention includes first and second light-emitting elements, first and second drive transistors that each output a drive current according to a gate potential, and a gate potential of the first drive transistor. Having a first storage capacitor, a first electrode, and a second electrode connected to the source of the second drive transistor, a second storage for holding the gate potential of the second drive transistor A capacitor, a first switching element provided between the gate of the first drive transistor and the data line, for switching between conduction and non-conduction between the gate of the first drive transistor and the data line, and the gate of the first drive transistor And a second switching element for switching between conduction and non-conduction between the gate of the first drive transistor and the first electrode, and a second drive transistor A third switching element provided between the gate of the first drive electrode and the first electrode for switching between conduction and non-conduction between the gate of the second drive transistor and the first electrode, and the first switching in the first writing period The element is set to the on state, the second switching element and the third switching element are set to the off state, and the data potential corresponding to the image data is supplied to the data line. In the transfer period after the first writing period, the first The switching element and the third switching element are set to an off state, the second switching element is set to an on state, and the first switching element and the second switching element are turned off and the third switching element is turned on in a set period after the transfer period. And a control unit for setting the state.

  Even in the above-described configuration, the control circuit controls the light emission of each of the first light-emitting element and the second light-emitting element by supplying the data potential (light emission control signal) to the data line only once. Therefore, there is an advantage that an increase in the transfer rate of the light emission control signal can be prevented. In addition, the control circuit transfers the data potential held in the first holding capacitor to the second holding capacitor while the gate of the first driving transistor and the gate of the second driving transistor are made non-conductive in the transfer period. Therefore, there is an advantage that the voltage value of the second storage capacitor quickly reaches a desired value as much as it is hardly influenced by the capacitance parasitic on the gate of the second drive transistor.

  In the above aspect, the emitted light from each of the first and second light emitting elements is irradiated to the same exposed surface at different timings. That is, since the multiple exposure method is employed, the light emission amount of each light emitting element can be reduced as compared with a configuration in which the multiple exposure method is not employed. Therefore, it is possible to suppress the deterioration of characteristics of the light emitting element.

  The light emitting device according to the present invention is used in various electronic devices. For example, an image forming apparatus according to one aspect of the present invention includes a light emitting device according to any one of the above aspects, an image carrier having an exposed surface on which a latent image is formed by light emission by the light emitting device, and an image carrier. A developing unit that forms a visible image by adding a developer to the latent image of the body.

  However, the use of the light emitting device according to the present invention is not limited to the exposure of the image carrier. For example, in an image reading apparatus such as a scanner, the light emitting device according to the present invention can be used for illuminating a document. The image reading apparatus includes an exposure apparatus according to each of the above aspects, and a light receiving apparatus (for example, a CCD (Charge Coupled Device) element) that converts light emitted from the exposure apparatus and reflected by a reading target (original) into an electrical signal. Light receiving element).

  The present invention is also specified as a method of driving a light emitting device. The driving method according to the present invention includes the first and second light emitting elements, the first and second driving transistors each outputting a driving current according to the gate potential, and the gate potential of the first driving transistor. A light emitting device driving method comprising: a first holding capacitor for holding a second holding capacitor for holding a potential of a gate of a second driving transistor, wherein the gate of the first driving transistor is written in a writing period And the gate of the second drive transistor are made non-conductive, a data signal having a magnitude corresponding to the exposure amount is supplied to the gate of the first drive transistor, and in the transfer period after the writing period, the first The gate of the driving transistor and the gate of the second driving transistor are made conductive, and the data potential held in the first holding capacitor is transferred to the second holding capacitor. The same effect as that of the light emitting device according to the present invention can be obtained by the above driving method.

1 is a perspective view showing a partial configuration of an image forming apparatus according to a first embodiment of the present invention. It is a figure which shows typically arrangement | positioning of a light emitting element. It is a circuit diagram of a light-emitting device. It is a figure showing the electrostatic latent image formed in a to-be-exposed surface. It is a timing chart which shows operation | movement of the light-emitting device which concerns on 1st Embodiment. It is a schematic diagram for demonstrating the mode of multiple exposure. It is a figure for demonstrating operation | movement of the light-emitting device in a writing period. It is a figure for demonstrating operation | movement of the light-emitting device in an initialization period. It is a figure for demonstrating operation | movement of the light-emitting device in a transfer period. It is a block diagram of the light-emitting device which concerns on contrast. It is a timing chart which shows operation | movement of the light-emitting device which concerns on contrast. It is a circuit diagram of the 1st unit of the light-emitting device which concerns on 2nd Embodiment of this invention. It is a timing chart which shows operation | movement of the light-emitting device which concerns on 2nd Embodiment. It is a figure for demonstrating operation | movement of the light-emitting device in a writing period. It is a figure for demonstrating operation | movement of the light-emitting device in a transfer period. It is a figure for demonstrating operation | movement of the light-emitting device in a setting period. It is a figure which shows the specific form of the electronic device which concerns on this invention. It is a figure which shows the specific form of the electronic device which concerns on this invention.

<A: First Embodiment>
FIG. 1 is a perspective view showing a partial configuration of the image forming apparatus according to the first embodiment of the present invention. As shown in the figure, the image forming apparatus includes a light emitting device 10, a condensing lens array 11, a photosensitive drum (image carrier) 12 whose outer peripheral surface functions as an exposed surface (image forming surface) 14, and including. The light emitting device 10 includes a large number of light emitting elements (not shown in FIG. 1) arranged linearly on the surface of the substrate 13. These light emitting elements selectively emit light according to the form of an image to be printed on a recording material such as paper. The photosensitive drum 12 is supported by a rotation shaft extending in the X direction (main scanning direction), and rotates with the exposed surface 14 facing the light emitting device 10. Therefore, the exposed surface 14 advances in the Y direction (sub-scanning direction in which the recording material is conveyed) with respect to the light emitting device 10.

  The condensing lens array 11 is disposed in the gap between the light emitting device 10 and the photosensitive drum 12. The condensing lens array 11 includes a plurality of lenses that array each optical axis in the Z direction shown in FIG. An example of such a condensing lens array 11 is SLA (Selfoc Lens Array) available from Nippon Sheet Glass Co., Ltd. (Selfoc / SELFOC is a registered trademark of Nippon Sheet Glass Co., Ltd.). Light emitted from each light emitting element of the light emitting device 10 passes through each lens of the condensing lens array 11 and then reaches the exposed surface 14 of the photosensitive drum 12. By this exposure, a latent image (electrostatic latent image) corresponding to a desired image is formed on the exposed surface 14 of the photosensitive drum 12.

  FIG. 2 is a diagram schematically showing the arrangement of light emitting elements formed on the substrate 13 of the light emitting device 10. As shown in FIG. 2, the first element group G <b> 1 and the second element group G <b> 2 arranged in parallel in the sub-scanning direction Y are formed on the substrate 13. The first element group G1 includes n light emitting elements (E11, E12,..., E1n) arranged along the main scanning direction X. The second element group G2 includes n light emitting elements (E21, E22,..., E2n) arranged along the main scanning direction X. In the present embodiment, the light emitting element is an organic EL element in which a light emitting layer of an organic EL material is interposed between an anode and a cathode.

  The position in the X direction of each light emitting element belonging to the first element group G1 coincides with the position in the X direction of each light emitting element belonging to the second element group G2. For example, the position of the i-th (1 ≦ i ≦ n) light emitting element E1i in the first element group G1 in the X direction matches the position of the i-th light emitting element E2i in the second element group G2 in the X direction. That's it. Here, when two light emitting elements arranged at a predetermined interval in the Y direction are regarded as one pair T, each of the light emitting elements of the first element group G1 and the light emitting elements of the second element group G2 is configured. N pairs T are arranged along the X direction. The i-th pair T includes an i-th light emitting element E1i of the first element group G1 and an i-th light emitting element E2i of the second element group G2. In the following description, each of E11, E12,..., E1n is referred to as “first light emitting element”, and each of E21, E22,. Call it.

  FIG. 3 is a circuit diagram of the light emitting device 10. The light emitting device 10 includes n units U (U1, U2,..., Un) each including one pair T, and a control circuit 20 that controls each unit U (U1 to Un). The i-th unit Ui includes the i-th pair Ti. As shown in FIG. 3, for example, the unit U1 in the first stage is configured to include the first pair T1. The control circuit 20 is supplied with a data potential Vd having a magnitude corresponding to the image data from an external circuit (not shown). The control circuit 20 supplies (transfers) the data potential Vd supplied from the outside to each unit U (U1 to Un). Here, the data potential Vd supplied to the i-th unit Ui is denoted as Vd [i]. In the present embodiment, n data lines 23 corresponding to n units U (U1 to Un) are provided in a one-to-one correspondence, and the data lines 23 corresponding to the i-th unit Ui are connected to 23 [i]. Is written. The data potential Vd [i] is supplied to the i-th unit Ui via the corresponding data line 23 [i]. Further, the control circuit 20 supplies a write signal GWR, a transfer signal GTR, and a reset signal GINI to each unit U (U1 to Un). Here, the write signal GWR, the transfer signal GTR, and the reset signal GINI supplied to the i-th unit Ui are expressed as GWR [i], GTR [i], and GINI [i], respectively.

  As shown in FIG. 3, each unit U (U1 to Un) is provided between a high power supply line 21 to which a high power supply potential VEL is supplied and a low power supply line 22 to which a low power supply potential VCT is supplied. Placed in. Hereinafter, the configuration will be described focusing on the first-stage unit U1, but the configurations of the other units U2 to Un are also the same.

  As shown in FIG. 3, the unit U1 includes a first circuit X1 and a second circuit X2. The first circuit X1 includes a first light emitting element E11, a first drive transistor Td1, a first storage capacitor C1, and a writing transistor Tr_W. The first light emitting element E11 and the first drive transistor Td1 are arranged in series on a path connecting the high-potential power line 21 and the low-potential power line 22.

  The first drive transistor Td1 is a P-channel transistor (for example, a thin film transistor) having a source connected to the high-potential power supply line 21 and a drain connected to the anode of the first light emitting element E11. The first storage capacitor C1 is interposed between the gate and source of the first drive transistor Td1.

  The write transistor Tr_W is interposed between the gate of the first drive transistor Td1 and the data line 23 [1] and controls the electrical connection (conduction / non-conduction) between them. As shown in FIG. 3, for example, a P-channel transistor (for example, a thin film transistor) is suitably employed as the writing transistor Tr_W. A write signal GWR [1] from the control circuit 20 is supplied to the gate of the write transistor Tr_W. The write transistor Tr_W is controlled to be turned on / off according to the level of the write signal GWR [1].

  On the other hand, as shown in FIG. 3, the second circuit X2 includes a second light emitting element E21, a second drive transistor Td2, a second storage capacitor C2, a transfer transistor Tr_R, and a reset transistor Tr_IN. The second light emitting element E21 and the second drive transistor Td2 are arranged in series on a path connecting the high-potential power supply line 21 and the low-potential power supply line 22.

  The second drive transistor Td2 is a P-channel transistor (for example, a thin film transistor) having a source connected to the high-potential power line 21 and a drain connected to the anode of the second light emitting element E21. The second storage capacitor C2 is interposed between the gate and the source of the second drive transistor Td2. A reset transistor Tr_IN is provided between one electrode of the second storage capacitor C2 and the other electrode (between the gate and source of the second drive transistor Td2). As shown in FIG. 3, for example, a P-channel transistor (for example, a thin film transistor) is preferably employed as the reset transistor Tr_IN. A reset signal GINI [1] from the control circuit 20 is supplied to the gate of the reset transistor Tr_IN. The reset transistor Tr_IN is controlled to be turned on / off according to the level of the reset signal GINI [1].

  The transfer transistor Tr_R is interposed between the gate of the second drive transistor Td2 and the gate of the first drive transistor Td1 of the first circuit X1, and controls the electrical connection (conduction / non-conduction) between them. As shown in FIG. 3, for example, a P-channel transistor (thin film transistor) is preferably employed as the transfer transistor Tr_R. A transfer signal GTR [1] from the control circuit 20 is supplied to the gate of the transfer transistor Tr_R. On / off of the transfer transistor Tr_R is controlled according to the level of the transfer signal GTR [1].

  Based on the above configuration, the light emitting device 10 according to the present embodiment includes light emitted from the first light emitting elements (E11, E12,..., E1n) and second light emitting elements (E21, E22,. .., E2n) and the exposed surface 14 of the photosensitive drum 12 are double-exposed with the light emitted from the E2n), thereby forming an electrostatic latent image on the exposed surface 14.

  Assume that an electrostatic image SZ as shown in FIG. 4 is formed on the exposed surface 14. The electrostatic latent image SZ shown in FIG. 4 is formed from a first exposure area I1 and a second exposure area I2 arranged in parallel in the Y direction. Here, for convenience of explanation, an example in which the electrostatic latent image SZ is formed from two rows of exposure areas is taken as an example. In the first exposure region I1, n exposure dots (D11, D12,..., D1n) arranged along the X direction are formed. The i-th exposure dot D1i is the i-th light-emitting element (first light-emitting element) E1i of the first element group G1, and the i-th light-emitting element (second light-emitting element) of the second element group G2. ) Each of the emitted light beams E2i passes through the condensing lens array 11 and reaches the surface 14 to be exposed. In other words, the i-th exposure dot D1i is formed by double exposure with the emitted light from each of the first light-emitting element and the second light-emitting element constituting the i-th pair Ti. In the second exposure region I2, n exposure dots (D21, D22,..., D2n) arranged along the X direction are formed. The i-th exposure dot D2i is formed by double exposure with the emitted light of each of the first light-emitting element and the second light-emitting element constituting the i-th pair Ti. In this embodiment, each exposure dot is designated as a gradation (exposure amount) of black (light emission) or white (light extinction), and the gradation of the image is determined by the density of the number of white pixels and the number of black pixels. Is expressed (so-called area gradation method).

  One frame period F in which the electrostatic latent image SZ shown in FIG. 4 is formed includes three unit periods (T1, T2, T3) as shown in FIG. As shown in FIG. 6, in the first unit period T1, each light emitting element (first light emitting element) of the first element group G1 faces the first exposure region I1 of the exposed surface 14. The first exposure is performed when the light emitted from each light emitting element of the first element group G1 reaches the first exposure region I1. In the next second unit period T2, each light emitting element of the first element group G1 faces the second exposure region I2 of the exposed surface 14, and each light emitting element (second element) of the second element group G2. Light emitting element) is opposed to the first exposure region I1 of the exposed surface. The second exposure is performed by the light emitted from the light emitting elements of the second element group G2 reaching the first exposure area I1, while the first element group G1 is present in the second exposure area I2. The first exposure is performed when the emitted light from each of the light emitting elements reaches. In the next third unit period T3, each light emitting element of the second element group G2 faces the second exposure region I2 of the exposed surface 14. Then, the second exposure is performed by the light emitted from each light emitting element of the second element group G2 reaching the second exposure region I2. The distance in the Y direction between the first exposure area I1 and the second exposure area I2 is set so that the positional relationship between the light emitting device 10 and the photosensitive drum 12 and the light emission timing satisfy the above relationship.

  Hereinafter, a specific operation of the light emitting device 10 will be described by focusing on the first-stage unit U1. For convenience of explanation, it is assumed that the gradations of the exposure dots D11 and D21 formed by the first unit U1 are designated as “black”. Therefore, in the first unit period T1, the first light emitting element E11 emits light, and in the second unit period T2, both the first light emitting element E11 and the second light emitting element E21 emit light. In the third unit period T3, the second light emitting element E21 emits light. As shown in FIG. 6, in the third unit period T3, each light emitting element (first light emitting element) of the first element group G1 is placed in an area of the exposed surface 14 where the electrostatic latent image SZ is not formed. Therefore, in the unit period T3, the first light emitting element E11 does not emit light, and only the second light emitting element E21 emits light.

  As shown in FIG. 5, each unit period (T1, T2, T3) includes a writing period TW, an initialization period TIN after the writing period TW, and a transfer period TR immediately after the initialization period TIN. Including. In the write period TW in each of the three unit periods (T1 to T3), the control circuit 20 sets the data potential after making the gate of the first drive transistor Td1 and the gate of the second drive transistor Td2 nonconductive. Control is performed so that Vd [1] is supplied to the gate of the first drive transistor Td1. Further, the control circuit 20 initializes the gate potential of the second drive transistor Td2 in the initialization period TIN in each of the three unit periods (T1 to T3). Further, the control circuit 20 causes the gate of the first drive transistor Td1 and the gate of the second drive transistor Td2 to conduct in the transfer period TR in each of the three unit periods (T1 to T3), so that the first holding capacitor C1. The data potential Vd [1] held in is transferred to the second holding capacitor C2. The specific contents will be described below.

  The writing period TW within the unit period starts simultaneously with the start of each unit period (T1 to T3). As shown in FIG. 5, when the write period TW in the first unit period T1 starts, the control circuit 20 sets the write signal GWR [1] to the active level (low level) while transferring the transfer signal. GTR [1] and reset signal GINI [1] are set to an inactive level (high level). Therefore, as shown in FIG. 7, the write transistor Tr_W is set to an on state, and the transfer transistor Tr_R and the reset transistor Tr_IN are set to an off state. As shown in FIGS. 5 and 7, the control circuit 20 supplies a low level potential VL to the data line 23 [1] as the data potential Vd [1]. In the present embodiment, when the first light emitting element E11 is turned on, the data potential Vd [1] is set to the low level potential VL, and when the first light emitting element E11 is turned off, the data potential Vd [1] is High level potential VH is set. As described above, since the first light emitting element E1 emits light during the first unit period T1, the data potential Vd [1] is set to the low level potential VL here.

  At this time, as shown in FIG. 7, the gate of the first drive transistor Td1 is electrically connected to the data line 23 [1] via the on-state write transistor Tr_W, so that the potential of the gate of the first drive transistor Td1 Is set to a low level potential VL. In the present embodiment, the low-level potential VL is such that the potential difference between the potential VL and the higher power supply potential VEL (the voltage between the gate and source of the first drive transistor Td1) is the threshold voltage of the first drive transistor Td1. Since the value is set to be sufficiently higher, the first drive transistor Td1 is turned on. The first drive transistor Td1 that has transitioned to the on state generates a drive current Id1 corresponding to the gate potential, and the drive current Id1 flows through the first light emitting element E11. Thereby, the first light emitting element E11 emits light.

  As shown in FIG. 5, when the write period TW in the unit period T1 ends, the control circuit 20 sets the write signal GWR [1] to the inactive level (high level), so the write transistor Tr_W Is turned off. Other signals are maintained at the level in the writing period TW. Here, even when the write transistor Tr_W is turned off, the potential of the gate of the first drive transistor Td1 is maintained at the potential VL at the end point of the write period TW by the first storage capacitor C1, so that the first The aforementioned drive current Id1 continues to flow through one light emitting element E11. That is, the first light emitting element E11 continues to emit light during the period until the writing period TW in the next second unit period T2 starts. As described above, in the first unit period T1, each light emitting element of the first element group G1 faces the first exposure region I1 of the exposed surface 14 (see FIG. 6). Among them, the region where the exposure dot D11 is formed is such that the first exposure is performed when the emitted light from the first light emitting element E11 arrives. In addition, when the writing period TW in the unit period T1 ends, the control circuit 20 continues the data potential Vd [with respect to the data line 23 until the writing period TW in the next second unit period T2 starts. 1] is not supplied.

  When a predetermined period elapses after the writing period TW ends, the initialization period TIN starts. As shown in FIG. 5, when the initialization period TIN in the first unit period T1 starts, the control circuit 20 sets the write signal GWR [1] and the transfer signal GTR [1] to the high level, and sets the reset signal GIN. Set [1] to low level. Therefore, as shown in FIG. 8, the write transistor Tr_W and the transfer transistor Tr_R are set to an off state, while the reset transistor Tr_IN is set to an on state. As a result, one electrode and the other electrode of the second holding capacitor C2 are conducted through the reset transistor Tr_IN that is in the ON state, so that the second holding capacitor C2 is stored in the second holding capacitor C2 just before the start of the initialization period TIN. The charged charge is completely removed. As a result, the potential of the gate of the second drive transistor Td2 is initialized, and the second drive transistor Td2 is turned off. By resetting the charge of the second storage capacitor C2, regardless of the state of the second storage capacitor C2 (charge remaining in the second storage capacitor C2) at the start of the initialization period TIN, It becomes possible to set the potential of the gate of the second drive transistor Td2 to an expected value with high accuracy.

  When the initialization period TIN ends, the immediately subsequent transfer period TR starts. As shown in FIG. 5, when the transfer period TR in the first unit period T1 starts, the control circuit 20 sets the write signal GWR [1] and the reset signal GIN [1] to the high level and the transfer signal GTR [ 1] is set to low level. Therefore, as shown in FIG. 9, the write transistor Tr_W and the reset transistor Tr_IN are set to the off state, while the transfer transistor Tr_R is set to the on state. Thereby, the gate of the first drive transistor Td1 and the gate of the second drive transistor Td2 are conducted through the transfer transistor Tr_R in the on state. At this time, since the writing transistor Tr_W is turned off, the gate of the first driving transistor Td1 and the gate of the second driving transistor Td2 are in an electrically floating state, and the charge held in the first holding capacitor C1. Is distributed to the second storage capacitor C2. When the capacitance value of the first holding capacitor C1 is Ca and the capacitance value of the second holding capacitor C2 is Cb, the potential supplied (transferred) to the second holding capacitor C2 is Ca × VL / (Ca + Cb), and the second drive The potential of the gate of the transistor Td2 is set to the potential Ca × VL / (Ca + Cb). In the present embodiment, the low-level potential VL is the potential difference between the potential expressed by Ca × VL / (Ca + Cb) and the high-potential power supply potential VEL (the voltage between the gate and source of the second drive transistor Td2). Is set to a value that sufficiently exceeds the threshold voltage of the second drive transistor Td2, so that the second drive transistor Td2 is turned on. The second drive transistor Td2 transitioned to the ON state generates a drive current Id2 corresponding to the gate potential, and the drive current Id2 flows through the second light emitting element E21. As a result, the second light emitting element E21 emits light. When the above-described transfer period TR ends, the first unit period T1 ends.

  The writing period TW in the second unit period T2 starts immediately after the transfer period TR in the first unit period T1 ends (immediately after the first unit period T1 ends). The operation of the unit U1 in the writing period TW in the unit period T2 is the same as the operation in the writing period TW in the first unit period T1. As described above, in the second unit period T2, since the first light emitting element E11 emits light, as shown in FIG. 5, the control circuit 20 uses the low level potential VL as the data potential Vd [1]. Is supplied to the data line 23 [1]. As a result, the gate of the first drive transistor Td1 is set to the low-level potential VL, so that the drive current Id1 flows through the first light-emitting element E11 and the first light-emitting element E11 emits light. Note that, similarly to the first unit period T1, when the writing period TW in the unit period T2 ends, the control circuit 20 starts the writing period TW in the next third unit period T3. During this period, the data potential Vd [1] is not supplied to the data line 23.

  In addition, when the writing period TW in the second unit period T2 starts, the transfer transistor set to the on state in the immediately preceding transfer period TR (transfer period TR in the first unit period T1). Although Tr_R transitions to the off state, the potential of the gate of the second drive transistor Td2 is set to the potential (Ca × VL / (Ca + Cb) at the end point of the transfer period TR in the first unit period T1 by the second storage capacitor C2. )), The above-described drive current Id2 continues to flow through the second light emitting element E21. That is, the second light emitting element E21 continues to emit light until the initialization period TIN in the second unit period T2 starts.

  As described above, in the second unit period T2, each light emitting element of the first element group G1 faces the second exposure region I2 of the exposed surface 14, and each light emitting element of the second element group G2 Is opposed to the first exposure region I1 of the exposed surface 14 (see FIG. 6), so that the emitted light from the second light emitting element E21 is in the region of the exposed surface 14 where the exposure dots D11 are formed. The second exposure is performed by arriving, and the first exposure is performed by the light emitted from the first light emitting element E11 reaching the area of the exposed surface 14 where the exposure dots D21 are formed. It is done.

  The operation of the unit U1 in the initialization period TIN in the second unit period T2 is the same as the operation in the initialization period TIN in the first unit period T1, and is stored in the second storage capacitor C2. The electric charge is completely removed, and the potential of the gate of the second drive transistor Td2 is initialized. Since the second driving transistor Td2 is turned off, the second light emitting element E21 is turned off. In the present embodiment, the amount of exposure from the second light emitting element E21 is sufficient for the time length from the start point of the second unit period T2 to the start of the initialization period TIN in the second unit period T2. It is set to a value that can be secured.

  The operation of the unit U1 in the transfer period TR in the second unit period T2 is the same as the operation in the transfer period TR in the first unit period T1. During the transfer period TR in the unit period T2, the gate of the first drive transistor Td1 and the gate of the second drive transistor Td2 become conductive, so that the potential held in the first storage capacitor C1 becomes the second storage capacitor C2. And the gate potential of the second drive transistor Td2 is set to Ca × VL / (Ca + Cb). The second drive transistor Td2 generates a drive current Id2 corresponding to the gate potential, and the drive current Id2 flows through the second light emitting element E21. Thereby, the second light emitting element E21 emits light. When the above-described transfer period TR ends, the second unit period T2 ends.

  The writing period TW in the third unit period T3 starts immediately after the transfer period TR in the second unit period T2 ends (immediately after the second unit period T2 ends). The operation of the unit U1 in the writing period TW in the unit period T3 is the same as the operation in the writing period TW in each unit period described above. As described above, in the third unit period T3, the first light-emitting element E11 is turned off. As shown in FIG. 5, the control circuit 20 uses the high-level potential as the data potential Vd [1]. VH is supplied to the data line 23 [1].

  At this time, the gate of the first drive transistor Td1 is conducted to the data line 23 [1] via the on-state write transistor Tr_W, so that the potential of the gate of the first drive transistor Td1 becomes the high level potential VH. Is set. In the present embodiment, the high level potential VH is such that the potential difference between the potential VH and the higher power supply potential VEL (the voltage between the gate and source of the first drive transistor Td1) is the threshold voltage of the first drive transistor Td1. Since the value is set to be sufficiently lower, the first drive transistor Td1 is turned off. Accordingly, no current flows through the first light emitting element E11, and the first light emitting element E11 is turned off. Similarly to each unit period described above, when the writing period TW in the unit period T3 ends, the control circuit 20 continues until the writing period TW in the next unit period T starts. Is not supplied with the data potential Vd [1].

  Further, when the writing period TW in the third unit period T3 starts, the transfer transistor set to the on state in the immediately preceding transfer period TR (transfer period TR in the second unit period T2). Although Tr_R is turned off, the potential of the gate of the second drive transistor Td2 is set to the potential (Ca × VL / (Ca + Cb) at the end point of the transfer period TR in the second unit period T2 by the second storage capacitor C2. ), The above-described drive current Id2 continues to flow through the second light emitting element E21. That is, the second light emitting element E21 continues to emit light until the initialization period TIN in the third unit period T3 starts. As described above, in the third unit period T3, each light emitting element of the second element group G2 faces the second exposure region I2 of the exposed surface 14 (see FIG. 6). Among them, the second exposure is performed when the light emitted from the second light emitting element E21 reaches the region where the exposure dot D21 is formed.

  The operation of the unit U1 in the initialization period TIN in the third unit period T3 is the same as the operation in the initialization period TIN in each unit period described above, and the potential of the gate of the second drive transistor Td2 is initialized. Thus, the second light emitting element E21 is turned off. Similarly to each unit period described above, the time length from the start point of the third unit period T3 to the start of the initialization period TIN in the third unit period T3 is the second light emitting element E21. Is set to such a value that a sufficient amount of exposure can be secured.

  The operation of the unit U1 in the transfer period TR in the third unit period T3 is the same as the operation in the transfer period TR in each unit period described above. In the transfer period TR within the unit period T3, the gate of the first drive transistor Td1 and the gate of the second drive transistor Td2 are turned on, so that the potential held in the first hold capacitor C1 becomes the second hold capacitor C2. And the gate potential of the second drive transistor Td2 is set to Ca × VH / (Ca + Cb). In the present embodiment, the high-level potential VH is the potential difference between the potential expressed by Ca × VH / (Ca + Cb) and the high-potential power supply potential VEL (the voltage between the gate and the source of the second drive transistor Td2). However, since it is set to a value sufficiently lower than the threshold voltage of the second drive transistor Td2, the second drive transistor Td2 is turned off. Therefore, the second light emitting element E21 is maintained in the extinguished state following the immediately preceding initialization period TIN. When the above-described transfer period TR ends, the third unit period T3 ends and one frame period F ends. With the above operation, the electrostatic latent image SZ shown in FIG. 4 is formed on the exposed surface 14.

  Here, each of the signal for controlling the light emission of the first light emitting element and the signal for controlling the light emission of the second light emitting element is supplied by the control circuit 20 (hereinafter referred to as “proportional”. ”). FIG. 10 is a circuit diagram of the light-emitting device according to the comparative example. Paying attention to the unit U1 in the first stage, the second circuit X2 is different from the first embodiment in that the transfer transistor Tr_R is not provided but the second write transistor Tr_W2 is provided. As shown in FIG. 10, the P-channel type second write transistor Tr_W2 is provided between the gate of the second drive transistor Td2 and the data line 23 [1]. The second write signal GWR_2 [1] from the control circuit 20 is supplied to the gate of the second write transistor Tr_W2, and the second write transistor Tr_W2 is set to the level of the second write signal GWR_2 [1]. On / off is controlled accordingly. Other configurations are the same as those in the first embodiment.

  FIG. 11 is a timing chart for explaining a specific operation of the light-emitting device in proportion (corresponding to FIG. 5). As shown in FIG. 11, in each of the three unit periods (T1 to T3), a second writing period TW2 is set instead of the transfer period TR. Here, the time length of the second writing period TW2 is the same as the time length of the transfer period TR. The second write signal GWR_2 [1] is set to an active level (low level) in the second write period TW2 in each unit period (T1 to T3), and is inactive (high) in other periods. Level).

  The control circuit 20 controls to supply the data potential Vd [1] corresponding to the image data to the gate of the second drive transistor Td2 in the second writing period TW2 in each of the three unit periods (T1 to T3). To do. More specifically, it is as follows. As shown in FIG. 11, for example, in the second writing period TW2 in the first unit period T1, the control circuit 20 sets the second writing signal GWR_2 [1] to the low level and the writing signal GWR [1]. ] And reset signal GINI [1] are set to high level. Accordingly, the second writing transistor Tr_W2 is set to the on state, and the writing transistor Tr-W and the reset transistor Tr-IN are set to the off state. At this time, as shown in FIG. 11, the control circuit 20 supplies a low-level potential VL to the data line 23 [1] as the data potential Vd [1]. Since the gate of the second drive transistor Td2 is conducted to the data line 23 [1] via the second write transistor Tr_W2 in the on state, the potential of the gate of the second drive transistor Td2 is set to VL, and the second The drive transistor Td2 is turned on. The second drive transistor Td2 transitioned to the ON state generates a drive current Id2 corresponding to the gate potential, and the drive current Id2 flows through the second light emitting element E21. Thereby, the second light emitting element E21 emits light as in the first embodiment described above (see FIGS. 5 and 9). Note that the operation of the light emitting device in the writing period TW and the initialization period TIN in the first unit period T1 is the same as that in the first embodiment.

  In the second write period TW2 in the second unit period T2, the control circuit 20 sets the second write signal GWR_2 [1] to the low level, the write signal GWR [1], and the reset signal GINI [ 1] is set to the high level, while the low level potential VL is supplied to the data line 23 [1] as the data potential Vd [1]. Further, in the second write period TW2 in the third unit period T3, the control circuit 20 sets the second write signal GWR_2 [1] to the low level, the write signal GWR [1], and the reset signal GINI [ 1] is set to the high level, and the high level potential VH is supplied to the data line 23 [1] as the data potential Vd [1].

  As can be understood from FIG. 11, the control circuit 20 in the proportionality needs to supply the data potential Vd [1] to the data line 23 [1] twice in each unit period (T1 to T3). . On the other hand, the control circuit 20 according to the first embodiment described above makes the gate of the first drive transistor Td1 and the gate of the second drive transistor Td2 non-conductive in the writing period TW in each unit period. Then, the data potential Vd [1] is supplied to the gate of the first drive transistor Td1, and in the subsequent transfer period, the gate of the first drive transistor Td1 and the gate of the second drive transistor Td2 are made conductive. The data potential Vd [1] held in the first holding capacitor C1 is transferred to the second holding capacitor C2. That is, the control circuit 20 only supplies the data potential Vd [1] to the data line 23 [1] once in each unit period (T1 to T3), and the first light emitting element E11 and the second light emission. Since the light emission of each of the elements E21 can be controlled, as a result, the transfer rate of the data potential Vd [1] can be halved. Therefore, according to this embodiment, there is an advantage that an increase in the transfer rate of the data potential Vd [1] (light emission control signal) can be prevented.

<B: Second Embodiment>
FIG. 12 is a circuit diagram of the unit U1 in the first stage of the light emitting device according to the second embodiment of the present invention. Here, the first-stage unit U1 will be described as an example, but the configurations of the other units U2 to Un are the same as those of the first-stage unit U1. As shown in FIG. 12, the second circuit X2 in the unit U1 is different from the first embodiment described above in that it includes a first transistor Tr_R1 and a second transistor Tr_R2 instead of the transfer transistor Tr_R and the reset transistor Tr_IN. To do. Other configurations are the same as those of the first embodiment.

  As shown in FIG. 12, the second storage capacitor C2 has a first electrode L1 and a second electrode L2, and the second electrode L2 is connected to the source of the second drive transistor Td2. A P-channel first transistor Tr_R1 for switching between conduction and non-conduction between the first electrode L1 and the gate of the first drive transistor Td1 of the first circuit X1 is provided. The first control signal GTR_1 [1] from the control circuit 20 is supplied to the gate of the first transistor Tr_R1. Here, the first control signal supplied to the i-th unit Ui is denoted as GTR_1 [i]. The first transistor Tr_R1 is controlled to be turned on / off according to the level of the first control signal GTR_1 [1]. Further, a second transistor Tr_R2 for switching between conduction and non-conduction between the first electrode L1 and the gate of the second drive transistor Td2 is provided. The second control signal GTR_2 [1] from the control circuit 20 is supplied to the gate of the second transistor Tr_R2. Here, the second control signal supplied to the i-th unit Ui is denoted as GTR_2 [i]. The second transistor Tr_R2 is controlled to be turned on / off according to the level of the second control signal GTR_2 [1].

  FIG. 13 is a timing chart for explaining a specific operation of the light emitting device according to the second embodiment (corresponding to FIG. 5). As shown in FIG. 13, each of the three unit periods (T1 to T3) is divided into a write period TW, a transfer period TR immediately after the write period TW, and a set period TS immediately after the transfer period TR. Is done. The time length of the transfer period TR is set to a value sufficiently longer than the time lengths of the writing period TW and the setting period TS.

  Now, focusing on the first unit period T1, the operation of the unit U1 will be described. In addition, about the part which overlaps with the above-mentioned 1st Embodiment, description is abbreviate | omitted suitably. As shown in FIG. 13, when the write period TW in the unit period T1 starts, the control circuit 20 sets the write signal GWR [1] to the low level, while the first control signal GTR_1 [1] and the first 2. Set the control signal GTR_2 [1] to high level. Therefore, as shown in FIG. 14, the writing transistor Tr_W is set to an on state, and the first transistor Tr_R1 and the second transistor Tr_R2 are set to an off state. As shown in FIGS. 13 and 14, the control circuit 20 supplies a low-level potential VL to the data line 23 [1] as the data potential Vd [1]. As a result, the gate of the first drive transistor Td1 is set to the low-level potential VL, so that the drive current Id1 flows through the first light-emitting element E11 and the first light-emitting element E11 emits light. Similar to the first embodiment described above, the first light emitting element E11 continues to emit light until the writing period TW in the next second unit period T2 starts.

  Next, when the transfer period TR within the unit period T1 starts, as shown in FIG. 13, the control circuit 20 sets the first control signal GTR_1 [1] to the low level, while the write signal GWR [1]. The second control signal GTR_2 [1] is set to the high level. Therefore, as shown in FIG. 15, the first transistor Tr_R1 is set to an on state, and the write transistor Tr_W and the second transistor Tr_R2 are set to an off state. As a result, the gate of the first drive transistor Td1 and the first electrode L1 are conducted through the first transistor Tr_R1 in the on state. At this time, since the writing transistor Tr_W is maintained in the off state, the gate of the first driving transistor Td1 and the gate of the second driving transistor Td2 are in an electrically floating state and are held in the first holding capacitor C1. The charged charges are distributed to the second holding capacitor C2. At this time, the potential supplied (transferred) to the second storage capacitor C2 is Ca × VL / (Ca + Cb).

  Next, when the set period TS in the unit period T1 starts, as shown in FIG. 13, the control circuit 20 sets the second control signal GTR_2 [1] to the low level, while the write signal GWR [1]. The first control signal GTR_1 [1] is set to the high level. Accordingly, as shown in FIG. 16, the second transistor Tr_R2 is set to an on state, and the write transistor Tr_W and the first transistor Tr_R1 are set to an off state. As a result, the first electrode L1 and the gate of the second drive transistor Td2 are conducted through the second transistor Tr_R2 in the on state, and the potential of the gate of the second drive transistor Td2 is transferred to the second storage capacitor C2. Since the potential Ca × VL / (Ca + Cb) is set, the drive current Id2 flows through the second light emitting element E21. Therefore, the second light emitting element E21 emits light. The operation of the unit U1 described above is the same in other unit periods (T2, T3).

  Also in the second embodiment, the control circuit 20 simply supplies the data potential Vd [1] to the data line 23 [1] once in each unit period (T1 to T3), and the first light emitting element E11. Since the light emission of each of the second light emitting elements E21 can be controlled, there is an advantage that an increase in the transfer rate of the data potential Vd [1] (light emission control signal) can be prevented. Further, the control circuit 20 according to the second embodiment is held in the first holding capacitor C1 in the transfer period TR in a state where the gate of the first drive transistor Td1 and the gate of the second drive transistor Td2 are made non-conductive. Since the data potential Vd [1] being transferred is transferred to the second holding capacitor C2, the voltage value of the second holding capacitor C2 is quickly desired by the amount that is hardly affected by the capacitance parasitic on the gate of the second drive transistor Td2. Has the advantage of reaching the value of.

<C: Modification>
The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible. Also, two or more of the modifications shown below can be combined.

(1) Modification 1
In the first embodiment described above, the reset transistor Tr_IN is provided in the second circuit X2. However, the present invention is not limited to this. For example, the second circuit X2 may be provided with no reset transistor Tr_IN. Is possible.

(2) Modification 2
The conductivity types of the various transistors included in each unit U1 to Un are arbitrary. In the above-described embodiment, the various transistors included in the units U1 to Un are all configured by P-channel transistors. However, the present invention is not limited to this, and for example, all of the various transistors included in the units U1 to Un are N. It may be a channel type. Further, for example, some of the various transistors included in each of the units U1 to Un may be configured as a P-channel type, and the other transistors may be configured as an N-channel type.

(3) Modification 3
In the light emitting device according to each of the embodiments described above, the double exposure method is adopted, but not limited to this, for example, a triple exposure method or a quadruple exposure method may be adopted. In short, any method may be used as long as the emitted light from each of the first and second light emitting elements is irradiated onto the same exposed surface at different timings.

(4) Modification 4
The number of rows of the electrostatic latent image SZ formed on the exposed surface 14 is arbitrary. In other words, the number of exposure dot groups constituting the electrostatic latent image SZ is arbitrary. For example, four or more exposure dot groups may be arranged in parallel along the Y direction. Further, the number of exposure dots included in the exposure dot group (that is, the number of light emitting elements belonging to one element group) is also arbitrary.

(5) Modification 5
In each of the embodiments described above, an OLED element is taken up as an example of a light emitting element, but an inorganic light emitting diode or LED (Light Emitting Diode) may be used. In short, any element may be used as long as it emits light with light emission luminance corresponding to the drive current.

<D: Electronic equipment>
Next, with reference to FIG. 17, an image forming apparatus which is one aspect of the electronic apparatus according to the invention will be described. This image forming apparatus is a tandem type full color image forming apparatus using a belt intermediate transfer body system.

  In this image forming apparatus, four light emitting devices 10K, 10C, 10M, and 10Y each having the same configuration are provided with four photosensitive drums (image carriers) 110K, 110C, and 110M having the same configuration. , 110Y are arranged at positions facing the image forming surface 110. The light emitting devices 10K, 10C, 10M, and 10Y have the same configuration as the light emitting device 10 according to each of the above embodiments.

  As shown in FIG. 17, this image forming apparatus is provided with a driving roller 121 and a driven roller 122. An endless intermediate transfer belt 120 is wound around these rollers 121 and 122, and an arrow indicates. As shown, the periphery of the rollers 121 and 122 is rotated. Although not shown, tension applying means such as a tension roller that applies tension to the intermediate transfer belt 120 may be provided.

  Around the intermediate transfer belt 120, four photosensitive drums 110K, 110C, 110M, and 110Y each having a photosensitive layer on the outer peripheral surface are arranged at a predetermined interval. The subscripts “K”, “C”, “M”, and “Y” mean that they are used to form black, cyan, magenta, and yellow visible images, respectively. The same applies to other members. The photosensitive drums 110K, 110C, 110M, and 110Y are rotationally driven in synchronization with the driving of the intermediate transfer belt 120.

  Around each photosensitive drum 110 (K, C, M, Y), there is a corona charger 111 (K, C, M, Y), a light emitting device 10 (K, C, M, Y), and a developing unit. 114 (K, C, M, Y) are arranged. The corona charger 111 (K, C, M, Y) uniformly charges the image forming surface 110A (outer peripheral surface) of the corresponding photosensitive drum 110 (K, C, M, Y). The light emitting device 10 (K, C, M, Y) writes an electrostatic latent image on the charged image forming surface 110A of each photosensitive drum. In each light emitting device 10 (K, C, M, Y), a plurality of light emitting elements are arranged along the bus (main scanning direction) of the photosensitive drum 110 (K, C, M, Y). The electrostatic latent image is written by irradiating the photosensitive drum 110 (K, C, M, Y) with light by a plurality of light emitting elements. The developing device 114 (K, C, M, Y) attaches toner as a developer to the electrostatic latent image to thereby develop a visible image (that is, a visible image) on the photosensitive drum 110 (K, C, M, Y). ).

  The black, cyan, magenta, and yellow developed images formed by the four-color single-color image forming station are superimposed on the intermediate transfer belt 120 by sequentially being sequentially transferred onto the intermediate transfer belt 120. As a result, a full-color visible image is formed. Four primary transfer corotrons (transfer devices) 112 (K, C, M, Y) are arranged inside the intermediate transfer belt 120. The primary transfer corotron 112 (K, C, M, Y) is disposed in the vicinity of the photosensitive drum 110 (K, C, M, Y), and the photosensitive drum 110 (K, C, M, Y). The electrostatic image is electrostatically attracted from the toner image to transfer the visible image to the intermediate transfer belt 120 passing between the photosensitive drum and the primary transfer corotron.

  A sheet 102 as an object (recording material) on which an image is to be finally formed is fed one by one from the sheet feeding cassette 101 by the pickup roller 103 and is subjected to secondary transfer with the intermediate transfer belt 120 in contact with the driving roller 121. Sent to the nip between the rollers 126. The full-color visible image on the intermediate transfer belt 120 is secondarily transferred to one side of the sheet 102 by the secondary transfer roller 126 and fixed on the sheet 102 through the fixing roller pair 127 as a fixing unit. . Thereafter, the sheet 102 is discharged onto a paper discharge cassette formed in the upper part of the apparatus by a paper discharge roller pair 128.

  Next, another embodiment of the image forming apparatus according to the present invention will be described with reference to FIG. This image forming apparatus is a rotary developing type full-color image forming apparatus using a belt intermediate transfer body system. As shown in FIG. 14, a corona charger 168, a rotary developing unit 161, the light emitting device 10 according to the above embodiment, and an intermediate transfer belt 169 are provided around the photosensitive drum 110. Yes.

  The corona charger 168 uniformly charges the outer peripheral surface of the photosensitive drum 110. The light emitting device 10 writes an electrostatic latent image on the charged image forming surface (outer peripheral surface) of the photosensitive drum 110. In the light emitting device 10, a plurality of light emitting elements are arranged along the bus (main scanning direction) of the photosensitive drum 110. The electrostatic latent image is written by irradiating the photosensitive drum 110 with light from these light emitting elements.

  The developing unit 161 is a drum in which four developing units 163Y, 163C, 163M, and 163K are arranged at an angular interval of 90 °, and can rotate counterclockwise about the shaft 161a. The developing units 163Y, 163C, 163M, and 163K supply yellow, cyan, magenta, and black toner to the photosensitive drum 110, respectively, and attach the toner as a developer to the electrostatic latent image, thereby causing the photosensitive drum 110 to adhere. A visible image (ie, a visible image) is formed.

  The endless intermediate transfer belt 169 is wound around a driving roller 170a, a driven roller 170b, a primary transfer roller 166, and a tension roller, and is rotated around these rollers in a direction indicated by an arrow. The primary transfer roller 166 transfers the visible image to the intermediate transfer belt 169 that passes between the photosensitive drum 110 and the primary transfer roller 166 by electrostatically attracting the visible image from the photosensitive drum 110.

  Specifically, in the first rotation of the photosensitive drum 110, an electrostatic latent image for a yellow (Y) image is written by the light emitting device 10, and a developed image of the same color is formed by the developing device 163Y. The image is transferred to the transfer belt 169. Further, in the next rotation, the electrostatic latent image for the cyan (C) image is written by the light emitting device 10A, and a developed image of the same color is formed by the developing device 163C, and the intermediate transfer is performed so as to overlap the yellow developed image. Transferred to the belt 169. Then, during the four rotations of the photosensitive drum 110 in this manner, the yellow, cyan, magenta, and black visible images are sequentially superimposed on the intermediate transfer belt 169, and as a result, a full-color visible image is formed on the transfer belt 169. Formed on top. When images are finally formed on both sides of a sheet as an object on which an image is to be formed, the same color images of the front and back surfaces are transferred to the intermediate transfer belt 169, and then the front and back surfaces are transferred to the intermediate transfer belt 169. A full-color visible image is formed on the intermediate transfer belt 169 in such a manner that the visible image of the next color is transferred.

  The image forming apparatus is provided with a sheet conveyance path 174 through which a sheet passes. The sheets are picked up one by one from the paper feed cassette 178 by the pick-up roller 179, advanced through the sheet transport path 174 by the transport roller, and between the intermediate transfer belt 169 and the secondary transfer roller 171 in contact with the drive roller 170a. Pass through the nip. The secondary transfer roller 171 transfers the developed image to one side of the sheet by electrostatically attracting a full-color developed image from the intermediate transfer belt 169 collectively. The secondary transfer roller 171 can be moved closer to and away from the intermediate transfer belt 169 by a clutch (not shown). The secondary transfer roller 171 is brought into contact with the intermediate transfer belt 169 when a full-color visible image is transferred onto the sheet, and is separated from the secondary transfer roller 171 while the visible image is superimposed on the intermediate transfer belt 169.

  The sheet on which the image has been transferred as described above is conveyed to the fixing device 172 and is passed between the heating roller 172a and the pressure roller 172b of the fixing device 172, whereby the visible image on the sheet is fixed. The sheet after the fixing process is drawn into the discharge roller pair 176 and proceeds in the direction of arrow F. In the case of double-sided printing, after most of the sheet passes through the paper discharge roller pair 176, the paper discharge roller pair 176 is rotated in the reverse direction and introduced into the double-sided printing conveyance path 175 as indicated by an arrow G. The Then, the visible image is transferred to the other surface of the sheet by the secondary transfer roller 171, the fixing process is performed again by the fixing device 172, and then the sheet is discharged by the discharge roller pair 176.

  Since the image forming apparatus illustrated in FIGS. 17 and 18 uses a light source (exposure means) that employs an OLED element as a light emitting element, the apparatus is made smaller than when a laser scanning optical system is used. Note that the light-emitting device 10 of the present invention can also be employed in electrophotographic image forming apparatuses other than those exemplified above. For example, the light emitting device according to the present invention is also applied to an image forming apparatus that directly transfers a visible image from a photosensitive drum to a sheet without using an intermediate transfer belt, and an image forming apparatus that forms a monochrome image 10 can be applied.

  The use of the light emitting device according to the present invention is not limited to exposure of a photoreceptor. For example, the light emitting device of the present invention is employed in an image reading device such as a scanner as a line type optical head (illumination device) that irradiates a reading target such as an original with light. As this type of image reading apparatus, there is a scanner, a copying machine or a reading part of a facsimile, a barcode reader, or a two-dimensional image code reader for reading a two-dimensional image code such as a QR code (registered trademark).

DESCRIPTION OF SYMBOLS 10 ... Light-emitting device, 11 ... Condensing lens array, 12 ... Photosensitive drum, 13 ... Substrate, 14 ... Exposed surface, 20 ... Control circuit, 23 ... Data line, C1 ... No. 1 holding capacitor, C2 ... second holding capacitor, G1 ... first element group, G2 ... second element group, GWR ... write signal, GTR ... transfer signal, GIN ... reset signal, GI1 ... 1st exposure area, I2 ... 2nd exposure area, E ... Light emitting element, SZ ... Electrostatic latent image, Td1 ... 1st drive transistor, Td2 ... 2nd drive transistor, Tr_W ... Writing Transistor, Tr_R: Transfer transistor, Tr_IN: Reset transistor, T: Pair, U: Unit, Vd: Data potential, X1: First circuit, X2: Second circuit

Claims (6)

First and second light emitting elements;
First and second drive transistors, each of which outputs a drive current according to a gate potential;
A first holding capacitor for holding the potential of the gate of the first driving transistor;
A second holding capacitor for holding the potential of the gate of the second driving transistor;
A first switching element provided between a gate of the first driving transistor and a data line, for switching between conduction and non-conduction between the gate of the first driving transistor and the data line;
Second switching is provided between the gate of the second driving transistor and the gate of the first driving transistor, and switches between conduction and non-conduction between the gate of the second driving transistor and the gate of the first driving transistor. Elements,
In the writing period, the first switching element is set to an on state and the second switching element is set to an off state, and a data potential corresponding to image data is supplied to the data line,
A control unit that sets the first switching element to an off state and the second switching element to an on state in a transfer period after the writing period;
A light emitting device characterized by that. A reset transistor for switching between conduction and non-conduction between one electrode of the second storage capacitor and the other electrode;
The controller is
The second switching element is turned off and the reset transistor is turned on in an initialization period immediately after the writing period and immediately before the transfer period.
The light-emitting device according to claim 1. First and second light emitting elements;
First and second drive transistors, each of which outputs a drive current according to a gate potential;
A first holding capacitor for holding the potential of the gate of the first driving transistor;
A second storage capacitor having a first electrode and a second electrode connected to a source of the second drive transistor, for holding a gate potential of the second drive transistor;
A first switching element provided between a gate of the first driving transistor and a data line, for switching between conduction and non-conduction between the gate of the first driving transistor and the data line;
A second switching element provided between the gate of the first drive transistor and the first electrode, for switching between conduction and non-conduction between the gate of the first drive transistor and the first electrode;
A third switching element provided between the gate of the second drive transistor and the first electrode for switching between conduction and non-conduction between the gate of the second drive transistor and the first electrode;
In the first writing period, the first switching element is turned on, the second switching element and the third switching element are turned off, and a data potential corresponding to image data is supplied to the data line,
In the transfer period after the first writing period, the first switching element and the third switching element are set in an off state, and the second switching element is set in an on state.
A control unit configured to set the first switching element and the second switching element to an off state and set the third switching element to an on state in a setting period after the transfer period;
A light emitting device characterized by that. The emitted light from each of the first and second light emitting elements is irradiated to the same exposed surface at different timings.
The light-emitting device according to claim 1, wherein the light-emitting device is a light-emitting device.   An electronic apparatus comprising the light-emitting device according to claim 1. First and second light emitting elements, first and second driving transistors that each output a driving current in accordance with a gate potential, and a first holding capacitor for holding the potential of the gate of the first driving transistor And a second storage capacitor for holding the potential of the gate of the second drive transistor, and a driving method of a light emitting device comprising:
In the writing period, the gate of the first drive transistor and the gate of the second drive transistor are made non-conductive, and then a data potential corresponding to image data is supplied to the gate of the first drive transistor,
In a transfer period after the writing period, the gate of the first driving transistor and the gate of the second driving transistor are made conductive, and the data potential held in the first holding capacitor is held in the second holding capacity. Transfer to capacity,
A driving method characterized by that.

Images