JP2011171488A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2011171488A
JP2011171488A JP2010033500A JP2010033500A JP2011171488A JP 2011171488 A JP2011171488 A JP 2011171488A JP 2010033500 A JP2010033500 A JP 2010033500A JP 2010033500 A JP2010033500 A JP 2010033500A JP 2011171488 A JP2011171488 A JP 2011171488A
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chip
semiconductor
mounting substrate
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semiconductor device
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Keizo Goto
敬造 後藤
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Renesas Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract

<P>PROBLEM TO BE SOLVED: To downsize the whole of a semiconductor device by reducing the area of a semiconductor IC chip, in a semiconductor device where a semiconductor integrated circuit (IC) chip and a semiconductor chip component are mounted on a mounting board. <P>SOLUTION: This semiconductor device 1 is composed by mounting a semiconductor IC chip 20 and a semiconductor chip component 30 electrically connected to the semiconductor IC chip 20 on a mounting board 10, wherein the semiconductor IC chip 20 is mounted in a recessed part 13 formed on the mounting board 10 and opened on a first board surface 11 of the mounting board 10; and the semiconductor chip component 30 is mounted straddling between a surface 22 of the semiconductor IC chip 20 on the first board surface side and the first board surface 11 of the mounting board 10. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、実装基板にＩＣチップ及びチップ部品が実装された半導体装置に関するものである。   The present invention relates to a semiconductor device in which an IC chip and a chip component are mounted on a mounting substrate.

半導体装置として、実装基板（モジュール基板）に半導体集積回路チップ（ＩＣチップ）とチップコンデンサ等の半導体チップ部品とが実装されたＭＣＭ(Multi Chip Module)が知られ、マイクロ波を用いた通信用途などに利用されている。ＭＣＭが搭載される各種電子機器の小型化・高機能化に伴って、ＭＣＭ自体についてもより一層の小型化及び高集積化が求められている。例えば、今後は、多機能の回路構成を１つのＭＣＭに盛り込んで高集積化したＦＥＭ(Front End Module)が主流になってくると考えられる。   As a semiconductor device, an MCM (Multi Chip Module) in which a semiconductor integrated circuit chip (IC chip) and a semiconductor chip component such as a chip capacitor are mounted on a mounting substrate (module substrate) is known. Has been used. Along with the downsizing and high functionality of various electronic devices in which the MCM is mounted, the MCM itself is required to be further downsized and highly integrated. For example, in the future, it is considered that FEM (Front End Module) in which a multi-functional circuit configuration is incorporated in one MCM and highly integrated will become mainstream.

ＭＣＭとしては、特許文献１に、実装基板（２）にフリップチップ実装されたＩＣチップ（４）の裏面にチップコンデンサ（６）を搭載した半導体装置が記載されている（図３及び図４を参照）。この半導体装置では、チップコンデンサ（６）は、ＩＣチップ（４）内に開孔された複数のビアホール（１０）を介してＩＣチップ（４）の表面に設けられた導電パッド（１２）と接続されている。
本発明の関連技術として特許文献２〜４が挙げられるが、詳細については後述する。 As an MCM, Patent Document 1 describes a semiconductor device in which a chip capacitor (6) is mounted on the back surface of an IC chip (4) flip-chip mounted on a mounting substrate (2) (see FIGS. 3 and 4). reference). In this semiconductor device, the chip capacitor (6) is connected to a conductive pad (12) provided on the surface of the IC chip (4) through a plurality of via holes (10) opened in the IC chip (4). Has been.
Patent Documents 2 to 4 can be cited as related techniques of the present invention, and details will be described later.

特開2002-184933号公報JP 2002-184933 A 特開2009-094319号公報JP 2009-094319 特開平08-148800号公報Japanese Unexamined Patent Publication No. 08-148800 特開2001-007352号公報JP 2001-007352 JP

特許文献１に記載の上記半導体装置において、例えば図４に示すような回路を実現しようとすると、図３のような回路構造になる。図中、ＦＥＴは電界効果トランジスタ、Ｃはチップコンデンサ、ＧＮＤはグランド、ＨＸは実装基板内のビアホール、ＨＹはＩＣチップ内のビアホールを各々示す。
特許文献１に記載の半導体装置では、チップコンデンサを実装基板に電気的に接続するために、ＩＣチップ内に複数のビアホールＨＹが必要であり、ＩＣチップの小面積化が難しく、半導体装置全体を小型化することが難しい。 In the semiconductor device described in Patent Document 1, for example, when a circuit as shown in FIG. 4 is to be realized, a circuit structure as shown in FIG. 3 is obtained. In the figure, FET is a field effect transistor, C is a chip capacitor, GND is ground, HX is a via hole in the mounting substrate, and HY is a via hole in the IC chip.
In the semiconductor device described in Patent Document 1, in order to electrically connect the chip capacitor to the mounting substrate, a plurality of via holes HY are necessary in the IC chip, and it is difficult to reduce the area of the IC chip. It is difficult to downsize.

本発明の半導体装置は、
実装基板に半導体集積回路チップ（半導体ＩＣチップ）と当該半導体集積回路チップに電気的に接続される半導体チップ部品とが実装されたものであり、
前記半導体集積回路チップは、前記実装基板に形成され、当該実装基板の第１の基板面において開口した凹部内に実装されており、
前記半導体チップ部品は、前記半導体集積回路チップの前記第１の基板面側の面と前記実装基板の前記第１の基板面とに跨って実装されたものである。 The semiconductor device of the present invention is
A semiconductor integrated circuit chip (semiconductor IC chip) and a semiconductor chip component electrically connected to the semiconductor integrated circuit chip are mounted on a mounting substrate,
The semiconductor integrated circuit chip is formed in the mounting substrate, and is mounted in a recess opened in the first substrate surface of the mounting substrate.
The semiconductor chip component is mounted across the first substrate surface side of the semiconductor integrated circuit chip and the first substrate surface of the mounting substrate.

本発明の半導体装置においては、半導体ＩＣチップが実装基板に形成された凹部内に実装され、半導体チップ部品が半導体集積回路チップと実装基板とに跨って実装されているので、半導体チップ部品を実装基板に電気的に接続するために、半導体ＩＣチップ内に１つのビアホール等の開孔導電部を設ければよく、半導体ＩＣチップの小面積化が可能であり、半導体装置全体を小型化することができる（図１及び図２を参照）。   In the semiconductor device of the present invention, the semiconductor IC chip is mounted in the recess formed on the mounting substrate, and the semiconductor chip component is mounted across the semiconductor integrated circuit chip and the mounting substrate. In order to be electrically connected to the substrate, it is only necessary to provide an opening conductive portion such as one via hole in the semiconductor IC chip, the area of the semiconductor IC chip can be reduced, and the entire semiconductor device can be reduced in size. (See FIGS. 1 and 2).

本発明によれば、実装基板に半導体集積回路チップ（半導体ＩＣチップ）及び半導体チップ部品が実装された半導体装置において、半導体ＩＣチップの小面積化が可能であり、半導体装置全体を小型化することが可能となる。   According to the present invention, in a semiconductor device in which a semiconductor integrated circuit chip (semiconductor IC chip) and a semiconductor chip component are mounted on a mounting substrate, the area of the semiconductor IC chip can be reduced, and the entire semiconductor device can be reduced in size. Is possible.

本発明に係る一実施形態の半導体装置の断面図である。It is sectional drawing of the semiconductor device of one Embodiment which concerns on this invention. 図１の半導体装置の等価回路図の例である。FIG. 2 is an example of an equivalent circuit diagram of the semiconductor device of FIG. 1. 特許文献１に記載の半導体装置の等価回路図の例である。10 is an example of an equivalent circuit diagram of a semiconductor device described in Patent Document 1. FIG. 等価回路図の例である。It is an example of an equivalent circuit diagram.

図面を参照して、本発明に係る一実施形態の半導体装置の構成について説明する。図１は本実施形態の半導体装置の概略断面図、図２は等価回路図の例である。図面上は視認しやすくするため、各部材の縮尺や位置は適宜、実際のものとは異ならせてある。   A configuration of a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view of the semiconductor device of this embodiment, and FIG. 2 is an example of an equivalent circuit diagram. In order to facilitate visual recognition on the drawings, the scale and position of each member are appropriately different from the actual ones.

本実施形態の半導体装置１は、実装基板（モジュール基板）１０に半導体集積回路チップ（半導体ＩＣチップ）２０と半導体チップ部品３０とが実装されたＭＣＭ(Multi Chip Module)である。半導体チップ部品３０としては、チップコンデンサ等が挙げられる。
本実施形態において、実装基板１０は、第１の基板面（図示上面）１１において開口し、内部にＩＣチップ２０が実装される凹部（キャビティ）１３が形成されたＣＩＢ（Chip In Board）構造の基板である。 The semiconductor device 1 of this embodiment is an MCM (Multi Chip Module) in which a semiconductor integrated circuit chip (semiconductor IC chip) 20 and a semiconductor chip component 30 are mounted on a mounting substrate (module substrate) 10. Examples of the semiconductor chip component 30 include a chip capacitor.
In the present embodiment, the mounting substrate 10 has a CIB (Chip In Board) structure in which an opening is formed on a first substrate surface (upper surface in the drawing) 11 and a recess (cavity) 13 in which the IC chip 20 is mounted is formed. It is a substrate.

ＩＣチップ２０は、実装基板１０の凹部１３内に、フリップチップ実装されている。ＩＣチップ２０において、凹部１３の底面１３Ｂ側の面（図示下面）を「ＩＣチップ２０の表面２１」、実装基板１０の第１の基板面１１側の面（図示上面）を「ＩＣチップ２０の裏面２２」と定義する。
実装基板１０において、凹部１３は、凹部１３内に実装されたＩＣチップ２０の裏面２２と実装基板１０の第１の基板面１１とが略面一となる深さで形成されている。
本実施形態において、チップ部品３０は、ＩＣチップ２０の裏面２２と実装基板１０の第１の基板面１１とに跨って実装されている。 The IC chip 20 is flip-chip mounted in the recess 13 of the mounting substrate 10. In the IC chip 20, the surface on the bottom surface 13 </ b> B side (the lower surface in the drawing) of the recess 13 is “the surface 21 of the IC chip 20”, and the surface on the first substrate surface 11 side (the upper surface in the drawing) of the mounting substrate 10 is “ It is defined as “Back 22”.
In the mounting substrate 10, the recess 13 is formed with a depth at which the back surface 22 of the IC chip 20 mounted in the recess 13 and the first substrate surface 11 of the mounting substrate 10 are substantially flush with each other.
In the present embodiment, the chip component 30 is mounted across the back surface 22 of the IC chip 20 and the first substrate surface 11 of the mounting substrate 10.

実装基板１０において、第２の基板面（図示下面）１２には金メッキ等によりグランド電極パターン（ＧＮＤパターン、導電部）１４が形成され、第１の基板面１１の凹部１３に隣接する領域にはチップ部品３０を実装基板１０に実装するための導電パッド１５が形成されている。   In the mounting substrate 10, a ground electrode pattern (GND pattern, conductive portion) 14 is formed on the second substrate surface (lower surface in the drawing) 12 by gold plating or the like, and in a region adjacent to the recess 13 on the first substrate surface 11. Conductive pads 15 for mounting the chip component 30 on the mounting substrate 10 are formed.

実装基板１０内には、凹部１３の底面１３Ｂから実装基板１０の第２の基板面１２との間に開孔され、内部に導電材料が充填された１つのビアホール（開孔導電部）１６が形成されている。実装基板１０内にはまた、第１の基板面１１に形成された導電パッド１５と第２の基板面１２に形成されたＧＮＤパターン１４との間に開孔され、内部に導電材料が充填された１つのビアホール（開孔導電部）１７が形成されている。   In the mounting substrate 10, one via hole (opening conductive portion) 16 is formed between the bottom surface 13 </ b> B of the recess 13 and the second substrate surface 12 of the mounting substrate 10 and filled with a conductive material. Is formed. The mounting substrate 10 is also opened between the conductive pads 15 formed on the first substrate surface 11 and the GND pattern 14 formed on the second substrate surface 12, and is filled with a conductive material. A single via hole (opening conductive portion) 17 is formed.

ＩＣチップ２０において、その表面２１にはＩＣチップ２０を実装基板１０に実装するための導電パッド２３、２４が形成され、裏面２２にはチップ部品３０をＩＣチップ２０に実装するための導電パッド２５が形成されている。
ＩＣチップ２０内には、一端が導電パッド２５に接続され、ＩＣチップ２０を貫通して開孔され、内部に導電材料が充填された１つのビアホール（開孔導電部）２６が形成されている。
ＩＣチップ２０の表面２１に設けられた導電パッド２３、２４が、実装基板１０の凹部１３の底面１３Ｂに対して半田等の導電材４１を介して接続されている。ＩＣチップ２０の表面２１に形成された導電パッド２３、２４のうち一方の導電パッド２４は、導電材４１を介して実装基板１０に形成されたビアホール１６に接続されている。 In the IC chip 20, conductive pads 23 and 24 for mounting the IC chip 20 on the mounting substrate 10 are formed on the front surface 21, and conductive pads 25 for mounting the chip component 30 on the IC chip 20 are formed on the back surface 22. Is formed.
In the IC chip 20, one end is connected to the conductive pad 25, opened through the IC chip 20, and one via hole (open conductive part) 26 filled with a conductive material is formed. .
Conductive pads 23 and 24 provided on the surface 21 of the IC chip 20 are connected to the bottom surface 13B of the recess 13 of the mounting substrate 10 via a conductive material 41 such as solder. One of the conductive pads 23 and 24 formed on the surface 21 of the IC chip 20 is connected to the via hole 16 formed in the mounting substrate 10 via the conductive material 41.

チップ部品３０は、ＩＣチップ２０の裏面２２に形成された導電パッド２５と、実装基板１０の第１の基板面１１に形成された導電パッド１５に対して半田等の導電材４２を介して接続されている。
導電パッド１５、２３〜２５、及びビアホール１６、１７、２６の位置は、上記電気的接続が実現される位置にそれぞれ設計されている。 The chip component 30 is connected to the conductive pads 25 formed on the back surface 22 of the IC chip 20 and the conductive pads 15 formed on the first substrate surface 11 of the mounting substrate 10 via a conductive material 42 such as solder. Has been.
The positions of the conductive pads 15, 23 to 25 and the via holes 16, 17, 26 are designed at positions where the electrical connection is realized.

チップ部品３０は、半田等の導電材４２を介してＩＣチップ２０と実装基板１０に実装されるので、凹部１３内に実装されたＩＣチップ２０の裏面２２の高さと実装基板１０の第１の基板面１１の高さとが多少ずれていても、チップ部品３０の実装は可能である。
換言すれば、凹部１３内に実装されたＩＣチップ２０の裏面２２の高さと実装基板１０の第１の基板面１１の高さは、チップ部品３０をＩＣチップ２０と実装基板１０とに跨って実装することができる範囲内であればよい。
本明細書において、「凹部１３内に実装されたＩＣチップ２０の裏面２２と実装基板１０の第１の基板面１１とが略面一」とは、凹部１３内に実装されたＩＣチップ２０の裏面２２の高さと実装基板１０の第１の基板面１１の高さとのずれが１００μｍ以内を目安としている。 Since the chip component 30 is mounted on the IC chip 20 and the mounting substrate 10 via the conductive material 42 such as solder, the height of the back surface 22 of the IC chip 20 mounted in the recess 13 and the first of the mounting substrate 10 are determined. Even if the height of the substrate surface 11 is slightly deviated, the chip component 30 can be mounted.
In other words, the height of the back surface 22 of the IC chip 20 mounted in the recess 13 and the height of the first substrate surface 11 of the mounting substrate 10 extend over the chip component 30 between the IC chip 20 and the mounting substrate 10. It may be within a range that can be implemented.
In this specification, “the back surface 22 of the IC chip 20 mounted in the recess 13 and the first substrate surface 11 of the mounting substrate 10 are substantially flush” refers to the IC chip 20 mounted in the recess 13. As a guide, the deviation between the height of the back surface 22 and the height of the first substrate surface 11 of the mounting substrate 10 is within 100 μm.

本実施形態では、以上の構成により、実装基板１０の第２の基板面１２に形成されたＧＮＤパターン１４とチップ部品３０とが、実装基板１０の凹部１３の底面１３Ｂから実装基板１０の第２の基板面１２との間に形成された１つのビアホール１６と、ＩＣチップ２０内に形成された１つのビアホール２６とを介して互いに導通されている。   In the present embodiment, with the above configuration, the GND pattern 14 and the chip component 30 formed on the second substrate surface 12 of the mounting substrate 10 are transferred from the bottom surface 13B of the recess 13 of the mounting substrate 10 to the second of the mounting substrate 10. These are electrically connected to each other through one via hole 16 formed between the substrate surface 12 and one via hole 26 formed in the IC chip 20.

本実施形態の半導体装置において、図４に示すような回路を実現しようとすると、図２のような回路構造になる。図中、ＦＥＴは電界効果トランジスタ、Ｃはチップコンデンサ、ＧＮＤはグランド、ＨＸは実装基板内のビアホール、ＨＹはＩＣチップ内のビアホールを各々示す。   In the semiconductor device of the present embodiment, when the circuit as shown in FIG. 4 is realized, the circuit structure as shown in FIG. 2 is obtained. In the figure, FET is a field effect transistor, C is a chip capacitor, GND is ground, HX is a via hole in the mounting substrate, and HY is a via hole in the IC chip.

「発明が解決しようとする課題」の項において、特許文献１に記載の半導体装置において、図４に示すような回路を実現しようとすると、図３のような回路構造になることを説明した。特許文献１に記載の半導体装置では、チップコンデンサ等のチップ部品を実装基板に電気的に接続するために、ＩＣチップ内に複数のビアホールが必要であり、ＩＣチップの小面積化が難しく、半導体装置全体を小型化することが難しいことを述べた。   In the section “Problems to be Solved by the Invention”, it has been explained that in the semiconductor device described in Patent Document 1, when a circuit as shown in FIG. 4 is realized, a circuit structure as shown in FIG. 3 is obtained. In the semiconductor device described in Patent Document 1, in order to electrically connect a chip component such as a chip capacitor to a mounting substrate, a plurality of via holes are required in the IC chip, and it is difficult to reduce the area of the IC chip. He stated that it was difficult to downsize the entire device.

本実施形態の半導体装置１では、チップコンデンサ等のチップ部品３０を実装基板１０に接続するために、ＩＣチップ２０内に１つのビアホール２６を設ければよく、ＩＣチップ２０の小面積化が可能であり、半導体装置１全体を小型化することができる。   In the semiconductor device 1 of this embodiment, in order to connect the chip component 30 such as a chip capacitor to the mounting substrate 10, one via hole 26 may be provided in the IC chip 20, and the IC chip 20 can be reduced in area. Thus, the entire semiconductor device 1 can be reduced in size.

基板に凹部を設けて、ＩＣチップ等の電子部品を搭載することに関しては、「背景技術」の項で挙げた特許文献２〜４に記載がある。
特許文献２の図２には、実装基板（１２１）の凹部に回路基板（１２２）が実装され、この回路基板（１２２）と実装基板（１２１）の凸部に設けられたＬＥＤチップ（３０）とがボンディングワイヤ（４０）を介して接続された発光装置が記載されている。この発明は発光装置に関するものであり、実装基板にＩＣチップとチップ部品とが搭載されたものではない。また、この装置では、ＬＥＤチップ（３０）は回路基板（１２２）と実装基板（１２１）に跨って形成されておらず、ＬＥＤチップ（３０）と回路基板（１２２）とはボンディングワイヤ（４０）を用いた電気的接続であるので、本発明のように装置の小型化を図ることは難しい。 Patent Documents 2 to 4 listed in the “Background Art” section relate to mounting a concave portion on a substrate and mounting an electronic component such as an IC chip.
In FIG. 2 of Patent Document 2, the circuit board (122) is mounted in the concave portion of the mounting substrate (121), and the LED chip (30) provided on the convex portion of the circuit board (122) and the mounting substrate (121). Describes a light-emitting device connected to each other via a bonding wire (40). The present invention relates to a light emitting device, and does not include an IC chip and a chip component mounted on a mounting substrate. In this device, the LED chip (30) is not formed across the circuit board (122) and the mounting board (121), and the LED chip (30) and the circuit board (122) are bonded to the bonding wire (40). Therefore, it is difficult to reduce the size of the apparatus as in the present invention.

特許文献３の図３には、実装基板（１）に設けられた凹部（１６）内に回路部品（１５）が搭載され、凹部（１６）を多層基板（２）により封止し、この上にＳＭＤ部品（３）が実装された半導体装置が記載されている。この装置は構成が複雑であり、ＳＭＤ部品（３）は回路部品（１５）と実装基板（１）とに跨って形成されておらず、実装基板（１）及び多層基板（２）内に多数のビアホール（１８、１９）が必要である。   In FIG. 3 of Patent Document 3, the circuit component (15) is mounted in the recess (16) provided in the mounting substrate (1), and the recess (16) is sealed by the multilayer substrate (2). Describes a semiconductor device on which an SMD component (3) is mounted. This apparatus has a complicated configuration, and the SMD component (3) is not formed across the circuit component (15) and the mounting substrate (1), and there are many SMD components (1) and multilayer substrates (2). Via holes (18, 19) are required.

特許文献４の図１には、実装基板（１）に設けられた凹部内に電気素子（２）を搭載し、実装基板（１）と電気素子（２）とに跨るように光素子（３）を搭載した光・電気モジュールが記載されている。この発明は光・電気モジュールに関するものであり、実装基板にＩＣチップとチップ部品とが搭載されたものではない。   In FIG. 1 of Patent Document 4, the electric element (2) is mounted in a recess provided in the mounting board (1), and the optical element (3) is straddled between the mounting board (1) and the electric element (2). ) Is installed. The present invention relates to an optical / electrical module and does not include an IC chip and a chip component mounted on a mounting substrate.

以上説明したように、本実施形態によれば、実装基板１０にＩＣチップ２０及びチップ部品３０が実装された半導体装置において、ＩＣチップ２０の小面積化が可能であり、半導体装置１全体を小型化することが可能となる。   As described above, according to the present embodiment, in the semiconductor device in which the IC chip 20 and the chip component 30 are mounted on the mounting substrate 10, the area of the IC chip 20 can be reduced, and the entire semiconductor device 1 can be reduced in size. Can be realized.

１ 半導体装置
１０ 実装基板
１１ 第１の基板面
１２ 第２の基板面
１３ 凹部
１３Ｂ 凹部の底面
１４ ＧＮＤパターン（導電部）
１５ 導電パッド
１６、１７ ビアホール（開孔導電部）
２０ 半導体集積回路チップ（半導体ＩＣチップ）
２１ 表面
２２ 裏面
２３〜２５ 導電パッド
２６ ビアホール（開孔導電部）
３０ 半導体チップ部品 DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Mounting board 11 1st board | substrate surface 12 2nd board | substrate surface 13 Recessed part 13B Bottom face 14 of a recessed part GND pattern (conductive part)
15 Conductive pads 16, 17 Via hole (opening conductive part)
20 Semiconductor integrated circuit chip (semiconductor IC chip)
21 Front surface 22 Back surface 23-25 Conductive pad 26 Via hole (opening conductive part)
30 Semiconductor chip parts

Claims (4)

実装基板に半導体集積回路チップと当該半導体集積回路チップに電気的に接続される半導体チップ部品とが実装されたものであり、
前記半導体集積回路チップは、前記実装基板に形成され、当該実装基板の第１の基板面において開口した凹部内に実装されており、
前記半導体チップ部品は、前記半導体集積回路チップの前記第１の基板面側の面と前記実装基板の前記第１の基板面とに跨って実装された半導体装置。 A semiconductor integrated circuit chip and a semiconductor chip component electrically connected to the semiconductor integrated circuit chip are mounted on a mounting substrate,
The semiconductor integrated circuit chip is formed in the mounting substrate, and is mounted in a recess opened in the first substrate surface of the mounting substrate.
The semiconductor chip component is a semiconductor device mounted across the first substrate surface side surface of the semiconductor integrated circuit chip and the first substrate surface of the mounting substrate. 前記凹部が、当該凹部内に実装された前記半導体集積回路チップの前記第１の基板面側の面と前記実装基板の前記第１の基板面とが略面一となる深さで形成された請求項１に記載の半導体装置。   The recess is formed at a depth such that a surface on the first substrate surface side of the semiconductor integrated circuit chip mounted in the recess is substantially flush with the first substrate surface of the mounting substrate. The semiconductor device according to claim 1. 前記実装基板の第２の基板面に形成された導電部と前記半導体チップ部品とが、
前記実装基板の前記凹部の底面から前記実装基板の前記第２の基板面との間に開孔され、内部に導電材料が充填された１つの開孔導電部と、前記半導体集積回路チップ内に開孔され、内部に導電材料が充填された１つの開孔導電部とを介して互いに導通された請求項１又は２に記載の半導体装置。 The conductive part formed on the second substrate surface of the mounting substrate and the semiconductor chip component,
One open conductive portion that is opened between the bottom surface of the recess of the mounting substrate and the second substrate surface of the mounting substrate and filled with a conductive material therein, and in the semiconductor integrated circuit chip The semiconductor device according to claim 1, wherein the semiconductor devices are electrically connected to each other through one hole conductive portion that is opened and filled with a conductive material. 前記半導体集積回路チップは、当該半導体集積回路チップにおいて前記実装基板の前記凹部の底面側の面に形成された導電パッドを介して、前記実装基板に実装されており、
前記半導体チップ部品は、前記半導体集積回路チップにおいて前記実装基板の前記第１の基板面側の面に形成された導電パッドを介して、前記半導体集積回路チップに実装されると共に、前記実装基板の前記第１の基板面において前記凹部に隣接する領域に形成された導電パッドを介して、前記実装基板の前記第１の基板面に実装された請求項１〜３のいずれかに記載の半導体装置。 The semiconductor integrated circuit chip is mounted on the mounting substrate via a conductive pad formed on the bottom surface of the concave portion of the mounting substrate in the semiconductor integrated circuit chip,
The semiconductor chip component is mounted on the semiconductor integrated circuit chip via a conductive pad formed on a surface of the mounting substrate on the first substrate surface side in the semiconductor integrated circuit chip. The semiconductor device according to claim 1, wherein the semiconductor device is mounted on the first substrate surface of the mounting substrate via a conductive pad formed in a region adjacent to the concave portion on the first substrate surface. .
JP2010033500A 2010-02-18 2010-02-18 Semiconductor device Pending JP2011171488A (en)

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