JP2009054860A - Chip-type semiconductor device - Google Patents

Chip-type semiconductor device Download PDF

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JP2009054860A
JP2009054860A JP2007221416A JP2007221416A JP2009054860A JP 2009054860 A JP2009054860 A JP 2009054860A JP 2007221416 A JP2007221416 A JP 2007221416A JP 2007221416 A JP2007221416 A JP 2007221416A JP 2009054860 A JP2009054860 A JP 2009054860A
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bonding
pattern
semiconductor device
type semiconductor
wire
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JP5041593B2 (en
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Norikazu Kadotani
典和 門谷
Satoru Kikuchi
悟 菊池
Koichi Fukazawa
孝一 深沢
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Citizen Electronics Co Ltd
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Citizen Electronics Co Ltd
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    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a chip-type semiconductor device capable of having a wire driven into a pattern on a field via hole without problems, when this is carried out by ball bonding. <P>SOLUTION: A substrate 2 of an LED 1 is such that a die-bonding pattern 2b and a second bonding pattern 2c as top-surface side electrodes and terminal electrodes 2d and 2d as reverse-surface side electrodes are arranged opposite each other with an insulating layer 2a, interposed therebetweeen and the top-surface and reverse-surface side electrodes are electrically connected to each other through a field via hole 2e, formed by charging a conductive agent in a through-hole. An LED element 3 is bonded to the die-bonding pattern 2b, and an electrode of the LED element 3 and the second bonding pattern 2c are connected to each other by a gold wire 4. The LED element 3 and wire 4 are sealed by sealing resin 5. The field via hole 2e of the second bonding pattern 2c is formed, apart from a bonding point, which will not vertically overlap tip diameter of a capillary. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、チップ型半導体装置に関し、更に詳しくは、半導体素子がワイヤボンディングによって実装されたチップ型半導体装置に関する。   The present invention relates to a chip type semiconductor device, and more particularly to a chip type semiconductor device in which a semiconductor element is mounted by wire bonding.

近年の電子機器の小形・薄形化傾向に伴って、回路基板へ表面実装が可能な電子部品、即ちチップ型半導体装置の需要が急速に増加している。チップ型半導体装置は、通常は直方体ブロックに近い形状をしており、絶縁基板の表面側にそれぞれ一対の電極を備え、裏面または裏面に近い側面に一対の端子電極が形成されている。そして、表裏面の電極同士はスルーホールによって導通する一方、表面側電極の一方に半導体素子を実装し、該半導体素子と他方の表面側電極とを金属細線によってワイヤボンディングしたのち、これらの半導体素子及び金属細線を透光性樹脂によって封止したものである。このようなチップ型半導体装置は、回路基板上の配線パターンと所定の端子電極とが接触するように回路基板上に配設して、半田などの導電性接着剤で回路基板上に固着する。   With the recent trend toward smaller and thinner electronic equipment, the demand for electronic components that can be surface-mounted on a circuit board, that is, chip-type semiconductor devices, is rapidly increasing. A chip-type semiconductor device usually has a shape close to a rectangular parallelepiped block, and includes a pair of electrodes on the surface side of the insulating substrate, and a pair of terminal electrodes formed on the back surface or a side surface close to the back surface. The electrodes on the front and back surfaces are electrically connected to each other by a through-hole, and a semiconductor element is mounted on one of the surface side electrodes, and the semiconductor element and the other surface side electrode are wire-bonded with a thin metal wire. And a thin metal wire sealed with a translucent resin. Such a chip-type semiconductor device is disposed on a circuit board so that a wiring pattern on the circuit board and a predetermined terminal electrode are in contact with each other, and is fixed on the circuit board with a conductive adhesive such as solder.

このようなチップ型半導体装置において、基板の表面側に半導体素子を接合するダイボンドパターン及び２ｎｄボンディングパターンと裏面側の端子電極とを絶縁層を挟んで対向配置させることによって、装置の小型化を追求したものが知られている（例えば、特許文献１、特許文献２及び特許文献３参照。）。   In such a chip-type semiconductor device, a die bonding pattern for bonding a semiconductor element to the front surface side of the substrate, a 2nd bonding pattern, and a terminal electrode on the back surface are arranged opposite to each other with an insulating layer interposed therebetween, thereby pursuing downsizing of the device. (For example, refer to Patent Document 1, Patent Document 2, and Patent Document 3).

図４は従来のこのようなチップ型半導体装置の一例である発光ダイオード（以下ＬＥＤと略記する）の断面図を示している。ＬＥＤ５１の基板５２は、絶縁層５２ａを挟んで表面側電極であるダイボンドパターン５２ｂ及び２ｎｄボンディングパターン５２ｃと裏面側電極である端子電極５２ｄ、５２ｄとをそれぞれ対向配置させ、絶縁層５２ａを貫通するレーザーで開けた穴内に導電剤を充填して形成したフィルドビア５２ｅによって表裏電極を導通させている。フィルドビア５２ｅはレーザーによって穴開けを行う都合上、基板５２はプリント配線板やフレキシブル基板等の薄いものである。ダイボンドパターン５２ｂにはＬＥＤ素子３が接合され、金ワイヤ４（径２０〜３０μｍ）によってＬＥＤ素子３の電極と２ｎｄボンディングパターン５２ｃとが接続されている。ＬＥＤ素子３と金ワイヤ４とは封止樹脂５によって封止されている。ＬＥＤ５１ではフィルドビア５１ｅの径がキャピラリの先端径より大きいのでキャピラリの片当たりが起きない。   FIG. 4 shows a cross-sectional view of a light emitting diode (hereinafter abbreviated as LED) which is an example of such a conventional chip type semiconductor device. The substrate 51 of the LED 51 has a die-bonding pattern 52b and 2nd bonding pattern 52c that are front-side electrodes and terminal electrodes 52d and 52d that are back-side electrodes facing each other across an insulating layer 52a, and a laser that penetrates the insulating layer 52a. The front and back electrodes are made conductive by a filled via 52e formed by filling a hole formed in step 1 with a conductive agent. The filled via 52e is thin, such as a printed wiring board or a flexible board, for convenience of drilling with a laser. The LED element 3 is bonded to the die bond pattern 52b, and the electrode of the LED element 3 and the 2nd bonding pattern 52c are connected by a gold wire 4 (diameter 20 to 30 μm). The LED element 3 and the gold wire 4 are sealed with a sealing resin 5. In the LED 51, since the diameter of the filled via 51e is larger than the diameter of the tip of the capillary, no contact of the capillary occurs.

図５は他の従来のチップ型半導体装置の一例であるＬＥＤの断面図を示しており、ワイヤボンディングをボールボンディングで行った場合の、２ｎｄボンディングの様子を表している。ＬＥＤ６１ではフィルドビア６２ｅの径（φｄ＝４０〜５０μｍ）はキャピラリ９の先端径（φＤ＝８０〜１００μｍ）よりも小さい径を有している。このような場合には、図５に示すように、キャピラリ９の先端の一部がフィルドビア上の電極に、他の一部が基板の基材上の電極にくる場合、即ちキャピラリ９の片当たりが発生する。
特開２００１−１０２６３８号公報 特開平０９−１８１３５９号公報 特開２００３−０１７７５４号公報 FIG. 5 shows a cross-sectional view of an LED which is an example of another conventional chip type semiconductor device, and shows a state of 2nd bonding when wire bonding is performed by ball bonding. In the LED 61, the diameter of the filled via 62e (φd = 40 to 50 μm) is smaller than the tip diameter (φD = 80 to 100 μm) of the capillary 9. In such a case, as shown in FIG. 5, when a part of the tip of the capillary 9 comes to the electrode on the filled via and the other part comes to the electrode on the base material of the substrate, that is, per piece of the capillary 9 Will occur.
JP 2001-102638 A JP 09-181359 A JP 2003-017754 A

しかし、ワイヤボンディングをウェッジボンディングで行った場合には、２ｎｄボンディング側においてより広いスペースを必要とする。また、キャピラリの構造上、同じ方向にしかワイヤのループを張れない。そこでボールボンディングで行おうとすると、フィルドビアの径がワイヤボンダーのキャピラリの先端径より小さい場合には、キャピラリの片当たりが発生する。この場合には超音波が基材部分には伝わり難くなるのでワイヤが２ｎｄボンディング位置で押しつぶしに不具合が生じやすく、ワイヤが引っ張られたときに接続部が剥がれたり、剥がれやすくなるという問題があった。   However, when wire bonding is performed by wedge bonding, a wider space is required on the 2nd bonding side. Moreover, the loop of the wire can be stretched only in the same direction due to the structure of the capillary. Accordingly, when trying to perform ball bonding, if the diameter of the filled via is smaller than the diameter of the tip of the capillary of the wire bonder, the capillary will come into contact with each other. In this case, since it is difficult for the ultrasonic wave to be transmitted to the base material portion, there is a problem that the wire is easily crushed at the 2nd bonding position, and the connecting portion is peeled off or easily peeled off when the wire is pulled. .

本発明は、上記問題を解決して、ワイヤボンディングをボールボンディングで行った場合に、フィルドビアの径がワイヤボンダーのキャピラリの先端径より小さい場合にもフィルドビア上のパターンに問題なくワイヤを打つことができるチップ型半導体装置を提供することを目的としている。   The present invention solves the above problem, and when wire bonding is performed by ball bonding, even if the diameter of the filled via is smaller than the tip diameter of the capillary of the wire bonder, the wire can be hit without any problem on the pattern on the filled via. An object of the present invention is to provide a chip-type semiconductor device that can be used.

前述した目的を達成するための本発明の手段は、絶縁層の両面に銅箔が張られ、表面側には半導体素子を実装するダイボンドパターンとワイヤボンディングされる２ｎｄボンディングパターンとを有し、裏面側には前記両パターンの端子電極となる裏パターンを有し、表裏の前記パターンが絶縁層を貫通して導通している実装基板と、前記実装基板上に固着された半導体素子と、前記半導体素子と前記２ｎｄボンディングパターンとをボールボンディングにより接続する金属線とから成り、前記半導体素子および前記金属線を封止する絶縁樹脂で前記実装基板の表面側全面を覆ったチップ型半導体装置において、前記フィルドビアと、前記キャピラリ先端とが垂直方向に重ならないように、２ｎｄボンディングがなされていることを特徴とする。   The means of the present invention for achieving the above-described object is that a copper foil is stretched on both surfaces of an insulating layer, a die bond pattern for mounting a semiconductor element and a 2nd bonding pattern for wire bonding are provided on the front surface side, and a back surface A mounting substrate having a back pattern to be a terminal electrode of the both patterns on the side, the pattern on the front and back passing through an insulating layer, a semiconductor element fixed on the mounting substrate, and the semiconductor In a chip type semiconductor device comprising an element and a metal wire connecting the 2nd bonding pattern by ball bonding, and covering the entire surface side of the mounting substrate with an insulating resin that seals the semiconductor element and the metal line. 2nd bonding is performed so that the filled via and the capillary tip do not overlap in the vertical direction. .

また、前記裏パターン側から前記ダイボンドパターンあるいは前記２ｎｄボンディングパターンの銅箔に達する穴をレーザー処理により設け、メッキにより表裏のパターンを導通し、さらに穴全体を塞ぎフィルドビアを形成したことを特徴する。   Also, a hole reaching the copper foil of the die bond pattern or the 2nd bonding pattern from the back pattern side is provided by laser processing, the front and back patterns are made conductive by plating, and the whole hole is closed to form a filled via.

また、前記フィルドビアの径がワイヤボンディングのキャピラリ先端径よりも小であることを特徴する。   Further, the diameter of the filled via is smaller than the diameter of the capillary tip of wire bonding.

また、前記フィルドビアは、ダイボンドパターン側に複数形成されていることを特徴する。   A plurality of filled vias are formed on the die bond pattern side.

また、前述した目的を達成するための本発明の他の手段は、絶縁層の両面に銅箔が張られ、表面側には半導体素子を実装するダイボンドパターンとワイヤボンディングされる２ｎｄボンディングパターンとを有し、裏面側には前記両パターンの端子電極となる裏パターンを有し、表裏の前記パターンが絶縁層を貫通して導通している実装基板と、前記実装基板上に固着された半導体素子と、前記半導体素子と前記２ｎｄボンディングパターンとをボールボンディングにより接続する金属線とから成り、前記半導体素子および前記金属線を封止する絶縁樹脂で前記実装基板の表面側全面を覆ったチップ型半導体装置において、前記フィルドビアは、２ｎｄボンディングパターン側に複数形成されており、前記キャピラリ先端と前記複数のフィルドビアの少なくとも２つ以上とが垂直方向に重なるように２ｎｄボンディングがなされていることを特徴とするチップ型半導体装置。   Further, another means of the present invention for achieving the above-described object is that a copper foil is stretched on both surfaces of the insulating layer, and a die bond pattern for mounting a semiconductor element and a 2nd bonding pattern for wire bonding are provided on the surface side. A mounting substrate having a back pattern to be a terminal electrode of the both patterns on the back surface side, and the pattern on the front and back surfaces being conducted through an insulating layer, and a semiconductor element fixed on the mounting substrate And a chip-type semiconductor that covers the entire surface of the mounting substrate with an insulating resin that seals the semiconductor element and the metal wire, and a metal wire that connects the semiconductor element and the 2nd bonding pattern by ball bonding. In the apparatus, a plurality of filled vias are formed on the 2nd bonding pattern side, and the tip of the capillary and the plurality of fill vias are formed. Chip type semiconductor device characterized by 2nd bonding have been made to at least two or more vias are overlapped in the vertical direction.

また、前記裏パターン側から前記ダイボンドパターンあるいは前記２ｎｄボンディングパターンの銅箔に達する穴をレーザー処理により設け、メッキにより表裏のパターンを導通し、さらに穴全体を塞ぎフィルドビアを形成したことを特徴とする。   Further, a hole reaching the copper foil of the die bond pattern or the 2nd bonding pattern from the back pattern side is provided by laser processing, the front and back patterns are made conductive by plating, and the whole hole is closed to form a filled via. .

また、前記フィルドビア径は、ワイヤボンディングのキャピラリ先端径よりも小であることを特徴とする。   The filled via diameter is smaller than the diameter of the capillary tip of wire bonding.

また、前記フィルドビアは、ダイボンドパターン側に複数形成されていることを特徴とする。   A plurality of filled vias are formed on the die bond pattern side.

本発明によれば、絶縁層の両面に銅箔が張られ、表面側には半導体素子を実装するダイボンドパターンとワイヤボンディングされる２ｎｄボンディングパターンとを有し、裏面側には前記両パターンの端子電極となる裏パターンを有し、表裏の前記パターンが絶縁層を貫通して導通している実装基板と、前記実装基板上に固着された半導体素子と、前記半導体素子と前記２ｎｄボンディングパターンとをボールボンディングにより接続する金属線とから成り、前記半導体素子および前記金属線を封止する絶縁樹脂で前記実装基板の表面側全面を覆ったチップ型半導体装置において、前記フィルドビアと、前記キャピラリ先端とが垂直方向に重ならないように、２ｎｄボンディングがなされているので、端子電極をボンディングパターンに対向する位置に配設して、チップ半導体装置を小型化することができる。また、フィルドビアやスルーホール形成に必要だったスペースを有効利用できるのでパターン面積を増やすことによって素子数増加（ＬＥＤ素子の場合には高輝度化）が可能になる。また、製品小型化に伴い基板取り個数の向上（低コスト化）が可能である。また、製品外形サイズの制約があって、端子を共有化させることが必要な場合でも各素子専用の端子を出すことが可能になる。また、ダイボンドパターンの直下にあるフィルドビアから端子電極へ放熱されるので、半導体素子の放熱性がよくなる。また、ワイヤボンディングをボールボンディングで行う場合に、２ｎｄボンディングにおいてフィルドビアがボンディングポイントから離れているために、フィルドビアの影響を受けないでボンディング不良の発生を未然に防止できる。   According to the present invention, copper foil is stretched on both surfaces of the insulating layer, the front surface side has a die bond pattern for mounting a semiconductor element and a 2nd bonding pattern to be wire bonded, and the back surface side has terminals of both the patterns. A mounting substrate having a back pattern to be an electrode, wherein the front and back patterns pass through an insulating layer, a semiconductor element fixed on the mounting substrate, the semiconductor element, and the 2nd bonding pattern. In a chip type semiconductor device comprising a metal wire connected by ball bonding and covering the entire surface side of the mounting substrate with an insulating resin that seals the semiconductor element and the metal wire, the filled via and the tip of the capillary are 2nd bonding is done so as not to overlap in the vertical direction, so the terminal electrode faces the bonding pattern. And disposed at a position that the chip semiconductor device can be miniaturized. In addition, since the space necessary for forming the filled vias and through holes can be used effectively, the number of elements can be increased (in the case of LED elements, the brightness can be increased) by increasing the pattern area. In addition, the number of substrates can be improved (cost reduction) as the product size is reduced. In addition, even when there is a restriction on the external size of the product and it is necessary to share the terminals, it is possible to provide dedicated terminals for each element. Further, since heat is radiated from the filled vias directly under the die bond pattern to the terminal electrode, the heat dissipation of the semiconductor element is improved. Further, when wire bonding is performed by ball bonding, since the filled via is separated from the bonding point in 2nd bonding, it is possible to prevent the occurrence of bonding failure without being affected by the filled via.

また、前記裏パターン側から前記ダイボンドパターンあるいは前記２ｎｄボンディングパターンの銅箔に達する穴をレーザー処理により設け、メッキにより表裏のパターンを導通し、さらに穴全体を塞ぎフィルドビアを形成したので、パターン側の熱を効率よく端子電極側へ放熱することができる。   Further, a hole reaching the copper foil of the die bond pattern or the 2nd bonding pattern from the back pattern side is provided by laser processing, the front and back patterns are made conductive by plating, and the entire hole is closed to form a filled via. Heat can be efficiently radiated to the terminal electrode side.

また、前記フィルドビアの径がワイヤボンディングのキャピラリ先端径よりも小であるので、キャピラリの片当たりが発生せず、ボールボンディングの不良発生を防ぐことができる。   In addition, since the diameter of the filled via is smaller than the diameter of the capillary tip of wire bonding, no contact of the capillary occurs, and the occurrence of defective ball bonding can be prevented.

また、前記フィルドビアは、ダイボンドパターン側に複数形成されているので、素子実装部直下のフィルドビアを経由して端子電極から放熱し易くなるので放熱性を向上させることができる。   In addition, since a plurality of filled vias are formed on the die bond pattern side, it is easy to radiate heat from the terminal electrode via the filled vias directly under the element mounting portion, so that heat dissipation can be improved.

また、前記フィルドビアと、前記キャピラリ先端とが垂直方向に重ならないように、２ｎｄボンディングがなされているので、２ｎｄボンディングの際に、フィルドビアの影響を受けず、ボールボンディングの不良発生を未然に防ぐことができる。   In addition, since the 2nd bonding is performed so that the filled via and the capillary tip do not overlap in the vertical direction, it is not affected by the filled via in the 2nd bonding, and the occurrence of a defective ball bonding is prevented in advance. Can do.

また、前述した目的を達成するための本発明の他の手段は、絶縁層の両面に銅箔が張られ、表面側には半導体素子を実装するダイボンドパターンとワイヤボンディングされる２ｎｄボンディングパターンとを有し、裏面側には前記両パターンの端子電極となる裏パターンを有し、表裏の前記パターンが絶縁層を貫通して導通している実装基板と、前記実装基板上に固着された半導体素子と、前記半導体素子と前記２ｎｄボンディングパターンとをボールボンディングにより接続する金属線とから成り、前記半導体素子および前記金属線を封止する絶縁樹脂で前記実装基板の表面側全面を覆ったチップ型半導体装置において、前記フィルドビアは、２ｎｄボンディングパターン側に複数形成されており、前記キャピラリ先端と前記複数のフィルドビアとが垂直方向に重なるように２ｎｄボンディングがなされているので、前記複数のフィルドビアの何れかとがキャピラリ先端と重なることになるのでキャピラリの片当たりが発生せず、ボールボンディングの不良発生を未然に防ぐことができる。また、小さなフィルドビアが、複数あることによりワイヤボンディングのボンディング条件をフィルドビアと基板との混成部に合わせることで、多少位置ズレが起きても、混成部の範囲内ならばどこでも同じ条件でボンディングできるので、ボンディング不良が発生しない。   Further, another means of the present invention for achieving the above-described object is that a copper foil is stretched on both surfaces of the insulating layer, and a die bond pattern for mounting a semiconductor element and a 2nd bonding pattern for wire bonding are provided on the surface side. A mounting substrate having a back pattern to be a terminal electrode of the both patterns on the back surface side, and the pattern on the front and back surfaces being conducted through an insulating layer, and a semiconductor element fixed on the mounting substrate And a chip-type semiconductor that covers the entire surface of the mounting substrate with an insulating resin that seals the semiconductor element and the metal wire, and a metal wire that connects the semiconductor element and the 2nd bonding pattern by ball bonding. In the apparatus, a plurality of filled vias are formed on the 2nd bonding pattern side, and the tip of the capillary and the plurality of fill vias are formed. Since the 2nd bonding is performed so that the vias overlap in the vertical direction, any one of the plurality of filled vias overlaps the capillary tip, so that no contact of the capillary occurs and the occurrence of defective ball bonding is obviated. Can be prevented. In addition, since there are multiple small filled vias, the bonding conditions of wire bonding can be matched to the hybrid via and substrate hybrid part, so even if a slight misalignment occurs, bonding can be performed anywhere under the hybrid part under the same conditions. Bonding failure does not occur.

以下、本発明を実施するための最良の形態であるチップ型半導体装置を図面に基づいて詳細に説明する。図１は本発明の第１の実施の形態であるＬＥＤの断面図である。   Hereinafter, a chip type semiconductor device which is the best mode for carrying out the present invention will be described in detail with reference to the drawings. FIG. 1 is a sectional view of an LED according to a first embodiment of the present invention.

まず、本発明の第１の実施の形態であるＬＥＤの構成について説明する。図１において、ＬＥＤ装置１は、従来技術で説明したものと同様であるが、ボンディング位置ズレが起きたとしても、２ｎｄボンディングパターン２ｃにおけるフィルドビア２ｅが、ボンディングポイントから離れた位置であるキャピラリの先端と垂直方向に重ならない位置に形成されているところに特徴がある。   First, the configuration of the LED according to the first embodiment of the present invention will be described. In FIG. 1, the LED device 1 is the same as that described in the prior art, but even if the bonding position shift occurs, the filled via 2e in the 2nd bonding pattern 2c is located at the tip of the capillary at a position away from the bonding point. It is characterized in that it is formed at a position that does not overlap with the vertical direction.

次に、本発明の第１の実施の形態であるＬＥＤの効果について説明する。ＬＥＤ１において、端子電極２ｄが絶縁層２ａを介してダイボンドパターン２ｂ及び２ｎｄボンディングパターン２ｃと対向配置されており、ＬＥＤ１の小型化に寄与している。フィルドビアやスルーホール形成に必要だったスペースを有効利用できるので、パターン面積を増やすことによって素子数増加（ＬＥＤ素子の場合には高輝度化）が可能になる。また、製品外形サイズの制約があって端子を共有化させることが必要な場合でも、各素子専用の端子を出すことが可能になる。製品小型化に伴い基板取り個数の向上による低コスト化が可能である。また、ＬＥＤ素子３の直下にフィルドビア２ｅがあるので、端子電極２ｄへ放熱されるのでＬＥＤ素子３の放熱性がよくなる。また、ワイヤボンディングをボールボンディングで行う場合に、２ｎｄボンディングにおいてフィルドビア２ｅがボンディングポイントから離れているために、フィルドビア２ｅの影響を受けないでボンディング不良の発生を未然に防止できる。   Next, the effect of the LED according to the first embodiment of the present invention will be described. In the LED 1, the terminal electrode 2d is disposed opposite to the die bond pattern 2b and the 2nd bonding pattern 2c via the insulating layer 2a, which contributes to the downsizing of the LED 1. Since the space required for forming filled vias and through-holes can be used effectively, the number of elements can be increased (in the case of LED elements, the brightness can be increased) by increasing the pattern area. In addition, even when there is a restriction on the external size of the product and it is necessary to share the terminals, it is possible to provide dedicated terminals for each element. The cost can be reduced by increasing the number of substrates that can be obtained with the miniaturization of the product. In addition, since the filled via 2e is located immediately below the LED element 3, heat is radiated to the terminal electrode 2d, so that the heat dissipation of the LED element 3 is improved. Further, when wire bonding is performed by ball bonding, since the filled via 2e is separated from the bonding point in 2nd bonding, it is possible to prevent the occurrence of bonding failure without being affected by the filled via 2e.

次に、本発明の第２の実施の形態であるＬＥＤの構成について説明する。図２において、ＬＥＤ装置１１には、２ｎｄボンディングパターン１２ｃにおいて複数のフィルドビア１２ｅが縦横に形成されており、ボールボンディングにおいてキャピラリの先端は必ず複数のフィルドビアの少なくとも２つ以上が垂直方向に重なるように２ｎｄボンディングされている。このように複数のフィルドビアの周辺に基材が存在する構成、即ちフィルドビアと基材との混成部では、キャピラリの先端部は複数（２つ以上）のフィルドビアにかかることになるので、片当たりは起きず、ボンディング不良を発生させない。   Next, the configuration of the LED according to the second embodiment of the present invention will be described. In FIG. 2, the LED device 11 has a plurality of filled vias 12e formed vertically and horizontally in a 2nd bonding pattern 12c, and at the tip of the capillary in ball bonding, at least two of the plurality of filled vias always overlap in the vertical direction. 2nd bonding is performed. As described above, in the configuration in which the base material exists around the plurality of filled vias, that is, in the mixed portion of the filled via and the base material, the tip of the capillary is applied to a plurality (two or more) filled vias. Does not occur and does not cause bonding failure.

次に、本発明の第３の実施の形態であるＬＥＤの構成について説明する。図３において、ＬＥＤ装置２１は、第２の実施の形態のＬＥＤ１１と同様であり、ダイボンドパターン２２ｂにおけるフィルドビア２２ｅが複数形成されているところに特徴がある。これにより、ＬＥＤ素子３の放熱性をＬＥＤ１やＬＥＤ１１よりも更に向上させることができる。   Next, the configuration of the LED according to the third embodiment of the present invention will be described. In FIG. 3, the LED device 21 is similar to the LED 11 of the second embodiment, and is characterized in that a plurality of filled vias 22e in the die bond pattern 22b are formed. Thereby, the heat dissipation of the LED element 3 can be further improved compared with LED1 and LED11.

本発明の第１の実施の形態であるＬＥＤの断面図である。It is sectional drawing of LED which is the 1st Embodiment of this invention. 本発明の第２の実施の形態であるＬＥＤの断面図である。It is sectional drawing of LED which is the 2nd Embodiment of this invention. 本発明の第３の実施の形態であるＬＥＤの断面図である。It is sectional drawing of LED which is the 3rd Embodiment of this invention. 従来のＬＥＤを示す断面図である。It is sectional drawing which shows the conventional LED. 他の従来のＬＥＤの２ｎｄボンディングを示す断面図である。It is sectional drawing which shows 2nd bonding of other conventional LED.

符号の説明Explanation of symbols

１、１１、２１ ＬＥＤ
２、１２、２２ 基板
２ａ、１２ａ、２２ａ 絶縁層
２ｂ、１２ｂ、２２ｂ ダイボンドパターン
２ｃ、１２ｃ、２２ｃ ２ｎｄボンディングパターン
２ｄ、１２ｄ、２２ｄ 端子電極
２ｅ、１２ｅ、２２ｅ フィルドビア
３ ＬＥＤ素子
４ 金ワイヤ
５ 封止樹脂 1, 11, 21 LED
2, 12, 22 Substrate 2a, 12a, 22a Insulating layer 2b, 12b, 22b Die bond pattern 2c, 12c, 22c 2nd Bonding pattern 2d, 12d, 22d Terminal electrode 2e, 12e, 22e Filled via 3 LED element 4 Gold wire 5 Sealing resin

Claims (8)

絶縁層の両面に銅箔が張られ、表面側には半導体素子を実装するダイボンドパターンとワイヤボンディングされる２ｎｄボンディングパターンとを有し、裏面側には前記両パターンの端子電極となる裏パターンを有し、表裏の前記パターンが絶縁層を貫通して導通している実装基板と、前記実装基板上に固着された半導体素子と、前記半導体素子と前記２ｎｄボンディングパターンとをボールボンディングにより接続する金属線とから成り、前記半導体素子および前記金属線を封止する絶縁樹脂で前記実装基板の表面側全面を覆ったチップ型半導体装置において、前記フィルドビアと、前記キャピラリ先端とが垂直方向に重ならないように、２ｎｄボンディングがなされていることを特徴とするチップ型半導体装置。   Copper foil is stretched on both sides of the insulating layer, the front side has a die bond pattern for mounting a semiconductor element and a 2nd bonding pattern for wire bonding, and the back side has a back pattern to be a terminal electrode of both patterns. A metal substrate for connecting the semiconductor element and the 2nd bonding pattern by ball bonding; a mounting substrate in which the patterns on the front and back sides are electrically connected through the insulating layer; a semiconductor element fixed on the mounting substrate; In a chip type semiconductor device comprising a wire and covering the entire surface side of the mounting substrate with an insulating resin that seals the semiconductor element and the metal wire, the filled via and the capillary tip do not overlap in the vertical direction. And a chip-type semiconductor device, wherein 2nd bonding is performed. 前記裏パターン側から前記ダイボンドパターンあるいは前記２ｎｄボンディングパターンの銅箔に達する穴をレーザー処理により設け、メッキにより表裏のパターンを導通し、さらに穴全体を塞ぎフィルドビアを形成したことを特徴とする請求項１記載のチップ型半導体装置。   The hole reaching the copper foil of the die bond pattern or the 2nd bonding pattern from the back pattern side is provided by laser processing, the front and back patterns are made conductive by plating, and the whole hole is closed to form a filled via. 2. The chip type semiconductor device according to 1. 前記フィルドビア径は、ワイヤボンディングのキャピラリ先端径よりも小であることを特徴とする請求項１又は請求項２記載のチップ型半導体装置。   3. The chip type semiconductor device according to claim 1, wherein the filled via diameter is smaller than a capillary tip diameter of wire bonding. 前記フィルドビアは、ダイボンドパターン側に複数形成されていることを特徴とする請求項１乃至請求項３のいずれかに記載のチップ型半導体装置。   The chip-type semiconductor device according to claim 1, wherein a plurality of filled vias are formed on a die bond pattern side. 絶縁層の両面に銅箔が張られ、表面側には半導体素子を実装するダイボンドパターンとワイヤボンディングされる２ｎｄボンディングパターンとを有し、裏面側には前記両パターンの端子電極となる裏パターンを有し、表裏の前記パターンが絶縁層を貫通して導通している実装基板と、前記実装基板上に固着された半導体素子と、前記半導体素子と前記２ｎｄボンディングパターンとをボールボンディングにより接続する金属線とから成り、前記半導体素子および前記金属線を封止する絶縁樹脂で前記実装基板の表面側全面を覆ったチップ型半導体装置において、前記フィルドビアは、２ｎｄボンディングパターン側に複数形成されており、前記キャピラリ先端と前記複数のフィルドビアの少なくとも２つ以上とが垂直方向に重なるように２ｎｄボンディングがなされていることを特徴とするチップ型半導体装置。   Copper foil is stretched on both sides of the insulating layer, the front side has a die bond pattern for mounting a semiconductor element and a 2nd bonding pattern for wire bonding, and the back side has a back pattern to be a terminal electrode of both patterns. A metal substrate for connecting the semiconductor element and the 2nd bonding pattern by ball bonding; a mounting substrate in which the patterns on the front and back sides are electrically connected through the insulating layer; a semiconductor element fixed on the mounting substrate; In a chip type semiconductor device comprising a wire and covering the entire surface side of the mounting substrate with an insulating resin that seals the semiconductor element and the metal wire, a plurality of filled vias are formed on the 2nd bonding pattern side, 2 so that the tip of the capillary and at least two or more of the plurality of filled vias overlap in the vertical direction. Chip type semiconductor device characterized by d bonding have been made. 前記裏パターン側から前記ダイボンドパターンあるいは前記２ｎｄボンディングパターンの銅箔に達する穴をレーザー処理により設け、メッキにより表裏のパターンを導通し、さらに穴全体を塞ぎフィルドビアを形成したことを特徴とする請求項５記載のチップ型半導体装置。   The hole reaching the copper foil of the die bond pattern or the 2nd bonding pattern from the back pattern side is provided by laser processing, the front and back patterns are made conductive by plating, and the whole hole is closed to form a filled via. 5. The chip type semiconductor device according to 5. 前記フィルドビア径は、ワイヤボンディングのキャピラリ先端径よりも小であることを特徴とする請求項５又は請求項６記載のチップ型半導体装置。   7. The chip type semiconductor device according to claim 5, wherein the filled via diameter is smaller than a diameter of a capillary tip of wire bonding. 前記フィルドビアは、ダイボンドパターン側に複数形成されていることを特徴とする請求項５乃至請求項７のいずれかに記載のチップ型半導体装置。   8. The chip type semiconductor device according to claim 5, wherein a plurality of filled vias are formed on a die bond pattern side.
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