EP2428105A1 - Method and apparatus for improving power and loss for interconect configurations - Google Patents

Method and apparatus for improving power and loss for interconect configurations

Info

Publication number
EP2428105A1
EP2428105A1 EP10772351A EP10772351A EP2428105A1 EP 2428105 A1 EP2428105 A1 EP 2428105A1 EP 10772351 A EP10772351 A EP 10772351A EP 10772351 A EP10772351 A EP 10772351A EP 2428105 A1 EP2428105 A1 EP 2428105A1
Authority
EP
European Patent Office
Prior art keywords
power
pads
vias
blinds
capacitance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP10772351A
Other languages
German (de)
French (fr)
Other versions
EP2428105A4 (en
Inventor
James V. Russell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
R&D Circuits Inc
Original Assignee
R&D Circuits Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by R&D Circuits Inc filed Critical R&D Circuits Inc
Publication of EP2428105A1 publication Critical patent/EP2428105A1/en
Publication of EP2428105A4 publication Critical patent/EP2428105A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231—Capacitors or dielectric substances
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0234—Resistors or by disposing resistive or lossy substances in or near power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4046—Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present disclosure provides for attaching and embedding a capacitance or a resistance directly to the bottom side of pads that are located to extend over and beyond the vias of the PCB so that a portion of the pad containing the embedded power modification component (capacitance or resistance) is located beyond where the visa are located.
  • Each of the pads will be connected to the endpoints of the power modification component located underneath it through an opening in the dielectric material under the pads to permit conduction through the opening. In this way the capacitance and the resistance will have a closer contact point with the electrical component.
  • FIG.1 is a an illustration of standard interconnect configuration showing placement of a capacitance or resistance
  • FIG.2 A is illustrates the interconnect configuration with placement of the capacitance or resistance in accordance with the present disclosure
  • FIG 2B is another embodiment of the present disclosure showing the vias aligned vertically one on top of another for a finer pitch;
  • FIG. 3 is another embodiment of the present disclosure in which the embedded component is a component aligned vertically within the board;
  • FIG. 4 is an embodiment of the present disclosure showing an embedded resistance and an embedded capacitance within the board aligned vertically and horizontally.
  • FIG.1 illustrates the typical interconnect configuration where the capacitance or resistance is placed a considerable distance away from the electrical test structure housing of an IC chip (not shown).
  • FIG.2 illustrates the interconnect configuration of the present disclosure.
  • the power modification component 5 which can be, but is not limited to, either the capacitance 5c (FIG. 4) or the resistance 5a (FIG. 3) is embedded under pads 7 within the footprint of the electrical test structure housing of an IC chip (not shown).
  • the pads 7 are located with the embedded portion not covering the vias or blinds 11 but placed in proximity of the electrical component.
  • the placement can provide for better power distribution by being close to the electrical component so that there is little power dissipation and the capacitance does not become inductive. Similarly by the same close proximity of the resistance to the electrical component power dissipation is provided when required. Distant placement of the resistance from the electrical component results in a reduction of the power dissipation, a problem addressed and resolved by the present disclosure as shown in FIG. 3 of the drawings.
  • FIG.2A illustrates an embodiment of the present disclosure showing an interconnect configuration in which a power modification component 5 e.g. resistance 5a (FIG. 3) or capacitance 5c (FIG. 4) is attached to the bottom sides of the pads 7 formed by preferably a copper layer of a printed circuit board (PCB).
  • the embedded power modification component 5 (such as but not limited to a capacitance or resistance) is located below a layer of copper foil followed by dielectric layer.
  • the power modification component 5 is surrounded on its sides by Prepreg material e.g. fiber reinforced or unreinforced epoxy or plastic material.
  • the power modification component 5 is attached to the pads 7 layer by solder paste, conductive epoxy, or metallic plating 14.
  • the present disclosure also is not limited to the particular materials of copper foil, dielectric layer and Prepreg material described herein.
  • the power modification component 5 is embedded so as to be near but not block the vias or blinds 11 for the PCB 8.
  • the capacitance 5c will be a 0201 cap. However any desired capacitance value or size that can be accommodated can be used.
  • the capacitance 5c is attached by a conductive epoxy, solder paste, or metallic plating 14.
  • FIG.3 shows another embodiment of improved power dissipation by embedding a resistor 5a in a pc board 8.
  • An opening is created beneath the pad 7a at the top of the interposer board and the pad 7b at the bottom of the pc board 10 and a resistor 5a is vertically positioned within the opening in-between the top and bottom pads 7 a and 7b, respectively, and in effect acts as a via for the effected layers of the pc board 10, which it is assumed can be a multilayer pc board, so that the electrical connection is through the resistance 5a embedded in the pc board 10.
  • the pads 7a and 7b, respectively, are connected to the resistance 5a. Openings between the ends points of the resistance 5a and the pads 7a and 7b, respectively, in the pc board 8 can be filled with solder, metallic plating or conductive epoxy 14.
  • FIG. 4 shows another embodiment of the present disclosure with an embedded capacitance 5c and the embedded resistance 5a of FIG.3 together in the same pc board 8.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

The present disclosure relates to embedding a power modification component such as a capacitance or a resistance inside of pads that are located to extend over and beyond the vias of the PCB so that a portion of the pad containing the embedded capacitance or resistance is located beyond where the vias or blinds are located. Each of the pads will include an opening that is located over a given one of the vias or blinds to permit that via to conduct through the opening. In this way the capacitance and the resistance will have a closer contact point the electrical component.

Description

METHOD AND APPARATUS FOR IMPROVING POWER GAIN AND LOSS FOR INTERCONECT CONFIGURATIONS
RELATED APPLICATIONS
This is a non provisional application of a provisional application serial number 61/215,369 by James V. Russell filed May 4, 2009
BACKGROUND 1. Field
In attaching an electrical component to the bottom side and/or the top side of a printed circuit board (PCB)1 there is the problem of power loss or due to the distance of the capacitance to the points on a corresponding integrated circuit (IC) for which it is intended. It is not possible to physically locate the capacitance directly to the contact pads on the printed circuit which correspond to the input output points of an integrated circuit or in the case of a test board the corresponding points of the test socket. Similarly there is the problem of inadequate dissipation due to the distance of a resistance to the electrical component. Again, it is not very likely to physically locate the resistance at the contact pads on the printed circuit board.
It would therefore be desirable to have a method and apparatus that provides for close proximate placement of the capacitance or of the resistance which shall be referred to as a power modification component since it either better dissipates power (power loss) (resistance) or better distributes power (power gain) (capacitance) to the IC or other electrical component on a PCB to provide better power gain or distribution or power loss or dissipation. SUMMARY
The present disclosure provides for attaching and embedding a capacitance or a resistance directly to the bottom side of pads that are located to extend over and beyond the vias of the PCB so that a portion of the pad containing the embedded power modification component (capacitance or resistance) is located beyond where the visa are located. Each of the pads will be connected to the endpoints of the power modification component located underneath it through an opening in the dielectric material under the pads to permit conduction through the opening. In this way the capacitance and the resistance will have a closer contact point with the electrical component.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG.1 is a an illustration of standard interconnect configuration showing placement of a capacitance or resistance;
FIG.2 A is illustrates the interconnect configuration with placement of the capacitance or resistance in accordance with the present disclosure;
FIG 2B is another embodiment of the present disclosure showing the vias aligned vertically one on top of another for a finer pitch;
FIG. 3 is another embodiment of the present disclosure in which the embedded component is a component aligned vertically within the board; and
FIG. 4 is an embodiment of the present disclosure showing an embedded resistance and an embedded capacitance within the board aligned vertically and horizontally. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)
Referring now to the drawings, FIG.1 illustrates the typical interconnect configuration where the capacitance or resistance is placed a considerable distance away from the electrical test structure housing of an IC chip (not shown). FIG.2 illustrates the interconnect configuration of the present disclosure. In this configuration, the power modification component 5 which can be, but is not limited to, either the capacitance 5c (FIG. 4) or the resistance 5a (FIG. 3) is embedded under pads 7 within the footprint of the electrical test structure housing of an IC chip (not shown). The pads 7 are located with the embedded portion not covering the vias or blinds 11 but placed in proximity of the electrical component. In this way the placement can provide for better power distribution by being close to the electrical component so that there is little power dissipation and the capacitance does not become inductive. Similarly by the same close proximity of the resistance to the electrical component power dissipation is provided when required. Distant placement of the resistance from the electrical component results in a reduction of the power dissipation, a problem addressed and resolved by the present disclosure as shown in FIG. 3 of the drawings.
FIG.2A illustrates an embodiment of the present disclosure showing an interconnect configuration in which a power modification component 5 e.g. resistance 5a (FIG. 3) or capacitance 5c (FIG. 4) is attached to the bottom sides of the pads 7 formed by preferably a copper layer of a printed circuit board (PCB). The embedded power modification component 5 (such as but not limited to a capacitance or resistance) is located below a layer of copper foil followed by dielectric layer. The power modification component 5 is surrounded on its sides by Prepreg material e.g. fiber reinforced or unreinforced epoxy or plastic material. The power modification component 5 is attached to the pads 7 layer by solder paste, conductive epoxy, or metallic plating 14. It is understood that any other known means of attachment can be used as well and that the present disclosure also is not limited to the particular materials of copper foil, dielectric layer and Prepreg material described herein. As shown in FIG. 2A the power modification component 5 is embedded so as to be near but not block the vias or blinds 11 for the PCB 8. Preferably the capacitance 5c will be a 0201 cap. However any desired capacitance value or size that can be accommodated can be used. As seen in FIG. 4, the capacitance 5c is attached by a conductive epoxy, solder paste, or metallic plating 14.
FIG.3 shows another embodiment of improved power dissipation by embedding a resistor 5a in a pc board 8. An opening is created beneath the pad 7a at the top of the interposer board and the pad 7b at the bottom of the pc board 10 and a resistor 5a is vertically positioned within the opening in-between the top and bottom pads 7 a and 7b, respectively, and in effect acts as a via for the effected layers of the pc board 10, which it is assumed can be a multilayer pc board, so that the electrical connection is through the resistance 5a embedded in the pc board 10. The pads 7a and 7b, respectively, are connected to the resistance 5a. Openings between the ends points of the resistance 5a and the pads 7a and 7b, respectively, in the pc board 8 can be filled with solder, metallic plating or conductive epoxy 14.
FIG. 4 shows another embodiment of the present disclosure with an embedded capacitance 5c and the embedded resistance 5a of FIG.3 together in the same pc board 8.
While certain embodiments have been shown and described, it is distinctly understood that the present disclosure is not limited thereto but may be otherwise embodied within the scope of the appended claims.

Claims

1. A method for providing improved power distribution or power dissipation to an electrical component on a printed circuit board (PCB), the steps comprising: embedding a power modification component inside of one or more pads; locating said one or more embedded pads to extend over and beyond the vias or blinds of said PCB so that a portion of the pad containing the embedded power modification component is located beyond where the visa or blinds are located, said one or more pads include an opening that is located over a given one of the vias or blinds to permit that via to conduct through the opening so that said power modification component will have a closer contact point to said electrical component thereby increasing power distribution or power dissipation, respectively.
2. The method according to claimi wherein said power modification component is a capacitance.
3. The method according to claimi wherein said power modification component is a resistance.
4. An apparatus for improved power distribution or power dissipation to an electrical component on a printed circuit board (PCB), comprising: a power modification component embedded inside of one or more pads; a PCB having one or more vias or blinds, said one or more embedded pads being located to extend over and beyond the vias or blinds of said PCB so that a portion of the pad containing the embedded power modification is located beyond where the vias or blinds are located, said one or more pads include an opening that is located over a given one of the vias or blinds to permit that via or blind to conduct through the opening so that said power modification component will have a closer contact point to said electrical component thereby increasing power distribution or power dissipation, respectively.
5. The apparatus according to claim 4 wherein said power modification component is a capacitance.
6. The apparatus according to claim 4 wherein said power modification component is a resistance.
EP10772351.2A 2009-05-04 2010-01-08 Method and apparatus for improving power and loss for interconect configurations Withdrawn EP2428105A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US21536909P 2009-05-04 2009-05-04
PCT/US2010/000043 WO2010129002A1 (en) 2009-05-04 2010-01-08 Method and apparatus for improving power and loss for interconect configurations

Publications (2)

Publication Number Publication Date
EP2428105A1 true EP2428105A1 (en) 2012-03-14
EP2428105A4 EP2428105A4 (en) 2013-05-29

Family

ID=43050319

Family Applications (1)

Application Number Title Priority Date Filing Date
EP10772351.2A Withdrawn EP2428105A4 (en) 2009-05-04 2010-01-08 Method and apparatus for improving power and loss for interconect configurations

Country Status (6)

Country Link
EP (1) EP2428105A4 (en)
JP (1) JP2012526380A (en)
KR (1) KR20120007521A (en)
CN (1) CN102415224A (en)
SG (1) SG178121A1 (en)
WO (1) WO2010129002A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9406462B2 (en) * 2013-06-28 2016-08-02 The Boeing Company Truss interconnect
KR102206150B1 (en) * 2016-09-02 2021-01-22 알&디 설킷트스 인크. 3D wire block structure and method
CN107255784A (en) * 2017-07-10 2017-10-17 深圳崇达多层线路板有限公司 The many physical quantity systems and measuring method of a kind of wiring board
CN109669059B (en) * 2017-10-17 2021-03-16 中华精测科技股份有限公司 Circuit structure for adjusting power signal impedance and semiconductor test interface system thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11103170A (en) * 1997-09-29 1999-04-13 Kyocera Corp Multilayered ceramic circuit board with built-in resistor
EP1098368A1 (en) * 1999-04-16 2001-05-09 Matsushita Electric Industrial Co., Ltd. Module component and method of manufacturing the same
US20080013295A1 (en) * 2006-03-16 2008-01-17 Fujitsu Limited Capacitor sheet and electronic circuit board

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4953499B2 (en) * 1999-09-02 2012-06-13 イビデン株式会社 Printed wiring board
JP3813402B2 (en) * 2000-01-31 2006-08-23 新光電気工業株式会社 Manufacturing method of semiconductor device
JP4683770B2 (en) * 2001-05-31 2011-05-18 京セラ株式会社 Wiring board with built-in electric element and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11103170A (en) * 1997-09-29 1999-04-13 Kyocera Corp Multilayered ceramic circuit board with built-in resistor
EP1098368A1 (en) * 1999-04-16 2001-05-09 Matsushita Electric Industrial Co., Ltd. Module component and method of manufacturing the same
US20080013295A1 (en) * 2006-03-16 2008-01-17 Fujitsu Limited Capacitor sheet and electronic circuit board

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2010129002A1 *

Also Published As

Publication number Publication date
SG178121A1 (en) 2012-03-29
CN102415224A (en) 2012-04-11
WO2010129002A1 (en) 2010-11-11
EP2428105A4 (en) 2013-05-29
JP2012526380A (en) 2012-10-25
KR20120007521A (en) 2012-01-20

Similar Documents

Publication Publication Date Title
US9107330B2 (en) Apparatus for improved power distribution in an electrical component board
US8238109B2 (en) Flex-rigid wiring board and electronic device
US20100276188A1 (en) Method and apparatus for improving power gain and loss for interconect configurations
JP5339384B2 (en) Laminated capacitor and integrated circuit board
US6784377B2 (en) Method and structure for repairing or modifying surface connections on circuit boards
US11393737B2 (en) Electronic equipment
US9462703B2 (en) Solder void reduction between electronic packages and printed circuit boards
KR101693747B1 (en) Electronic components embedded substrate and manufacturing method thereof
KR20150064976A (en) Printed circuit board and manufacturing method thereof
WO2010129002A1 (en) Method and apparatus for improving power and loss for interconect configurations
JP2008130955A (en) Multilayer wiring board device with built-in components and manufacturing method therefor
KR101167453B1 (en) A printed circuit board comprising embeded electronic component within and a method for manufacturing
JP2007027472A5 (en)
KR102107033B1 (en) Heat Dissipation
KR20140060115A (en) Printed circuit board and manufacturing the same
CN209861251U (en) Circuit board
WO2008117213A2 (en) An assembly of at least two printed circuit boards and a method of assembling at least two printed circuit boards
JP6839099B2 (en) Manufacturing method of component-embedded board and component-embedded board
KR101580355B1 (en) Semiconductor Package and Manufacturing Method for the same
EP3346809A1 (en) Electronic circuit module and method for testing electronic circuit module
KR20110122044A (en) Substrate for a semiconductor package and manufacturing method thereof
JP2008181938A (en) Conductive sheet and electronic apparatus using this conductive sheet
KR20140126571A (en) Circuit Board
KR20120023940A (en) Chip on board package using anodizing and manufacturing method of the same

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20111201

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR

DAX Request for extension of the european patent (deleted)
A4 Supplementary search report drawn up and despatched

Effective date: 20130502

RIC1 Information provided on ipc code assigned before grant

Ipc: H05K 3/30 20060101ALI20130424BHEP

Ipc: H05K 1/18 20060101AFI20130424BHEP

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20130801