JP2011154117A - Method for designing semiconductor device, method for manufacturing semiconductor device, apparatus for designing semiconductor, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct a mask pattern while considering the position of a projection pattern formed on a substrate upon designing the mask pattern for forming a diffusion area in a substrate. <P>SOLUTION: First, first pattern information representing a first pattern is acquired (step S10), wherein the first pattern is a projection pattern formed on a substrate and is a gate electrode in one embodiment. Then second pattern information representing a second pattern is acquired (step S20), wherein the second pattern is a mask pattern for forming a diffusion area by injecting impurities into the substrate, and is a resist pattern in the embodiment. Then, whether or not the position of an edge of the second pattern is to be corrected is determined based on the distance from the edge of the second pattern to an edge of the first pattern, and the position of the edge of the second pattern is corrected in accordance with the determination result (steps 40, 50). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device design method having a convex pattern and a diffusion layer on a substrate, a semiconductor device manufacturing method, a semiconductor design device, and a program.

  Currently, semiconductor devices are being miniaturized. For this reason, in the process of exposing and developing the photoresist film, the pattern of the photomask cannot be directly transferred to the photoresist film. Therefore, after designing the pattern of the semiconductor device, the pattern is corrected in consideration of deformation in the exposure and development processes (OPC correction). In this OPC correction, for example, a portion where patterns are close to each other in the same layer is extracted, and correction is performed on this portion.

  Japanese Patent Application Laid-Open No. HEI 10-110826 responds to the deformation of the pattern of the photoresist film on the interlayer insulating film due to reflection of light at the time of exposure from the substrate side circuit pattern located below the interlayer insulating film. It is disclosed to correct the pattern of a photoresist film on an interlayer insulating film. Specifically, the position of the focal point of the reflected light is obtained based on the level difference due to the substrate-side circuit pattern, the thickness of the interlayer insulating film, and the thickness of the film that becomes the substrate-side circuit pattern. Then, the photoresist film pattern is corrected in a predetermined region including the focal point.

  In Patent Document 2, the opening of the photoresist film is likely to be deformed when the opening is dense, and a dummy opening is also formed in a region where a circuit pattern is not formed in order to suppress the deformation. Is disclosed.

JP 2004-191596 A JP 2003-188111 A

  As described above, when a mask pattern is formed by exposure and development, the actually formed mask pattern often deviates from the design shape. Therefore, as described above, OPC correction is generally performed. However, as a result of studies by the present inventor, when the miniaturization of the semiconductor device progresses, when designing a mask pattern for injecting impurities into the substrate or a structure (for example, a gate electrode) thereon, the first conductivity type impurity If the shape of the mask pattern is not corrected in consideration of the distance from the portion where the impurity is implanted to the mask pattern, the region into which the second conductivity type impurity is implanted protrudes from the mask pattern, or the first conductivity type impurity is removed. It has been found that the region to be implanted is covered by the mask pattern.

According to the present invention, obtaining a first pattern information indicating a first pattern formed on a substrate and introduced with an impurity of a first conductivity type;
Obtaining second pattern information indicating a second pattern which is a pattern of a mask when implanting impurities into the substrate;
Based on the distance from the edge of the second pattern to the edge of the first pattern, it is determined whether to correct the position of the edge of the second pattern, and the position of the edge of the second pattern is determined according to the determination result. A process of correcting,
A method of designing a semiconductor device is provided.

  According to the present invention, it is determined whether to correct the position of the edge of the second pattern based on the distance from the edge of the second pattern to the edge of the first pattern. For this reason, it can suppress that the area | region where the 2nd conductivity type impurity is inject | poured protrudes from a mask pattern, or the area | region which should implant 1st conductivity type impurity is covered with a mask pattern.

According to the present invention, obtaining a first pattern information indicating a first pattern formed on a substrate and introduced with an impurity of a first conductivity type;
Obtaining second pattern information indicating a second pattern which is a pattern of a mask when implanting impurities into the substrate;
Based on the distance from the edge of the second pattern to the edge of the first pattern, it is determined whether to correct the position of the edge of the second pattern, and the position of the edge of the second pattern is determined according to the determination result. A process of correcting,
Producing a photomask for projecting the second pattern after correction;
Forming the first pattern on a substrate;
Forming a resist film on the substrate and the first pattern;
Exposing the resist film using the photomask and then developing the resist pattern; and
Implanting impurity ions into the substrate using the resist pattern as a mask;
A method for manufacturing a semiconductor device is provided.

According to the present invention, a first pattern acquisition unit that acquires first pattern information indicating a first pattern formed on a substrate and introduced with an impurity of a first conductivity type;
A second pattern acquisition unit for acquiring second pattern information indicating a second pattern which is a pattern of a mask when impurities are implanted into the substrate;
Based on the distance from the edge of the second pattern to the edge of the first pattern, it is determined whether to correct the position of the edge of the second pattern, and the position of the edge of the second pattern is determined according to the determination result. A correction processing unit to correct;
A semiconductor design apparatus is provided.

According to the present invention, there is provided a program for causing a base computer to function as a semiconductor design device,
On the computer,
A function of obtaining first pattern information indicating a first pattern formed on a substrate and introduced with an impurity of a first conductivity type;
A function of acquiring second pattern information indicating a second pattern which is a pattern of a mask when implanting impurities into the substrate;
Based on the distance from the edge of the second pattern to the edge of the first pattern, it is determined whether to correct the position of the edge of the second pattern, and the position of the edge of the second pattern is determined according to the determination result. A function to correct,
A program for realizing the above is provided.

  According to the present invention, it is possible to prevent the region into which the second conductivity type impurity is implanted from protruding from the mask pattern, or the region to be implanted with the first conductivity type impurity from being covered with the mask pattern.

3 is a flowchart illustrating a method for designing a semiconductor device according to the first embodiment. It is a top view which shows the structure of the semiconductor device designed by 1st Embodiment. It is AA 'sectional drawing of FIG. It is a top view which shows the shape of the resist pattern after correction | amendment. It is a block diagram which shows the function structure of the semiconductor design apparatus for performing the process shown in FIG. It is a top view which shows the structure of the semiconductor device designed by 2nd Embodiment. It is a top view which shows the shape of the resist pattern after correction | amendment. It is a top view which shows the structure of the semiconductor device which concerns on 3rd Embodiment. It is a top view for demonstrating the design method of the semiconductor device which concerns on 4th Embodiment. FIG. 10 is a cross-sectional view taken along line AA ′ of FIG. 9. It is a top view which shows the shape of the resist pattern after correction | amendment. It is a top view for demonstrating the design method of the semiconductor device which concerns on 5th Embodiment. It is a top view for demonstrating the design method of the semiconductor device which concerns on 6th Embodiment. It is a top view which shows the shape of the resist pattern after correction | amendment. It is a top view for demonstrating the design method of the semiconductor device which concerns on 7th Embodiment. It is a top view which shows the shape of the resist pattern after correction | amendment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a flowchart showing a method for designing a semiconductor device according to the first embodiment. This semiconductor device design method includes the following steps. First, first pattern information indicating the first pattern is acquired (step S10). The first pattern is a pattern of a portion formed on the substrate and into which the first conductivity type impurity is introduced. For example, the first pattern is a diffusion region of the first conductivity type and a gate electrode into which the first conductivity type impurity is to be implanted. . Next, second pattern information indicating the second pattern is acquired (step S20). The second pattern is a mask pattern when impurities are implanted into the substrate, and is the resist pattern 200 in this embodiment. Next, based on the distance from the edge of the second pattern to the edge of the first pattern, it is determined whether or not to correct the position of the edge of the second pattern, and the position of the edge of the second pattern is corrected according to the determination result. (Steps S40, 50). Hereinafter, it demonstrates in detail using FIGS. 1-4.

  First, the configuration of the semiconductor device designed according to the present embodiment will be described with reference to the plan view of FIG. 2 and the AA ′ cross-sectional view of FIG. This semiconductor device includes a substrate 100, an element isolation region 110, diffusion regions 120 and 130, and a gate electrode 140. The substrate 100 is a semiconductor substrate such as a silicon substrate. The element isolation region 110 has, for example, an STI (Shallow Trench Isolation) structure, and is a region in which an insulating film such as a silicon oxide film is embedded in a groove formed in the substrate 100. The diffusion region 120 is the first conductivity type, and is a region that becomes a source and a drain of the transistor. The gate electrode 140 is a convex pattern formed on the substrate 100, and is a portion where an impurity of the first conductivity type is to be implanted. The diffusion region 130 is of the second conductivity type, and may be, for example, a region for applying a substrate potential of a transistor having the gate electrode 140 and the diffusion region 120, or a region to be a source and a drain of the second conductivity type transistor. May be.

  In the example shown in this figure, when the first conductivity type impurity ions are implanted into the diffusion region 120 and the gate electrode 140, the diffusion region 130 needs to be covered with the resist pattern 200. On the other hand, the diffusion region 130 is close to the diffusion region 120 and the gate electrode 140. In this case, when the mask pattern 200 is actually formed, the gate electrode 140 and the diffusion region 120, which are regions where the first conductivity type impurity should be implanted, are covered with the mask pattern 200, or the second conductivity type impurity is removed. There is a possibility that the diffusion region 130 to be implanted protrudes from the mask pattern 200.

For example, in the example shown in FIG. 2, the distance t ₁ from the edge 202 which is a part of the outline of the resist pattern 200 to the edge 142 of the gate electrode 140 is shortened. In this case, the exposure light may be reflected on the side surface constituting the edge 142 of the gate electrode 140 and may be incident on the side surface constituting the edge 202 of the resist pattern 200. When the resist pattern 200 is a positive type, when this reflected light is incident on the side surface, a recess 203 is formed on the side surface of the resist pattern 200 as shown in FIG. 3, and the resist pattern 200 becomes thin. When the resist pattern 200 becomes thinner, the diffusion region 130 may protrude from the mask pattern 200, and in the worst case, the resist pattern 200 may fall. This tendency becomes particularly remarkable when the design value of the width of the resist pattern 200 is narrower than, for example, the second reference. The second reference is set in a range smaller than the wavelength of light for exposure, for example. For example, when KrF is used as the light source for exposure, the second reference is, for example, 240 nm, 150 nm, or 135 nm.

On the other hand, in the present embodiment, a region where the distance t ₁ is equal to or smaller than the first reference is extracted, and the position of the edge 202 of the resist pattern 200 is corrected in the extracted region. Specifically, as shown in FIG. 4, the edge 202 is moved in the direction in which the resist pattern 200 becomes thicker. This process may be performed, for example, when the design value of the width of the resist pattern 200 is narrower than, for example, the second reference.

  The resist pattern 200 covers the diffusion region 130, but the diffusion region 130 is the substrate 100. The substrate 100 has a higher light reflectance than the element isolation region 110. Therefore, the portion of the resist pattern 200 that covers the diffusion region 130 is likely to be thinner than the portion that is located on the element isolation region 110. Therefore, the process shown in FIG. 4 is performed on a portion of the resist pattern 200 that covers the diffusion region 130.

  Next, the flow shown in FIG. 1 will be described in detail. First, first pattern information indicating the pattern of the gate electrode 140 is acquired (step S10). Next, second pattern information indicating the pattern of the resist pattern 200 is acquired (step S20).

  Next, OPC (Optical Proximity Correction) correction is performed on the resist pattern 200 (step S30). This OPC correction is a process of thinning a part of the resist pattern 200, for example. The region in which such correction is performed is a region (not shown) in which the resist pattern 200 becomes thicker during exposure due to the proximity of the resist patterns 200, and is other than the region in which steps S40 and S50 are performed. Is one of the areas.

Next, a region where the distance t ₁ from the edge 202 of the resist pattern 200 to the edge 142 of the gate electrode 140 is not more than the first reference is extracted (step S40). In this process, a region including the edge 202 of the resist pattern 200 shown in FIGS. 2 and 3 is extracted. At this time, it is preferable to perform the process shown in step S40 only for an area where the width of the resist pattern 200 is narrower than the second reference. Further, it is preferable to perform the process shown in step S40 only on the region of resist pattern 200 that covers substrate 100 (for example, diffusion region 130). That is, the process shown in step S40 is not performed on a portion of the resist pattern 200 that does not cover the substrate 100 when viewed in the width direction.

Next, in the region extracted in step S40, the edge 202 of the resist pattern 200 is moved in the direction in which the resist pattern 200 becomes thick (step S50). The moving direction of the edge 202 is a direction in which the edge 202 approaches the edge 142 of the gate electrode 140. On the other hand, there is a case where a third reference, which is an interval to be secured between the resist pattern 200 and the gate electrode 140, is defined. In this case, it is necessary to move the edge 202 of the resist pattern 200 on condition that the distance t ₁ from the edge 202 of the resist pattern 200 to the edge 142 of the gate electrode 140 is equal to or greater than the third reference. Thus, even after the edge 202 is moved, the distance t ₂ (shown in FIG. 4) from the edge 202 to the edge 142 of the gate electrode 140 becomes equal to or greater than the third reference.

  Thereafter, a photomask having a pattern corrected in step S50 is created. Then, an element isolation region 110, a gate insulating film (not shown), and a gate electrode 140 are actually formed on the substrate 100. Next, a resist film is formed over the substrate 100, the element isolation region 110, and the gate electrode 140, and this resist film is exposed using the above-described photomask. Then, a resist pattern 200 is formed by developing the resist film. Next, impurity ions of the first conductivity type are implanted into the substrate 100 using the resist pattern 200 as a mask. Thereby, the diffusion region 120 is formed.

  Note that after step S30, the width of both ends of the resist pattern 200 having a width equal to or smaller than the second reference may be widened on the condition that the width is located on the element isolation region 110. If it does in this way, it will become difficult for the resist pattern 200 to fall down. This process is performed in parallel with the processes performed in steps S40 and S50, for example.

  FIG. 5 is a block diagram showing a functional configuration of the semiconductor design apparatus for performing the processing shown in FIG. The semiconductor design apparatus includes a first pattern acquisition unit 410, a second pattern acquisition unit 420, an OPC processing unit 430, and a correction processing unit 440. The first pattern acquisition unit 410 performs the process shown in step S10 of FIG. The second pattern acquisition unit 420 performs the process shown in step S20 of FIG. The OPC processing unit 430 performs the process shown in step S30 of FIG. The correction processing unit 440 performs the processing shown in steps S40 and S50 in FIG.

  In FIG. 5, the configuration of parts not related to the essence of the present invention is omitted. Each component of the semiconductor design apparatus shown in FIG. 5 is not a hardware unit configuration but a functional unit block. Each component of the semiconductor design apparatus is centered on an arbitrary computer CPU, memory, a program for realizing the components shown in the figure loaded in the memory, a storage unit such as a hard disk for storing the program, and a network connection interface. It is realized by any combination of hardware and software. Note that this program may be installed in the computer via a removable medium.

  Next, the operation and effect of this embodiment will be described. According to the present embodiment, when it is assumed that the width of the resist pattern 200 is narrowed because the gate electrode 140 is located nearby, the resist pattern 200 can be corrected so that the width of the resist pattern 200 is thick. . Therefore, it is possible to suppress the width of the resist pattern 200 from becoming smaller than a desired value. Thereby, it can suppress that the resist pattern 200 falls, for example.

(Second Embodiment)
6 and 7 are plan views for explaining a method for designing a semiconductor device according to the second embodiment, and correspond to FIGS. 2 and 4 in the first embodiment, respectively. In the present embodiment, as shown in FIG. 6, the plurality of gate electrodes 140 and 144 are provided in a direction parallel to each other and intersecting the edge 202 of the resist pattern 200 (for example, a direction orthogonal). The gate electrode 144 extends closer to the edge 202 of the resist pattern 200 than the gate electrode 140. A distance t ₃ from the edge of the gate electrode 144 to the edge 202 of the resist pattern 200 is a distance to be secured between the resist pattern 200 and the gate electrode 140 in the state before the correction shown in Step S50 of FIG. It is almost equal to the third standard.

  In such a case, the correction processing unit 440 of the semiconductor design apparatus shown in FIG. 5 applies the gate electrode 144 in the edge 202 of the resist pattern 200 as shown in FIG. 7 in the process shown in step S50 of FIG. The facing portion is not moved, but only the portion of the edge 202 of the resist pattern 200 facing the gate electrode 140 is moved to widen the width of the resist pattern 200.

  According to this embodiment, the same effect as that of the first embodiment can be obtained. Further, since the portion of the edge 202 of the resist pattern 200 whose distance from the gate electrode is substantially equal to the third reference is not moved, the distance from the edge of the gate electrode 144 to the edge 202 of the resist pattern 200 is set to the third value. It can be maintained above the standard.

(Third embodiment)
FIG. 8 is a plan view showing the configuration of the semiconductor device according to the third embodiment. The semiconductor device according to the first embodiment except that the diffusion region 120 is not located in the vicinity of the diffusion region 130 and the gate electrode 140 extends in parallel with the edge 202 of the resist pattern 200. The configuration is similar to that of a semiconductor device.

  Even when designing such a semiconductor device, the process shown in FIG. 1 is performed using the semiconductor design device shown in FIG. 5, as in the first embodiment. As a result, when it is assumed that the width of the resist pattern 200 becomes narrow due to the gate electrode 140 being positioned nearby, the resist pattern 200 can be corrected so that the width of the resist pattern 200 becomes thick.

(Fourth embodiment)
FIG. 9 is a plan view for explaining a method for designing a semiconductor device according to the fourth embodiment, and FIG. 10 is a cross-sectional view taken along the line AA ′ of FIG. The semiconductor device designed according to this embodiment is the same as that of the first embodiment. In this embodiment, the shape of the resist pattern 201 when the second conductivity type impurity ions are implanted into the diffusion region 130 is corrected.

  The resist pattern 201 covers the diffusion region 120 and the gate electrode 140 and has an opening 204. The opening 204 is provided to expose the diffusion region 130 and is provided on the diffusion region 130 and its periphery.

  When the width w of the opening 204 is narrow and equal to or smaller than the fourth reference, even if exposure and development are performed on the resist film to be the resist pattern 201, a portion where the opening 204 should be formed may not be opened. In such a case, it is necessary to increase the width w of the opening 204. However, if the width w of the opening 204 is unconditionally widened, a part of the gate electrode 140 may be exposed by the opening 204. The fourth reference is set in a range smaller than the wavelength of the exposure light, for example. For example, when KrF is used as a light source for exposure, the fourth reference is, for example, 240 nm, 150 nm, or 135 nm.

Therefore, in the present embodiment, when the width w of the opening 204 is equal to or smaller than the fourth reference, the distance t ₄ from the edge 206 that is the portion facing the gate electrode 140 in the outline of the opening 204 to the gate electrode 140. Is determined to be greater than or equal to a fifth reference, which is an interval to be secured between the opening 204 of the resist pattern 201 and the gate electrode 140. And if the distance t ₄ is the fifth reference above, as shown in FIG. 11, to move the edge 206 in the direction of the width w of the opening 204 becomes thick. In this case, the distance t ₅ from the edge 206 in the state after moving the edge 206 to the edge 142 of the gate electrode 140 so that a fifth criterion above. This process is performed by the correction processing unit 440 of the semiconductor design apparatus shown in FIG. This process is performed in place of steps S40 and S50 in the flowchart of FIG.

  According to this embodiment, when the width of the opening 204 to be formed in the resist pattern 200 is too small and it is assumed that the opening 204 is not formed in the exposure and development processes, the gate electrode 140 is affected. The opening width can be widened in a range that does not exist. Note that the processing shown in the present embodiment is preferably performed together with the processing shown in the first embodiment.

(Fifth embodiment)
FIG. 12 is a plan view for explaining the method for designing a semiconductor device according to the fifth embodiment. The semiconductor device designed according to this embodiment is the same as the semiconductor device shown in the second embodiment. And in a state before correcting the position of the edge 206 of the opening 204 of the resist pattern 201, the distance t ₆ from the edge of the gate electrode 144 to the edge 206 of the opening 204 and the fifth reference shown in the fourth embodiment Almost equal.

  In such a case, the correction processing unit 440 of the semiconductor design apparatus shown in FIG. 5 moves the portion of the edge 206 of the opening 204 facing the gate electrode 144 in the correction processing shown in the fourth embodiment. Instead, only the part of the edge 206 facing the gate electrode 140 is moved to widen the width of the opening 204.

  According to this embodiment, the same effect as that of the fourth embodiment can be obtained. Further, since the portion of the edge 206 of the opening 204 of the resist pattern 200 that is substantially equal to the fifth reference is not moved, the distance from the edge of the gate electrode 144 to the edge 206 of the opening 204 is It can be maintained above 5 criteria.

(Sixth embodiment)
13 and 14 are plan views for explaining the semiconductor device design method according to the sixth embodiment. In the semiconductor device designed according to the present embodiment, the second conductivity type diffusion region 132 is formed between each of the three or more convex patterns 146 extending in parallel with each other. The convex pattern 146 is, for example, a dummy gate wiring, and either the first conductivity type impurity ions or the second conductivity type impurity ions may be introduced, or the impurity ions may not be introduced.

When the resist pattern 205 for implanting the first conductivity type impurity ions is designed using a normal semiconductor design tool, a plurality of resist patterns 205 are formed so as not to overlap the convex pattern 146 as shown in FIG. The diffusion regions 132 are individually provided. However, in such a pattern, when the distance t ₁ from the edge of the resist pattern 205 to the edge of the convex pattern 146 is short, the resist pattern 205 is thinned by the operation described with reference to FIG. 3 in the first embodiment. Sometimes.

  On the other hand, in this embodiment, since the impurity ions do not have to be introduced into the convex pattern 146, correction is performed so as to combine the plurality of resist patterns 205 as shown in FIG. That is, the corrected resist pattern 205 covers the plurality of diffusion regions 132 and the convex pattern 146 located between them.

  This correction processing is performed by the correction processing unit 440 shown in FIG. 5 as, for example, part of steps S40 and S50 in FIG. This process is performed together with the process shown in the first embodiment and the process shown in the fourth embodiment.

  Also according to this embodiment, the same effect as that of the first embodiment can be obtained. Further, even when the second conductivity type diffusion region 132 is formed between each of the three or more convex patterns 146 extending in parallel with each other, the resist pattern 205 can be prevented from being thinned.

(Seventh embodiment)
15 and 16 are plan views for explaining the semiconductor device design method according to the seventh embodiment. The semiconductor device designed according to this embodiment is the same as that of the sixth embodiment. In this embodiment, the resist pattern 207 when the second conductivity type impurity ions are implanted into the diffusion region 132 is corrected.

  When the resist pattern 207 for implanting the second conductivity type impurity ions into the diffusion region 132 is designed using a normal semiconductor design tool, as shown in FIG. 15, the resist pattern 207 has an opening 208 having a convex shape. The plurality of diffusion regions 132 are individually provided so as not to overlap the pattern 146. In such a case, as in the fourth embodiment, when the width of the opening 208 is narrow and equal to or smaller than the fourth reference, the opening 208 is formed even if the resist film to be the resist pattern 207 is exposed and developed. There is a possibility that the part to be done does not open.

  On the other hand, in this embodiment, since either the first conductivity type impurity ions or the second conductivity type impurity ions may be introduced into the convex pattern 146, a plurality of impurity ions as shown in FIG. Correction is performed so that the openings 208 are combined into one. That is, the corrected opening 208 includes a plurality of diffusion regions 132 and a convex pattern 146 located between them.

  This correction process is performed by the correction processing unit 440 shown in FIG. This process is performed together with the process shown in the first embodiment, the process shown in the fourth embodiment, and the process shown in the sixth embodiment.

  According to this embodiment, the same effect as that of the fourth embodiment can be obtained. Further, even when the second conductivity type diffusion region 132 is formed between each of the three or more convex patterns 146 extending in parallel with each other, the opening 208 should be formed in the resist pattern 207. It can suppress that an area | region does not open.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

100 substrate 110 element isolation region 120 diffusion region 130 diffusion region 132 diffusion region 140 gate electrode 142 edge 144 gate electrode 146 pattern 200 resist pattern 201 resist pattern 202 edge 203 recess 204 opening 205 resist pattern 206 edge 207 resist pattern 208 opening 410 first Pattern acquisition unit 420 Second pattern acquisition unit 430 OPC processing unit 440 Correction processing unit

Claims (15)

Obtaining first pattern information indicating a first pattern formed on the substrate and introduced with an impurity of the first conductivity type;
Obtaining second pattern information indicating a second pattern which is a pattern of a mask when implanting impurities into the substrate;
Based on the distance from the edge of the second pattern to the edge of the first pattern, it is determined whether to correct the position of the edge of the second pattern, and the position of the edge of the second pattern is determined according to the determination result. A process of correcting,
A method for designing a semiconductor device comprising: The method for designing a semiconductor device according to claim 1,
In the step of correcting the position of the edge of the second pattern, an area where the distance from the edge of the second pattern to the edge of the first pattern is not more than a first reference is extracted, and the second pattern is extracted in the extracted area Of designing a semiconductor device for correcting the position of the edge of the semiconductor device. The method for designing a semiconductor device according to claim 2,
The edge of the second pattern is the outline of the second pattern;
The method for designing a semiconductor device, wherein the second pattern is a pattern of a mask when an impurity of a first conductivity type is implanted into the substrate. The method for designing a semiconductor device according to claim 3,
A method of designing a semiconductor device, wherein, in the step of correcting the position of the edge of the second pattern, the edge of the second pattern is moved in a direction in which the second pattern becomes thicker. The method for designing a semiconductor device according to claim 4,
A design method of a semiconductor device for correcting the position of the edge of the second pattern when the width of the second pattern is narrower than a second reference. In the design method of the semiconductor device as described in any one of Claims 2-5,
The substrate has a semiconductor region and an element isolation region that separates the semiconductor region from other regions,
A method for designing a semiconductor device, wherein the correction is performed on a portion of the second pattern that covers the semiconductor region. In the design method of the semiconductor device as described in any one of Claims 2-6,
A method for designing a semiconductor device, wherein the semiconductor device has a third reference value that is smaller than the first reference value and is an interval to be secured between the second pattern and the first pattern. The method for designing a semiconductor device according to claim 7,
In the step of correcting the position of the edge of the second pattern, the position of the edge of the second pattern is corrected so that the distance between the diffusion region and the first pattern in the extracted region is equal to or greater than the third reference. For designing a semiconductor device. The method for designing a semiconductor device according to claim 1,
The second pattern has an opening;
The edge of the second pattern is the outline of the opening;
The method for designing a semiconductor device, wherein the second pattern is a pattern of a mask when an impurity of a second conductivity type is implanted into the substrate. The method for designing a semiconductor device according to claim 9,
In the step of correcting the position of the edge of the second pattern, the width of the opening is equal to or smaller than a fourth reference, and the distance from the edge of the second pattern to the edge of the first pattern is the second pattern. And an edge of the second pattern in a direction in which the opening becomes thicker when the gap is larger than a fifth reference which is an interval to be secured between the first pattern and the first pattern. In the design method of the semiconductor device as described in any one of Claims 1-10,
In addition to the step of correcting the position of the edge of the second pattern, a method for designing a semiconductor device comprising the step of performing OPC correction on the second pattern and narrowing the second pattern in any region. In the design method of the semiconductor device as described in any one of Claims 1-11,
A method of designing a semiconductor device, wherein the first pattern is a gate electrode. Obtaining first pattern information indicating a first pattern formed on the substrate and introduced with an impurity of the first conductivity type;
Obtaining second pattern information indicating a second pattern which is a pattern of a mask when implanting impurities into the substrate;
Based on the distance from the edge of the second pattern to the edge of the first pattern, it is determined whether to correct the position of the edge of the second pattern, and the position of the edge of the second pattern is determined according to the determination result. A process of correcting,
Producing a photomask for projecting the second pattern after correction;
Forming the first pattern on a substrate;
Forming a resist film on the substrate and the first pattern;
Exposing the resist film using the photomask and then developing the resist pattern; and
Implanting impurity ions into the substrate using the resist pattern as a mask;
A method for manufacturing a semiconductor device comprising: A first pattern acquisition unit configured to acquire first pattern information indicating a first pattern formed on a substrate and introduced with an impurity of a first conductivity type;
A second pattern acquisition unit for acquiring second pattern information indicating a second pattern which is a pattern of a mask when impurities are implanted into the substrate;
Based on the distance from the edge of the second pattern to the edge of the first pattern, it is determined whether to correct the position of the edge of the second pattern, and the position of the edge of the second pattern is determined according to the determination result. A correction processing unit to correct;
A semiconductor design apparatus comprising: A program for causing a computer to function as a semiconductor design device,
On the computer,
A function of obtaining first pattern information indicating a first pattern formed on a substrate and introduced with an impurity of a first conductivity type;
A function of acquiring second pattern information indicating a second pattern which is a pattern of a mask when implanting impurities into the substrate;
Based on the distance from the edge of the second pattern to the edge of the first pattern, it is determined whether to correct the position of the edge of the second pattern, and the position of the edge of the second pattern is determined according to the determination result. A function to correct,
A program that realizes

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