JP2005332968A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To remove a cause that a crystal defect occurs, to reduce man-hours and cost, to flatten a surface, and to suppress thermal hysteresis of impurity diffusion in mask alignment. <P>SOLUTION: In the manufacturing method of a semiconductor device, impurity is diffused for a plurality of times on a semiconductor substrate 1 and diffusion layers are sequentially formed. The semiconductor substrate 1 is previously etched and an alignment mark (recessed part 1a) is formed. A mask is positioned when respective impurities are diffused with the alignment mark as a reference. The semiconductor substrate 1 is an Si substrate, for example. An alignment mark forming position on the semiconductor substrate 1 is fixed irrespective of a model. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an improvement in a mask alignment method when a diffusion layer is sequentially formed by a plurality of impurity diffusions.

  In the manufacture of a semiconductor device, a desired circuit function is built on a semiconductor substrate by combining a photoresist process, an etching process, an impurity diffusion process, and the like and repeating this many times. The alignment accuracy of the photomask at this time is an important factor for determining the integration degree of the semiconductor device. If the alignment accuracy of the mask can be improved, it is expected that the integration degree can be further improved.

  Under such circumstances, an alignment mark for aligning the mask position of each layer during photolithography is necessary. Conventionally, for example, as the first alignment mark, an oxide film is formed on the diffusion layer when the first diffusion layer is formed. An alignment mark is manufactured using a step difference from the semiconductor substrate that can be formed. A conventional mask alignment method will be described below.

  FIG. 2 illustrates a conventional alignment method. First, as shown in FIG. 2A, an oxide film 102 is formed on a semiconductor substrate 101 such as a Si substrate, and FIG. As shown, a resist pattern 103 having an opening 103 a corresponding to the first diffusion layer is formed on the oxide film 102. Next, as shown in FIG. 2C, the oxide film 102 is etched using the resist pattern 103 as a mask to form an opening 102a. As shown in FIG. 2D, ion implantation or deposition is performed. Impurity diffusion is performed to form the first diffusion layer 104.

  After forming the first diffusion layer 104 as described above, an oxide film 105 is formed on the first diffusion layer 104 as shown in FIG. At this time, when the surface of the first diffusion layer 104 is oxidized to form the oxide film 105, the surface of the first diffusion layer 104 recedes from the surface of the semiconductor substrate 101, and the surface of the semiconductor substrate 101 and the first diffusion layer are diffused. A step is formed between the surfaces of the layer 104. Conventionally, this step is used as an alignment mark and used as a reference for mask alignment in impurity diffusion for forming the second diffusion layer.

That is, when a step is formed between the surface of the semiconductor substrate 101 and the surface of the first diffusion layer 104, the step is recognized as a square alignment mark A as shown in FIG. It becomes possible. Therefore, when the resist pattern for forming the second diffusion layer is patterned by the photolithographic technique, the alignment mark A is used as a positioning reference, and the second alignment layer is formed with respect to the alignment mark A as shown in FIG. The alignment mark B of the second diffusion layer forming mask is aligned, and a resist pattern 106 is formed.
JP-A-7-99147

  However, this conventional technique has several problems to be solved. First, according to the prior art, after the first diffusion layer 104 is formed, it is necessary to form an oxide film 105 on the surface thereof to form a step, but the oxidation of the diffusion layer 104 is caused by crystal defects. In addition, since the oxidation time is necessary, production takes a long time. Therefore, it is better not to oxidize the diffusion layer 104 if possible.

  In addition, in the manufacture of semiconductor devices, it is estimated that finer and shallower diffusion will be required in the future, but in that case, planarization of the surface and suppression of thermal history of impurity diffusion are essential technologies. Become. From this point of view, oxidation of the diffusion layer 104 is not preferable.

  Furthermore, in the prior art, the first alignment mark is formed by, for example, an embedded mask, but the mask cannot be used in all models even though the pattern position is fixed regardless of the model. . The reason is that the element pattern in the circuit is different for each model.

  The present invention has been proposed in view of such problems of the prior art, and it is not necessary to oxidize the surface of the diffusion layer for forming the alignment mark, and there is no deterioration in performance due to crystal defects. It is an object to provide a method for manufacturing a semiconductor device that requires less time. Further, the present invention can realize surface flattening and suppression of thermal history of impurity diffusion, and can suppress an increase in cost due to an increase in masks by using it as a mask common to all models. An object is to provide a method for manufacturing a semiconductor device.

  In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a diffusion layer is sequentially formed by performing impurity diffusion multiple times on a semiconductor substrate. The substrate is etched to form an alignment mark, and mask alignment is performed for each impurity diffusion with reference to the alignment mark.

  In the present invention, an oxide film is formed on the diffusion layer at the time of forming the first diffusion layer, and the alignment mark is not formed using the step difference from the semiconductor substrate formed at that time, but by separately etching the semiconductor substrate. An alignment mark is formed. In the subsequent impurity diffusion for forming the diffusion layer, mask alignment is performed with reference to the concave portion formed in the semiconductor substrate, so that oxidation of the surface of the diffusion layer is unnecessary. If oxidation of the surface of the diffusion layer is unnecessary, generation of crystal defects is avoided, and time for oxidation is unnecessary. Further, the surface can be planarized and the thermal history of impurity diffusion can be suppressed.

  Furthermore, since the alignment mark is performed separately from the formation of the diffusion layer, the formation position thereof is not limited and can be formed at an arbitrary place. Therefore, if the location where the alignment mark is made is fixed regardless of the model, only one mask is required for all models, and an increase in cost due to an increase in the mask is suppressed. Further, by repeatedly using the alignment mark, the area of the evaluation pattern on the semiconductor substrate is reduced, which leads to an increase in the number of products obtained from the semiconductor substrate having the same area.

  According to the present invention, it is not necessary to oxidize the surface of a diffusion layer for forming an alignment mark, and therefore, it is possible to provide a method for manufacturing a semiconductor device that does not deteriorate performance due to crystal defects and that requires a short manufacturing time. Is possible. In addition, according to the present invention, it is possible to realize surface flattening and suppression of thermal history of impurity diffusion, and it becomes possible to cope with finer and shallower diffusion, etc., as well as an increase in cost due to an increase in masks. It is possible to provide a method for manufacturing a semiconductor device capable of suppressing the above problem.

  Hereinafter, a method of manufacturing a semiconductor device to which the present invention is applied will be described in detail with reference to the drawings.

  In the present embodiment, in order to manufacture a semiconductor device, first, as shown in FIG. 1A, an oxide film 2 is formed on a semiconductor substrate 1 such as a Si substrate, and further as shown in FIG. Then, a resist pattern 3 having an opening 3 a corresponding to the position where the alignment mark is formed is formed on the oxide film 2.

  Next, as shown in FIG. 1C, the oxide film 2 is etched using the resist pattern 3 as a mask to form an opening, and the etching is further performed to etch the surface of the semiconductor substrate 1. A rectangular recess 1a is formed. The rectangular recess 1a formed in the semiconductor substrate 1 can be easily recognized and functions as an alignment mark. Although the depth of the concave portion 1a is arbitrary, it is preferable to set it appropriately in consideration of the fact that if it is too deep, it takes a long time for etching, and conversely, it becomes difficult to recognize if it is too shallow. The etching method for forming the recess 1a in the semiconductor substrate 1 may be either dry etching or wet etching. However, when dry etching capable of anisotropic etching is used, the contour of the recess 1a is sharp. Therefore, it can be easily recognized, which is preferable.

  In the present invention, the concave portion 1a of the semiconductor substrate 1 formed here is used as an alignment mark, and this is used as a reference for positioning, and then mask alignment is performed at a plurality of subsequent impurity diffusions. Hereinafter, a case where the first diffusion layer and the second diffusion layer are formed by impurity diffusion twice will be described as an example.

  As described above, the recess 1a is formed by etching in the semiconductor substrate 1 to produce an alignment mark, and then the first diffusion layer is formed. When forming the first diffusion layer, as shown in FIG. 1 (d), a resist layer 4 is formed on the oxide film 2, and the resist layer 4 is exposed and developed by mask exposure to form a first diffusion layer. The opening 4a is formed at the corresponding position. At the time of mask exposure for forming the opening 4a in the resist layer 4, as shown in FIG. 1D, the alignment mark 5 of the mask to be used coincides with the recess 1a of the semiconductor substrate 1 as a reference alignment mark. And align.

  After the opening 4a is formed in the resist layer 4 as described above, impurity diffusion is performed by ion implantation using the resist layer 4 as a mask as shown in FIG. 1E, and as shown in FIG. Corresponding to the opening 4 a of the layer 4, for example, a first diffusion layer 6 which is an N-type buried diffusion layer is formed. The first diffusion layer 6 can be formed by ion implantation through the oxide film 2 and annealing. If oxidation is not performed at the time of formation, generation of crystal defects is avoided, oxidation time is not required, and man-hours are reduced. Reduced. In addition, the flatness of the semiconductor device in which the first diffusion layer 6 is formed can be maintained, and the thermal history can be minimized.

  In the impurity diffusion for forming the first diffusion layer 6, the impurity diffusion is also performed in the recess 1 a of the semiconductor substrate 1 corresponding to the alignment mark 5 of the mask, and the N-type buried diffusion layer 7 is formed. Although formed but not oxidized at the time of formation, there is no step between the surface of the diffusion layer 7 and the surface of the etched semiconductor substrate 1, so that the N-type buried diffusion layer 7 recognizes the recess 1 a of the semiconductor substrate 1. It won't interfere with anything.

  After the formation of the first diffusion layer 6, a second diffusion layer is formed. The method for forming the second diffusion layer is the same as that for forming the first diffusion layer 6 above. That is, when forming the second diffusion layer, as shown in FIG. 1G, a resist layer 8 is formed on the oxide film 2, the resist layer 8 is exposed and developed by mask exposure, and the second diffusion layer is formed. An opening 8a is formed at a position corresponding to the layer. At the time of mask exposure for forming the opening 8a in the resist layer 8, as shown in FIG. 1G, the alignment mark 9 of the mask to be used coincides with the recess 1a of the semiconductor substrate 1 as a reference alignment mark. And align.

  After the opening 8a is formed in the resist layer 8 as described above, impurity diffusion is performed by ion implantation using the resist layer 8 as a mask as shown in FIG. 1 (h), and as shown in FIG. In correspondence with the opening 8a of the layer 8, for example, a second diffusion layer 10 which is a P-type buried diffusion layer is formed. The second diffusion layer 10 can be formed by ion implantation through the oxide film 2 and annealing. Further, since the second diffusion layer 10 to be formed is formed by mask alignment using the recess 1a of the semiconductor substrate 1 as an alignment mark, the second diffusion layer 10 of the second diffusion layer 10 is independent of the position of the first diffusion layer 6. The position can be formed with high accuracy.

  Further, when forming the third diffusion layer or less, the same process may be repeated using the concave portion 1a of the semiconductor substrate 1 as a reference for alignment. In addition to the formation of the diffusion layer, the concave portion 1a of the semiconductor substrate 1 can be used as an alignment mark in mask alignment in other photolithography processes.

  As described above, according to the present invention, the mask alignment accuracy can be improved, and the degree of integration of the semiconductor device can be improved. Moreover, since the surface can be flattened and the thermal history of the diffusion layer can be suppressed, the introduction of the technique of the present invention is useful for future process development.

  Further, in the above process, the recess 1a of the semiconductor substrate 1 to be the alignment mark is formed separately and completely independently from the first diffusion layer, so the position where the recess 1a is formed is determined regardless of the model. If this is the case, only one mask may be used to form the recesses 1a that will serve as alignment marks, regardless of which model is manufactured. Therefore, an increase in expenses due to an increase in the mask can be suppressed.

1 shows an example of a manufacturing process of a semiconductor device to which the present invention is applied, (a) is a sectional view showing an oxide film forming step, (b) is a sectional view showing a resist pattern forming step, and (c) is a semiconductor substrate. Sectional view showing etching process and plan view showing shape of recess of semiconductor substrate serving as alignment mark, (d) is a sectional view showing a resist pattern forming process for forming the first diffusion layer and alignment state of alignment mark (E) is a cross-sectional view showing an impurity diffusion step, (f) is a cross-sectional view showing a formation state of the first diffusion layer, and (g) is a resist pattern formation for forming the second diffusion layer. FIG. 6 is a cross-sectional view showing the process and a plan view showing the alignment state of the alignment mark, (h) is a cross-sectional view showing the impurity diffusion process, and (i) is a cross-sectional view showing the formation state of the second diffusion layer. An example of the manufacturing process of the conventional semiconductor device is shown, (a) is sectional drawing which shows an oxide film formation process, (b) is sectional drawing which shows the resist pattern formation process for the 1st diffused layer formation, (C) is a cross-sectional view showing an oxide film etching step, (d) is a cross-sectional view showing an impurity diffusion step, (e) is a cross-sectional view showing an oxidation step on the surface of the first diffusion layer, and a step formed thereby ( (F) is a cross-sectional view showing a resist pattern forming step in forming a second diffusion layer, and a plan view showing the alignment state of the alignment mark at that time.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 1a Recessed part (alignment mark), 2 oxide film, 3 resist pattern, 4 resist layer, 5 alignment mark, 6 1st diffusion layer, 7 1st diffusion layer, 8 resist layer, 9 alignment mark, 10 Second diffusion layer, 11 Second diffusion layer

Claims (3)

A method of manufacturing a semiconductor device in which a diffusion layer is sequentially formed by performing impurity diffusion a plurality of times on a semiconductor substrate,
A method of manufacturing a semiconductor device, wherein an alignment mark is formed by etching a semiconductor substrate in advance, and mask alignment is performed for each impurity diffusion with reference to the alignment mark.   The method of manufacturing a semiconductor device according to claim 1, wherein the alignment mark is formed as a concave portion of the semiconductor substrate. 3. The method of manufacturing a semiconductor device according to claim 1, wherein each diffusion layer is formed by impurity diffusion from an oxide film formed on a semiconductor substrate.

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