JP2011146625A - High-frequency circuit board device - Google Patents

High-frequency circuit board device Download PDF

Info

Publication number
JP2011146625A
JP2011146625A JP2010007987A JP2010007987A JP2011146625A JP 2011146625 A JP2011146625 A JP 2011146625A JP 2010007987 A JP2010007987 A JP 2010007987A JP 2010007987 A JP2010007987 A JP 2010007987A JP 2011146625 A JP2011146625 A JP 2011146625A
Authority
JP
Japan
Prior art keywords
ceramic substrate
substrate
resin
bga
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2010007987A
Other languages
Japanese (ja)
Other versions
JP5581701B2 (en
Inventor
Kazuhiro Yamaguchi
和宏 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2010007987A priority Critical patent/JP5581701B2/en
Publication of JP2011146625A publication Critical patent/JP2011146625A/en
Application granted granted Critical
Publication of JP5581701B2 publication Critical patent/JP5581701B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a necessary circuit scale can not be formed on a ceramic substrate with a BGA connection structure having the ceramic substrate and a resin substrate connected by many bumps since thermal stress operating on bumps positioned at an outer edge portion becomes larger as the ceramic substrate becomes larger in size so that a connection portion is broken. <P>SOLUTION: When the ceramic substrate 1 is bump-joined with the resin substrate 6, a BGA formation region is defined as a size range wherein the bump connection portion is not broken, and bumps are gathered only at a part of the ceramic substrate to form the BGA formation region. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

この発明は、セラミック基板と樹脂基板をバンプで接続した高周波回路基板装置に関する。   The present invention relates to a high-frequency circuit board device in which a ceramic substrate and a resin substrate are connected by bumps.

従来、セラミック基板と樹脂基板を多数配列されたバンプで接合するBGA(Ball Grid Array;ボールグリッドアレイ)実装では、両者の線膨張係数に2倍以上の差があるため、両基板のバンプ間に樹脂等アンダーフィル剤を充填して固定することで、周囲温度変化により生じる熱応力を抑制し、バンプ接合部の破損を防止していた(例えば、特許文献1参照)。また、セラミック基板と樹脂基板の間に、線膨張係数が中間値を持つ線膨張中間層(ラミネート)を入れて2階建ての段積み構造とし、応力を分散させるバンプ実装技術も知られている(例えば、特許文献2参照)。   Conventionally, in BGA (Ball Grid Array) mounting, in which a large number of ceramic substrates and resin substrates are bonded together, there is a difference of two or more in the linear expansion coefficient between the two. By filling and fixing an underfill agent such as a resin, thermal stress caused by a change in ambient temperature is suppressed, and damage to the bump joint is prevented (for example, see Patent Document 1). Also known is a bump mounting technique in which a linear expansion intermediate layer (laminate) having an intermediate value of linear expansion coefficient is inserted between a ceramic substrate and a resin substrate to form a two-storied stacked structure to disperse stress. (For example, refer to Patent Document 2).

特開平11−17044JP-A-11-17044 特開2002−237553JP 2002-237553 A

しかしながら、このような従来のバンプ実装を行う場合、熱応力抑制策を何も取らない場合に比してセラミック基板寸法を大きくすることができるものの、線膨張係数差が大きい2種の構成物を接合する以上は、依然としてセラミック基板寸法の制約が残ってしまう。   However, when such conventional bump mounting is performed, the ceramic substrate dimensions can be increased as compared with the case where no thermal stress suppression measures are taken, but two types of components having a large difference in linear expansion coefficient are used. As long as they are joined, the ceramic substrate size still remains a limitation.

また、特許文献1について言えば、アンダーフィルは誘電物質であることから、バンプに高周波電流が流れる高周波回路で使用すると電気的特性劣化が避けられず、製法としても、液状樹脂を流しこむことから樹脂の充填位置および量のコントロールが非常に難しくて煩雑なものとなっていた。   As for Patent Document 1, since the underfill is a dielectric material, if it is used in a high-frequency circuit in which a high-frequency current flows through the bumps, the electrical characteristics are inevitably deteriorated, and a liquid resin is poured as a manufacturing method. It was very difficult and complicated to control the filling position and amount of the resin.

また、特許文献2について言えば、線膨張中間層を設けた複雑な段積み構成になると、高周波特性の劣化が避けられないだけでなく、高周波回路設計が非常に複雑となり、組立工数も増えて高価なものとなっていた。   In addition, as for Patent Document 2, in a complicated stacked structure with a linear expansion intermediate layer, not only is the deterioration of the high frequency characteristics unavoidable, but also the high frequency circuit design becomes very complicated and the number of assembly steps increases. It was expensive.

したがって、高周波回路のBGA実装において、アンダーフィルや線膨張中間層を使用せずに、セラミック基板の大きさを熱応力破壊が生じない寸法に限定しているのが実情である。このように、BGA実装は立体的に回路接続が出来ることから、回路基板や回路モジュールの小型化に大変有効な実装構成であるが、BGA実装に伴う強度劣化に耐え得る寸法に限定しなければならないため、必要な回路規模を大きく構成することが出来なくなる場合が多い、という問題があった。   Therefore, in BGA mounting of high-frequency circuits, the actual situation is that the size of the ceramic substrate is limited to dimensions that do not cause thermal stress breakdown without using an underfill or a linear expansion intermediate layer. As described above, since BGA mounting can connect circuits three-dimensionally, it is a very effective mounting configuration for miniaturization of circuit boards and circuit modules, but it must be limited to dimensions that can withstand the strength degradation associated with BGA mounting. Therefore, there is a problem in that it is often impossible to make a necessary circuit scale large.

この発明による高周波回路基板装置は、セラミック基板と樹脂基板をバンプ接続する際に、セラミック基板に所要規模の高周波回路を形成しても、アンダーフィルや線膨張中間層を使用すること無く、バンプ接合部の熱応力破壊を防ぐことのできる基板接合構造を得ることを目的とする。   In the high frequency circuit board device according to the present invention, when the ceramic substrate and the resin substrate are bump-connected, even if a high frequency circuit of a required scale is formed on the ceramic substrate, the bump bonding is performed without using an underfill or a linear expansion intermediate layer. An object of the present invention is to obtain a substrate bonding structure that can prevent thermal stress destruction of a portion.

この発明による高周波回路基板装置は、複数のランドが配列されたセラミック基板と、複数のランドが配列された樹脂基板と、前記樹脂基板のランドと前記セラミック基板のランドの間に接合され、ボールグリッドアレイを構成する複数のバンプと、を備え、前記セラミック基板の外形幅は、前記ボールグリッドアレイの形成領域よりも大きく、前記ボールグリッドアレイが前記セラミック基板の中央部にのみ形成されたものである。   A high frequency circuit board device according to the present invention includes a ceramic substrate on which a plurality of lands are arranged, a resin substrate on which a plurality of lands are arranged, a land between the lands of the resin substrate and the lands of the ceramic substrate, and a ball grid A plurality of bumps constituting the array, wherein an outer width of the ceramic substrate is larger than a formation region of the ball grid array, and the ball grid array is formed only at a central portion of the ceramic substrate. .

また、複数のランドが配列されたセラミック基板と、複数のランドが配列された樹脂基板と、前記樹脂基板のランドと前記セラミック基板のランドの間に接合され、ボールグリッドアレイを構成する複数のバンプと、を備え、前記ボールグリッドアレイを前記セラミック基板の一部にのみ形成し、前記セラミック基板がバンプにより支えられていない位置に、弾性樹脂からなる支持部材を設けても良い。   Also, a ceramic substrate on which a plurality of lands are arranged, a resin substrate on which a plurality of lands are arranged, and a plurality of bumps that are bonded between the lands on the resin substrate and the lands on the ceramic substrate to form a ball grid array The ball grid array may be formed only on a part of the ceramic substrate, and a support member made of an elastic resin may be provided at a position where the ceramic substrate is not supported by the bumps.

この発明によれば、バンプを配列して形成するBGA実装領域をバンプ接合部の熱応力破壊が生じない大きさの寸法領域に限定することができるため、セラミック基板全体の大きさに限定されずに、所要回路規模のBGA実装構造を得ることが可能となる。   According to the present invention, the BGA mounting area formed by arranging the bumps can be limited to a size area that does not cause the thermal stress breakdown of the bump bonding portion. In addition, a BGA mounting structure with a required circuit scale can be obtained.

この発明に係る実施の形態1によるセラミック基板と樹脂基板の接続構造の断面図を示す。Sectional drawing of the connection structure of the ceramic substrate and resin substrate by Embodiment 1 which concerns on this invention is shown. この発明に係る実施の形態1によるセラミック基板のバンプ形成面を示す図である。It is a figure which shows the bump formation surface of the ceramic substrate by Embodiment 1 which concerns on this invention. この発明に係る実施の形態2によるセラミック基板と樹脂基板の接続構造の断面図を示す。Sectional drawing of the connection structure of the ceramic substrate and resin substrate by Embodiment 2 which concerns on this invention is shown. この発明に係る実施の形態2によるセラミック基板のバンプ形成面を示す図である。It is a figure which shows the bump formation surface of the ceramic substrate by Embodiment 2 which concerns on this invention. この発明に係る実施の形態2の他の態様によるセラミック基板のバンプ形成面を示す図である。It is a figure which shows the bump formation surface of the ceramic substrate by the other aspect of Embodiment 2 which concerns on this invention.

実施の形態1.
図1は、この発明に係る実施の形態1による高周波回路基板装置の、セラミック基板と樹脂基板との接続構造を示す断面図である。図2は、この発明に係る実施の形態1によるセラミック基板のバンプ形成面を示す図である。
図1、2において、実施の形態1による高周波回路基板装置100は、セラミック基板1とセラミック基板6を、導体のバンプ4を介して接続することで構成される。セラミック基板1の一方の面には、部品2を実装するための回路パターン3が形成される。セラミック基板1の他方の面には、バンプ4を接合するための複数のランド5が配列されている。ランド5は、導体パターンによって構成され、セラミック基板1の中央に集中して配列される。樹脂基板6はガラスエポキシ樹脂やBTレジンなどの樹脂を素材として構成され、樹脂基板6の一方の面には、複数のランド7が配列されている。ランド7は導体パターンによって構成され、ランド5に対向する位置に配置されて、ランド5と同じ数および同じピッチで配列される。
Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing a connection structure between a ceramic substrate and a resin substrate in the high-frequency circuit board device according to Embodiment 1 of the present invention. FIG. 2 is a diagram showing a bump forming surface of the ceramic substrate according to the first embodiment of the present invention.
1 and 2, the high-frequency circuit board device 100 according to the first embodiment is configured by connecting a ceramic substrate 1 and a ceramic substrate 6 via conductor bumps 4. A circuit pattern 3 for mounting the component 2 is formed on one surface of the ceramic substrate 1. A plurality of lands 5 for bonding the bumps 4 are arranged on the other surface of the ceramic substrate 1. The land 5 is constituted by a conductor pattern, and is concentrated and arranged at the center of the ceramic substrate 1. The resin substrate 6 is made of a resin such as glass epoxy resin or BT resin, and a plurality of lands 7 are arranged on one surface of the resin substrate 6. The lands 7 are formed of a conductor pattern, are arranged at positions facing the lands 5, and are arranged at the same number and the same pitch as the lands 5.

セラミック基板1のランド5と樹脂基板6のランド7とがそれぞれバンプ4によって接合されることでBGA領域8が形成されて、BGA実装構造が構成される。セラミック基板1と樹脂基板6を接合する際、熱応力破壊が生じない寸法以内にのみバンプを集めて、BGA実装構造が形成されている。セラミック基板1の外形寸法(縦または横の外形幅)は、BGA領域8の寸法(縦または横の領域幅)よりも大きく、例えば(縦または横の)寸法差が20mm以上大きくなるようになされている。   The lands 5 of the ceramic substrate 1 and the lands 7 of the resin substrate 6 are joined by the bumps 4 to form the BGA region 8, thereby forming a BGA mounting structure. When the ceramic substrate 1 and the resin substrate 6 are bonded, the bumps are collected only within a dimension that does not cause thermal stress destruction, and a BGA mounting structure is formed. The external dimensions (vertical or horizontal external width) of the ceramic substrate 1 are larger than the dimensions (vertical or horizontal area width) of the BGA region 8, for example, the dimensional difference (vertical or horizontal) is larger than 20 mm. ing.

BGA実装構造は、基板同士の電気的接続を、基板面対基板面で接合する方法であり、基板面には所定の配列にボールまたはバンプと呼ぶ突起形状の電極を、格子状に平面的に並べることから、BGAと称されている。
BGA実装構造では、半導体素子、受動素子等の部品をセラミック基板(ここではセラミック基板1)に搭載して形成した回路ブロックを、マザーボード(ここでは樹脂基板6)に最小面積で実装することができる。また、セラミック基板とマザーボード間の全接合点が最短接続及び一括同時接合できる利点がある。ボールまたはバンプには、半田、導体膜で覆われた樹脂、メッキ積上げ、金属ボール、等各種有り、用途、目的により使い分けられている。ここでは、これらを総てバンプと称する。
The BGA mounting structure is a method in which electrical connection between substrates is bonded on a substrate surface-to-substrate surface. Projected electrodes called balls or bumps are arranged in a predetermined arrangement on the substrate surface in a lattice shape in a plane. Because it is arranged, it is called BGA.
In the BGA mounting structure, a circuit block formed by mounting components such as semiconductor elements and passive elements on a ceramic substrate (here, ceramic substrate 1) can be mounted on a mother board (here, resin substrate 6) with a minimum area. . In addition, there is an advantage that all joint points between the ceramic substrate and the mother board can be shortest and collectively joined. There are various types of balls or bumps, such as solder, resin covered with a conductor film, stacked plating, metal balls, and the like, and they are properly used depending on applications and purposes. Here, these are all called bumps.

セラミック基板1の線膨張係数は、5〜7PPM程度であるのに対し、樹脂基板5の線膨張係数は16PPM前後と、その差は2倍以上ある。このため、高周波回路基板装置100が加熱されれば、樹脂基板6は大きく進展し、セラミック基板1の伸びは小さいことから、使用環境の温度変化により最外縁に位置するバンプ4の接続部に最大の熱応力が発生する。バンプ4をはんだなど接合工程の温度が高い方法で接合する場合には、その接合冷却後において、バンプ4の各接合部にセラミック基板1の中心方向に向かう引張り力が残留応力として残ることとなる。これら熱応力は、BGA領域8の外縁部ほど大きく、中心部ほど小さい。また、BGA領域8の領域寸法が大きいほど、外縁部の熱応力は増大する。各基板が晒される実使用環境では、70〜100℃程度の温度変化幅のヒートサイクルが加わるため、伸び縮みによる繰り返し応力が加わることとなる。   The linear expansion coefficient of the ceramic substrate 1 is about 5 to 7 PPM, whereas the linear expansion coefficient of the resin substrate 5 is around 16 PPM, and the difference is more than twice. For this reason, if the high-frequency circuit board device 100 is heated, the resin substrate 6 greatly progresses and the ceramic substrate 1 has a small elongation. Thermal stress is generated. When the bumps 4 are joined by a method such as soldering at a high temperature in the joining process, a tensile force toward the center of the ceramic substrate 1 remains as a residual stress in each joined portion of the bumps 4 after the joining cooling. . These thermal stresses are larger at the outer edge of the BGA region 8 and smaller at the center. Moreover, the thermal stress of an outer edge part increases, so that the area | region dimension of the BGA area | region 8 is large. In an actual use environment where each substrate is exposed, a heat cycle with a temperature change width of about 70 to 100 ° C. is applied, so that repeated stress due to expansion and contraction is applied.

BGA領域8の領域寸法が大きいほど使用環境の温度変化による熱応力は大きくなり、その寸法限度を超えるとBGA領域8の外周部からバンプ4接続点の構造劣化が進み、最終的には断裂となり、セラミック基板1と樹脂基板6との電気的接続を絶つ故障に至ることとなる。   The larger the area size of the BGA region 8, the greater the thermal stress due to temperature changes in the usage environment. When the size limit is exceeded, the structural deterioration of the bump 4 connection point proceeds from the outer periphery of the BGA region 8 and eventually the fracture occurs. As a result, the electrical connection between the ceramic substrate 1 and the resin substrate 6 is broken.

従来のBGA実装構造では、セラミック基板1の全面にバンプ4を配列して、全面全てが樹脂基板6と接合されていた。このため、セラミック基板1の寸法はBGA領域8の寸法とほぼ同寸となり、セラミック基板1の寸法が大きくなるほどBGA外縁部の断裂が発生し易くなっていた。使用環境の温度変化があってもBGAの断裂が生じないセラミック基板の寸法は、素材の線膨張係数と環境温度幅によっても異なってくるが、概ね20mm角(□)以内が寸法限度となっていた。   In the conventional BGA mounting structure, the bumps 4 are arranged on the entire surface of the ceramic substrate 1, and the entire surface is bonded to the resin substrate 6. For this reason, the dimensions of the ceramic substrate 1 are almost the same as the dimensions of the BGA region 8, and the larger the dimension of the ceramic substrate 1, the easier the tearing of the outer edge of the BGA occurs. The size of the ceramic substrate that does not cause BGA tearing even when the temperature of the operating environment changes varies depending on the linear expansion coefficient of the material and the environmental temperature range, but is generally within 20 mm square (□). It was.

一方、高周波回路基板100では、セラミック基板1と樹脂基板6との間で、電気信号や電源の授受を行ってインターフェースを取るべきランド5およびランド7の数(インターフェース数または接続信号数)が実際には少ない。このように、回路面積に対するインターフェース数または接続信号数の比率が小さいので、セラミック基板1の全面にバンプ4を形成する必要が無い。   On the other hand, in the high-frequency circuit board 100, the number of lands 5 and lands 7 (number of interfaces or number of connection signals) to be interfaced by exchanging electrical signals and power between the ceramic substrate 1 and the resin substrate 6 is actually the same. There are few. Thus, since the ratio of the number of interfaces or the number of connection signals to the circuit area is small, it is not necessary to form the bumps 4 on the entire surface of the ceramic substrate 1.

実施の形態1ではこの性質を利用して、樹脂基板6との接続が必要なバンプ4をセラミック基板1の中央部だけに集め、BGA領域8の形成領域寸法を従来構成でもバンプ4の断裂が生じない程度の大きさの範囲内で形成している。具体的には、BGA領域8の形成領域寸法を概ね20mm角以内とする。   In the first embodiment, by utilizing this property, the bumps 4 that need to be connected to the resin substrate 6 are collected only in the central portion of the ceramic substrate 1, and the bumps 4 may be broken even if the formation area size of the BGA region 8 is the conventional configuration. It is formed within a size range that does not occur. Specifically, the size of the formation area of the BGA area 8 is approximately within 20 mm square.

このようにすることで、セラミック基板1は中央のBGA領域8の部分を柱とする平屋根型或いは平傘型で樹脂基板6上に実装されこととなり、セラミック基板1と樹脂基板6の間でBGA領域8の周囲に形成される中空部の寸法分だけ、回路形成領域を拡大することができる。   In this way, the ceramic substrate 1 is mounted on the resin substrate 6 in a flat roof shape or a flat umbrella shape with the central BGA region 8 as a column, and between the ceramic substrate 1 and the resin substrate 6. The circuit formation region can be enlarged by the size of the hollow portion formed around the BGA region 8.

また、搭載される部品重量や使用される機械的環境の制約によりセラミック基板1の最大寸法が決められるが、少なくとも従来面積比で9倍程度まで大きくすることが可能である。例えば、BGA領域8の形成領域寸法が20mm角であるとすれば、セラミック基板1の寸法を60mm角とすることが可能である。   Further, although the maximum dimension of the ceramic substrate 1 is determined by restrictions on the weight of components to be mounted and the mechanical environment to be used, it can be increased to at least about 9 times the conventional area ratio. For example, if the formation region size of the BGA region 8 is 20 mm square, the size of the ceramic substrate 1 can be 60 mm square.

以上により、この実施の形態に係るセラミック基板1と樹脂基板6のBGA型実装構造による高周波回路基板装置は、複数のランド5が配列されたセラミック基板1と、複数のランド7が配列された樹脂基板6と、樹脂基板6のランド7とセラミック基板1のランド5の間に接合され、ボールグリッドアレイを構成する複数のバンプ4とを備え、セラミック基板1の外形幅は、前記ボールグリッドアレイの形成領域よりも大きく、前記ボールグリッドアレイが前記セラミック基板1の中央部にのみ形成されたことを特徴とする。
また、前記セラミック基板1の最大外形幅と、前記ボールグリッドアレイの形成領域におけるセラミック基板1の最大外形幅と同一方向での最大幅との差は、20mm以上であっても良い。
また、前記セラミック基板1をバンプ接合した際に、バンプ接続部の破壊が生じない寸法範囲を、前記ボールグリッドアレイの形成領域としても良い。
As described above, the high frequency circuit board device having the BGA type mounting structure of the ceramic substrate 1 and the resin substrate 6 according to this embodiment has the ceramic substrate 1 on which the plurality of lands 5 are arranged and the resin on which the plurality of lands 7 are arranged. The substrate 6 is provided between a land 7 of the resin substrate 6 and a land 5 of the ceramic substrate 1 and includes a plurality of bumps 4 constituting a ball grid array. The outer width of the ceramic substrate 1 is the same as that of the ball grid array. The ball grid array is larger than the formation region, and is formed only at the center of the ceramic substrate 1.
Further, the difference between the maximum outer width of the ceramic substrate 1 and the maximum width in the same direction as the maximum outer width of the ceramic substrate 1 in the formation region of the ball grid array may be 20 mm or more.
In addition, when the ceramic substrate 1 is bump-bonded, a dimension range in which the bump connection portion is not broken may be used as the formation area of the ball grid array.

このようにして、実施の形態によるセラミック基板1と樹脂基板6のBGA型実装構造では、バンプを配列して形成するBGA領域において、はんだ割れやセラミック割れなどのバンプ接合部における熱応力破壊が生じない大きさの寸法領域に限定しているため、BGA領域に何らの熱応力破壊防止構造を設けなくても、熱応力破壊が生じることは無く、かつセラミック基板全体の大きさが限定されないので、必要な回路規模を形成したBGA実装構造を得ることが可能となる。   In this way, in the BGA type mounting structure of the ceramic substrate 1 and the resin substrate 6 according to the embodiment, thermal stress failure occurs at the bump joint such as solder crack or ceramic crack in the BGA region formed by arranging the bumps. Since it is limited to a dimensional region having no size, even if no thermal stress destruction prevention structure is provided in the BGA region, thermal stress failure does not occur and the size of the entire ceramic substrate is not limited. It is possible to obtain a BGA mounting structure in which a necessary circuit scale is formed.

特に、アンダーフィルや線膨張中間層を用いた複雑な2段構造をとらずとも、セラミック基板の寸法を従来面積比で約9倍の大きさとすることが可能となり、所望の回路規模の高周波回路をセラミック基板上に形成することができる。   In particular, without taking a complicated two-stage structure using an underfill or a linear expansion intermediate layer, the size of the ceramic substrate can be made about nine times as large as the conventional area ratio, and a high-frequency circuit having a desired circuit scale can be obtained. Can be formed on a ceramic substrate.

また、セラミック基板1と樹脂基板6のBGA接合部において、接合部周辺に何らの補強固定を行わないことから、高周波回路基板装置の組立工程は最小限で済むこととなり、高周波回路装置の低コスト化に有利な効果を得られる。   In addition, since no reinforcement is fixed around the joint at the BGA joint between the ceramic substrate 1 and the resin substrate 6, the assembly process of the high-frequency circuit board device can be minimized, and the cost of the high-frequency circuit device can be reduced. An advantageous effect can be obtained.

実施の形態2.
図3は、この発明に係る実施の形態2による高周波回路基板装置の、セラミック基板と樹脂基板との接続構造を示す断面図である。図4は、この発明に係る実施の形態2によるセラミック基板のバンプ形成面を示す図である。図5は、この発明に係る実施の形態2による他の態様のセラミック基板のバンプ形成面を示す。図3、4、5において、符号1〜7に示す構成は、実施の形態1の場合と類似の構成を示す。
Embodiment 2. FIG.
3 is a cross-sectional view showing a connection structure between a ceramic substrate and a resin substrate in a high-frequency circuit board device according to Embodiment 2 of the present invention. FIG. 4 is a view showing a bump forming surface of the ceramic substrate according to the second embodiment of the present invention. FIG. 5 shows a bump forming surface of a ceramic substrate according to another embodiment of the second embodiment of the present invention. 3, 4, and 5, the configurations indicated by reference numerals 1 to 7 are similar to those of the first embodiment.

この実施の形態2による図3、4に示す態様の高周波回路基板装置100では、セラミック基板1と樹脂基板6の接合されるBGA領域8が、セラミック基板1の中央ではなく、基板端部に向かって偏った位置に設けてある。このため、BGA領域8で支えるセラミック基板1の重量に偏りを生じないように、セラミック基板1の重量を共に支えるゴム状樹脂9が、セミック基板1の端に設けてあり、セラミック基板1が樹脂基板6に対して両持ちで支持される。ゴム状樹脂9は、弾性樹脂であれば良く、また図4の水平方向のみならず、さらに図4の上下方向にも配置されても良い。   3 and 4 according to the second embodiment, the BGA region 8 to which the ceramic substrate 1 and the resin substrate 6 are joined is not located at the center of the ceramic substrate 1 but toward the end of the substrate. It is provided at a biased position. Therefore, a rubber-like resin 9 that supports both the weight of the ceramic substrate 1 is provided at the end of the ceramic substrate 1 so that the weight of the ceramic substrate 1 supported by the BGA region 8 is not biased. The substrate 6 is supported by both ends. The rubber-like resin 9 may be an elastic resin, and may be arranged not only in the horizontal direction in FIG. 4 but also in the vertical direction in FIG.

次に、この実施の形態2による図5に示す態様の高周波回路基板装置では、セラミック基板1と樹脂基板6の接合されるBGA領域8を、セラミック基板1の中央に設けている。図5ではセラミック基板1の大きさが非常に長い場合を示しており、セラミック基板1の重量を支える必要がある基板両端部にゴム状樹脂9を設けている。これによって、セラミック基板1は、樹脂基板6に対してBGA領域8と少なくとも2つ以上のゴム状樹脂9の少なくとも3個所以上で支持される。ゴム状樹脂9は、図4の水平方向のみならず、さらに図4の上下方向に配置されても良い。   Next, in the high-frequency circuit board device according to the second embodiment shown in FIG. 5, the BGA region 8 where the ceramic substrate 1 and the resin substrate 6 are joined is provided in the center of the ceramic substrate 1. FIG. 5 shows a case where the size of the ceramic substrate 1 is very long, and the rubber-like resin 9 is provided at both ends of the substrate that need to support the weight of the ceramic substrate 1. Thus, the ceramic substrate 1 is supported by the resin substrate 6 at at least three locations of the BGA region 8 and at least two or more rubber-like resins 9. The rubber-like resin 9 may be arranged not only in the horizontal direction in FIG. 4 but also in the vertical direction in FIG.

なお、ゴム状樹脂9は、セラミック基板1と樹脂基板6の双方に接着してあっても一方にのみ接着してあっても構わない。ただし、ゴム状樹脂9をセラミック基板1と樹脂基板6の双方に接着する場合は、双方の線膨張差から発生する変移を吸収し得る材質を選ぶと良く、例えばテフロン(登録商標)樹脂や弾性を有したナノチューブから成る樹脂体などを用いるのが良い。   The rubber-like resin 9 may be adhered to both the ceramic substrate 1 and the resin substrate 6 or may be adhered to only one of them. However, when the rubber-like resin 9 is bonded to both the ceramic substrate 1 and the resin substrate 6, it is preferable to select a material that can absorb the transition generated by the difference in linear expansion between the two, for example, Teflon (registered trademark) resin or elastic material. It is preferable to use a resin body made of a nanotube having a carbon nanotube.

以上により、この実施の形態に係るセラミック基板1と樹脂基板6のBGA型実装構造による高周波回路基板装置は、複数のランド5が配列されたセラミック基板1と、複数のランド7が配列された樹脂基板6と、樹脂基板6のランド7とセラミック基板1のランド5の間に接合され、ボールグリッドアレイを構成する複数のバンプ4とを備え、前記ボールグリッドアレイをセラミック基板1の一部にのみ形成し、セラミック基板1がバンプ4により支えられていない位置に、弾性樹脂からなる支持部材(ゴム状樹脂9)を設けたことを特徴とする。   As described above, the high frequency circuit board device having the BGA type mounting structure of the ceramic substrate 1 and the resin substrate 6 according to this embodiment has the ceramic substrate 1 on which the plurality of lands 5 are arranged and the resin on which the plurality of lands 7 are arranged. A substrate 6 and a plurality of bumps 4 which are bonded between a land 7 of the resin substrate 6 and a land 5 of the ceramic substrate 1 and constitute a ball grid array are provided, and the ball grid array is formed only on a part of the ceramic substrate 1. A support member (rubber-like resin 9) made of an elastic resin is provided at a position where the ceramic substrate 1 is formed and not supported by the bumps 4.

この実施の形態2によるセラミック基板1と樹脂基板6のBGA型実装構造では、支えとなるゴム状樹脂9を用いて複数個所でセラミック基板1を支持することができるので、BGA領域8の形成位置は回路構成上所望の位置に設けることが可能となり、セラミック基板1の寸法自由度及び回路規模の自由度は格段に増すこととなる。   In the BGA type mounting structure of the ceramic substrate 1 and the resin substrate 6 according to the second embodiment, the ceramic substrate 1 can be supported at a plurality of locations by using the rubber-like resin 9 that serves as a support. Can be provided at a desired position in terms of the circuit configuration, and the degree of freedom in the dimensions and the circuit scale of the ceramic substrate 1 are remarkably increased.

この発明は、特に接続信号数が少ない高周波回路基板の接合に有効であるが、BGA領域寸法が従来構成でもバンプ接合部に断裂が生じない大きさを超えない範囲で用いる限り、デジタル回路基板の接合にも有効である。またセラミック基板と樹脂基板との接合のように線膨張の差が大きいものをバンプにより接合する構成物全般に対しても適用可能である。   The present invention is particularly effective for bonding a high-frequency circuit board with a small number of connection signals. However, as long as the BGA region size is used within a range that does not exceed the size at which the bump bonding part does not break, the digital circuit board It is also effective for bonding. Further, the present invention can be applied to all structures in which a member having a large difference in linear expansion, such as bonding between a ceramic substrate and a resin substrate, is bonded by a bump.

1 セラミック基板、2 部品、3 回路パターン、4 バンプ、5 ランド、6 樹脂基板、7 ランド、8 BGA領域、9 ゴム状樹脂、100 高周波回路基板装置。   DESCRIPTION OF SYMBOLS 1 Ceramic substrate, 2 components, 3 circuit pattern, 4 bump, 5 land, 6 resin substrate, 7 land, 8 BGA area | region, 9 rubber-like resin, 100 high frequency circuit board apparatus.

Claims (4)

複数のランドが配列されたセラミック基板と、
複数のランドが配列された樹脂基板と、
前記樹脂基板のランドと前記セラミック基板のランドの間に接合され、ボールグリッドアレイを構成する複数のバンプと、
を備え、
前記セラミック基板の外形幅は、前記ボールグリッドアレイの形成領域よりも大きく、前記ボールグリッドアレイが前記セラミック基板の中央部にのみ形成された高周波回路基板装置。
A ceramic substrate on which a plurality of lands are arranged; and
A resin substrate on which a plurality of lands are arranged;
A plurality of bumps that are bonded between the land of the resin substrate and the land of the ceramic substrate and constitute a ball grid array,
With
A high frequency circuit board device in which an outer width of the ceramic substrate is larger than a formation region of the ball grid array, and the ball grid array is formed only at a central portion of the ceramic substrate.
前記セラミック基板の最大外形幅と前記ボールグリッドアレイの形成領域の最大幅との差は、20mm以上であることを特徴とする請求項1記載の高周波回路基板装置。   The high-frequency circuit board device according to claim 1, wherein a difference between a maximum outer width of the ceramic substrate and a maximum width of a formation region of the ball grid array is 20 mm or more. セラミック基板をバンプ接合した際にバンプ接続部の破壊が生じない寸法範囲を、前記ボールグリッドアレイの形成領域としたことを特徴とする請求項1記載の高周波回路基板装置。   2. The high-frequency circuit board device according to claim 1, wherein a dimension range in which the bump connection portion is not destroyed when the ceramic substrate is bump-bonded is defined as a formation area of the ball grid array. 複数のランドが配列されたセラミック基板と、
複数のランドが配列された樹脂基板と、
前記樹脂基板のランドと前記セラミック基板のランドの間に接合され、ボールグリッドアレイを構成する複数のバンプと、を備え、
前記ボールグリッドアレイを前記セラミック基板の一部にのみ形成し、前記セラミック基板がバンプにより支えられていない位置に、弾性樹脂からなる支持部材を設けた高周波回路基板装置。
A ceramic substrate on which a plurality of lands are arranged; and
A resin substrate on which a plurality of lands are arranged;
A plurality of bumps which are bonded between the land of the resin substrate and the land of the ceramic substrate and constitute a ball grid array,
A high-frequency circuit board device in which the ball grid array is formed only on a part of the ceramic substrate, and a support member made of an elastic resin is provided at a position where the ceramic substrate is not supported by bumps.
JP2010007987A 2010-01-18 2010-01-18 High frequency circuit board device Expired - Fee Related JP5581701B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010007987A JP5581701B2 (en) 2010-01-18 2010-01-18 High frequency circuit board device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010007987A JP5581701B2 (en) 2010-01-18 2010-01-18 High frequency circuit board device

Publications (2)

Publication Number Publication Date
JP2011146625A true JP2011146625A (en) 2011-07-28
JP5581701B2 JP5581701B2 (en) 2014-09-03

Family

ID=44461195

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010007987A Expired - Fee Related JP5581701B2 (en) 2010-01-18 2010-01-18 High frequency circuit board device

Country Status (1)

Country Link
JP (1) JP5581701B2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07226422A (en) * 1994-02-14 1995-08-22 Sumitomo Electric Ind Ltd Package of electronic component
JPH08139233A (en) * 1994-11-08 1996-05-31 Matsushita Electric Ind Co Ltd Module component
JPH0964095A (en) * 1995-08-24 1997-03-07 Matsushita Electric Ind Co Ltd Work with bump and its mounting method
JP2006086161A (en) * 2004-09-14 2006-03-30 Canon Inc Semiconductor device
JP2007157775A (en) * 2005-11-30 2007-06-21 Matsushita Electric Ind Co Ltd Semiconductor device, and method of manufacturing same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07226422A (en) * 1994-02-14 1995-08-22 Sumitomo Electric Ind Ltd Package of electronic component
JPH08139233A (en) * 1994-11-08 1996-05-31 Matsushita Electric Ind Co Ltd Module component
JPH0964095A (en) * 1995-08-24 1997-03-07 Matsushita Electric Ind Co Ltd Work with bump and its mounting method
JP2006086161A (en) * 2004-09-14 2006-03-30 Canon Inc Semiconductor device
JP2007157775A (en) * 2005-11-30 2007-06-21 Matsushita Electric Ind Co Ltd Semiconductor device, and method of manufacturing same

Also Published As

Publication number Publication date
JP5581701B2 (en) 2014-09-03

Similar Documents

Publication Publication Date Title
JP4450113B2 (en) Semiconductor device and manufacturing method thereof
US9048332B2 (en) Semiconductor device manufacturing method and semiconductor mounting substrate
JP2015038927A (en) Electronic device and manufacturing method of electronic device
WO2013085492A1 (en) Shaped and oriented solder joints
JP4844216B2 (en) Multilayer circuit wiring board and semiconductor device
TW201528448A (en) Wiring substrate and method for mounting a semiconductor component on the wiring substrate
JP2006245076A (en) Semiconductor device
JP5581701B2 (en) High frequency circuit board device
JP2009238855A (en) Mounting structure of semiconductor device, and electronic apparatus using mounting structure
JP2008205184A (en) Mounting structure, manufacturing method of the mounting structure, semiconductor device and manufacturing method of semiconductor device
JP2018535551A (en) Stress suppression interposer for ceramic no-lead surface mount electronic devices.
JP4894347B2 (en) Semiconductor integrated circuit element mounting substrate and semiconductor device
JP2010283215A (en) Electronic device and method of manufacturing the same
US10314166B2 (en) Printed wiring board
JP6464762B2 (en) Semiconductor package substrate, semiconductor package, semiconductor package substrate manufacturing method, and semiconductor package manufacturing method
JP5708489B2 (en) Semiconductor device having metallic power supply side and ground side reinforcing members insulated from each other
JP2011166096A (en) Surface-mounted device and printed board, and structure for mounting surface-mounted device using them
JP2017034224A (en) Electronic module
JP2011159840A (en) Packaging connection structure of electronic component
JP2011108892A (en) Package structure
JP7459610B2 (en) electronic equipment
JP2013012570A (en) Semiconductor device and semiconductor device manufacturing method
JP2011155190A (en) Circuit board device
WO2015033509A1 (en) Printed wiring board and semiconductor device provided with same
US8432034B2 (en) Use of a local constraint to enhance attachment of an IC device to a mounting platform

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20121015

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130610

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130618

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130717

RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20140326

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140415

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140522

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140617

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140630

R151 Written notification of patent or utility model registration

Ref document number: 5581701

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees