JP2011155190A - Circuit board device - Google Patents

Circuit board device Download PDF

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Publication number
JP2011155190A
JP2011155190A JP2010016658A JP2010016658A JP2011155190A JP 2011155190 A JP2011155190 A JP 2011155190A JP 2010016658 A JP2010016658 A JP 2010016658A JP 2010016658 A JP2010016658 A JP 2010016658A JP 2011155190 A JP2011155190 A JP 2011155190A
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circuit board
ceramic substrate
printed circuit
thermal stress
absorbing member
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Japanese (ja)
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Kunifumi Matsuo
邦史 松尾
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2010016658A priority Critical patent/JP2011155190A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board device that relaxes elongation and stress of a printed board and a ceramic substrate due to temperature change, and has high bonding reliability of a BGA mounting structure. <P>SOLUTION: A thermal stress-absorbing member 3 made of metal having a coefficient of thermal expansion between coefficients of thermal expansion of the ceramic substrate 1 and printed board 2 is joined between the both, and is disposed so as to surround a solder bump 4, thereby a junction structure has high bonding reliability while relaxing thermal stress generated at a BGA junction part due to the solder bump 4. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

この発明は、セラミック基板をプリント基板にＢＧＡ（ボールグリッドアレイ）実装して構成される、回路基板装置に関する。   The present invention relates to a circuit board device configured by mounting a ceramic substrate on a printed circuit board by BGA (ball grid array).

複数のはんだバンプを用いたＢＧＡ実装により、セラミック基板をプリント基板に実装する場合、プリント基板の有機基材とセラミック基板の熱膨張率の差が大きいことから、熱衝撃が印加される際、はんだバンプの接合部に熱応力が発生し、ＢＧＡ実装部またはセラミック基板の破断により要求寿命熱サイクルを満たせないことがある。
従来、このような破断を防ぐため、ＢＧＡ実装部の補強材として、セラミック基板とプリント基板の間に絶縁樹脂（アンダーフィル）を充填していた（例えば、特許文献１参照）。 When a ceramic substrate is mounted on a printed circuit board by BGA mounting using multiple solder bumps, the difference in thermal expansion coefficient between the organic substrate of the printed circuit board and the ceramic substrate is large. Thermal stress is generated at the joint of the bump, and the required life thermal cycle may not be satisfied due to the breakage of the BGA mounting portion or the ceramic substrate.
Conventionally, in order to prevent such breakage, an insulating resin (underfill) is filled between the ceramic substrate and the printed circuit board as a reinforcing material for the BGA mounting portion (see, for example, Patent Document 1).

特開２００４−１７２２６０号公報JP 2004-172260 A

しかしながら、アンダーフィルを充填する場合、アンダーフィル内部にボイド（気泡）が発生することにより、セラミック基板とプリント基板の接合信頼性に問題があった。
例えば、ボイドの存在によりＢＧＡ実装部周囲の応力バランスが崩れ、反って応力集中するはんだバンプが発生する。また、熱衝撃や高温度下に晒される際、ボイドにより孤立した空気が膨張して、接合部に過大な内部応力が発生する、などの問題がある。また、はんだバンプを介してＲＦ（Radio Frequency）信号を伝送する場合は、アンダーフィルに内在するボイドによりはんだバンプ周囲の誘電率が不均一化し、ＲＦ通過特性が劣化したり、個体差を生じるという問題がある。 However, when the underfill is filled, voids (bubbles) are generated inside the underfill, which causes a problem in the bonding reliability between the ceramic substrate and the printed circuit board.
For example, due to the presence of voids, the stress balance around the BGA mounting portion is lost, and solder bumps that generate warp concentration occur. In addition, when exposed to a thermal shock or high temperature, there is a problem in that isolated air expands due to voids and excessive internal stress is generated at the joint. In addition, when RF (Radio Frequency) signals are transmitted via solder bumps, the dielectric constant around the solder bumps becomes non-uniform due to voids existing in the underfill, resulting in deterioration of RF transmission characteristics and individual differences. There's a problem.

この発明は、係る課題を解決するためになされたものであり、温度変化に伴いプリント基板とセラミック基板のＢＧＡ実装部に加わる応力を緩和し、かつＢＧＡ実装部の接合信頼性の高い回路基板装置を得ることを目的とする。   SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and a circuit board device that relieves stress applied to a BGA mounting portion of a printed circuit board and a ceramic substrate in accordance with a temperature change and has high bonding reliability of the BGA mounting portion. The purpose is to obtain.

この発明による回路基板装置は、セラミック基板と、有機材料からなるプリント基板と、上記セラミック基板とプリント基板を接合する複数のはんだバンプと、上記複数のはんだバンプの接合部を取り囲むように、上記セラミック基板とプリント基板の間に接合され、上記セラミック基板とプリント基板の中間の線膨張係数を有した金属からなる熱応力吸収部材とを備えたものである。   The circuit board device according to the present invention includes a ceramic board, a printed board made of an organic material, a plurality of solder bumps for joining the ceramic board and the printed board, and the ceramic so as to surround a joint portion of the plurality of solder bumps. A thermal stress absorbing member made of a metal bonded between the substrate and the printed circuit board and having a linear expansion coefficient intermediate between the ceramic substrate and the printed circuit board is provided.

この発明によれば、セラミック基板とプリント基板の間に、両者の熱膨張率の中間の熱膨張率を有する熱応力吸収部材を接合することで、はんだ接合部に発生する応力を低減し、かつ接合信頼性が高いＢＧＡ実装構造を得ることができる。   According to this invention, between the ceramic substrate and the printed circuit board, by joining a thermal stress absorbing member having a thermal expansion coefficient intermediate between both thermal expansion coefficients, the stress generated in the solder joint portion is reduced, and A BGA mounting structure with high bonding reliability can be obtained.

この発明に係る実施の形態１による回路基板装置の構成を示す図である。It is a figure which shows the structure of the circuit board apparatus by Embodiment 1 which concerns on this invention. 実施の形態１による回路基板装置の断面を示す図である。1 is a diagram showing a cross section of a circuit board device according to Embodiment 1. FIG. 実施の形態１によるＢＧＡ接合前のセラミック基板の裏面を示す図である。FIG. 3 is a diagram showing the back surface of the ceramic substrate before BGA bonding according to the first embodiment. 実施の形態１によるＢＧＡ接合前のプリント基板の表面を示す図である。3 is a diagram showing a surface of a printed circuit board before BGA bonding according to Embodiment 1. FIG.

実施の形態１．
図１は、この発明に係る実施の形態１による回路基板装置の構成を示す図である。図２は、実施の形態１による回路基板装置の図１におけるＸＸ断面図である。図３は実施の形態１によるＢＧＡ接合前のセラミック基板の裏面を示す図であり、図４は実施の形態１によるＢＧＡ接合前のプリント基板の表面を示す図である。 Embodiment 1 FIG.
FIG. 1 is a diagram showing a configuration of a circuit board device according to Embodiment 1 of the present invention. 2 is a cross-sectional view of the circuit board device according to the first embodiment taken along line XX in FIG. FIG. 3 is a diagram showing the back surface of the ceramic substrate before BGA bonding according to the first embodiment, and FIG. 4 is a diagram showing the surface of the printed circuit board before BGA bonding according to the first embodiment.

図１において、実施の形態１の回路基板装置は、セラミック基板１と、プリント基板２と、セラミック基板１とプリント基板２の間に接合された熱応力吸収部材６から構成される。セラミック基板１は、アルミナを素材とするセラミックを焼結して構成され、表層および内層に配線パターンや導体ビア（ＶＩＡ）が形成されている。プリント基板２は、ガラスやレジンを素材とした有機系のプリント配線板によって構成される。セラミック基板１は、プリント基板２の表面にＢＧＡ実装されている。   In FIG. 1, the circuit board device of the first embodiment includes a ceramic substrate 1, a printed board 2, and a thermal stress absorbing member 6 joined between the ceramic board 1 and the printed board 2. The ceramic substrate 1 is configured by sintering a ceramic made of alumina, and wiring patterns and conductor vias (VIA) are formed on the surface layer and the inner layer. The printed circuit board 2 is composed of an organic printed wiring board made of glass or resin. The ceramic substrate 1 is BGA mounted on the surface of the printed circuit board 2.

図２、３に示すように、セラミック基板１の裏面には、複数のはんだバンプ４が接合されている。はんだバンプ４は、ボール状または樽形状または繭型形状や円筒形状で形成される。はんだバンプ４は、セラミック基板１の表層および内層に設けられる配線パターンまたは導体ランドや、導体スルーホールに電気的に接続されている。   As shown in FIGS. 2 and 3, a plurality of solder bumps 4 are bonded to the back surface of the ceramic substrate 1. The solder bump 4 is formed in a ball shape, a barrel shape, a saddle shape, or a cylindrical shape. The solder bumps 4 are electrically connected to wiring patterns or conductor lands provided on the surface layer and inner layer of the ceramic substrate 1 or conductor through holes.

また、セラミック基板１の裏面には、内側が抜けた矩形の枠型形状板からなる熱応力吸収部材６が接合されている。熱応力吸収部材６は、セラミック基板１の外周縁部に沿う位置で、複数のはんだバンプ４を取り囲むように配置されている。熱応力吸収部材６は、セラミック基板１に設けられた接地導体（図示せず）を介して、セラミック基板１にはんだ付けまたはろう付けによって接合される。   Further, a thermal stress absorbing member 6 made of a rectangular frame-shaped plate with an inner side removed is joined to the back surface of the ceramic substrate 1. The thermal stress absorbing member 6 is arranged at a position along the outer peripheral edge of the ceramic substrate 1 so as to surround the plurality of solder bumps 4. The thermal stress absorbing member 6 is joined to the ceramic substrate 1 by soldering or brazing via a ground conductor (not shown) provided on the ceramic substrate 1.

熱応力吸収部材６は、例えば銅タングステンまたは銅モリブデンを含有する導電性金属からなり、熱膨張係数がセラミック基板１とプリント基板２の中間の値を有する材料が用いられる。セラミック基板１の熱膨張係数が５．５×１０−６[１／℃]、プリント基板２の熱膨張係数が１６×１０−６[１／℃]であるので、熱応力吸収部材６の熱膨張係数は、７×１０−６乃至８×１０−６[１／℃]の部材を用いるのが良い。熱応力吸収部材６の表層には、はんだ濡れ性を向上させるニッケルめっきや金めっきなどのめっき層が付着している。熱応力吸収部材６は、セラミック基板１のグランドに接続される。 The thermal stress absorbing member 6 is made of a conductive metal containing, for example, copper tungsten or copper molybdenum, and a material having a thermal expansion coefficient between the ceramic substrate 1 and the printed substrate 2 is used. The thermal expansion coefficient of the ceramic substrate 1 is 5.5 × 10 −6 [1 / ° C.], and the thermal expansion coefficient of the printed circuit board 2 is 16 × 10 −6 [1 / ° C.]. A member having an expansion coefficient of 7 × 10 −6 to 8 × 10 −6 [1 / ° C.] is preferably used. A plating layer such as nickel plating or gold plating for improving solder wettability is attached to the surface layer of the thermal stress absorbing member 6. The thermal stress absorbing member 6 is connected to the ground of the ceramic substrate 1.

また、図２、４に示すように、プリント基板２は、表面にはんだバンプ４を接合するための複数の導体ランド５が形成され、導体ランド５は導体ビアを介してプリント基板２の内層および表層の配線パターンに接続される。   As shown in FIGS. 2 and 4, the printed circuit board 2 has a plurality of conductor lands 5 formed on the surface for joining the solder bumps 4, and the conductor lands 5 are formed on the inner layer of the printed circuit board 2 through the conductor vias. Connected to the surface wiring pattern.

また、プリント基板２は、表面に熱応力吸収部材６をはんだ付けするための接地導体パターン７が形成されている。接地導体パターン７は、熱応力吸収部材６と同様に、内側が抜けた矩形の枠型形状をなし、複数の導体ランド５を取り囲むように配置されている。接地導体パターン７は、プリント基板２の接地導体（グランド）に接続される。接地導体パターン７の表層には、はんだ濡れ性を向上させるニッケルめっきや金めっきなどのめっき層が付着している。   The printed circuit board 2 has a ground conductor pattern 7 for soldering the thermal stress absorbing member 6 on the surface. Similarly to the thermal stress absorbing member 6, the ground conductor pattern 7 has a rectangular frame shape with the inner side removed, and is disposed so as to surround the plurality of conductor lands 5. The ground conductor pattern 7 is connected to the ground conductor (ground) of the printed circuit board 2. A plating layer such as nickel plating or gold plating for improving solder wettability is attached to the surface layer of the ground conductor pattern 7.

次に、セラミック基板１とプリント基板２の接合工程について説明する。
まず、セラミック基板１の裏面に、熱応力吸収部材６をはんだ接合またはろう付けで接合し、複数のはんだバンプ４を印刷する。 Next, the joining process of the ceramic substrate 1 and the printed circuit board 2 will be described.
First, the thermal stress absorbing member 6 is joined to the back surface of the ceramic substrate 1 by soldering or brazing, and a plurality of solder bumps 4 are printed.

また、プリント基板２の表面の導体ランド５および接地導体パターン７に、熱応力吸収部材６およびはんだバンプ４のそれぞれと接合するための、はんだを印刷する。
このとき、熱応力吸収部材６とはんだバンプ４における、プリント基板２との接合面の高さの寸法差を吸収するように、接地導体パターン７に印刷するはんだ厚みを調整しておく。 In addition, solder for bonding the thermal stress absorbing member 6 and the solder bump 4 to each of the conductor land 5 and the ground conductor pattern 7 on the surface of the printed board 2 is printed.
At this time, the thickness of the solder printed on the ground conductor pattern 7 is adjusted so as to absorb the dimensional difference in the height of the joint surface between the thermal stress absorbing member 6 and the solder bump 4 and the printed board 2.

次いで、プリント基板２のはんだ印刷後、セラミック基板１とプリント基板２をはんだリフローにより接合することで、熱応力吸収部材６およびはんだバンプ４をプリント基板２に接合する。
かくして、セラミック基板１とプリント基板２のはんだバンプ４によるＢＧＡ実装が施されることとなる。 Next, after the printed circuit board 2 is solder-printed, the ceramic substrate 1 and the printed circuit board 2 are joined by solder reflow to join the thermal stress absorbing member 6 and the solder bump 4 to the printed circuit board 2.
Thus, BGA mounting by the solder bumps 4 of the ceramic substrate 1 and the printed circuit board 2 is performed.

なお、このはんだリフロー時に、プリント基板２に実装する他の電気部品（図示せず）についても、同様にリフローによりはんだ付けしても良い。これによって、電気部品の実装とＢＧＡ実装を同時に行うことができるので、回路基板装置の組み立て効率が良く、熱応力吸収部材６を設けることによる製造コストの増加を抑えることができる。   At the time of this solder reflow, other electrical components (not shown) mounted on the printed circuit board 2 may be similarly soldered by reflow. As a result, electrical component mounting and BGA mounting can be performed simultaneously, so that the assembly efficiency of the circuit board device is good and an increase in manufacturing cost due to the provision of the thermal stress absorbing member 6 can be suppressed.

以上説明した通り、実施の形態１による回路基板装置は、ＢＧＡ実装により接合されるセラミック基板１とプリント基板２の間に熱応力吸収部材６を接合し、熱応力吸収部材６として熱膨張係数がセラミック基板１とプリント基板２の中間の値を有する金属材料を用いることで、回路基板装置の晒される環境に温度変化が生じても、プリント基板２とセラミック基板１に生じる熱歪みや伸び、熱応力を緩和することができるので、ＢＧＡ実装の接合信頼性を高めることができる。   As described above, the circuit board device according to the first embodiment joins the thermal stress absorbing member 6 between the ceramic substrate 1 and the printed board 2 to be joined by BGA mounting, and the thermal stress absorbing member 6 has a thermal expansion coefficient. By using a metal material having an intermediate value between the ceramic substrate 1 and the printed circuit board 2, even if a temperature change occurs in the environment to which the circuit board device is exposed, thermal distortion and elongation generated in the printed circuit board 2 and the ceramic substrate 1 Since stress can be relieved, the joining reliability of BGA mounting can be improved.

また、熱応力吸収部材６は金属からなるので、熱応力や破壊に強い。さらに、熱応力吸収部材６の内側は中空のため、セラミック基板１とプリント基板２間の誘電率に影響を与えることがなく、ＲＦ通過特性が劣化したり個体差を生じることもない。このため、セラミック基板１とプリント基板２との異種材料基板間の接合において、接合信頼性の高い構造を得ることができる。   Further, since the thermal stress absorbing member 6 is made of metal, it is resistant to thermal stress and destruction. Further, since the inside of the thermal stress absorbing member 6 is hollow, the dielectric constant between the ceramic substrate 1 and the printed circuit board 2 is not affected, and the RF transmission characteristics are not deteriorated or individual differences are not caused. For this reason, in the joining between the dissimilar material substrates of the ceramic substrate 1 and the printed circuit board 2, a structure with high bonding reliability can be obtained.

さらに、熱応力吸収部材６は導電性金属からなり、セラミック基板１に設けられた接地導体に接続されるとともに、プリント基板２に設けられた接地導体パターン７に対して、はんだ付けにより接合されるので、ＢＧＡ実装部の周囲を電磁遮蔽することができる。これにより、セラミック基板１とプリント基板２のはんだバンプ４接合部からの信号漏洩を抑えることができるとともに、外部からＢＧＡ実装部に混入するノイズを遮断することができる。   Further, the thermal stress absorbing member 6 is made of a conductive metal, and is connected to a ground conductor provided on the ceramic substrate 1 and is joined to a ground conductor pattern 7 provided on the printed circuit board 2 by soldering. Therefore, the surroundings of the BGA mounting part can be electromagnetically shielded. Thereby, while being able to suppress the signal leakage from the solder bump 4 junction part of the ceramic board | substrate 1 and the printed circuit board 2, the noise mixed in a BGA mounting part from the outside can be interrupted | blocked.

なお、接地導体パターン７は、ＢＧＡ実装部の周囲に断続的、または部分的に設けても良い。このようにすることで、熱応力吸収部材６とセラミック基板１およびプリント基板２との接合部の剛性を低下させることができるので、熱応力吸収部材６とセラミック基板１およびプリント基板２との接合部での熱応力を、緩和することができる。   The ground conductor pattern 7 may be provided intermittently or partially around the BGA mounting portion. By doing so, the rigidity of the joint between the thermal stress absorbing member 6 and the ceramic substrate 1 and the printed board 2 can be reduced, so that the thermal stress absorbing member 6 and the ceramic substrate 1 and the printed board 2 are joined. The thermal stress at the part can be relaxed.

１ セラミック基板、２ プリント基板、４ はんだバンプ、５ 導体ランド、６ 熱応力吸収部材、７ 接地導体パターン。   DESCRIPTION OF SYMBOLS 1 Ceramic substrate, 2 Printed circuit board, 4 Solder bump, 5 Conductor land, 6 Thermal stress absorption member, 7 Grounding conductor pattern.

Claims (2)

セラミック基板と、
有機材料からなるプリント基板と、
上記セラミック基板とプリント基板を接合する複数のはんだバンプと、
上記複数のはんだバンプの接合部を取り囲むように、上記セラミック基板とプリント基板の間に接合され、上記セラミック基板とプリント基板の中間の線膨張係数を有した金属からなる熱応力吸収部材と、
を備えた回路基板装置。 A ceramic substrate;
Printed circuit boards made of organic materials,
A plurality of solder bumps for joining the ceramic substrate and the printed circuit board;
A thermal stress absorbing member made of a metal having a linear expansion coefficient intermediate between the ceramic substrate and the printed circuit board, which is bonded between the ceramic substrate and the printed circuit board so as to surround the joint portions of the plurality of solder bumps;
A circuit board device comprising: 上記熱応力吸収部材は、銅タングステンまたは銅モリブデンを含有する導電性金属からなり、
上記熱応力吸収部材は、上記セラミック基板に設けられた接地導体に接続されるとともに、上記プリント基板に設けられた接地導体に対し、はんだにより接合されたことを特徴とする請求項１記載の回路基板装置。 The thermal stress absorbing member is made of a conductive metal containing copper tungsten or copper molybdenum,
2. The circuit according to claim 1, wherein the thermal stress absorbing member is connected to a ground conductor provided on the ceramic substrate and is joined to a ground conductor provided on the printed board by solder. Board device.
JP2010016658A 2010-01-28 2010-01-28 Circuit board device Pending JP2011155190A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10126127B2 (en) 2016-04-29 2018-11-13 Microsoft Technology Licensing, Llc Athermalized mounting of inertial measurement unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10126127B2 (en) 2016-04-29 2018-11-13 Microsoft Technology Licensing, Llc Athermalized mounting of inertial measurement unit

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