JP2007027341A - Printed wiring board and electronic-components mounting structure - Google Patents

Printed wiring board and electronic-components mounting structure Download PDF

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Publication number
JP2007027341A
JP2007027341A JP2005206325A JP2005206325A JP2007027341A JP 2007027341 A JP2007027341 A JP 2007027341A JP 2005206325 A JP2005206325 A JP 2005206325A JP 2005206325 A JP2005206325 A JP 2005206325A JP 2007027341 A JP2007027341 A JP 2007027341A
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Prior art keywords
electrode pad
wiring board
printed wiring
semiconductor device
outer peripheral
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Japanese (ja)
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Masahiro Kawate
昌大 河手
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Canon Inc
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Canon Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide the structure which improves the reliability of the solder joint between a multilayer wiring board and a BGA. <P>SOLUTION: The printed wiring board is laminated alternately with an insulating layer 10 and a conductive wiring layer 20, in such a way that a conductive wiring layer has a circuit pattern 21 and the through-hole 11 of the insulating layer has a filled via 12 made by a filler which is connected to a via land 13. The wiring layer of the uppermost layer having an electrode pad 22 constitutes a mounting surface for mounting a BGA40. A solder resist layer 30 covers a perimeter 22a of an electrode pad, and has an opening 31 by which a central solder joint 22b is made exposed. On the perimeter edge of the electrode pad, a perimeter notch 22c is formed in the diagonal direction of the BGA, so that bending deformation should not be prevented for heat distortion by making the perimeter notch inscribed to the opening of a solder resist layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、電子部品をはんだ接合するための電極パッド直下に、フィルドビア等を垂直に配置した多層のプリント配線板において、特に、曲げ応力が繰り返し電極パッドのはんだ接合部に加わっても、クラック等の欠陥が発生することがない信頼性の高いプリント配線板および電子部品実装構造に関するものである。   The present invention relates to a multilayer printed wiring board in which filled vias and the like are arranged vertically immediately below an electrode pad for soldering an electronic component, particularly when a bending stress is repeatedly applied to a solder joint of an electrode pad. The present invention relates to a highly reliable printed wiring board and an electronic component mounting structure in which no defects occur.

小さな面積で多端子の接続を可能にする電子部品として、ボールグリッドアレイパッケージ(BGA)型やチップサイズパッケージ(CSP)型の半導体装置が多くの電子機器に使用されている。BGA型の半導体装置は、パッケージ裏面のインターポーザ基板上に接続端子であるはんだボールが格子状に配置され、プリント配線板表面に同じく格子状に配置された電極パッド上にはんだ接合される。   Ball grid array package (BGA) type and chip size package (CSP) type semiconductor devices are used in many electronic devices as electronic components that enable connection of multiple terminals in a small area. In the BGA type semiconductor device, solder balls as connection terminals are arranged in a grid pattern on an interposer substrate on the back side of the package, and are soldered onto electrode pads that are also arranged in a grid pattern on the surface of the printed wiring board.

BGA型の半導体装置とプリント配線板上の電極パッドをはんだ接合する際のはんだ接合構造には、2種類あり、1つは、図5の(a)に示すように、BGA型の半導体装置140を電極パッド122にSMD(Solder Masked Defined )構造で実装したものである。この構成は、絶縁層110と配線パターン121を有する導体配線層120を交互に積層し、絶縁層110の貫通孔111にフィルドビア112を充填して上層側にビアランド113を設けた多層のプリント配線板である。また、電極パッド122の外径よりもソルダーレジスト層130の開口131の開口径が小さく形成され、電極パッド122の外周部がソルダーレジスト層130によって覆われている。このため落下衝撃など機械的ストレスを受けた場合、電極パッド122と絶縁層110との界面での剥離が生じにくい構造となっている。   There are two types of solder joint structures when soldering the BGA type semiconductor device and the electrode pads on the printed wiring board, one is a BGA type semiconductor device 140 as shown in FIG. Is mounted on the electrode pad 122 with an SMD (Solder Masked Defined) structure. This configuration is a multilayer printed wiring board in which insulating wiring layers 120 and conductive wiring layers 120 having wiring patterns 121 are alternately stacked, filled vias 112 are filled in through holes 111 of insulating layers 110, and via lands 113 are provided on the upper layer side. It is. In addition, the opening diameter of the opening 131 of the solder resist layer 130 is smaller than the outer diameter of the electrode pad 122, and the outer peripheral portion of the electrode pad 122 is covered with the solder resist layer 130. Therefore, when subjected to mechanical stress such as a drop impact, the structure is such that peeling at the interface between the electrode pad 122 and the insulating layer 110 does not easily occur.

一方、図4は、BGA型の半導体装置140と電極パッド122をNSMD(Non Solder Masked Defined )構造で実装したものを示す。電極パッド122の外径よりもソルダーレジスト層130の開口131の開口径が大きく形成され、電極パッド122の外周縁を含む全体が剥き出しの構造となっている。このためリフローなどのはんだ接合時に、はんだ132が電極パッド122の表面だけでなく側面まで回りこむように接合される。従って、はんだ接合強度が増し温度サイクル寿命が長くなるが、電極パッド122の外径が小さくて、しかもソルダーレジスト層130で覆われていないので、機械的ストレスによる電極パッド122の剥離が生じやすい。   On the other hand, FIG. 4 shows a BGA type semiconductor device 140 and an electrode pad 122 mounted with an NSMD (Non Solder Masked Defined) structure. The opening diameter of the opening 131 of the solder resist layer 130 is formed larger than the outer diameter of the electrode pad 122, and the entire structure including the outer peripheral edge of the electrode pad 122 is exposed. For this reason, at the time of soldering such as reflow, the solder 132 is joined not only to the surface of the electrode pad 122 but also to the side surface. Therefore, although the solder joint strength is increased and the temperature cycle life is increased, the outer diameter of the electrode pad 122 is small and is not covered with the solder resist layer 130, so that the electrode pad 122 is easily peeled off due to mechanical stress.

現在、BGA型の半導体装置は高密度化を図るために狭ピッチ、多端子化が求められている。端子間のピッチが狭くなると、プリント配線板において電極パッド間も狭ピッチになることから隣接する電極パッド間に配線を通すことが困難になる。また内層に配線を落とすスルーホールを配置するスペースを確保するのも同様に困難になる。従って、BGA型の半導体装置の接続端子を実装する電極パッド直下にビアホールなどを配置しパッドオンビア構造とすることでしか、狭ピッチ、多端子のBGA型の半導体装置の配線を引き出すことができなくなる。   Currently, a BGA type semiconductor device is required to have a narrow pitch and multiple terminals in order to increase the density. If the pitch between the terminals is narrowed, the electrode pads on the printed wiring board are also narrowed, so it is difficult to pass the wiring between the adjacent electrode pads. It is also difficult to secure a space for arranging a through hole for dropping the wiring in the inner layer. Therefore, the wiring of a narrow-pitch, multi-terminal BGA semiconductor device can be drawn only by arranging a via hole or the like immediately below the electrode pad on which the connection terminal of the BGA semiconductor device is mounted to have a pad-on-via structure.

このようなビアホールにはスルーホール内を樹脂などの充填材などで充填したものや、ビアをめっきや導電ペーストなどの導電材料によって充填してフィルドビアとしたものがある。フィルドビアを垂直に配置したスタックドビア構造とすることで、第2、第3、第4層など、内層の深くまで配線を引き出すことが可能になる。   Such via holes include those in which the through holes are filled with a filler such as a resin, and those that are filled with a conductive material such as plating or conductive paste to form a filled via. By adopting a stacked via structure in which filled vias are arranged vertically, it becomes possible to lead out wiring deep into the inner layer such as the second, third, and fourth layers.

従来、フィルドビアを垂直に配置したスタックドビア構造を有するプリント配線板の接続信頼性が低下する問題は、例えば特許文献1で指摘されている。
特開2004−6576号公報
Conventionally, for example, Patent Document 1 points out a problem that connection reliability of a printed wiring board having a stacked via structure in which filled vias are arranged vertically is lowered.
JP 2004-6576 A

電極パッド直下にフィルドビアまたはスルーホールを垂直に配置したスタックドビア構造等においては、多層のプリント配線板とBGA型の半導体装置のはんだ接合部に熱が印加された場合、プリント配線板と半導体装置とのはんだ接合部に曲げおよび反り変形が生じる。この時、図5の装置では、(b)に示すように、電極パッド122の直下に配置したスタックドビア構造がプリント配線板とBGA型の半導体装置140のはんだ接合部の反りおよび曲げ変形を拘束する。そのため、はんだ接合部を基点として矢印で示す向きに曲げ応力が働き、はんだ132の曲げ変形を電極パッド122が妨げることにより、BGA型の半導体装置140の内側から外側方向にクラックが生じ、はんだ接合部の信頼性を著しく低下させるという問題があった。   In a stacked via structure in which filled vias or through-holes are vertically arranged immediately below the electrode pad, when heat is applied to the solder joint between the multilayer printed wiring board and the BGA type semiconductor device, the printed wiring board and the semiconductor device Bending and warping deformation occurs in the solder joint. At this time, in the apparatus of FIG. 5, as shown in FIG. 5B, the stacked via structure arranged immediately below the electrode pad 122 restrains the warpage and bending deformation of the solder joint portion between the printed wiring board and the BGA type semiconductor device 140. . For this reason, bending stress acts in the direction indicated by the arrow with the solder joint as a base point, and the electrode pad 122 prevents the solder 132 from bending deformation, thereby generating a crack from the inside to the outside of the BGA type semiconductor device 140. There is a problem that the reliability of the part is remarkably lowered.

本発明は、上記従来の技術の有する未解決の課題に鑑みてなされたものであり、スタックドビア構造等を有する多層のプリント配線板とBGA型の半導体装置等の電子部品のはんだ接合の信頼性を向上させるものである。また、熱が繰り返し印加された場合でも曲げ応力によるクラックが発生し難いプリント配線板および電子部品実装構造を提供することを目的とするものである。   The present invention has been made in view of the above-mentioned unsolved problems of the prior art, and has improved the reliability of solder bonding between a multilayer printed wiring board having a stacked via structure and the like and an electronic component such as a BGA type semiconductor device. It is to improve. Another object of the present invention is to provide a printed wiring board and an electronic component mounting structure in which cracks due to bending stress hardly occur even when heat is repeatedly applied.

本発明のプリント配線板は、絶縁層と導体配線層が交互に積層された多層回路と、前記多層回路の最上層に電子部品をはんだ接合するための電極パッドと、前記電極パッドのはんだ接合部を除く外周部および前記多層回路の最上層を覆うソルダーレジスト層と、を有し、前記電極パッドの外周縁の一部が、前記電極パッドの前記はんだ接合部を露出させるための前記ソルダーレジスト層の開口に内接していることを特徴とする。   A printed wiring board according to the present invention includes a multilayer circuit in which insulating layers and conductor wiring layers are alternately laminated, an electrode pad for soldering an electronic component to the uppermost layer of the multilayer circuit, and a solder joint portion of the electrode pad A solder resist layer that covers an outer peripheral portion excluding the uppermost layer of the multilayer circuit, and a part of the outer peripheral edge of the electrode pad exposes the solder joint portion of the electrode pad. It is characterized by inscribed in the opening.

BGA型の半導体装置等の電子部品のはんだ接合部に熱が印加された場合に、電極パッド直下に配置したスタックドビア構造やパットオンビア構造がはんだ接合部の反りや曲げ変形を拘束し、その結果、はんだ接合部を基点とした曲げ応力が働く。そこで、曲げ応力が働く向きに電極パッドの外径寸法を縮小して、ソルダーレジスト層の開口に内接させるための外周切欠部を形成することで、はんだ接合部の曲げ変形等を妨げないように構成する。これによって、はんだ接合部の熱歪に起因するクラック発生を抑制し、電気接合の信頼性を向上させる。   When heat is applied to a solder joint of an electronic component such as a BGA type semiconductor device, the stacked via structure or the pad-on-via structure arranged immediately below the electrode pad restrains the warp or bending deformation of the solder joint, and as a result, the solder Bending stress based on the joint acts. Therefore, the outer diameter of the electrode pad is reduced in the direction in which the bending stress works, and the outer peripheral notch for inscribed in the opening of the solder resist layer is formed so as not to hinder bending deformation of the solder joint. Configure. As a result, the occurrence of cracks due to the thermal strain of the solder joint is suppressed, and the reliability of electrical joining is improved.

電子部品を実装する電極パッドを信頼性の高いSMD構造にすることで高密度な配線を可能とし、しかも電極パッドの剥離強度等を向上させることで、高密度で信頼性の高い電子部品実装構造を実現できる。   High-density and highly reliable electronic component mounting structure by enabling high-density wiring by making the electrode pad for mounting electronic components a highly reliable SMD structure and improving the peel strength of the electrode pad Can be realized.

本発明を実施するための最良の形態を図面に基づいて説明する。   The best mode for carrying out the present invention will be described with reference to the drawings.

図1の(b)、(c)に示すように、本実施の形態によるプリント配線板は、絶縁樹脂による絶縁層10と導体配線層20を交互に積層した多層回路を有する。導体配線層20は配線パターン21を有し、絶縁層10の貫通孔11は充填材によるフィルドビア12を有し、各フィルドビア12は上層側の導体配線層20に形成されたビアランド13に接続される。   As shown in FIGS. 1B and 1C, the printed wiring board according to the present embodiment has a multilayer circuit in which insulating layers 10 and conductor wiring layers 20 made of insulating resin are alternately stacked. The conductor wiring layer 20 has a wiring pattern 21, the through hole 11 of the insulating layer 10 has a filled via 12 made of a filler, and each filled via 12 is connected to a via land 13 formed in the upper conductor wiring layer 20. .

最上層の導体配線層20は、電極パッド22を備えており、電子部品であるBGA型の半導体装置40を実装するための実装面を構成する。ソルダーレジスト層30は、電極パッド22の外周部22aを覆い、中央のはんだ接合部22bを露出させる開口31を有する。はんだ接合部22bをはんだ32によって半導体装置40のパッケージに接合することで、はんだ接合構造が形成される。   The uppermost conductor wiring layer 20 includes electrode pads 22 and constitutes a mounting surface for mounting a BGA type semiconductor device 40 which is an electronic component. The solder resist layer 30 has an opening 31 that covers the outer peripheral portion 22a of the electrode pad 22 and exposes the central solder joint portion 22b. By joining the solder joint portion 22b to the package of the semiconductor device 40 with the solder 32, a solder joint structure is formed.

このプリント配線板は、例えばガラス繊維を織り込んだガラスクロスにエポキシ樹脂等を含浸させて成る板状の絶縁層10の両面に銅めっき膜または銅箔からなる配線パターン21を形成し、互いを交互に積層した多層構造を有する。プリント配線板の最上層において、半導体装置40と接合する電極パッド22のはんだ接合部22bの外側の外周部22aはソルダーレジスト層30で覆われている。絶縁層10の貫通孔11はレーザ光などで形成され、フィルドビア12の材質は銅等のめっきや導電性のペーストなど導電材あるいは樹脂などの非導電材である。各電極パッド22の直下に複数のフィルドビア12が垂直に配列され、各導体配線層20の配線パターン21を電気的に接続している。BGA型の半導体装置40は、底部インターポーザ上にはんだボールがアレイ状に配列されている。   In this printed wiring board, for example, a wiring pattern 21 made of a copper plating film or a copper foil is formed on both surfaces of a plate-like insulating layer 10 formed by impregnating a glass cloth woven with glass fiber with an epoxy resin or the like, and alternately. It has a multilayer structure laminated on. In the uppermost layer of the printed wiring board, the outer peripheral portion 22 a outside the solder joint portion 22 b of the electrode pad 22 to be joined to the semiconductor device 40 is covered with the solder resist layer 30. The through hole 11 of the insulating layer 10 is formed by a laser beam or the like, and the material of the filled via 12 is a conductive material such as a plating such as copper or a conductive paste or a non-conductive material such as a resin. A plurality of filled vias 12 are vertically arranged immediately below each electrode pad 22 to electrically connect the wiring patterns 21 of each conductor wiring layer 20. In the BGA type semiconductor device 40, solder balls are arranged in an array on the bottom interposer.

電極パッド22上にソルダーペーストが塗布され、BGA型の半導体装置40が搭載される。例えばリフローなどではんだ32の融点以上に加熱し、BGA型の半導体装置40を電極パッド22上にはんだ接合する。   A solder paste is applied on the electrode pad 22, and the BGA type semiconductor device 40 is mounted. For example, the BGA type semiconductor device 40 is soldered onto the electrode pad 22 by heating to the melting point of the solder 32 or higher by reflow or the like.

図1の(a)に示すように電極パッド22の外周縁には、A−A線に沿って半導体装置40の対角線の方向に外周切欠部22cが形成され、この外周切欠部22cをソルダーレジスト層30の開口31に内接させることで、熱歪による曲げ変形を妨げないように構成される。   As shown in FIG. 1A, an outer peripheral notch 22c is formed on the outer peripheral edge of the electrode pad 22 along the line AA in the diagonal direction of the semiconductor device 40. The outer peripheral notch 22c is formed as a solder resist. By being inscribed in the opening 31 of the layer 30, it is configured so as not to prevent bending deformation due to thermal strain.

図1の(a)に示すように、電極パッド22は真円形状であって、その外周部22aはソルダーレジスト層30によって覆われている。また、中央のはんだ接合部22bのみソルダーレジスト層30の開口31から露出し、(b)に示すように、BGA型の半導体装置40にはんだ接合される。電極パッド22は、図2に示すように、A−A線に沿った半導体装置40の対角方向の両側に、一対の外周切欠部22cを備えている。すなわち、ソルダーレジスト層30の開口31の接線方向に、それより外側の領域にある電極パッド22の外周縁の一部を、プリント配線板作製工程においてエッチングによって局所的に除去し、外周切欠部22cを形成する。なお、ソルダーレジスト層30の開口31は真円で形成されている。   As shown in FIG. 1A, the electrode pad 22 has a perfect circle shape, and the outer peripheral portion 22 a is covered with a solder resist layer 30. Further, only the central solder joint portion 22b is exposed from the opening 31 of the solder resist layer 30, and is soldered to the BGA type semiconductor device 40 as shown in FIG. As shown in FIG. 2, the electrode pad 22 includes a pair of outer peripheral notches 22 c on both sides in the diagonal direction of the semiconductor device 40 along the line AA. In other words, in the tangential direction of the opening 31 of the solder resist layer 30, a part of the outer peripheral edge of the electrode pad 22 in the region outside it is locally removed by etching in the printed wiring board manufacturing process, and the outer peripheral notch 22c. Form. The opening 31 of the solder resist layer 30 is formed in a perfect circle.

図2に示すように、半導体装置40の接続端子41の間隔が例えば、0.5mmピッチの場合、SMD構造でソルダーレジスト精度を±0.050mmとすると、電極パッド22の外径を0.4mm、ソルダーレジスト層30の開口31の開口径は0.3mmとする必要がある。内層には、電気的接続をするためにビア径0.15mmのフィルドビア12を各層にわたり同心状に配置しスタックドビア構造としている。   As shown in FIG. 2, when the interval between the connection terminals 41 of the semiconductor device 40 is, for example, 0.5 mm pitch, the outer diameter of the electrode pad 22 is 0.4 mm when the solder resist accuracy is ± 0.050 mm in the SMD structure. The opening diameter of the opening 31 of the solder resist layer 30 needs to be 0.3 mm. In the inner layer, a filled via 12 having a via diameter of 0.15 mm is disposed concentrically over each layer in order to make an electrical connection, thereby forming a stacked via structure.

図1の(b)は、半導体装置40の実装後における図1の(a)のA−A線に沿ってとった断面図、(c)は(a)のA−A線に直交するB−B線に沿ってとった断面図である。図1の(b)に示すA−A線に沿った断面では、外周切欠部22cが形成されているためソルダーレジスト層30の開口31の開口径が電極パッド22の外径と等しく、内接しており、従って、はんだ接合部22bより外側に電極パッド22が存在しない。一方、図1の(c)に示すように、B−B線に沿った断面では、電極パッド22の外径よりもソルダーレジスト層30の開口31の開口径が小さく、電極パッド22の外周部22aがソルダーレジスト層30によって覆われている。   1B is a cross-sectional view taken along the line AA in FIG. 1A after mounting the semiconductor device 40, and FIG. 1C is a cross-sectional view taken along the line AA in FIG. It is sectional drawing taken along the -B line. In the cross section along the line AA shown in FIG. 1B, since the outer peripheral notch 22c is formed, the opening diameter of the opening 31 of the solder resist layer 30 is equal to the outer diameter of the electrode pad 22 and is inscribed. Therefore, the electrode pad 22 does not exist outside the solder joint portion 22b. On the other hand, as shown in FIG. 1C, the opening diameter of the opening 31 of the solder resist layer 30 is smaller than the outer diameter of the electrode pad 22 in the cross section along the line BB, and the outer peripheral portion of the electrode pad 22. 22 a is covered with the solder resist layer 30.

熱が印加された場合は、電極パッド22の直下に配置したスタックドビア構造が半導体装置40との間のはんだ接合領域の反りや曲げ変形を拘束するため、はんだ接合領域を基点とした曲げ応力が働く。しかし、曲げ応力が働く方向に電極パッド22の外周切欠部22cが設けられていると、はんだ接合部22bの曲げ変形が妨げられることがない。そのため、BGA型の半導体装置40の内側から外側方向、すなわち図1の(a)のA−A線の方向に生じるクラック発生を抑制できる。その結果、信頼性の高いはんだ接合構造を実現できる。   When heat is applied, the stacked via structure disposed immediately below the electrode pad 22 restrains warpage or bending deformation of the solder joint area with the semiconductor device 40, and therefore bending stress based on the solder joint area acts. . However, if the outer circumferential notch 22c of the electrode pad 22 is provided in the direction in which the bending stress acts, the bending deformation of the solder joint 22b is not hindered. Therefore, it is possible to suppress the occurrence of cracks occurring from the inner side to the outer side of the BGA type semiconductor device 40, that is, in the direction of the AA line in FIG. As a result, a highly reliable solder joint structure can be realized.

また、ソルダーレジスト層30の開口径は従来構造と同じであるから、同じ接合面積で実装可能であり、電極パッド構造をSMD構造とすることで、電極パッド22および電極パッド22からの引き出しネック部の剥離などの問題が起こらない。加えて、電極パッド22がBGA型の半導体装置40の対角方向に対して実質的に直角方向に長尺形状となっていることから、その方向に対して配線が引き出しやすい電極構造となっている。   Further, since the opening diameter of the solder resist layer 30 is the same as that of the conventional structure, the solder resist layer 30 can be mounted with the same bonding area, and by making the electrode pad structure an SMD structure, the electrode pad 22 and the neck portion that is drawn from the electrode pad 22 There will be no problems such as peeling. In addition, since the electrode pad 22 is elongated in a direction substantially perpendicular to the diagonal direction of the BGA type semiconductor device 40, an electrode structure in which wiring is easily drawn out in the direction is obtained. Yes.

図3の(a)に示すように、本実施例の電極パッド22は真円形状からBGA型の半導体装置40の対角方向(A−A線の方向)においてソルダーレジスト層30の開口31との接線より外側の部分に外周切欠部22cを形成している。外周切欠部22cは、半導体装置40の対角方向内側に位置する領域のみを、プリント配線板作製過程におけるエッチングで除去されている。一方、ソルダーレジスト層30の開口31は真円で形成されている。   As shown in FIG. 3A, the electrode pad 22 of the present embodiment has an opening 31 of the solder resist layer 30 in the diagonal direction (the direction of the line AA) of the BGA type semiconductor device 40 from the perfect circle shape. The outer peripheral notch 22c is formed in a portion outside the tangent line. Only the region located on the diagonally inner side of the semiconductor device 40 is removed by etching in the printed wiring board manufacturing process. On the other hand, the opening 31 of the solder resist layer 30 is formed in a perfect circle.

図3の(b)に示すように、(a)のA−A線に沿った断面では、半導体装置40の対角方向内側においてはソルダーレジスト開口径が電極パッド径と同じであって内接しているために、はんだ接合部22bより外側に電極パッド22が存在していない。一方、半導体装置40の対角方向外側においては、電極パッド径よりもソルダーレジスト開口径が小さく形成され、電極パッド22の外周部22aがソルダーレジスト層30によって覆われている。また、図3の(c)に示すように、B−B線に沿った断面では、電極パッド径よりもソルダーレジスト開口径が小さく形成され、電極パッド22の外周部22aがソルダーレジスト層30によって覆われている。   As shown in FIG. 3B, in the cross section taken along line AA in FIG. 3A, the solder resist opening diameter is the same as the electrode pad diameter on the diagonally inner side of the semiconductor device 40, and is inscribed. Therefore, the electrode pad 22 does not exist outside the solder joint portion 22b. On the other hand, on the diagonally outer side of the semiconductor device 40, the solder resist opening diameter is formed smaller than the electrode pad diameter, and the outer peripheral portion 22 a of the electrode pad 22 is covered with the solder resist layer 30. Further, as shown in FIG. 3C, the solder resist opening diameter is formed smaller than the electrode pad diameter in the cross section along the line BB, and the outer peripheral portion 22 a of the electrode pad 22 is formed by the solder resist layer 30. Covered.

熱が印加された場合、電極パッド22の直下に配置したスタックドビア構造が多層のプリント配線板とBGA型の半導体装置40とのはんだ接合領域の反りや曲げ変形を拘束する。そのため、はんだ接合領域を基点とした曲げ応力が働くが、曲げ応力が働く向きに電極パッド22が存在しないため、はんだ接合領域の曲げ変形を妨げない。従って、BGA型の半導体装置40の内側から外側方向に生じるクラック発生を抑制でき、信頼性の高い接合構造を提供できる。   When heat is applied, the stacked via structure disposed immediately below the electrode pad 22 restrains warpage and bending deformation of the solder joint region between the multilayer printed wiring board and the BGA type semiconductor device 40. Therefore, a bending stress with the solder joint region as a base point works, but the electrode pad 22 does not exist in the direction in which the bending stress acts, and thus bending deformation of the solder joint region is not hindered. Therefore, it is possible to suppress the generation of cracks that occur from the inside to the outside of the BGA type semiconductor device 40, and to provide a highly reliable joint structure.

また、ソルダーレジスト開口径を変化させないため、従来と同様の実装方法でかつ同じ接合面積で電極パッド構造をSMD構造とすることが可能であり、電極パッドおよび電極パッドからの引き出しネック部の剥離などの問題が起こらない。   Also, since the solder resist opening diameter is not changed, it is possible to make the electrode pad structure into the SMD structure with the same mounting area as the conventional mounting method, peeling of the electrode pad and the lead neck portion from the electrode pad, etc. The problem does not occur.

実施例1によるプリント配線板および電子部品実装構造を示すもので、(a)は電極パッドの形状とソルダーレジスト層の開口寸法を説明する平面図、(b)は(a)のA−A線に沿ってとった断面図、(c)は(a)のB−B線に沿ってとった断面図である。The printed wiring board and electronic component mounting structure by Example 1 are shown, (a) is a top view explaining the shape of an electrode pad and the opening dimension of a soldering resist layer, (b) is the AA line of (a). (C) is sectional drawing taken along the BB line of (a). BGA型の半導体装置の実装領域を示す平面図である。It is a top view which shows the mounting area | region of a BGA type semiconductor device. 実施例2によるプリント配線板および電子部品実装構造を示すもので、(a)は電極パッドの形状とソルダーレジスト層の開口寸法を説明する平面図、(b)は(a)のA−A線に沿ってとった断面図、(c)は(a)のB−B線に沿ってとった断面図である。The printed wiring board and electronic component mounting structure by Example 2 are shown, (a) is a top view explaining the shape of an electrode pad and the opening dimension of a soldering resist layer, (b) is the AA line of (a). (C) is sectional drawing taken along the BB line of (a). 一従来例による電子部品実装構造を説明する図である。It is a figure explaining the electronic component mounting structure by one prior art example. 別の従来例を説明する図である。It is a figure explaining another prior art example.

符号の説明Explanation of symbols

10 絶縁層
12 フィルドビア
13 ビアランド
20 導体配線層
21 配線パターン
22 電極パッド
22c 外周切欠部
30 ソルダーレジスト層
31 開口
32 はんだ
40 半導体装置
41 接続端子
DESCRIPTION OF SYMBOLS 10 Insulating layer 12 Filled via 13 Via land 20 Conductor wiring layer 21 Wiring pattern 22 Electrode pad 22c Outer periphery notch 30 Solder resist layer 31 Opening 32 Solder 40 Semiconductor device 41 Connection terminal

Claims (6)

絶縁層と導体配線層が交互に積層された多層回路と、前記多層回路の最上層に電子部品をはんだ接合するための電極パッドと、前記電極パッドのはんだ接合部を除く外周部および前記多層回路の最上層を覆うソルダーレジスト層と、を有し、前記電極パッドの外周縁の一部が、前記電極パッドの前記はんだ接合部を露出させるための前記ソルダーレジスト層の開口に内接していることを特徴とするプリント配線板。   A multilayer circuit in which insulating layers and conductor wiring layers are alternately laminated, an electrode pad for soldering an electronic component to the uppermost layer of the multilayer circuit, an outer peripheral portion of the electrode pad excluding the solder joint, and the multilayer circuit A part of the outer peripheral edge of the electrode pad is inscribed in an opening of the solder resist layer for exposing the solder joint portion of the electrode pad. Printed wiring board characterized by 前記電極パッドの直下にフィルドビアを各層にわたり同心状に配置したスタックドビア構造を有することを特徴とする請求項1記載のプリント配線板。   2. The printed wiring board according to claim 1, wherein the printed wiring board has a stacked via structure in which filled vias are arranged concentrically over the respective layers immediately below the electrode pads. 前記電極パッドの直下にスルーホールを同心状に配置したパッドオンビア構造を有することを特徴とする請求項1記載のプリント配線板。   The printed wiring board according to claim 1, wherein the printed wiring board has a pad-on-via structure in which through holes are arranged concentrically immediately below the electrode pads. 前記電子部品がBGA型の半導体装置であり、前記電極パッドの前記外周縁に、前記半導体装置の対角線の方向に対称に配設された一対の外周切欠部を備えていることを特徴とする請求項1ないし3いずれか1項記載のプリント配線板。   The electronic component is a BGA type semiconductor device, and is provided with a pair of outer peripheral notches disposed symmetrically in a diagonal direction of the semiconductor device at the outer peripheral edge of the electrode pad. Item 4. The printed wiring board according to any one of Items 1 to 3. 前記電子部品がBGA型の半導体装置であり、前記電極パッドの前記外周縁に、前記半導体装置の対角線の方向の内側に配設された外周切欠部を備えていることを特徴とする請求項1ないし3いずれか1項記載のプリント配線板。   2. The electronic component according to claim 1, wherein the electronic component is a BGA type semiconductor device, and an outer peripheral notch portion disposed on an inner side in a diagonal direction of the semiconductor device is provided on the outer peripheral edge of the electrode pad. The printed wiring board according to any one of 3 to 3. 請求項1ないし5いずれか1項記載のプリント配線板と、前記プリント配線板に実装された電子部品を有することを特徴とする電子部品実装構造。   6. An electronic component mounting structure comprising: the printed wiring board according to claim 1; and an electronic component mounted on the printed wiring board.
JP2005206325A 2005-07-15 2005-07-15 Printed wiring board and electronic-components mounting structure Pending JP2007027341A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009094216A (en) * 2007-10-05 2009-04-30 Sumitomo Bakelite Co Ltd Manufacturing method of semiconductor device, and manufacturing method of printed circuit board for semiconductor device
WO2010073831A1 (en) * 2008-12-25 2010-07-01 インターナショナル・ビジネス・マシーンズ・コーポレーション Multilayer circuit board and method for manufacturing same
WO2022107389A1 (en) 2020-11-18 2022-05-27 株式会社フジクラ Wiring board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009094216A (en) * 2007-10-05 2009-04-30 Sumitomo Bakelite Co Ltd Manufacturing method of semiconductor device, and manufacturing method of printed circuit board for semiconductor device
WO2010073831A1 (en) * 2008-12-25 2010-07-01 インターナショナル・ビジネス・マシーンズ・コーポレーション Multilayer circuit board and method for manufacturing same
WO2022107389A1 (en) 2020-11-18 2022-05-27 株式会社フジクラ Wiring board
US11864316B2 (en) 2020-11-18 2024-01-02 Fujikura Ltd. Wiring substrate

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