JP2006211620A - Filter and duplexer - Google Patents

Filter and duplexer Download PDF

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JP2006211620A
JP2006211620A JP2005024639A JP2005024639A JP2006211620A JP 2006211620 A JP2006211620 A JP 2006211620A JP 2005024639 A JP2005024639 A JP 2005024639A JP 2005024639 A JP2005024639 A JP 2005024639A JP 2006211620 A JP2006211620 A JP 2006211620A
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reference potential
terminal
filter
gnd
duplexer
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Yoshiichi Kihara
芳一 木原
Masaki Takahashi
正樹 高橋
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TDK Corp
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TDK Corp
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<P>PROBLEM TO BE SOLVED: To reduce a thermal resistance difference between a signal terminal and a reference potential terminal while excellently keeping filter characteristics in a filter and a duplexer, and to improve the reliability of soldering at the time of mounting. <P>SOLUTION: The filter or the duplexer is provided with the signal terminal for external connection, the reference potential terminal and a common reference potential part electrically connected with the reference potential terminal, which are all formed of conductors, on one surface of a package, and a slit part for partially separating the common reference potential part and the reference potential terminal is provided between the common reference potential part and the reference potential terminal. The common reference potential part is formed over the almost entire one surface of the package, the slit part and a bridging part composed of the conductor are provided between the common reference potential part and the reference potential terminal, and the reference potential terminal is formed of solder resist. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、フィルタ及びデュプレクサに係り、特にこれらデバイスのパッケージ底面に設けられる外部接続端子の構造に関する。   The present invention relates to a filter and a duplexer, and more particularly to a structure of an external connection terminal provided on a bottom surface of a package of these devices.

電子機器の小型・高密度・高性能・低コスト化を実現するため、電子部品の実装に表面実装技術が広く用いられている。この技術は、プリント配線板表面の接続パッドに部品端子をはんだで固定するもので、例えば携帯電話機をはじめとする各種の通信機器等で使用されるフィルタやデュプレクサも近年、かかる技術を前提とした表面実装部品(SMD:Surface Mount Device)として製造されることが多い。   Surface mounting technology is widely used for mounting electronic components in order to realize small size, high density, high performance, and low cost of electronic devices. In this technology, component terminals are fixed to the connection pads on the surface of the printed wiring board with solder. For example, filters and duplexers used in various communication devices such as mobile phones have recently been based on this technology. It is often manufactured as a surface mount device (SMD).

図14及び図15はそれぞれ、このようなSMDとして構成された従来のデュプレクサの一例を示す底面図である。図14に示すように従来のデュプレクサは、実装すべきプリント配線板(実装基板)の接続パッドにはんだ接続される外部接続用端子がパッケージの底面に設けられる。これら外部接続用端子は、送信端子1、受信端子2及びアンテナ端子3からなる信号端子と、実装基板の基準電位端子に接続される基準電位端子4とからなる。   14 and 15 are each a bottom view showing an example of a conventional duplexer configured as such an SMD. As shown in FIG. 14, in the conventional duplexer, external connection terminals that are solder-connected to connection pads of a printed wiring board (mounting substrate) to be mounted are provided on the bottom surface of the package. These external connection terminals include a signal terminal including a transmission terminal 1, a reception terminal 2, and an antenna terminal 3, and a reference potential terminal 4 connected to a reference potential terminal of the mounting board.

また、図15に示す例では、信号端子部を除くパッケージ底面の略全面に導体層が設けられ、この導体層により各基準電位端子4と、これら基準電位端子4を互いに電気的に接続する共通基準電位部5とが形成されている。尚、各基準電位端子4は、はんだ付けされる領域を限定するために、基準電位端子を形成すべき各領域を抜いて(除いて)当該導体層の表面にソルダーレジスト(図示せず)をコーティングすることにより形成される場合がある。   In the example shown in FIG. 15, a conductor layer is provided on substantially the entire bottom surface of the package excluding the signal terminal portion, and each reference potential terminal 4 and these reference potential terminals 4 are electrically connected to each other by this conductor layer. A reference potential portion 5 is formed. In addition, in order to limit the area | region to which each reference potential terminal 4 is soldered, each area | region which should form a reference potential terminal is extracted (except), and the soldering resist (not shown) is provided on the surface of the said conductor layer. It may be formed by coating.

ところで、フィルタやデュプレクサ部品は、その電気的に基準となる電位を、実装すべきプリント配線板の接地電位と、できるだけ同一とすることが、設計された本来の電気特性(フィルタ特性)を得るために必要である。例えば、実装すべきプリント配線板の接地電位とフィルタの基準となる電位との間にインダクタンス成分が存在する場合、周波数の上昇に伴い両者間の電位差が拡大し、フィルタ本来の性能を発揮できない場合がある。特に近年の信号周波数の高域化に伴いその重要性は大きい。   By the way, in order to obtain the designed original electrical characteristics (filter characteristics), it is necessary to make the electrical reference potential of the filter and duplexer parts as identical as possible to the ground potential of the printed wiring board to be mounted. Is necessary. For example, when there is an inductance component between the ground potential of the printed wiring board to be mounted and the reference potential of the filter, the potential difference between the two increases as the frequency increases, and the original filter performance cannot be achieved. There is. In particular, with the recent increase in signal frequency, its importance is great.

このため、フィルタ部品の各基準電位端子同士を電気的に接続する共通の基準電位部をフィルタのパッケージ内に設けることが行われる。このようにすれば、フィルタ部品内部のインダクタンスやレジスタンスを並列効果により小さくすることが出来る。この場合、インダクタンスやレジスタンスを可能な限り最小にするよう、各基準電位端子間は、接続される。また、フィルタ部品が実装されるプリント配線板側の基準電位端子は、配線板の面積や形状等の制約から、実際には各端子の電位にばらつきが生じてしまうことがあるが、この実装先の基準電位のばらつきの影響を排除ないし軽減するためにも、フィルタ部品内に共通の基準電位部を設けることは有効である。   For this reason, a common reference potential portion that electrically connects the reference potential terminals of the filter components is provided in the filter package. In this way, the inductance and resistance inside the filter component can be reduced by the parallel effect. In this case, the reference potential terminals are connected so as to minimize the inductance and resistance as much as possible. Also, the reference potential terminal on the printed wiring board side where the filter components are mounted may actually vary in the potential of each terminal due to restrictions on the area and shape of the wiring board. In order to eliminate or reduce the influence of variations in the reference potential, it is effective to provide a common reference potential portion in the filter component.

図16から図22はこれを説明する模式図である。まず、図16に示すデバイスは、パッケージ基板6の上面にフィルタ素子7を備え、この素子7の基準電位端子と、パッケージ基板6の底面に設けた外部接続用の基準電位端子4とをビアホール8を通じて電気的に接続しており、パッケージ内には共通の基準電位部を備えていない。尚、外部接続用の基準端子4は、はんだ9を介して実装基板10の基準電位端子11に接続される。   16 to 22 are schematic diagrams for explaining this. First, the device shown in FIG. 16 includes a filter element 7 on the upper surface of the package substrate 6. A reference potential terminal of the element 7 and a reference potential terminal 4 for external connection provided on the bottom surface of the package substrate 6 are connected to the via hole 8. And the package does not have a common reference potential portion. The reference terminal 4 for external connection is connected to the reference potential terminal 11 of the mounting substrate 10 via the solder 9.

このようなデバイス構造では、図17に示すように、フィルタ素子7と実装基板の基準電位面との間に前記ビアホール8に起因する寄生インダクタンス成分L0が生じる。他の何らかの接続方法をもってしても、インダクタンス成分は生じる。そのため、フィルタ素子7の基準電位面は、パッケージの基準電位面に対して、高インピーダンスな状態となる。特に、高周波になるに従い、そのインピーダンスは大きくなる。信号電力を接地により消費させる原理のフィルタの場合、フィルタの減衰特性は、図21の構造と比較し、構造的に劣化してしまう。また、上述したように実装されるプリント配線板側の基準電位端子に電位の偏差があった場合は、図18に示すようフィルタ素子7の基準電位端子に電位差が生じることとなる。この場合、フィルタ素子7の動作が、設計条件とは異なる構造となる。そのため、フィルタの電気特性(特に減衰特性)が、図21の構造と比較し、実装基板側の影響(実装基板の寄生インダクタンス成分L1)を受け易くなってしまうこととなる。 In such a device structure, as shown in FIG. 17, a parasitic inductance component L 0 caused by the via hole 8 is generated between the filter element 7 and the reference potential surface of the mounting substrate. Even with some other connection method, an inductance component is generated. Therefore, the reference potential surface of the filter element 7 is in a high impedance state with respect to the reference potential surface of the package. In particular, as the frequency increases, the impedance increases. In the case of a filter based on the principle that signal power is consumed by grounding, the attenuation characteristic of the filter is structurally degraded as compared with the structure of FIG. Further, when there is a potential deviation in the reference potential terminal on the printed wiring board side mounted as described above, a potential difference is generated in the reference potential terminal of the filter element 7 as shown in FIG. In this case, the operation of the filter element 7 has a structure different from the design condition. For this reason, the electrical characteristics (particularly the attenuation characteristics) of the filter are more susceptible to the influence on the mounting board side (parasitic inductance component L 1 of the mounting board) than the structure of FIG.

図20に示すフィルタは、フィルタ部品内の、パッケージ基板6の内部に共通の基準電位部12を備えたものである。このフィルタ部品では、フィルタ素子7の基準電位端子4が共通の基準電位部12によって互いに電気的に接続されることとなるから、実装基板側の基準電位偏差の影響を受け難くなる。しかしながら、共通基準電位部12と外部接続端子4との間に距離(例えばビアホール8a)が存在し、図20に示すようにこれによる寄生インダクタンス成分L2は生じてしまう。 The filter shown in FIG. 20 includes a common reference potential portion 12 inside the package substrate 6 in the filter component. In this filter component, the reference potential terminal 4 of the filter element 7 is electrically connected to each other by the common reference potential portion 12, and thus is less susceptible to the influence of the reference potential deviation on the mounting substrate side. However, the distance (e.g., via holes 8a) is present between the common reference potential section 12 and the external connection terminal 4, the parasitic inductance component L 2 by which as shown in FIG. 20 occurs.

さらに図21に示すフィルタは、前記図15に示した例のようにフィルタ部品(パッケージ基板6)の底面に共通の基準電位部5を備えたものである。このデバイス構造によれば、図22に示すようにフィルタ素子7の基準電位端子4が共通の基準電位部5によって互いに電気的に接続され、かつこの共通基準電位部5が実装基板10に最も近い位置に形成されているから、実装基板側の基準電位偏差の影響を受け難く、かつデバイス内の寄生インダクタンス成分も小さい点で有利である。また、共通基準電位部5を、前記図15に示すようにフィルタ部品底面の略全面に亘って形成すれば、基準電位端子4同士を接続する共通基準電位部5の寄生インダクタンス成分L3を最も小さく抑えることが出来る。 Further, the filter shown in FIG. 21 is provided with a common reference potential portion 5 on the bottom surface of the filter component (package substrate 6) as in the example shown in FIG. According to this device structure, as shown in FIG. 22, the reference potential terminals 4 of the filter elements 7 are electrically connected to each other by the common reference potential portion 5, and the common reference potential portion 5 is closest to the mounting substrate 10. Since it is formed at the position, it is advantageous in that it is hardly affected by the reference potential deviation on the mounting substrate side and the parasitic inductance component in the device is small. Further, if the common reference potential portion 5 is formed over substantially the entire bottom surface of the filter component as shown in FIG. 15, the parasitic inductance component L 3 of the common reference potential portion 5 that connects the reference potential terminals 4 to each other is maximized. It can be kept small.

一方、上記図15及び図21に示したような端子構造は、フィルタの電気特性の観点からは良好な構造であるが、信号端子1〜3と基準電位端子4とで熱抵抗の差が大きく、はんだ実装時における、実装基板とのはんだ接合の信頼性の点で改良の余地がある。   On the other hand, the terminal structures as shown in FIGS. 15 and 21 are good structures from the viewpoint of the electrical characteristics of the filter, but there is a large difference in thermal resistance between the signal terminals 1 to 3 and the reference potential terminal 4. There is room for improvement in terms of reliability of solder joints with the mounting board during solder mounting.

具体的に述べれば、上記図15の構造では、基準電位端子4は底面の略全面を覆う大きな面積を有する導体部(共通基準電位部5)と一体となって相互に接続されているため、熱抵抗が小さいのに対し、信号端子1〜3は当該導体部5から分離されて小さく孤立しているため、熱抵抗が大きい。したがって、例えばリフロー炉で加熱された場合に、各端子1〜4が均一の温度とならず、信号端子1〜3は基準電位端子4に較べて昇温し難く、接合不良を生じやすい。   More specifically, in the structure of FIG. 15, the reference potential terminal 4 is integrally connected to a conductor portion (common reference potential portion 5) having a large area covering substantially the entire bottom surface. While the thermal resistance is small, the signal terminals 1 to 3 are separated from the conductor portion 5 and are small and isolated, and therefore the thermal resistance is large. Therefore, for example, when heated in a reflow furnace, each of the terminals 1 to 4 does not have a uniform temperature, and the signal terminals 1 to 3 are less likely to be heated than the reference potential terminal 4 and are likely to have poor bonding.

特に、フィルタの場合、信号端子1〜3の数に較べ基準電位端子4の数が通常多く、このため信号端子1〜3と基準電位端子4との間の熱抵抗差はより顕著となる傾向にある。   In particular, in the case of a filter, the number of reference potential terminals 4 is usually larger than the number of signal terminals 1 to 3, and therefore the thermal resistance difference between the signal terminals 1 to 3 and the reference potential terminal 4 tends to become more prominent. It is in.

したがって、本発明の目的は、フィルタ及びデュプレクサにおいて電気的特性(フィルタ特性)を良好に保持しつつ、信号端子と基準電位端子間の熱抵抗差を低減して実装時のはんだ付けの信頼性を向上させる点にある。   Therefore, an object of the present invention is to reduce the thermal resistance difference between the signal terminal and the reference potential terminal while maintaining good electrical characteristics (filter characteristics) in the filter and duplexer, and to improve the reliability of soldering during mounting. The point is to improve.

前記目的を達成して課題を解決するため、本発明に係るフィルタは、パッケージの一方の面に、いずれも導体で形成した、外部接続用の信号端子と、外部接続用の基準電位端子と、当該外部接続用の基準電位端子と電気的に接続された共通基準電位部とを備えたフィルタであって、前記共通基準電位部と前記基準電位端子との間に、当該共通基準電位部と当該基準電位端子とを部分的に分離するスリット部を設けた。   In order to achieve the above object and solve the problem, the filter according to the present invention includes a signal terminal for external connection, a reference potential terminal for external connection, both formed of a conductor on one surface of the package, A filter including a common reference potential portion electrically connected to the reference potential terminal for external connection, and the common reference potential portion and the reference potential terminal between the common reference potential portion and the reference potential terminal A slit portion for partially separating the reference potential terminal was provided.

かかる本発明のフィルタ構造によれば、共通基準電位部と基準電位端子との間に設けたスリット部により、良熱導体で形成された基準電位端子が共通基準電位部から部分的に分断されるから、実装されるプリント基板の基準電位端子からの熱抵抗を大きくし、パッケージ表面で他の基準電位端子から電気的に(=熱的に)分離して設けられる信号端子の熱抵抗値に近づけることが出来る。したがって、基準電位端子と信号端子との熱抵抗差が低減され、実装時の各端子の温度をより均一化にし、はんだ接合の信頼性を向上させることが可能となる。   According to the filter structure of the present invention, the reference potential terminal formed of a good heat conductor is partially separated from the common reference potential portion by the slit portion provided between the common reference potential portion and the reference potential terminal. Therefore, the thermal resistance from the reference potential terminal of the printed circuit board to be mounted is increased, and the thermal resistance value of the signal terminal provided on the package surface is electrically (= thermally) separated from the other reference potential terminals. I can do it. Therefore, the difference in thermal resistance between the reference potential terminal and the signal terminal is reduced, the temperature of each terminal during mounting can be made more uniform, and the reliability of solder joint can be improved.

尚、上記フィルタには、例えば弾性表面波(SAW)フィルタやLCフィルタ等の接地電極を設けた各種のフィルタが含まれる。下記デュプレクサについても同様である。   The filter includes various filters provided with a ground electrode such as a surface acoustic wave (SAW) filter or an LC filter. The same applies to the following duplexer.

また、本発明に係るデュプレクサは、パッケージの一方の面に、いずれも導体で形成した、外部接続用の信号端子と、外部接続用の基準電位端子と、当該外部接続用の基準電位端子と電気的に接続された共通基準電位部とを備えたデュプレクサであって、前記共通基準電位部と前記基準電位端子との間に、当該共通基準電位部と当該基準電位端子とを部分的に分離するスリット部を設けたものである。   In addition, the duplexer according to the present invention includes a signal terminal for external connection, a reference potential terminal for external connection, a reference potential terminal for external connection, and an electrical connection, which are all formed of a conductor on one surface of the package. A duplexer having a common reference potential portion connected to each other, wherein the common reference potential portion and the reference potential terminal are partially separated between the common reference potential portion and the reference potential terminal A slit portion is provided.

このようなデュプレクサ構造によっても、上記フィルタと同様に実装時のはんだ接合の信頼性を向上させることが出来る。   Even with such a duplexer structure, it is possible to improve the reliability of solder joints at the time of mounting as in the case of the filter.

また、上記フィルタ又はデュプレクサでは、前記共通基準電位部は、前記信号端子の形成部を除いた前記パッケージの一方の面の略全面に亘って形成されて前記基準電位端子と電気的に接続されており、前記共通基準電位部と前記基準電位端子との間には、前記スリット部と、前記共通基準電位部と前記基準電位端子と電気的に接続する導体からなる橋絡部とが形成され、前記基準電位端子は、前記パッケージの一方の面に配されたソルダーレジストにより画成されるようにしても良い。   In the filter or duplexer, the common reference potential portion is formed over substantially the entire surface of one side of the package excluding the signal terminal forming portion and is electrically connected to the reference potential terminal. In addition, between the common reference potential portion and the reference potential terminal, the slit portion and a bridge portion made of a conductor that is electrically connected to the common reference potential portion and the reference potential terminal are formed, The reference potential terminal may be defined by a solder resist disposed on one surface of the package.

このようなフィルタ又はデュプレクサによれば、上記橋絡部により各基準電位端子が電気的に接続されて実装基板の基準電位偏差の影響を受け難くすることが出来るとともに、共通基準電位部がパッケージの一方の面の略全域に亘って形成されることによりフィルタ部品内の寄生インダクタンス成分を小さく抑えることが可能となる。また、スリット部の形成によって基準電位端子と信号端子との熱抵抗差を低減し、実装時のはんだ接合の信頼性を向上させることも出来る。   According to such a filter or duplexer, each reference potential terminal is electrically connected by the bridge portion so that it is difficult to be influenced by the reference potential deviation of the mounting substrate, and the common reference potential portion is not connected to the package. By forming over substantially the entire area of one surface, it is possible to keep the parasitic inductance component in the filter component small. Further, the formation of the slit portion can reduce the difference in thermal resistance between the reference potential terminal and the signal terminal, and can improve the reliability of solder joint during mounting.

尚、本発明においては、上記パッケージの構成材料は限定されず、例えば樹脂あるいは当該樹脂に無機材料を混合した複合材料、セラミックス等であって良い。ただし、樹脂材料はセラミック材料等に較べ熱抵抗が大きいことから、樹脂パッケージを有するフィルタ部品に適用して本発明は特にメリットが大きい。   In the present invention, the constituent material of the package is not limited, and may be, for example, a resin, a composite material in which an inorganic material is mixed with the resin, ceramics, or the like. However, since the heat resistance of the resin material is larger than that of the ceramic material or the like, the present invention is particularly advantageous when applied to a filter component having a resin package.

本発明によれば、フィルタ及びデュプレクサの電気的特性(フィルタ特性)を良好に保持しつつ、信号端子と基準電位端子間の熱抵抗差を低減して実装時のはんだ付けの信頼性を向上させることが出来る。   According to the present invention, while maintaining the electrical characteristics (filter characteristics) of the filter and the duplexer satisfactorily, the thermal resistance difference between the signal terminal and the reference potential terminal is reduced to improve the soldering reliability during mounting. I can do it.

本発明の他の目的、特徴及び利点は、図面に基づく以下の本発明の実施の形態の説明により明らかにする。尚、本発明は下記実施形態に限定されるものではなく、特許請求の範囲に記載の範囲内で種々の変更を行うことができることは当業者に明らかである。また各図中、同一の符号は、同一又は相当部分を示す。   Other objects, features, and advantages of the present invention will become apparent from the following description of embodiments of the present invention based on the drawings. It should be noted that the present invention is not limited to the following embodiments, and it will be apparent to those skilled in the art that various modifications can be made within the scope of the claims. Moreover, in each figure, the same code | symbol shows the same or an equivalent part.

図1は、本発明の一実施形態に係るデュプレクサを示すものである。同図に示すようにこのデュプレクサ21は、基板22の上面に実装された送信用フィルタ素子24と受信用フィルタ素子25とを備え、これらのフィルタ素子24,25を蓋体23により封止したものである。基板22の底面には、デュプレクサ内の各基準電位端子(以下、GND端子という)を互いに電気的に接続する共通GND部(共通基準電位部)35を設け、さらにその表面(下面)には実装時のはんだによる短絡を防ぎパッケージ底面のGND端子4を画成するソルダーレジスト(はんだマスク)40を配してある。   FIG. 1 shows a duplexer according to an embodiment of the present invention. As shown in the figure, the duplexer 21 includes a transmission filter element 24 and a reception filter element 25 mounted on the upper surface of a substrate 22, and the filter elements 24 and 25 are sealed with a lid 23. It is. A common GND portion (common reference potential portion) 35 that electrically connects each reference potential terminal (hereinafter referred to as GND terminal) in the duplexer is provided on the bottom surface of the substrate 22, and further mounted on the surface (lower surface). A solder resist (solder mask) 40 is disposed to prevent a short circuit due to soldering and to define the GND terminal 4 on the bottom surface of the package.

図2及び図3は上記デュプレクサの底面を示すもので、図2はソルダーレジスト40を取り除いた状態を、図3はソルダーレジスト40を配した状態をそれぞれ示している。また、図4は底面端子部(後に述べるスリット)の拡大図である。   2 and 3 show the bottom surface of the duplexer. FIG. 2 shows a state where the solder resist 40 is removed, and FIG. 3 shows a state where the solder resist 40 is arranged. FIG. 4 is an enlarged view of a bottom terminal portion (a slit described later).

図2に示すように基板22の底面には、当該デュプレクサ21を実装すべき基板(実装基板)の接続パッドにはんだ接続される複数の外部接続用端子1〜4を設ける。これらの外部接続端子1〜4は、送信端子1、受信端子2及びアンテナ端子3からなる信号端子と、GND端子4とからなり、GND端子4は実装基板のGND端子(接続パッド)に接続され、信号端子1〜3は実装基板の対応する接続パッドにそれぞれ接続される。また、フィルタ素子24,25や当該デュプレクサ21内に設けられる他の回路要素と、各外部接続端子1〜4との電気的接続は、ビアホールやキャスタレーション(サイドビア)26等を介して行う。   As shown in FIG. 2, a plurality of external connection terminals 1 to 4 that are solder-connected to connection pads of a substrate (mounting substrate) on which the duplexer 21 is to be mounted are provided on the bottom surface of the substrate 22. These external connection terminals 1 to 4 include a signal terminal including a transmission terminal 1, a reception terminal 2, and an antenna terminal 3, and a GND terminal 4. The GND terminal 4 is connected to a GND terminal (connection pad) of the mounting board. The signal terminals 1 to 3 are respectively connected to corresponding connection pads on the mounting board. The filter elements 24 and 25 and other circuit elements provided in the duplexer 21 are electrically connected to the external connection terminals 1 to 4 through via holes, castellations (side vias) 26, and the like.

また、上記信号端子1〜3の配置部を除くベース基板底面の略全面には導体層を設け、この導体層により、上記各GND端子4と、これらGND端子4を互いに電気的に接続する共通GND部35とを形成する。   In addition, a conductor layer is provided on substantially the entire bottom surface of the base substrate excluding the arrangement portion of the signal terminals 1 to 3, and the GND terminals 4 and the GND terminals 4 are electrically connected to each other by the conductor layer. A GND portion 35 is formed.

GND端子4は、共通GND部35と同一の導体箔(上記導体層)より一体に形成され、GND端子4の周縁部(GND端子4と共通GND部35との境界部)は、後に述べるようにソルダーレジスト40により区切られ画成されるが、各GND端子4の周縁部には、当該GND端子4と共通GND部35との間を部分的に分断するスリット36を設ける。GND端子周縁部のうちスリット36を形成しない部分は、上記導体層により接続されたままの状態とし、これによりGND端子4と共通GND部35とを電気的に接続する橋絡部37を形成する。   The GND terminal 4 is integrally formed from the same conductor foil (the above-mentioned conductor layer) as the common GND part 35, and the peripheral part of the GND terminal 4 (the boundary part between the GND terminal 4 and the common GND part 35) is described later. However, a slit 36 that partially divides between the GND terminal 4 and the common GND portion 35 is provided at the peripheral portion of each GND terminal 4. Of the peripheral portion of the GND terminal, the portion where the slit 36 is not formed is left connected by the conductor layer, thereby forming a bridging portion 37 that electrically connects the GND terminal 4 and the common GND portion 35. .

スリット36及び橋絡部37の寸法は、特にこれらの値に限定されるものではないが、スリット36の幅W1(図4参照)を例えば100〜200μm、橋絡部37の幅W2を例えば50μm程度とすることが出来る。   The dimensions of the slit 36 and the bridging portion 37 are not particularly limited to these values, but the width W1 (see FIG. 4) of the slit 36 is, for example, 100 to 200 μm, and the width W2 of the bridging portion 37 is, for example, 50 μm. It can be about.

ソルダーレジスト40は、図3に示すように、信号端子1〜3の形成部と、GND端子4を形成すべき各領域とを除いた基板底面の略全域に亘り上記導体層の表面にコーティングしてあり、これにより上記導体層を覆ってベース基板底面に各GND端子4が形成され、また実装時に外部接続端子1〜4以外の部分にはんだが付着することが防止される。GND端子の形状は、ソルダーレジストにより任意に形成することが出来る。   As shown in FIG. 3, the solder resist 40 is coated on the surface of the conductor layer over almost the entire area of the bottom surface of the substrate excluding the formation portions of the signal terminals 1 to 3 and the regions where the GND terminals 4 are to be formed. Thus, each GND terminal 4 is formed on the bottom surface of the base substrate so as to cover the conductor layer, and solder is prevented from adhering to portions other than the external connection terminals 1 to 4 at the time of mounting. The shape of the GND terminal can be arbitrarily formed by a solder resist.

本実施形態では、上記のようにGND端子4の周縁部にスリット36を設けてあるから、共通GND部35との接続部分が制限されることでGND端子4の熱抵抗を増大させることができ、ベース基板底面において他の導体から分離して設けられた信号端子1〜3との熱抵抗差を小さくすることが出来る。一方、上記スリット36を設けても各GND端子4は橋絡部37によって共通GND部35及び他のGND端子4と互いに電気的に接続されているから、実装基板側の基準電位偏差の影響を受け難い。さらに、共通GND部35は、デバイス底面の略全面に亘り形成されかつデバイス底面という実装基板に最も近い位置に設けられているから、当該デバイス内の寄生インダクタンス成分を小さく抑えることが出来る。   In the present embodiment, since the slit 36 is provided in the peripheral portion of the GND terminal 4 as described above, the thermal resistance of the GND terminal 4 can be increased by restricting the connection portion with the common GND portion 35. The difference in thermal resistance from the signal terminals 1 to 3 provided separately from other conductors on the bottom surface of the base substrate can be reduced. On the other hand, even if the slit 36 is provided, each GND terminal 4 is electrically connected to the common GND part 35 and the other GND terminals 4 by the bridging part 37, so that the influence of the reference potential deviation on the mounting board side is affected. It is hard to receive. Furthermore, since the common GND portion 35 is formed over substantially the entire bottom surface of the device and is provided at a position closest to the mounting substrate, that is, the bottom surface of the device, the parasitic inductance component in the device can be kept small.

〔信号端子及びGND端子の熱抵抗に関する検討〕
(1)スリット幅と信号端子‐GND端子間の熱抵抗差の関係
図5から図9を参照しつつ、信号端子‐GND端子間の熱抵抗差について検討する。前記図15に示すような共通GND部を底面に備えた端子構造を考えると、GND端子はデバイス底面の導体と一体に形成されて当該導体の熱抵抗は非常に小さいのに対し、信号端子は周囲の導体から分離され、基板絶縁層(例えば樹脂)の熱抵抗は導体に較べ格段に大きいことから、実装される基板の基準電位端子を基準とした、信号端子‐GND端子間の熱抵抗差は、信号端子周囲の間隙部、すなわち基板絶縁層の熱抵抗に起因するものと考えることが出来る。換言すれば、信号端子と同一形状のGND端子を形成すれば、熱抵抗差を小さくし、より均一にすることが出来る。
[Study on thermal resistance of signal terminal and GND terminal]
(1) Relationship between slit width and difference in thermal resistance between signal terminal and GND terminal The difference in thermal resistance between the signal terminal and the GND terminal will be examined with reference to FIGS. Considering a terminal structure having a common GND portion as shown in FIG. 15 on the bottom surface, the GND terminal is formed integrally with the conductor on the bottom surface of the device, and the thermal resistance of the conductor is very small, whereas the signal terminal is The thermal resistance difference between the signal terminal and the GND terminal with respect to the reference potential terminal of the mounted board is separated from the surrounding conductors and the thermal resistance of the board insulating layer (for example, resin) is much higher than that of the conductor. Can be considered to be caused by the gap around the signal terminal, that is, the thermal resistance of the substrate insulating layer. In other words, if a GND terminal having the same shape as the signal terminal is formed, the difference in thermal resistance can be reduced and made more uniform.

そこで、図5に示すように、信号端子51と周囲導体(共通GND部)5との間の間隙52の幅(スリット幅)によって熱抵抗値がどのようになるか、基板材料として樹脂、LTCC(Low Temperature Co-fired Ceramics/低温同時焼成セラミックス)及びHTCC(High Temperature Co-fired Ceramics/高温同時焼成セラミックス)を使用する場合について各々計算を行った。尚、端子51の縦横寸法xは共に1mm、スリット幅W1は0.2mmとする。   Therefore, as shown in FIG. 5, the thermal resistance value depends on the width (slit width) of the gap 52 between the signal terminal 51 and the surrounding conductor (common GND portion) 5, and the substrate material is resin, LTCC. The calculation was performed for each of the cases using (Low Temperature Co-fired Ceramics / Low Temperature Co-fired Ceramics) and HTCC (High Temperature Co-fired Ceramics / High Temperature Co-fired Ceramics). The vertical and horizontal dimensions x of the terminals 51 are both 1 mm, and the slit width W1 is 0.2 mm.

図6は、樹脂基板の場合の算出結果を示すものである。樹脂材料として一般的なエポキシ樹脂を用いることを想定し、熱抵抗率を3.33[m・K/W]とすると、スリット幅W1が10から500μmの各値の場合、熱抵抗値は、同図の表に示すようになる。尚、この表において熱通過断面積:3.00×10-6[m2]は、間隙52部の樹脂基板の厚さを1mmとして計算したものである(以下同様)。また図7はLTCC基板の場合であり、熱抵抗率を0.33[m・K/W]としている。さらに図8はHTCC基板の場合であり、熱抵抗率を0.03[m・K/W]とした。またこれらスリット幅と熱抵抗差との関係を図9に線図により示した。 FIG. 6 shows a calculation result in the case of a resin substrate. Assuming that a general epoxy resin is used as the resin material and the thermal resistivity is 3.33 [m · K / W], when the slit width W1 is 10 to 500 μm, the thermal resistance value is As shown in the table of FIG. In this table, the heat passage cross-sectional area: 3.00 × 10 −6 [m 2 ] is calculated assuming that the thickness of the resin substrate at the gap 52 is 1 mm (the same applies hereinafter). FIG. 7 shows the case of the LTCC substrate, in which the thermal resistivity is 0.33 [m · K / W]. Further, FIG. 8 shows the case of the HTCC substrate, and the thermal resistivity is 0.03 [m · K / W]. Further, the relationship between the slit width and the thermal resistance difference is shown by a diagram in FIG.

これらの図から明らかなように、例えば、はんだリフロー時の端子の温度(熱抵抗)のばらつきの許容差を±10℃(10〔K/W〕)とすると、樹脂系材料の場合は、スリット幅を10μm未満にし、LTCC系材料の場合でもスリット幅を100μm未満にすることが必要であることがわかる。HTCC系材料の場合には、スリット幅が1mm未満であれば、信号端子‐GND端子間の温度差は、10℃以内にほぼ保たれる。   As is apparent from these figures, for example, if the tolerance of variation in terminal temperature (thermal resistance) during solder reflow is ± 10 ° C. (10 [K / W]) It can be seen that the width should be less than 10 μm and the slit width should be less than 100 μm even in the case of LTCC materials. In the case of an HTCC-based material, if the slit width is less than 1 mm, the temperature difference between the signal terminal and the GND terminal is almost kept within 10 ° C.

これら検討結果から、熱抵抗の大きい樹脂系基板については、信号端子と共通GND部との間隔幅(上記スリット幅)が10μm以上、LTCC基板については100μm以上となる場合には、GND端子の周囲にスリットを設けてGND端子の熱抵抗を増大させ、信号端子との温度差(熱抵抗差)を小さくすることが必要である。   From these examination results, when the distance width (the slit width) between the signal terminal and the common GND part is 10 μm or more for the resin-based substrate having a large thermal resistance and 100 μm or more for the LTCC substrate, the periphery of the GND terminal It is necessary to reduce the temperature difference (thermal resistance difference) from the signal terminal by providing a slit on the GND terminal to increase the thermal resistance of the GND terminal.

一方、信号端子と、当該信号端子と同一面にあるGNDパターン(GND端子や共通GND部)との間隔は、一般に電気的特性と基板の製造プロセス上の制約から決定される。   On the other hand, the distance between a signal terminal and a GND pattern (GND terminal or common GND portion) on the same plane as the signal terminal is generally determined by electrical characteristics and restrictions on the manufacturing process of the substrate.

すなわち電気的には、フィルタやデュプレクサの場合、信号端子とGNDパターンとの距離に起因して発生する寄生容量分を小さく抑えるよう両者(信号端子とGNDパターン)の間隔は出来るだけ大きくすることが望ましい。尚、基板材料として通常の比誘電率(3〜10程度)を有する材料では、当該パターン間隔は50〜300μm程度とするのが一般的である。   In other words, in the case of a filter or duplexer, the distance between the two (the signal terminal and the GND pattern) can be made as large as possible so as to suppress the parasitic capacitance generated due to the distance between the signal terminal and the GND pattern. desirable. In the case of a material having a normal relative dielectric constant (about 3 to 10) as a substrate material, the pattern interval is generally set to about 50 to 300 μm.

また製造プロセス面からは、樹脂系・セラミック系材料ともにパターン幅/スリット幅で30/30μm程度が現時点での細線化の限界である。したがって、端子周囲の間隙幅を10μm未満として端子間の熱抵抗差を許容値内に収めることは、製造プロセス面から困難である。   In terms of the manufacturing process, the pattern width / slit width of about 30/30 μm is the limit of thinning at the present time for both resin-based and ceramic-based materials. Therefore, it is difficult from the viewpoint of the manufacturing process to make the gap width around the terminals less than 10 μm and to keep the thermal resistance difference between the terminals within an allowable value.

本発明は、かかる状況下で信号端子とGNDパターンとの間隔を確保して電気特性を劣化させることなく、なおかつ信号端子‐GND端子間の熱抵抗差を低減する手段を提供することが出来るものである。   The present invention can provide means for reducing the difference in thermal resistance between the signal terminal and the GND terminal without deteriorating the electrical characteristics by securing the distance between the signal terminal and the GND pattern under such circumstances. It is.

(2)端子構造の違いによる信号端子‐GND端子間の熱抵抗差
図10は端子の周囲構造を模式的に示す図であり、同図の(a)は信号端子51の周囲にスリット52を形成した場合、(b)はGND端子4の周囲にスリットを全く形成しない場合、(c)はGND端子4の周囲にスリット36を形成した場合、(d)は本発明に基づいてGND端子4の周囲にスリット36と橋絡部37を形成した場合をそれぞれ示している。尚、各端子4,51の縦横寸法xは共に1mm、スリット幅W1は0.2mmとする。
(2) Difference in thermal resistance between signal terminal and GND terminal due to difference in terminal structure FIG. 10 is a diagram schematically showing the peripheral structure of the terminal. FIG. 10A shows a slit 52 around the signal terminal 51. When formed, (b) does not form any slit around the GND terminal 4, (c) forms a slit 36 around the GND terminal 4, and (d) shows the GND terminal 4 according to the present invention. The case where the slit 36 and the bridge part 37 were formed in the circumference | surroundings is shown, respectively. The vertical and horizontal dimensions x of the terminals 4 and 51 are both 1 mm, and the slit width W1 is 0.2 mm.

図11は、上記図10の(a)〜(d)の各端子構造における熱抵抗の算出結果を示す表である。この表に示すように、信号端子の周囲にスリットを形成した場合(a)の熱抵抗は222[K/W]、GND端子の周囲にスリットを形成しない場合(b)の熱抵抗は0.169[K/W]、GND端子の周囲にスリットを形成した場合(c)の熱抵抗は222[K/W]、GND端子の周囲にスリットと橋絡部を形成した場合(d)の熱抵抗は67.26[K/W]となる。   FIG. 11 is a table showing calculation results of thermal resistance in each of the terminal structures shown in FIGS. As shown in this table, when the slit is formed around the signal terminal (a), the thermal resistance is 222 [K / W], and when the slit is not formed around the GND terminal (b), the thermal resistance is 0. 169 [K / W], when the slit is formed around the GND terminal (c), the thermal resistance is 222 [K / W], when the slit and the bridge are formed around the GND terminal (d) The resistance is 67.26 [K / W].

したがって、上記図10(a)及び(b)のように信号端子の周囲にスリット52を有し且つGND端子の周囲にスリットを有しない場合には、信号‐GND両端子間の熱抵抗差は、約222(K/W)となる。これに対し、上記図10(d)のようにGND端子の周辺の3方向にスリット36を設け、且つ各スリット部分に橋絡部37を設けた場合には、信号‐GND両端子間の熱抵抗差は、154.74[K/W]に低減することが出来る。   Therefore, as shown in FIGS. 10A and 10B, when the slit 52 is provided around the signal terminal and the slit is not provided around the GND terminal, the difference in thermal resistance between the signal and GND terminals is , Approximately 222 (K / W). On the other hand, when the slits 36 are provided in the three directions around the GND terminal as shown in FIG. 10 (d) and the bridging portion 37 is provided in each slit portion, the heat between the signal-GND terminals is provided. The resistance difference can be reduced to 154.74 [K / W].

(3)GND端子周囲のスリット幅と信号端子‐GND端子間の熱抵抗差との関係
図12及び図13は、GND端子の周囲に幅10〜500μmのスリットを設けたときの信号端子‐GND端子間の熱抵抗差を示す表と線図である。これらの図表において、熱抵抗差(表の右端)は、信号端子周囲のスリット幅が200μmで、GND端子の周囲にはスリットがない場合の信号端子‐GND端子間の熱抵抗差:222[K/W]を基準値とし、この基準値との差をGND端子周囲にスリットのみを形成した場合と、スリットと橋絡部を設けた場合とについて算出した結果を示している。これらの図に示すように、GND端子の周囲にスリットを設けた場合には、いずれの場合も熱抵抗差は小さくなる。
(3) Relationship between slit width around GND terminal and difference in thermal resistance between signal terminal and GND terminal FIGS. 12 and 13 show signal terminal-GND when a slit having a width of 10 to 500 μm is provided around the GND terminal. It is the table | surface and diagram which show the thermal resistance difference between terminals. In these charts, the thermal resistance difference (right end of the table) is the difference in thermal resistance between the signal terminal and the GND terminal when the slit width around the signal terminal is 200 μm and there is no slit around the GND terminal: 222 [K / W] is a reference value, and the difference from this reference value is calculated for the case where only the slit is formed around the GND terminal and the case where the slit and the bridge are provided. As shown in these figures, when a slit is provided around the GND terminal, the thermal resistance difference is reduced in any case.

(4)(スリット+橋絡部)構造による熱抵抗差の低減効果
GND端子の周囲にスリットを設けると寄生インダクタンスが生じるが、これを打ち消すには、スリットを跨いでGND端子と共通GND部とを電気的に接続する橋絡部を設けることが有効である。
(4) Reduction effect of thermal resistance difference by (slit + bridging portion) structure When a slit is provided around the GND terminal, a parasitic inductance is generated. It is effective to provide a bridge portion that electrically connects the two.

このときの橋絡部のインダクタンスを計算する。橋絡部は、厚さ35μmの銅箔で形成することを想定し、幅が50μm、長さはスリット幅と同一の200μmであるとすると、橋絡部1つ当りのインダクタンスは、0.156nHである。フィルタの減衰量にとって、このインダクタンスが許容できない場合には、熱抵抗差に配慮しながら、橋絡部の幅を大きくするか、数を増やせばインダクタンスを軽減することが出来る。このように本発明では、橋絡部の寸法又は配設個数を調整することによりデバイスの寄生インダクタンスを調整することが可能である。   The inductance of the bridge portion at this time is calculated. Assuming that the bridge portion is formed of a copper foil having a thickness of 35 μm, and assuming that the width is 50 μm and the length is 200 μm, which is the same as the slit width, the inductance per bridge portion is 0.156 nH. It is. If this inductance is unacceptable for the attenuation of the filter, it is possible to reduce the inductance by increasing the width of the bridge portion or increasing the number while considering the thermal resistance difference. As described above, in the present invention, it is possible to adjust the parasitic inductance of the device by adjusting the dimensions or the number of the bridge portions.

以上のようにGND端子の周囲にスリットを形成し且つ橋絡部を設ける本発明の構造によれば、実装基板のGND面と最近傍位置でフィルタ部品のGNDを共通にすることができ、且つ信号‐GND端子間の熱抵抗差にも配慮したデバイスを構成することが出来る。   As described above, according to the structure of the present invention in which the slit is formed around the GND terminal and the bridging portion is provided, the GND of the filter component can be made common at the position closest to the GND surface of the mounting substrate, and It is possible to configure a device that takes into account the thermal resistance difference between the signal and GND terminals.

本発明の一実施形態に係るデュプレクサを示す側面断面図である。It is side surface sectional drawing which shows the duplexer which concerns on one Embodiment of this invention. 前記実施形態に係るデュプレクサ(ソルダーレジストを除去した状態)を示す底面図である。It is a bottom view which shows the duplexer (state which removed the soldering resist) which concerns on the said embodiment. 前記実施形態に係るデュプレクサ(ソルダーレジストを配した状態)を示す底面図である。It is a bottom view which shows the duplexer (state which has arrange | positioned the soldering resist) which concerns on the said embodiment. 前記実施形態に係るデュプレクサの底面端子部(スリット及び橋絡部)を拡大して示す図である。It is a figure which expands and shows the bottom face terminal part (a slit and a bridge part) of the duplexer which concerns on the said embodiment. 信号端子の形成部を示す模式図である。It is a schematic diagram which shows the formation part of a signal terminal. ベース基板材料として樹脂材を使用した場合におけるスリット幅と熱抵抗値との関係を示す表である。It is a table | surface which shows the relationship between the slit width at the time of using a resin material as a base substrate material, and a thermal resistance value. ベース基板材料としてLTCCを使用した場合におけるスリット幅と熱抵抗値との関係を示す表である。It is a table | surface which shows the relationship between the slit width at the time of using LTCC as a base substrate material, and a thermal resistance value. ベース基板材料としてHTCCを使用した場合におけるスリット幅と熱抵抗値との関係を示す表である。It is a table | surface which shows the relationship between the slit width at the time of using HTCC as a base substrate material, and a thermal resistance value. ベース基板材料として樹脂材、LTCC及びHTCCを使用した各場合のスリット幅と熱抵抗差との関係を示す線図である。It is a diagram which shows the relationship between the slit width and the thermal resistance difference in each case where a resin material, LTCC and HTCC are used as the base substrate material. 外部接続端子(信号端子,GND端子)の形成部を示す模式図であり、(a)は信号端子、(b)はGND端子(スリットを形成しない場合)、(c)はGND端子(スリットを形成した場合)、(d)はGND端子(スリットと橋絡部を形成した場合)をそれぞれ示す。It is a schematic diagram which shows the formation part of an external connection terminal (a signal terminal, a GND terminal), (a) is a signal terminal, (b) is a GND terminal (when a slit is not formed), (c) is a GND terminal (a slit is formed). (When formed), (d) shows a GND terminal (when a slit and a bridging portion are formed), respectively. 前記図10の(a)〜(d)の各端子構造における熱抵抗の算出結果を示す表である。It is a table | surface which shows the calculation result of the thermal resistance in each terminal structure of (a)-(d) of the said FIG. GND端子の周囲に幅10〜500μmのスリットを設けたときの信号端子‐GND端子間の熱抵抗差を示す表である。It is a table | surface which shows the thermal resistance difference between a signal terminal -GND terminal when the slit of width 10-500 micrometers is provided around the GND terminal. GND端子の周囲に形成したスリット幅と、信号端子‐GND端子間の熱抵抗差との関係を示す線図である。It is a diagram which shows the relationship between the slit width formed in the circumference | surroundings of a GND terminal, and the thermal resistance difference between a signal terminal -GND terminal. 従来のデュプレクサの一例を示す底面図である。It is a bottom view which shows an example of the conventional duplexer. 従来のデュプレクサを別の例を示す底面図である。It is a bottom view which shows another example of the conventional duplexer. 従来のデュプレクサの一例を示す側面断面図である。It is side surface sectional drawing which shows an example of the conventional duplexer. 前記図16のデュプレクサ(実装基板に基準電位偏差がない場合)における寄生インダクタンスを示す模式図である。FIG. 17 is a schematic diagram showing parasitic inductance in the duplexer of FIG. 16 (when the mounting substrate has no reference potential deviation). 前記図16のデュプレクサ(実装基板に基準電位偏差がある場合)における寄生インダクタンスを示す模式図である。FIG. 17 is a schematic diagram showing parasitic inductance in the duplexer of FIG. 16 (when the mounting substrate has a reference potential deviation). 従来のデュプレクサの別の例を示す側面断面図である。It is side surface sectional drawing which shows another example of the conventional duplexer. 前記図19のデュプレクサにおける寄生インダクタンスを示す模式図である。FIG. 20 is a schematic diagram showing parasitic inductance in the duplexer of FIG. 19. 従来のデュプレクサのさらに別の例を示す側面断面図である。It is side surface sectional drawing which shows another example of the conventional duplexer. 前記図21のデュプレクサにおける寄生インダクタンスを示す模式図である。It is a schematic diagram which shows the parasitic inductance in the duplexer of the said FIG.

符号の説明Explanation of symbols

1 信号端子(送信端子)
2 信号端子(受信端子)
3 信号端子(アンテナ端子)
4 GND端子
21 デュプレクサ
22 ベース基板
23 蓋体
24 送信用フィルタ素子
25 受信用フィルタ素子
35 共通GND部
36 スリット
37 橋絡部
40 ソルダーレジスト(はんだマスク)
1 Signal terminal (transmission terminal)
2 Signal terminal (Reception terminal)
3 Signal terminal (antenna terminal)
4 GND terminal 21 Duplexer 22 Base substrate 23 Cover 24 Transmission filter element 25 Reception filter element 35 Common GND part 36 Slit 37 Bridge part 40 Solder resist (solder mask)

Claims (5)

パッケージの一方の面に、いずれも導体で形成した、外部接続用の信号端子と、外部接続用の基準電位端子と、当該外部接続用の基準電位端子と電気的に接続された共通基準電位部とを備えたフィルタであって、
前記共通基準電位部と前記基準電位端子との間に、当該共通基準電位部と当該基準電位端子とを部分的に分離するスリット部
を設けたことを特徴とするフィルタ。
A signal terminal for external connection, a reference potential terminal for external connection, and a common reference potential portion electrically connected to the reference potential terminal for external connection, all formed of a conductor on one surface of the package A filter with
A filter comprising a slit for partially separating the common reference potential portion and the reference potential terminal between the common reference potential portion and the reference potential terminal.
前記フィルタが弾性表面波フィルタである請求項1に記載のフィルタ。   The filter according to claim 1, wherein the filter is a surface acoustic wave filter. パッケージの一方の面に、いずれも導体で形成した、外部接続用の信号端子と、外部接続用の基準電位端子と、当該外部接続用の基準電位端子と電気的に接続された共通基準電位部とを備えたデュプレクサであって、
前記共通基準電位部と前記基準電位端子との間に、当該共通基準電位部と当該基準電位端子とを部分的に分離するスリット部
を設けたことを特徴とするデュプレクサ。
A signal terminal for external connection, a reference potential terminal for external connection, and a common reference potential portion electrically connected to the reference potential terminal for external connection, all formed of a conductor on one surface of the package A duplexer with
A duplexer characterized in that a slit portion for partially separating the common reference potential portion and the reference potential terminal is provided between the common reference potential portion and the reference potential terminal.
前記デュプレクサが弾性表面波デュプレクサである請求項3に記載のデュプレクサ。   The duplexer according to claim 3, wherein the duplexer is a surface acoustic wave duplexer. 前記共通基準電位部は、前記信号端子の形成部を除いた前記パッケージの一方の面の略全面に亘って形成されて前記基準電位端子と電気的に接続され、
前記共通基準電位部と前記基準電位端子との間には、前記スリット部と、前記共通基準電位部と前記基準電位端子と電気的に接続する導体からなる橋絡部とが形成され、
前記基準電位端子は、前記パッケージの一方の面に配されたソルダーレジストにより画成されている
ことを特徴とする請求項1から4のいずれか一項に記載のフィルタ又はデュプレクサ。
The common reference potential portion is formed over substantially the entire one surface of the package excluding the signal terminal forming portion and is electrically connected to the reference potential terminal.
Between the common reference potential portion and the reference potential terminal, the slit portion and a bridging portion made of a conductor electrically connected to the common reference potential portion and the reference potential terminal are formed,
The filter or duplexer according to any one of claims 1 to 4, wherein the reference potential terminal is defined by a solder resist disposed on one surface of the package.
JP2005024639A 2005-01-31 2005-01-31 Filter and duplexer Withdrawn JP2006211620A (en)

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Application Number Priority Date Filing Date Title
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009088908A (en) * 2007-09-28 2009-04-23 Murata Mfg Co Ltd Elastic wave device
JP2010087586A (en) * 2008-09-29 2010-04-15 Fujitsu Media Device Kk Elastic wave device
JP2010526456A (en) * 2007-04-30 2010-07-29 エプコス アクチエンゲゼルシャフト Electrical component
WO2011089747A1 (en) * 2010-01-25 2011-07-28 株式会社村田製作所 Electronic module and communication equipment
TWI651042B (en) * 2015-01-06 2019-02-11 南韓商愛思開海力士有限公司 Electromagnetic interference suppression structure and electronic device having the same

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010526456A (en) * 2007-04-30 2010-07-29 エプコス アクチエンゲゼルシャフト Electrical component
JP2009088908A (en) * 2007-09-28 2009-04-23 Murata Mfg Co Ltd Elastic wave device
JP2010087586A (en) * 2008-09-29 2010-04-15 Fujitsu Media Device Kk Elastic wave device
JP4663770B2 (en) * 2008-09-29 2011-04-06 太陽誘電株式会社 Elastic wave device
WO2011089747A1 (en) * 2010-01-25 2011-07-28 株式会社村田製作所 Electronic module and communication equipment
CN102714491A (en) * 2010-01-25 2012-10-03 株式会社村田制作所 Electronic module and communication equipment
JP5382141B2 (en) * 2010-01-25 2014-01-08 株式会社村田製作所 Electronic module and communication device
US8797759B2 (en) 2010-01-25 2014-08-05 Murata Manufacturing Co., Ltd. Electronic module and communication apparatus
CN102714491B (en) * 2010-01-25 2015-02-18 株式会社村田制作所 Electronic module and communication equipment
TWI651042B (en) * 2015-01-06 2019-02-11 南韓商愛思開海力士有限公司 Electromagnetic interference suppression structure and electronic device having the same

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