JP2011134983A - Method of manufacturing silicon semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology of manufacturing a semiconductor substrate including a monocrystalline silicon carbide layer, and particularly, a technology of manufacturing a semiconductor substrate further including a stress relief silicon carbide layer on a surface layer part of a silicon substrate. <P>SOLUTION: The method of manufacturing a silicon semiconductor substrate sequentially executes a step (1) of preparing the silicon substrate, a step (2) of implanting carbon ions into the silicon substrate to form a carbon-containing layer where silicon is mixed with carbon, a step (3) of heat-treating the substrate to form the stress relief silicon carbide film layer and an oxide film cap from the carbon-containing layer, a step (4) of removing the oxide film cap, a step (5) of forming a second oxide film cap, a step (6) of implanting carbon ions into a silicon layer between the stress relief silicon carbide film layer and the second oxide film cap to form a carbon-containing layer where silicon is mixed with carbon, a step (7) of heat-treating the substrate to form a crystal growth silicon carbide film layer from the carbon-containing layer, and a step (8) of removing the oxide film caps formed on the surface of the substrate. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a technique for manufacturing a semiconductor substrate including a single crystal silicon carbide layer, and more particularly to a technique for manufacturing a semiconductor substrate in which a surface layer portion of the silicon substrate further includes a stress relaxation silicon carbide layer.

  Silicon carbide has a high Schottky barrier, a high breakdown field strength, and a high heat transfer property, and thus is suitable as a material for power devices. Silicon carbide has a lattice constant close to that of a nitride semiconductor, which is a typical optoelectronic semiconductor material, and allows nitride compound semiconductors to be epitaxially grown with low defects, making it suitable as an optoelectronic material. ing. As a method for producing such single crystal silicon carbide, a single crystal growth method and a thin film epitaxial method are known. However, it is difficult to realize a substrate having a large area of 6 inches or more, and there is a problem that the substrate becomes very expensive. . As a method for realizing a single crystal silicon carbide substrate in a large area of 6 inches or more at a low cost, a method for manufacturing a semiconductor substrate having a single crystal silicon carbide layer as a surface layer is already known (Patent Document 1). The thickness of the crystalline silicon carbide layer is only obtained in the range of 50 to 100 nm.

  On the other hand, as a recent semiconductor material for optoelectronics, a material obtained by epitaxially growing gallium nitride (GaN) on a single crystal silicon carbide layer with a few defects on the order of several μm has been required. However, the gallium nitride epitaxial layer having such a thickness has a strong stress (internal strain), and there is a problem that a crack occurs on the surface or inside of the GaN layer.

JP2007-339041

  The present invention provides a technique for manufacturing a semiconductor substrate having a silicon carbide layer on the surface layer portion of a silicon substrate that does not crack on the surface even when nitride is epitaxially grown by several μm.

  The present inventor has found that the above problem can be solved by providing a silicon carbide layer for relaxing stress under a single crystal silicon carbide layer for epitaxially growing nitride by several μm.

  That is, the manufacturing method of the present invention is a method of manufacturing a silicon semiconductor substrate comprising a single crystal silicon carbide layer having a surface layer portion of a silicon substrate having a stress relaxation silicon carbide layer, wherein the following steps are sequentially performed. To: (1) Prepare a silicon semiconductor substrate; (2) Implant carbon ions into the silicon substrate to form a first carbon-containing layer in which silicon and carbon are mixed in the silicon substrate. An implantation step; (3) heat-treating the silicon substrate to form a silicon semiconductor substrate comprising the first carbon-containing layer as a stress relaxation silicon carbide film layer and a first surface oxide film cap; (4) removing the first surface oxide film cap; (5) forming a second surface oxide film cap; and (6) the stress relieving silicon carbide. A second carbon ion implantation step of implanting carbon ions into the silicon layer between the layer and the second surface oxide film cap to form a second carbon-containing layer in which silicon and carbon are mixed; (7 ) Heat treating the silicon substrate to make the second carbon-containing layer a crystal-grown silicon carbide film layer; and (8) removing the second oxide film cap formed on the surface of the silicon substrate. .

  The manufacturing method of the present invention includes a method of using the substrate 30 obtained in the above step (3) as the substrate 50 used in the step (5).

  Furthermore, the present invention provides a carbon atom concentration on the carbon-containing layer side at the interface between the silicon-containing layer and the silicon-containing layer between the silicon oxide layer and the single-crystal silicon carbide layer immediately after the second carbon ion implantation. Is a method for producing a silicon semiconductor substrate, wherein the ion implantation conditions are adjusted so that the maximum value of the carbon atom concentration in the carbon-containing layer is not less than 15 atom% and not more than 55 atom%.

  Furthermore, the present invention provides a carbon atom concentration on the carbon-containing layer side at the interface between the silicon-containing layer and the silicon-containing layer between the silicon oxide layer and the single-crystal silicon carbide layer immediately after the second carbon ion implantation. Is a method for manufacturing a silicon semiconductor substrate, characterized by being 25 atom% or more.

  Furthermore, the present invention is a method for producing a silicon semiconductor substrate, wherein the carbon ion implantation is performed in a state where the silicon substrate is heated to a temperature of 400 ° C. or higher and 1000 ° C. or lower.

  Furthermore, the present invention is a method for producing a silicon semiconductor substrate, wherein the silicon substrate is produced by a Czochralski method or a float zone method.

  A semiconductor substrate having a single crystal silicon carbide layer on the surface portion of a silicon substrate obtained by the method of the present invention has a silicon carbide layer for stress relaxation, and nitride is epitaxially grown on the surface of the single crystal silicon carbide by several μm. Even if it makes it, it does not produce a crack in the epitaxial surface.

The process of this invention is shown. The silicon semiconductor substrate in each process of FIG. 1 is shown.

(Embodiment 1)
Next, the form for implementing this invention is demonstrated in detail based on FIG.1 and FIG.2. The silicon semiconductor substrate 80 obtained by the manufacturing method of the present invention has the following characteristics. The silicon layer 1 comprises a silicon carbide layer 3 for stress relaxation and a surface single crystal silicon carbide layer 8 for growing a single crystal nitride.

  Here, the silicon carbide layer 8 is a commonly known single crystal silicon carbide layer. The silicon carbide layer has a high Schottky barrier, high breakdown field strength and high heat transfer, and is an ideal material for high voltage power devices, devices made of silicon carbide were heavily loaded Even in such a case, it is difficult to overheat and an expensive external cooling device is not required, so that it is possible to manufacture a lighter device with a shorter switching time and a smaller size. Furthermore, silicon carbide is suitable for the production of optoelectronic devices because its lattice constant is close to that of typical optoelectronic semiconductor materials, such as nitride compound semiconductors, compared to the lattice constant of silicon or sapphire. . This is advantageous for avoiding defects when epitaxially growing a nitride compound semiconductor on silicon carbide.

  Further, the silicon carbide layer 3 for stress relaxation is formed on the silicon layer below the surface single crystal silicon carbide layer 8 for growing the single crystal nitride, and is nitrided on the surface single crystal silicon carbide layer 8. This means that the stress accumulated when epitaxially growing an object (for example, GaN) is relaxed. For example, by having amorphous silicon carbide in the single crystal silicon carbide, it is accumulated in the surface single crystal silicon carbide layer 8. It is possible to relieve the stress. The flatness of the exposed surface of the surface single crystal silicon carbide layer 8 is at most 0.5 nm RMS.

  In addition, the silicon semiconductor substrate 80 obtained by the manufacturing method of the present invention is formed by using a normal nitride, for example, GaN, to a thickness of about 10 μm by using a generally known method / apparatus while suppressing the occurrence of surface cracks. It can be epitaxially grown.

  The first step (S1) of the present invention is a process for preparing the silicon semiconductor substrate 10. Here, the substrate 10 usable in the present invention is a substrate having the silicon layer 1 and is not limited in size or shape. Specifically, a silicon wafer for producing a conventionally known SiC wafer (a silicon substrate having a single crystal silicon carbide layer on the surface) can be mentioned.

  The second step (S2) of the present invention is a technique similar to a method known as a so-called IBS-SiC process in combination with the subsequent third step (S3) (references J. K. L. LIndner, A. et al. Fronwieseer, B. Rauschenbach and B. Stritzker, Fall Meeting of the Materials Research Society, Boston, USA (1994), Mater. Res. Syn., Vol. The second step is a process in which carbon ions are implanted into the silicon layer 1 of the silicon substrate 10 to form the carbon-containing layer 2. In the present invention, the carbon ion implantation position, carbon ion concentration, and implantation distribution of the carbon-containing layer 2 are not particularly limited as long as the stress relaxation silicon carbide layer 3 is formed by the third step of the subsequent heat treatment. .

  In the present invention, the implantation position is preferably selected such that the peak of the carbon ion concentration is selected at a depth of 400 to 500 nm from the surface of the substrate 10. Further, the implantation concentration is preferably set so that the maximum value of the carbon atom concentration is in the range of 45 to 55 atom%. The carbon-containing layer 2 obtained under such carbon ion implantation conditions becomes the silicon carbide layer 3 at a position in the range of 300 to 400 nm from the surface of the substrate 20 and is optimal for stress relaxation.

In the present invention, the carbon ion implantation method and apparatus are not particularly limited, and a conventionally known method and apparatus can be used (references JKN LIndner, A. Frönwieser, B. Rauschenbach, and B. Stritzker, Fall meeting of the Materials Research Society, Boston, USA (1994), Mater. Res. Syn. Proc, Vol. 354 (1995), 171). For example, the carbon ion implantation energy is about 170 to 200 keV, and the carbon ion implantation amount is 7 × 10 ^{17 to} 8 × 10 ¹⁷ cm ⁻² .

  In the third step (S3) of the present invention, the carbon-containing layer 2 formed in the second step is annealed to form a silicon carbide layer 3, and a first oxide film cap is formed on the surface at the same time. This is a step of obtaining a semiconductor substrate 30 in which the silicon layer 11 is provided between the cap 4 and the siliconized layer 3. The heat treatment is not particularly limited as long as it is a condition for changing the carbon-containing layer 2 to the silicon carbide layer 3, and a generally known method is preferably applicable (reference document JP 2007-339041). Specifically, the substrate 20 is heat-treated in an argon gas atmosphere containing about 0.5% by volume of oxygen at a temperature of 1100 ° C. or higher and lower than the silicon melting point. The time required for this heat treatment is about 10 hours. Such a small amount of oxygen is added for the purpose of protecting the heating furnace. Simultaneously with the heat treatment in this step, the surface of the exposed silicon layer 1 is oxidized to form a thin oxide film (first oxide film cap 4). The thickness of the first oxide film cap 4 is about 130 to 140 nm. Accordingly, the substrate 30 obtained in the third step includes the silicon layer 1, the silicon carbide layer 3, the silicon layer 11 thereon, and the thin first oxide film cap 4.

  The fourth step (S4) of the present invention is a step of removing the first surface oxide film cap 4 and exposing the silicon layer 11. There are no particular restrictions on the removal method and apparatus here, and any method that removes the silicon oxide film on the surface of a commonly known so-called silicon semiconductor substrate is applicable. Specifically, there are a dry method and a wet method, and either method is applicable. In the present invention, a wet etching method is particularly preferable, and dilute hydrofluoric acid or ammonium fluoride can be used as the liquid phase etchant. In this case, the fourth step includes cleaning with pure water to further clean the etched semiconductor 40.

  The fifth step (S5) of the present invention is a heat treatment step for forming the second surface oxide film cap 5 on the surface of the silicon surface 11 obtained above. The oxide film cap 5 only needs to have a thickness capable of forming the carbon-containing layer 6 between the silicon carbide layer 3. Specifically, for example, when 100 to 200 keV is used as the implantation energy of carbon ions, it is selected from a value in the range of about 250 nm to 550 nm.

  The sixth step (S6) of the present invention is a step of forming the carbon-containing layer 6 by implanting second carbon ions into the obtained silicon layer 11. Similar conditions as in the second step of the present invention can be used. In the present invention, the implantation position, carbon ion concentration, and implantation distribution of the carbon-containing layer 6 are not particularly limited, and the surface single crystal silicon carbide layer 8 for growing single crystal nitride is formed by the seventh step of the subsequent heat treatment. Anything can be used. In the present invention, immediately after the implantation of carbon ions, the carbon atom concentration at the interface (on the carbon-containing layer 6 side) between the carbon-containing layer 6 and the second surface oxide film cap 5 is 15 atom% or more, and the carbon in the carbon-containing layer 6 The ion implantation conditions are adjusted so that the maximum value of the atomic concentration is 55 atom% or less, and carbon ions are implanted.

  Setting the carbon atom concentration at the interface of the second surface oxide film cap 5 / carbon-containing layer 6 (carbon-containing layer 6 side) to 15 atom% or more is extremely important in order to achieve good surface roughness. When the carbon atom concentration at the interface between the second surface oxide film cap 5 and the carbon-containing layer 6 (the carbon-containing layer 6 side) is less than 15 atom%, the polysilicon carbide grains are formed on the single crystal silicon carbide layer 8 after annealing. A transition layer made of Si crystals begins to appear, and the surface roughness after the completion of all the processes deteriorates. On the other hand, if the carbon atom concentration at the interface between the second surface oxide film cap 5 and the carbon-containing layer 6 (the carbon-containing layer 6 side) is 15 atom% or more, the transition layer disappears and a good surface roughness is realized. It is possible.

  More preferably, in order to stably realize a good surface roughness, the carbon atom concentration at the second surface oxide film cap 5 / carbon-containing layer 6 interface (carbon-containing layer 6 side) is set to 25 atom% or more. desirable.

  Setting the maximum value of the carbon atom concentration in the carbon-containing layer 6 to 55 atom% or less is extremely important in order to maintain the crystallinity of the single-crystal silicon carbide layer 8. If the maximum value of carbon atom concentration in the carbon-containing layer 6 exceeds 55 atom%, after annealing, defects composed of fine carbon grains appear in the single crystal silicon carbide layer 8, and the crystallinity of the single crystal silicon carbide layer 8 is reduced. Deteriorate. On the other hand, when the maximum value of the carbon atom concentration in the carbon-containing layer 6 is set to 55 atom% or less, it is possible to suppress the appearance of the above-described carbon particles.

  More preferably, the maximum value of the carbon atom concentration in the carbon-containing layer 6 is preferably set to 50 atom% or less in order to stably suppress the carbon particles.

  The implantation of carbon ions is preferably performed in a state where the silicon substrate is heated to a temperature of 400 ° C. or higher. If the heating temperature of the substrate is lower than 400 ° C., the orientation of the single crystal silicon carbide grains constituting the carbon-containing layer 6 is disturbed after the implantation. Therefore, the crystallinity of the single crystal silicon carbide layer 8 is disturbed after annealing, which is extremely serious. In some cases, it may be a poly layer.

  More preferably, in order to further enhance the crystallinity of the single crystal silicon carbide layer 8, it is desirable to implant carbon ions while the silicon substrate is heated to a temperature of 500 ° C. or higher.

  The implantation of carbon ions is desirably performed in a state where the silicon substrate is heated to a temperature of 1000 ° C. or lower. If the heating temperature of the substrate exceeds 1000 ° C., the single crystal silicon carbide grains constituting the carbon-containing layer 6 are fused in a dendritic shape after implantation, and after annealing, the denseness and uniformity of the single crystal silicon carbide layer 8 are improved. Damaged.

  More preferably, in order to further improve the density and uniformity of the single crystal silicon carbide layer 8, it is desirable to implant carbon ions while the silicon substrate is heated to a temperature of 800 ° C. or lower.

The carbon-containing layer 6 obtained by such carbon ion implantation conditions becomes a silicon carbide layer 8 between the surface of the substrate 70 and the silicon carbide layer 3, and has an optimal crystallinity and surface for epitaxial growth of single crystal nitride. It becomes single crystal silicon carbide having roughness. In the present invention, the carbon ion implantation method and apparatus are not particularly limited, and a conventionally known method and apparatus can be used (references JKN LIndner, A. Frönwieser, B. Rauschenbach, and B. Stritzker, Fall Meeting of the Materials Research Society, Boston, USA (1994), Mater. Res. Syn. Proc, Vol. 354 (1995), 171). For example, the carbon ion implantation energy is about 100 to 200 keV, and the carbon ion implantation amount is 7 × 10 ^{17 to} 8 × 10 ¹⁷ cm ⁻² .

  In the seventh step (S7) of the present invention, the carbon-containing layer 6 formed in the sixth step is annealed to form a silicon carbide layer 8, and nitrided between the second oxide film cap 4 and the silicon carbide layer 3. This is a step of obtaining the semiconductor substrate 70 provided with the silicon carbide layer 8 for material growth. The heat treatment is not particularly limited as long as it is a condition for changing the carbon-containing layer 6 to the single crystal silicon carbide layer 8, and a generally known method is preferably applicable. (Reference document JP2007-339041). Specifically, the substrate 60 is heat-treated in an argon gas atmosphere containing about 0.5% by volume of oxygen at a temperature of 1100 ° C. or higher and lower than the silicon melting point. The time required for this heat treatment is about 10 hours. Such a small amount of oxygen is added for the purpose of protecting the heating furnace.

  In the eighth step (S8) of the present invention, the second oxide film cap on the surface of the substrate 70 is removed to obtain the substrate 80 from which the single crystal silicon carbide film 8 is exposed. There are no particular restrictions on the removal method and apparatus here, and any method that removes the silicon oxide film on the surface of a commonly known so-called silicon semiconductor substrate is applicable. Specifically, there are a dry method and a wet method, and either method is applicable. In the present invention, a wet etching method is particularly preferable, and dilute hydrofluoric acid or ammonium fluoride can be used as the liquid phase etchant. In this case, the eighth step includes cleaning with pure water in order to further clean the etched semiconductor 80.

(Embodiment 2)
Although not shown, in addition to the method of the present invention described above, as another embodiment of the present invention, the substrate 30 obtained in step 3 (S3) of the present invention is used as it is in step 5 (S5) of the present invention. It is an aspect used as the board | substrate 50 obtained by. In this aspect, in the present invention, the first oxide film cap corresponds to the second oxide film cap.

  Here, the thickness of the oxide film cap 5 preferable as the substrate 50 can be easily adjusted by controlling the conditions of the heat treatment in step 3. Specifically, in step 3, it is possible mainly by controlling the heat treatment time or the amount of a small amount of oxygen. Specifically, the substrate 30 obtained by heat-treating the substrate 20 for about 10 hours in an argon gas atmosphere containing about 0.5% by volume of oxygen at a temperature of 1100 ° C. or higher and lower than the silicon melting point continues to have a temperature of 1100 ° C., for example. By performing heat treatment for about 2 hours to about 12 hours in a 100% oxygen atmosphere at a temperature, it is possible to form the oxide film cap 5 having a thickness of about 250 nm to 550 nm.

  EXAMPLES Hereinafter, although this invention is demonstrated in more detail based on an Example, this invention is not limited to these Examples.

Example 1
A (111) n-type float zone silicon wafer having a diameter of 150 mm is prepared, and carbon ion (C +) implantation is performed on the wafer at a wafer heating temperature of 550 ° C., an acceleration energy of 200 keV, and a dose of 7.5 × 10 ¹⁷ / cm ^2. A carbon-containing layer was formed inside the silicon substrate. After the injection, the sample was annealed at 1350 ° C. in an Ar + 0.5 volume% O ₂ atmosphere for 10 hours in a vertical high-temperature heat treatment furnace. At this time, the thicknesses of the respective layers were as follows: surface oxide layer 129 nm / silicon layer 325 nm / single crystal silicon carbide layer 135 nm. Thereafter, the surface oxide film formed on the sample surface was removed with diluted hydrofluoric acid. Subsequently, the sample was heat-treated in a dry oxidation atmosphere at 1100 ° C. to form a 430 nm surface oxide film on the wafer. At this time, the thickness of each layer was as follows: surface oxide layer 430 nm / silicon layer 134 nm / single crystal silicon carbide layer 135 nm. Subsequently, carbon ion (C +) implantation is performed at a wafer heating temperature of 550 ° C., an acceleration energy of 180 keV, and a dose of 7.5 × 10 ¹⁷ / cm ² , and carbon is contained inside the silicon substrate between the surface oxide layer and the single crystal silicon carbide layer. A layer was formed. After the injection, the oxide film layer formed on the sample was removed with diluted hydrofluoric acid. Subsequently, the sample was annealed at 1350 ° C. in an Ar + 0.5 volume% O ₂ atmosphere for 10 hours in a vertical high-temperature heat treatment furnace, and then the surface oxide film formed on the sample surface was removed with diluted hydrofluoric acid. At this time, the thickness of the single crystal silicon carbide layer was 201 nm. When the surface roughness (RMS) of the sample was evaluated by AFM (measurement area 10 μm × 10 μm), it was 0.43 nm. Thereafter, a 6 μm GaN layer was formed on the surface of the sample at a growth temperature of 1200 ° C. using a MOVPE (Metal Organic Vapor Phase Epitaxy) method. At this time, the length of the crack generated in the GaN layer was 13 mm / mm ² per unit area.

(Comparative Example 1)
A (111) n-type float zone silicon wafer having a diameter of 150 mm is prepared, and carbon ion (C +) implantation is performed on the wafer at a wafer heating temperature of 550 ° C., an acceleration energy of 200 keV, and a dose of 7.5 × 10 ¹⁷ / cm ^2. A carbon-containing layer was formed inside the silicon substrate. After the injection, the sample was annealed at 1350 ° C. in an Ar + 0.5 volume% O ₂ atmosphere for 10 hours in a vertical high-temperature heat treatment furnace. At this time, the thickness of each layer was as follows: surface oxide layer 130 nm / silicon layer 329 nm / single crystal silicon carbide layer 136 nm. Subsequently, the surface oxide film and the silicon layer were oxidized in a dry oxidation atmosphere at 1100 ° C., and the surface oxide film formed on the sample surface by the oxidation was removed with diluted hydrofluoric acid. Then, when the surface roughness (RMS) of the sample was evaluated by AFM (measurement area 10 μm × 10 μm), it was as large as 3.6 nm and it was difficult to grow GaN directly, so CMP treatment was performed. The surface roughness of the sample at this time was 0.49 nm, and the thickness of the single crystal silicon carbide layer was 76 nm. Thereafter, a 6 μm GaN layer was formed on the surface of the sample at a growth temperature of 1200 ° C. using a MOVPE (Metal Organic Vapor Phase Epitaxy) method. At this time, the length of the crack generated in the GaN layer was 50 mm / mm ² per unit area.

(Comparative Example 2)
A (111) n-type float zone silicon wafer having a diameter of 150 mm was prepared and heat-treated in a dry oxidation atmosphere at 1100 ° C. to form a 430 nm surface oxide film on the wafer. Thereafter, carbon ion (C +) implantation was performed at a wafer heating temperature of 550 ° C., an acceleration energy of 180 keV, and a dose of 7.5 × 10 ¹⁷ / cm ² to form a carbon-containing layer under the surface oxide layer. After the injection, the oxide film layer formed on the sample was removed with diluted hydrofluoric acid. Subsequently, the sample was annealed at 1350 ° C. in an Ar + 0.5 volume% O ₂ atmosphere for 10 hours in a vertical high-temperature heat treatment furnace, and then the surface oxide film formed on the sample surface was removed with diluted hydrofluoric acid. At this time, the thickness of the single crystal silicon carbide layer was 78 nm. When the surface roughness (RMS) of the sample was evaluated by AFM (measurement area 10 μm × 10 μm), it was 0.45 nm. Thereafter, a 6 μm GaN layer was formed on the surface of the sample at a growth temperature of 1200 ° C. using a MOVPE (Metal Organic Vapor Phase Epitaxy) method. At this time, the length of the crack generated in the GaN layer was 48 mm / mm ² per unit area.

(Example 2)
A (111) n-type float zone silicon wafer having a diameter of 150 mm is prepared, and carbon ion (C +) implantation is performed on the wafer at a wafer heating temperature of 550 ° C., an acceleration energy of 200 keV, and a dose of 7.5 × 10 ¹⁷ / cm ^2. A carbon-containing layer was formed inside the silicon substrate. After the implantation, the sample was annealed in a vertical high temperature heat treatment furnace at 1350 ° C. in an Ar + 0.5 volume% O ₂ atmosphere for 10 hours, and then the sample was heat treated in a dry oxidation atmosphere at 1100 ° C. to 550 nm on the wafer. A surface oxide film was formed. The thickness of each layer at this time was 550 nm of the surface oxide layer / 138 nm of the silicon layer / 135 nm of the single crystal silicon carbide layer. Subsequently, carbon ions (C +) are implanted at a wafer heating temperature of 550 ° C., an acceleration energy of 200 keV, and a dose of 7.5 × 10 ¹⁷ / cm ² , and carbon is contained inside the silicon substrate between the surface oxide layer and the single crystal silicon carbide layer. A layer was formed. After the injection, the oxide film layer formed on the sample was removed with diluted hydrofluoric acid. Subsequently, the sample was annealed at 1350 ° C. in an Ar + 0.5 volume% O ₂ atmosphere for 10 hours in a vertical high-temperature heat treatment furnace, and then the surface oxide film formed on the sample surface was removed with diluted hydrofluoric acid. At this time, the thickness of the single crystal silicon carbide layer was 221 nm. When the surface roughness (RMS) of the sample was evaluated by AFM (measurement area 10 μm × 10 μm), it was 0.47 nm. Thereafter, a 6 μm GaN layer was formed on the surface of the sample at a growth temperature of 1200 ° C. using a MOVPE (Metal Organic Vapor Phase Epitaxy) method. At this time, the length of the crack generated in the GaN layer was 16 mm / mm ² per unit area.

(Example 3)
A (111) n-type float zone silicon wafer having a diameter of 150 mm is prepared, and carbon ion (C +) implantation is performed on the wafer at a wafer heating temperature of 550 ° C., an acceleration energy of 180 keV, and a dose of 7.5 × 10 ¹⁷ / cm ^2. A carbon-containing layer was formed inside the silicon substrate. After the injection, the sample was annealed at 1350 ° C. in an Ar + 0.5 volume% O ₂ atmosphere for 10 hours in a vertical high-temperature heat treatment furnace. The thickness of each layer at this time was as follows: surface oxide layer 132 nm / silicon layer 273 nm / single crystal silicon carbide layer 137 nm. Thereafter, the surface oxide film formed on the sample surface was removed with diluted hydrofluoric acid. The sample was subsequently heat-treated in a dry oxidation atmosphere at 1100 ° C. to form a 250 nm surface oxide film on the wafer. At this time, the thickness of each layer was as follows: surface oxide layer 250 nm / silicon layer 164 nm / single crystal silicon carbide layer 137 nm. Subsequently, carbon ion (C +) implantation is performed at a wafer heating temperature of 550 ° C., an acceleration energy of 100 keV, and a dose of 7.5 × 10 ¹⁷ / cm ² , and carbon is contained inside the silicon substrate between the surface oxide layer and the single crystal silicon carbide layer. A layer was formed. After the injection, the oxide film layer formed on the sample was removed with diluted hydrofluoric acid. Subsequently, the sample was annealed at 1350 ° C. in an Ar + 0.5 volume% O ₂ atmosphere for 10 hours in a vertical high-temperature heat treatment furnace, and then the surface oxide film formed on the sample surface was removed with diluted hydrofluoric acid. At this time, the thickness of the single crystal silicon carbide layer was 217 nm. When the surface roughness (RMS) of the sample was evaluated by AFM (measurement area 10 μm × 10 μm), it was 0.49 nm. Thereafter, a 6 μm GaN layer was formed on the surface of the sample at a growth temperature of 1200 ° C. using a MOVPE (Metal Organic Vapor Phase Epitaxy) method. At this time, the length of the crack generated in the GaN layer was 18 mm / mm ² per unit area.

Example 4
A (111) n-type float zone silicon wafer having a diameter of 150 mm is prepared, and carbon ion (C +) implantation is performed on the wafer at a wafer heating temperature of 550 ° C., an acceleration energy of 180 keV, and a dose of 7.5 × 10 ¹⁷ / cm ^2. A carbon-containing layer was formed inside the silicon substrate. After the implantation, the sample was annealed in a vertical high temperature heat treatment furnace at 1350 ° C. in an Ar + 0.5 volume% O ₂ atmosphere for 10 hours, and then the sample was heat treated in a dry oxidation atmosphere at 1100 ° C. A surface oxide film was formed. The thickness of each layer at this time was as follows: surface oxide layer 400 nm / silicon layer 155 nm / single crystal silicon carbide layer 136 nm. Subsequently, carbon ion (C +) implantation is performed at a wafer heating temperature of 550 ° C., an acceleration energy of 180 keV, and a dose of 7.5 × 10 ¹⁷ / cm ² , and carbon is contained inside the silicon substrate between the surface oxide layer and the single crystal silicon carbide layer. A layer was formed. After the injection, the oxide film layer formed on the sample was removed with diluted hydrofluoric acid. Subsequently, the sample was annealed at 1350 ° C. in an Ar + 0.5 volume% O ₂ atmosphere for 10 hours in a vertical high-temperature heat treatment furnace, and then the surface oxide film formed on the sample surface was removed with diluted hydrofluoric acid. At this time, the thickness of the single crystal silicon carbide layer was 214 nm. When the surface roughness (RMS) of the sample was evaluated by AFM (measurement area 10 μm × 10 μm), it was 0.50 nm. Thereafter, a 6 μm GaN layer was formed on the surface of the sample at a growth temperature of 1200 ° C. using a MOVPE (Metal Organic Vapor Phase Epitaxy) method. At this time, the length of the crack generated in the GaN layer was 19 mm / mm ² per unit area.

  The method of the present invention is likely to be used particularly in the field of optoelectronic semiconductor materials.

DESCRIPTION OF SYMBOLS 1 Silicon layer 2 Carbon-containing layer 3 Silicon carbide layer for stress relaxation 4 First oxide film cap 5 Second oxide film cap 6 Carbon-containing layer 8 Surface single crystal silicon carbide layer for growing single crystal nitride 11 Silicon layer 10 Substrate in Step 1 (S1) 20 Substrate in Step 2 (S2) 30 Substrate in Step 3 (S3) 40 Substrate in Step 4 (S4) 50 Substrate in Step 5 (S5) 60 Step Substrate in 6 (S6) 70 Substrate in Step 7 (S7) 80 Substrate in Step 8 (S8)

Claims (5)

A method for producing a silicon semiconductor substrate comprising a single crystal silicon carbide layer in which a surface layer portion of a silicon substrate has a stress relaxation silicon carbide layer, wherein the following steps are sequentially performed:
(1) Prepare a silicon semiconductor substrate,
(2) a first carbon ion implantation step of implanting carbon ions into the silicon substrate to form a first carbon-containing layer in which silicon and carbon are mixed in the silicon substrate;
(3) heat-treating the silicon substrate to form a silicon semiconductor substrate including the first carbon-containing layer including a stress relaxation silicon carbide film layer and a first surface oxide film cap;
(4) removing the first surface oxide film cap;
(5) forming a second surface oxide film cap;
(6) Carbon ions are implanted into the silicon layer between the stress relaxation silicon carbide film layer and the second surface oxide film cap to form a second carbon-containing layer in which silicon and carbon are mixed. A carbon ion implantation step,
(7) heat-treating the silicon substrate to form the second carbon-containing layer as a crystal-grown silicon carbide film layer;
(8) A step of removing the second oxide film cap formed on the surface of the silicon substrate.   Immediately after the second carbon ion implantation, the carbon atom concentration on the carbon-containing layer side at the interface between the silicon-containing layer and the silicon-containing layer between the silicon oxide layer and the single crystal silicon carbide layer is 15 atom% or more, The method for manufacturing a silicon semiconductor substrate according to claim 1, wherein the ion implantation conditions are adjusted so that the maximum value of the carbon atom concentration in the carbon-containing layer is 55 atom% or less.   Immediately after the second carbon ion implantation, the carbon atom concentration on the carbon containing layer side at the interface between the silicon containing layer and the silicon oxide layer between the silicon oxide layer and the single crystal silicon carbide layer is 25 atom% or more. A method for manufacturing a silicon semiconductor substrate according to claim 2.   The method for producing a silicon semiconductor substrate according to claim 1, wherein the carbon ion implantation is performed in a state where the silicon substrate is heated to a temperature of 400 ° C. or more and 1000 ° C. or less.   The manufacturing method of the silicon semiconductor substrate of any one of Claims 1-4 with which the said silicon substrate was manufactured by the Czochralski method or the float zone method.

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