JP2011114038A - Method of adjusting resistance value of resistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of adjusting a resistance value capable of adjusting a resistance value when stamping individual resistors from a multiple-patterning board. <P>SOLUTION: A metal plate is employed for forming resistive bodies 2, columnar insulation layers 6 are formed on the metal plate, the columnar insulation layer regions correspond to resistor regions, respectively, and resistance value adjusting holes 4 are formed in the resistor regions, respectively, while intervals between the holes 4 are set equal, as shown in Fig.3 (A). When a stamping region 7 of the resistor is located at a lower position relative to the position of the stamping region 7 shown in Fig.3 (B), the resistance value is increased. Therefore, the resistance value of the resistor to be cut out can be adjusted by the adjustment of the cut-out position. Calculation of a first stamping position is performed by measuring a specific resistance value, and next a resistance value of the stamped resistor 1a is measured, as shown in Fig.3 (C). A stamping position of the resistor to be stamped next corresponds to a length at which the resistance value adjusting hole 4b enters a cut-out region 7b as shown in Fig.3 (D), the stamping position can be calculated and stamping is performed at the calculated stamping position. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a resistance value adjusting method for a resistor, and more particularly to a resistance value adjusting method for a resistor using a metal plate as a resistor.

  It is known to use a resistor (shunt resistor) having a very small resistance value of about milliohm for detecting a large current. In detection of a large current using a shunt resistor, a current value can be calculated by measuring a voltage drop at both ends of the shunt resistor when a current is passed through a shunt resistor having a known low resistance value. .

  8A and 8B are diagrams for explaining the outline of the resistor described in Patent Document 1. FIG. 8A is a perspective view, and FIG. 8B is a cross-sectional view, which is used as a shunt resistor. It is. In the figure, 20 is a resistor, 21 is a resistor, 22 is an electrode, and 23 is a solder film. The shunt resistor has a structure in which two rectangular parallelepiped electrodes 22 are joined to a resistor 21 having one rectangular parallelepiped shape as shown in the figure. The thickness of the resistor 21 is about 100 to 1000 μm. Moreover, the thickness of each electrode 22 is about 10-300 micrometers. Further, a solder film 23 of about 2 to 10 μm is formed on the surface of each electrode 22. Examples of the material of the resistor 21 include copper / nickel alloy, nickel / chromium alloy, iron / chromium alloy, manganese / copper / nickel alloy, platinum / palladium / silver alloy, gold / silver alloy, gold / platinum / silver alloy. Various metal alloys and various precious metal alloys are used, and metal alloys and precious metal alloys that meet various characteristics such as specific resistance, temperature coefficient (TCR), and resistance value change determined according to specifications Are appropriately selected and used. The electrode 22 is a thick copper plate having good thermal conductivity, and is joined by clad bonding. For the solder film 23, a molten solder material or a lead-free solder material is used.

  FIG. 9 is an explanatory diagram of the manufacturing process of the resistor 20 of FIG. An alloy of the resistance material 24 and a copper alloy of the electrode material 25 are prepared and processed into predetermined dimensions (step a). Next, in the joining step (step b), the resistance material 24 and the electrode material 25 are clad joined. The interface between the resistance material 24 and the electrode material 25 in the joined body 26 is firmly bonded to the diffusion layer. Next, part of the electrode material 24 is removed from the joined body 26 in the electrode processing step (step c). For example, using a cutting device, the central portion 27 of the electrode material 25 is removed until the resistance material 24 is exposed, and the electrode material is divided into two to form the electrode 22. Next, in the melting solder processing step (step d), the solder film 23 is formed on the surfaces of the electrodes 22 on both sides, and a long body 28 as a plurality of substrates can be manufactured. Next, after the long body 28 is cut into a predetermined length using a laser processing machine, a press processing machine, a wire electric discharge machine, a disk cutting machine, or the like in a cutting process (e process), In the resistance value adjusting step, the resistor 20 is adjusted to have a predetermined resistance value, and the resistor 20 having the predetermined resistance value is obtained. This resistance value adjusting step is performed by removing a part of the side surface portion or the surface portion of the resistor 21 using a sandblasting method or various cutting machines such as a laser processing machine while measuring the resistance value. .

  10A and 10B are diagrams for explaining the outline of the resistor described in Patent Document 2. FIG. 10A is a perspective view, FIG. 10B is a cross-sectional view, and the resistor described in FIG. It is used as a shunt resistor in the same way. In the figure, 30 is a resistor, 31 is a resistor, 32 is an overcoat layer, 33 is an insulating layer, 34 is an electrode, and 35 is a solder layer. This resistor 30 can eliminate the error of the inter-electrode resistance value or can be made very small without performing trimming for adjusting the resistance value, and can make the quality of the resistor very high. .

  The resistor 31 has a rectangular shape in which the thickness of each part is constant, and is made of metal. Examples thereof include a Cu—Mn alloy, a Ni—Cu alloy, and a Ni—Cr alloy. Those having a resistivity corresponding to the target resistance value are appropriately selected. The overcoat layer 32 is provided so as to cover the entire surface of the resistor 31, and has electrical insulation. The overcoat layer 2 is formed by thick film printing, and is, for example, an epoxy resin-based resin film. The insulating layer 33 is provided in an intermediate portion of the back surface of the resistor 31 in the width direction of the resistor 31 (left and right width direction in the drawing). The insulating layer 33 is made of the same material as the overcoat layer 32 and is a resin film formed by thick film printing in the same manner as the overcoat layer 2. The pair of electrodes 34 is provided on the back surface of the resistor 31 and is separated with the insulating layer 33 interposed therebetween. The pair of electrodes 3 is formed, for example, by applying copper plating to the resistor 31. Each electrode 34 is in contact with the end face so that no gap is formed between the end face in the width direction of the insulating layer 33. Thus, the distance between the pair of electrodes 34 is defined by the insulating layer 33 and has the same dimension as the width s1 of the insulating layer 33. On the lower surface of each electrode 34, a solder layer 35 is laminated to improve solderability.

  For example, the thickness of each part is about 20 μm for the overcoat layer 32 and the insulating layer 33, about 30 μm for each electrode 34, and about 5 μm for each solder layer 35. The resistor 31 has a thickness of about 0.1 mm to 1 mm and vertical and horizontal dimensions of about 2 mm to 7 mm. The size of the resistor 31 varies depending on the target resistance value. Be changed. The resistor 30 is configured as a low resistance of about 0.5 mΩ to 50 mΩ. The resistance between the electrodes of the resistor 30 is determined by the resistivity of the resistor 31, the distance between the electrodes 34, and the thickness of the resistor 31.

  FIG. 11 is an explanatory diagram of a method for manufacturing the resistor 30 of FIG. First, as shown to (a), the metal plate 31a used as the material of the resistor 31 is prepared. The plate 31a has a vertical and horizontal size that allows a plurality of resistors 31 to be obtained, and has a uniform thickness throughout. As shown in (b), an overcoat layer 32a is formed on the entire upward surface of the plate 31a. The overcoat layer 32a is formed by thick-film printing a resin as a material of the overcoat layer 32a in a solid coating shape. Next, as shown in FIG. 3C, after the plate 31a is turned upside down, a plurality of insulating layers 33a are formed in a stripe shape on the surface of the plate 31a facing upward. The plurality of insulating layers 33a are formed by thick film printing using the same resin and apparatus used for forming the overcoat layer 2. According to the thick film printing method, the width of each insulating layer 33a can be accurately finished to a predetermined dimension. In the region between the plurality of formed insulating layers 33a, a conductive layer 34a and a solder layer 35a are sequentially formed as shown in FIG. The conductive layer 34a is formed by plating copper, for example. According to this plating process, it is possible to uniformly form the conductive layer 34a in the region between the adjacent insulating layers 33a without generating a gap between the conductive layer 34a and the insulating layer 33a. The solder layer 35a is also formed by a plating process. Thereafter, as shown in (e), punching (blanking) is repeatedly performed on the plate 31a, and the plate 31a is used as a substrate to be divided into a plurality of resistors 30. When such a punching operation is repeated, one punching die (not shown) is repeatedly used.

  In the punching operation, as shown in FIG. 12, each of two adjacent strip-like conductive layers 34a and solder layers 35a, and a portion of one insulating layer 33a sandwiched between them, They are punched out together with the plate 31a so as to remain on one side of the punched resistor (the portion where the cross-hatching in FIG. 12 is inserted is the insulating layer 33a). As a result of the punching, a part of each of the two conductive layers 34 a becomes a pair of electrodes 34 of the resistor 30 shown in FIG. 10, and a part of the insulating layer 33 a becomes an insulating layer 33. In this way, a plurality of resistors 30 can be appropriately taken from the plate 31a. As shown by broken lines in FIG. 12, the punching of the plate 31a is advanced so that a plurality of punched regions are arranged in a matrix at a minute interval. Therefore, if punching means is employed as means for dividing the plate 31a into the plurality of resistors 31, the vertical and horizontal dimensions of the resistor 31 can be finished to accurate dimensions with almost no error.

  In this resistor 30, the vertical and horizontal dimensions of the resistor 31 can be finished to a desired dimension with high accuracy by punching. The thickness of the resistor 1 can be accurately finished from the stage of the plate 31a. In addition, the dimension s1 (FIG. 10) between the pair of electrodes 34 matches the width of the insulating layer 33, and the insulating layer 33 can be formed with a considerably high dimensional accuracy by thick film printing. The dimension s1 can also be finished to a desired dimension with high accuracy. As described above, if the size of the resistor 31 and the dimension s1 between the pair of electrodes 34 are finished with high accuracy, there is no error in the resistance value between the electrodes of the resistor 30, or even if there is an error. Becomes smaller. Therefore, in this resistor 30, unlike the prior art, it is not necessary to perform trimming for adjusting the resistance value thereafter, and the cost of the resistor 30 can be reduced by the amount that the work can be omitted. Is.

  In the above-described conventional technology, in the resistor manufacturing method described in Patent Document 1, a plurality of substrates are cut into a predetermined length in a cutting process and divided into individual resistors. The resistance value is trimmed by the value adjustment process. In the case of a resistor in which a resistor part is formed using a conductive paste, when forming a plurality of substrates, the resistor part and the electrode part are formed into independent patterns for each resistor region. Trimming can be performed in the state of a plurality of substrates before being divided into individual resistors, so that the trimming operation is easy, but in the case of a resistor using a metal plate as a resistor, the electrode portions are individually Even if it is an independent pattern for each resistor area, it is impossible to perform trimming in the state of multiple substrates because the resistor part cannot be made independent, and trimming after cutting into individual resistors This increases the cost of the resistor. The manufacturing method of the resistor described in Patent Document 2 is performed without performing trimming for adjusting the resistance value by forming the insulating layer with high dimensional accuracy to increase the width of the resistor region. It is possible to reduce the cost of the resistor without requiring a resistance value adjusting step. However, if the thickness of the multi-piece resistor is non-uniform, the variation in thickness becomes an error in the resistance value as it is, so that there is a problem that the thickness must be made uniform with high accuracy throughout. is there.

JP 2002-57009 A JP 2004-63503 A

  The present invention can adjust the resistance value when punching individual resistors from a plurality of substrates, and can reduce the cost of adjusting the resistance value, and the thickness of the resistor is not uniform. It is an object of the present invention to provide a resistance value adjusting method capable of reducing the error of the resistance value.

  The present invention is a resistance value adjusting method for adjusting a resistance value when an individual resistor is cut out by punching out a plurality of substrates using a metal plate as a resistor. The body region extends in a line in one direction, and a resistor / electrode overlapping region in which a resistor and an electrode are superposed on both sides of the resistor region in a direction orthogonal to the one direction is the same as the one direction. A resistance value adjusting hole forming step of forming a small hole as a resistance value adjusting hole in the resistor region, the resistor region, and the resistor on both sides thereof. A punching process in which one resistor is punched so that the electrode overlapping region is aligned in a direction orthogonal to the one direction, and the adjustment of the punching position in the punching process is performed by punching the resistor before punching By measuring the resistance of the Based on the obtained resistance value, it is characterized in that performed by adjusting the position of entry of the resistance value adjustment holes entering the punching area.

  According to the present invention, when one resistor is punched from a plurality of substrates, the resistance value can be adjusted by adjusting the punching position. Therefore, it is necessary to perform trimming for adjusting the resistance value after punching. The cost can be reduced. The punching position is adjusted based on the resistance value of the resistor punched one time before. That is, since the position of punching each resistor is determined by the resistance value of the adjacent cutout region, even if there is a difference in the thickness of the resistor, the difference in thickness from the adjacent cutout region is small, and the resistance The value error is small. In addition, since the resistance value of the resistor punched one time before depends on the electrode resistance, the resistance value between the resistor and the electrode is also taken into consideration. Obtainable.

FIG. 1 is an explanatory view of one embodiment of a resistor manufactured by using the resistance value adjusting method of the present invention, FIG. 1 (A) is a perspective view, and FIG. 1 (B) is a sectional view. It is explanatory drawing for demonstrating the process until it produces a multi-piece substrate. It is explanatory drawing of one Example of the resistance value adjustment method of this invention. It is explanatory drawing of the formation method of an adjustment hole. It is explanatory drawing of the process of punching out a resistor. It is explanatory drawing of the other Example of the formation process of a resistance value adjustment hole, and the cutting-out process of a resistor. It is a distribution map of an example of the result of having measured distribution of the specific resistance value of a resistance board. It is for demonstrating the outline of the resistor of a prior art example, (A) is a perspective view, (B) is sectional drawing. It is explanatory drawing of the manufacturing process of the resistor 20 of FIG. It is for demonstrating the outline of the resistor of another prior art example, (A) is a perspective view, (B) is sectional drawing. It is explanatory drawing of the manufacturing method of the resistor of FIG. It is explanatory drawing of the punching operation | work of FIG.

  An embodiment of the resistance value adjusting method of the present invention will be described with reference to FIGS. FIG. 1 is an explanatory view of an embodiment of a resistor manufactured by using the resistance value adjusting method of the present invention, FIG. 2 is an explanatory view for explaining steps until a multi-chip substrate is manufactured, and FIG. FIG. 4 is an explanatory diagram of an embodiment of a resistance value adjusting method, FIG. 4 is an explanatory diagram of a method of forming an adjustment hole, and FIG. 5 is an explanatory diagram of a process of punching out a resistor. In the figure, 1 is a resistor, 2 is a resistor, 3 is an electrode, 3a is a Cu layer, 3b is a Ni layer, 3c is a Sn layer, 4 is a resistance adjustment hole, 5 and 6 are insulating layers, and 7 is a cutout region. 8 is a punch, 9 is a guide, 10 is a die, 11 is a punch, 12 is a guide, 13 is a die, 14 is a punch hole, 15 is a guide, 16 is a resistor punch, 17 is a resistance adjustment hole punch It is a punch.

  1A is a perspective view, and FIG. 1B is a cross-sectional view. The resistor 1 is provided with an insulating layer 5 on one surface (upper surface in the drawing) of the resistor 2 and a pair of electrodes 2 provided on the other surface (lower surface in the drawing) at a predetermined interval. An insulating layer 6 is provided between the electrodes 2 and 2 on the other surface of the resistor 2. As basic components of the resistor 1, the resistor 2, the electrode 3, and the resistance value adjusting hole 4 are indispensable.

  The material of the resistor 2 is the same as the material used for the resistor described in FIGS. 8 to 11, and a material having a resistivity corresponding to the size of the resistor to be manufactured and the target resistance value is appropriately selected. Is done. The material of the electrode 2 may be the same as that used in the resistor described in FIGS. 8 to 11, but in this embodiment, the three layers of the Cu layer 3a, the Ni layer 3b, and the Sn layer 3c are arranged in this order. It was formed by plating. The insulating layers 5 and 6 are, for example, resin films formed by thick film printing, for example, epoxy resin-based resin films.

  2A to 2E, each figure shows a plan view at the top and a cross-sectional view at the bottom. FIG. 2A shows the resistor 2. FIG. 2B shows a process for forming an insulating layer. An insulating layer 6 is patterned on one surface (upper surface in the drawing) of the resistor 1 in accordance with the position where the resistor is formed, and an insulating layer 5 is formed on the entire surface on the other surface (lower surface in the drawing). . The pattern of the insulating layer 2 has an intermittent shape in a line in one direction, and one of the island-shaped insulating layers corresponds to one resistor. That is, one island-like insulating layer 6 is provided for each resistor region. A portion of the resistor 1 where the island-like insulating layers 6 are arranged in a row is a resistor region that forms a resistor portion of the resistor. 2C to 2E show a plating process. In FIG. 2C, Cu is applied by electrolytic plating. The Cu plating is formed on the entire surface excluding the portion where the island-like insulating layer 6 is provided on the one surface. FIG. 2D shows a Ni layer plating process, and FIG. 2E shows a Sn layer plating process. A plurality of substrates are manufactured by these electrode forming processes. The portion where the electrode is superposed on the resistor formed so as to sandwich the resistor region from both sides of the resistor portion is the resistor / electrode overlapping region. A resistor region is formed by the resistor region and the resistor / electrode overlapping regions on both sides thereof.

  In one embodiment of the resistance value adjusting method shown in FIG. 3, first, a resistance value adjusting hole is formed. As shown in FIG. 3A, the resistance adjustment hole 4 is a portion of the insulating layer 6 that is a resistor region of a plurality of substrates, and is located within a range that intersects the periphery of the cutout region. As shown in FIG. The resistance adjustment hole 4 is drilled so as to penetrate the insulating layer 6, the resistor 2, and the insulating layer 5. The perforation is performed by punching, but may be performed by other methods. The planar shape of the resistance adjustment hole 4 is circular in this embodiment, but may be an appropriate shape such as an ellipse, a rectangle, or a rectangle with rounded corners. Any shape may be used as long as the resistor is cut in the row direction of the insulating layers 6.

  FIG. 3B is an explanatory diagram for explaining the relationship between the resistance value adjusting hole 4 and the cutout region 7. The cut-out region 7 is composed of a part of the resistor region and a part of the resistor / electrode overlapping region on both sides thereof. In this explanatory diagram, the cutout region 7 is illustrated at a position where the periphery passes through the center of the circular resistance value adjusting hole 4. If the cutout region 7 is a position above the position shown in the drawing, that is, a position where the penetration length of the resistance adjustment hole 4 entering the cutout region 7 is small, the resistance value of the cut out resistor is small. On the contrary, if the cutout region 7 is a position below the position shown in the drawing, that is, a position where the penetration length of the resistance value adjusting hole 4 entering the cutout region 7 is large, the resistance of the cut out resistor The value gets bigger. Therefore, the resistance value of the resistor to be cut out can be adjusted by adjusting the cutting position. The adjustment method performed in this way is a feature of the present invention.

  FIG. 3C is a flowchart for explaining an embodiment of the resistance value adjusting method, and FIG. 3D is an explanatory diagram thereof. A resistor region is cut out by punching from a plurality of substrates shown in FIG. The position of the puncher is fixed, the plurality of substrates are moved, and the resistor is cut out by punching out at the set position. The initial punching position is calculated based on the specific resistance of the multiple substrates. The specific resistance value may be a measured value using specification data or by cutting out a part of the substrate. In this example, measurement was performed (S1). Based on the measured specific resistance value, the resistance value between the electrodes in the cutout region is calculated and stored, and the punching position is calculated so as to be the resistance value (predetermined resistance value) to be manufactured. As described above, since the resistance value corresponds to the length that the resistance value adjustment hole that enters the cut-out region enters, the punching position can be calculated. The punching position is adjusted by moving a plurality of substrates to the punching position calculated according to the calculated value (S2), and punching is performed (S3). The resistance value of the resistor 1a is measured by punching and stored. The measured resistance value is the resistance value between the electrodes. Using the measurement result, it is determined whether or not the measurement value is within a predetermined error range, and defect selection is performed (S4). Next, the punching position of the resistor to be punched next is calculated based on the measured resistance value. Since the punching position corresponds to the length of the resistance value adjusting hole 4b entering the cutout region 7b (FIG. 3D), the punching position can be calculated. The punching position is adjusted by moving a plurality of substrates to the punching position calculated according to the calculated value (S5), and punching is performed (S3). Next, the process proceeds to S4, where the resistance value of the punched resistor is measured and stored, and defect selection is performed. The process proceeds to S5, and the next punching position is adjusted. Thereafter, S3 to S5 are looped, and similarly, punching and resistance value adjustment are performed, and resistors are cut out from one column. The adjustment of the cutout position by moving a plurality of substrates can be performed using an appropriate method such as a method of detecting a moving distance by an encoder or a method of image analysis.

  As shown in FIG. 3A, in the case where a plurality of rows are formed on a plurality of substrates, the resistance value of the resistor is processed for the next row in the flow described with reference to FIG. In conjunction with the adjustment, the cutout is performed. Although the insulating layer 6 is formed in an island shape in a plurality of substrates, the insulating layer 6 may be continuous without being in an island shape. When the insulating layers 6 are formed in a continuous row, the continuous row region becomes a resistor region. The electrodes are also formed in a continuous row, and the region where the electrodes are formed becomes a resistor / electrode polymerization region. In addition, although an electrode is good also as an island shape, the area | region in which the island-shaped electrode was formed in this case is a resistor and electrode superposition | polymerization area | region.

  FIG. 4 is an explanatory diagram in the case of punching out the resistance value adjusting hole with a punch. FIG. 4A shows a state before punching. A plurality of aligned substrates are sandwiched between the guide 9 and the die 10. Although the orientation of the front and back sides of the plurality of substrates may be any, it is preferable that the electrodes 3 be placed so that the electrode 3 side is the punch side. The reason will be described later. FIG. 4B shows a punched state. A small hole is punched by pressing down the punch 8. FIG. 4C shows a state in which the punch is released. As shown in FIG. 4D, the resistance adjustment hole 4 is formed by punching. The resistance value adjusting holes may be punched at the same time depending on the die, but the die becomes expensive.

  FIG. 5 is an explanatory diagram of a punch for punching a resistor. FIG. 5A shows a planar shape in the vicinity of one insulating layer 6 as viewed from the lower side of FIG. FIG. 5B is a state before punching, and is a cross-sectional view taken along the line BB of FIG. A plurality of aligned substrates are sandwiched between the guide 12 and the die 13. The orientation of the front and back sides of the plurality of substrates may be either, but it is preferable that the front and back sides are reversed when the resistance value adjusting hole is punched out. If both the resistance adjustment hole and the resistor are punched from the same direction, the punched resistor may be bent. In addition, when punching the resistance adjustment hole from the electrode 3 side in the punching direction of the resistor, burrs may be generated at the edge of the electrode. In this case, the mounting property on the substrate is lowered. Therefore, as shown in FIG. 5 (B), the insulating layer 5 side should be placed on the punch side, and in order to do so, the resistance value adjustment hole is punched as shown in FIG. 4 (A). As described above, the electrode 3 was placed on the punch side. FIG. 5C shows a punched state. When the punch 11 is pushed down, the resistor is punched out. FIG. 5D is a plan view of the vicinity of the punched hole 14 after being punched, and FIG. 5E is a perspective view of the resistor 1 cut out by punching. By adjusting the punching position, FIG. The resistance value has been adjusted.

  FIG. 6 is a view for explaining another embodiment of the resistance value adjusting hole forming step and the resistor cutting out step. FIG. 6 (A) is an explanatory view of a punch, and FIGS. 6 (B) and (C). These are explanatory drawings of the punching process using the punch of FIG. 6 (A). In the embodiment described above, the punching position is formed with respect to the opened resistance value adjusting holes after forming the resistance value adjusting holes for at least a plurality of the cutting regions or all the cutting regions for the plurality of cut substrates. The resistor was punched out after adjusting. In contrast, in this embodiment, when one resistor is punched, the resistance value adjusting hole for punching the next resistor is punched.

  With respect to the punch and guide shown in FIG. 6A, the guide 15 is provided with holes for the resistor punch 16 and the resistance adjustment hole punch 17 for punching the resistor. A punch 16 and a resistance value adjusting hole punching punch 17 are inserted. At the time of punching, the resistor punch 16 and the resistance value adjusting hole punch 17 are operated simultaneously. This “simultaneous” does not mean that they are completely simultaneous, and there may be a time shift, and the positioning of the guide 15 and the plurality of substrates is performed, and the positional relationship between the two is determined. In the fixed state, both the resistor punching punch 16 and the resistance value adjusting hole punching punch 17 need only be operated.

  FIG. 6B shows the first punching process for one row. Simultaneously with this punching, the resistance adjustment hole 4a for the next punching is punched. The punched resistor 1a does not have a resistance value adjusting hole, but the resistance value is measured and stored, and for the next punching so that the resistance value to be manufactured (predetermined resistance value) is obtained. The punching position is calculated. In FIG. 6C, the resistor 1b is punched by the calculated punching position 7b (shown by a broken line), and at the same time, the resistance value adjusting hole 4b for the next punching is punched. Since the resistance adjustment hole for the next punching is formed simultaneously with the punching of one resistor, the manufacturing process is simplified. The punching position of the next resistor is calculated based on the measurement result of the resistance value of the resistor 1b punched immediately before. The same applies thereafter.

  In these embodiments described above, the punching position is adjusted based on the resistance value of the resistor punched immediately before the resistor to be punched. However, if the resistance value of the already punched resistor is measured and stored together with the punching position data, the resistance value can be adjusted by adjusting the punching position based on the stored resistance value. The “resistor already punched” is not limited to the resistor punched immediately before. A resistor that has already been punched in the vicinity of the punching position of the resistor to be punched may be used. If the substrate is a multi-piece substrate with a small distribution of specific resistance values and small changes in electrode resistance, it may be located at a distance of about 10 pieces. In this case, the resistance value may be measured and stored every 10 pieces. Efficiency is improved. When higher accuracy is desired, the “already punched resistor” is preferably a resistor punched at a position adjacent to the position to be punched.

  FIG. 7 is an example of the result of measuring the distribution of the specific resistance value of the resistance plate. A resistance plate cut to a length of 150 mm from a roll having a width of 150 mm was partitioned into 10 mm × 10 mm, and the specific resistance value of a chip punched from the central portion was measured. In the figure, the ratio of the deviation with respect to the average value of all the measured values is calculated, and the value is shown as a 10 mm × 10 mm section. The horizontal direction in the figure is the rolling direction. From this measurement result, it can be seen that the range of resistance variation is smaller in the direction orthogonal to the rolling direction than in the rolling direction. Therefore, the above-mentioned one direction (the row direction of the island-like insulating layers 6), that is, the direction of the row resistor region is the direction perpendicular to the rolling direction of the resistance plate. Is small.

  As described above, the present invention is a method for adjusting the resistance value of a resistor in a stage before punching of the resistor when punching out each resistor from a plurality of substrates by punching. A resistance value adjusting hole is formed. As a previous step, there is a method of forming all or a part of a plurality of resistance value adjustment holes in one row of cutout regions, and then cutting out individual resistors sequentially. In this method, the formation of the resistance adjustment hole and the cutting of the resistor are performed separately. In addition, as described with reference to FIG. 6, a method of punching a resistance adjustment hole for cutting out the next resistor may be used at the same time when cutting out one resistor by punching. Therefore, the multiple substrate according to the present invention extends so that the resistor regions are arranged in one direction, and is orthogonal to the one direction of the resistor regions. It is sufficient that the resistor / electrode overlapping region in which the resistor and the electrode are superimposed on both sides in the direction to be extended is arranged in a row in the same direction as the one direction.

  Therefore, the multiple substrate according to the present invention is not limited to the multiple substrate described with reference to FIGS. The substrate described in FIG. 8 and FIG. 9 is a multiple substrate in which a resistor region is formed of a strip-like insulator and a resistor / electrode overlapping region is formed on both sides by a conductor layer. Further, in the substrate described with reference to FIGS. 10 to 12, a resistor region is formed by removing a part of the electrode material from the clad bonded assembly made of the resistor material and the electrode material. A body part is a plurality of substrates in which a resistor / electrode polymerization region is formed. Therefore, it is obvious that the present invention can be applied to the multiple substrate described with reference to FIGS. 8 and 9 and the multiple substrate described with reference to FIGS.

  In the embodiment described above, the order of punching the individual resistors from the plurality of substrates in which the resistor regions are formed in a plurality of rows is the row direction. However, the resistors are sequentially punched in the direction perpendicular to the row direction. Also good.

  DESCRIPTION OF SYMBOLS 1 ... Resistor, 2 ... Resistor, 3 ... Electrode, 3a ... Cu layer, 3b ... Ni layer, 3c ... Sn layer, 4 ... Resistance value adjustment hole, 5, 6 ... Insulating layer, 7 ... Cut-out area | region, 8 ... Punch, 9 ... Guide, 10 ... Die, 11 ... Punch, 12 ... Guide, 13 ... Die, 14 ... Punching hole, 15 ... Guide, 16 ... Punch for resistor punching, 17 ... Punch for punching resistance adjustment hole

Claims (8)

A resistance value adjusting method for adjusting a resistance value when punching out individual resistors from a plurality of substrates using a metal plate as a resistor,
The plurality of substrates are formed such that the resistor regions extend in a row in one direction, and resistors and electrodes are superposed on both sides of the resistor region in a direction perpendicular to the one direction. The electrode overlapping region is a substrate extended in a row in the same direction as the one direction,
A resistance value adjusting hole forming step for forming a small hole as a resistance value adjusting hole in the resistor region;
A punching step of punching out one resistor so that the resistor region and the resistor / electrode overlap region on both sides thereof are aligned in a direction perpendicular to the one direction;
The punching position adjustment in the punching step is based on the resistance value obtained by measuring the resistance value of the resistor punched before the punching of the resistor, and the entry position of the resistance adjustment hole that enters the punching region A method for adjusting the resistance value of a resistor, wherein the resistance value is adjusted by adjusting the resistance. The resistance value adjusting hole forming step is a resistance value adjusting hole forming step of forming a plurality at a predetermined interval in the resistor region of the plurality of substrates.
The resistance value adjusting method for a resistor according to claim 1, wherein the punching step is performed after the resistance value adjusting hole forming step. The resistance value adjusting hole forming step is a resistance value adjusting hole forming step performed by punching,
The resistance value adjusting method for a resistor according to claim 2, wherein the front and back punching directions with respect to the substrate are different depending on the punching in the resistance value adjusting hole forming step and the punching in the punching step. .   2. The resistance value adjusting method for a resistor according to claim 1, wherein in the punching step for punching one resistor, a subsequent punching step for a resistance value adjusting hole of the next resistor is performed.   The resistor according to any one of claims 1 to 4, wherein the resistor punched before the punching of the resistor is a resistor punched immediately before the punching of the resistor. Resistance value adjustment method.   The resistor punched before the punching of the resistor is a resistor punched in the vicinity of a position where the resistor is to be punched. The method for adjusting the resistance value of the resistor according to item.   5. The resistor punched before the punching of the resistor is a resistor punched at a position adjacent to a position where the resistor is to be punched. The resistance value adjusting method of the resistor according to claim 1.   The resistance value adjusting method according to claim 1, wherein the one direction is a direction orthogonal to a rolling direction of the metal plate.

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