JP2011114034A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device which miniaturizes each memory cell while suppressing degradation of a characteristic of the semiconductor memory device. <P>SOLUTION: The semiconductor memory device includes: a substrate 101; gate insulating films 111 formed on the substrate and each functioning as an FN (Fowler-Nordheim) tunneling film; first floating gates 112 formed on the gate insulating films; first inter-gate insulating films 113 formed on the first floating gates and each functioning as an FN tunneling film; second floating gates 114 formed on the first inter-gate insulating films; a second inter-gate insulating film 115 formed on the second floating gates and functioning as a charge blocking film; and a control gate 116 formed on the second inter-gate insulating film. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device.

  In a semiconductor memory device such as a NAND flash memory, miniaturization of memory cells has been an issue due to demands for large capacity and low bit unit price.

  However, when the memory cell is miniaturized, the following characteristic deterioration cannot be avoided. First, in miniaturization of memory cells, an increase in coupling between adjacent cells becomes a problem. Second, in miniaturization of memory cells, a variation in coupling ratio due to drop of the control gate becomes a problem. Therefore, miniaturization of the memory cell causes a decrease in performance of the NAND flash memory.

JP 2009-141354 A JP 2007-250974 A

  An object of the present invention is to provide a semiconductor memory device capable of miniaturizing a memory cell while suppressing a decrease in performance of the semiconductor memory device.

  One embodiment of the present invention includes, for example, a substrate, a gate insulating film formed on the substrate and functioning as an FN (Fowler-Nordheim) tunnel film, and a first floating gate formed on the gate insulating film. A first inter-gate insulating film formed on the first floating gate and functioning as an FN tunnel film, a second floating gate formed on the first inter-gate insulating film, and the second A semiconductor memory device comprising: a second inter-gate insulating film that functions as a charge blocking film, and a control gate formed on the second inter-gate insulating film. It is.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the semiconductor memory device which can miniaturize a memory cell, suppressing the fall of the performance of a semiconductor memory device.

1 is a plan view schematically showing a configuration of a semiconductor memory device according to a first embodiment. 1 is a side sectional view showing a configuration of a semiconductor memory device according to a first embodiment. It is a conceptual diagram for demonstrating a direct tunnel film | membrane and a FN tunnel film | membrane. It is the graph which showed the actual value of the direct tunnel current and the FN tunnel current. 6 is a timing chart showing a flow of a read operation. FIG. 6 is a side cross-sectional view (1/2) illustrating the method for manufacturing the semiconductor memory device of the first embodiment. FIG. 4 is a side cross-sectional view (2/2) illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. It is a side sectional view showing the configuration of the semiconductor memory device of the second embodiment. It is a sectional side view (1/2) which shows the manufacturing method of the semiconductor memory device of 2nd Embodiment. FIG. 10 is a side cross-sectional view (2/2) showing the method for manufacturing the semiconductor memory device of the second embodiment. It is a side sectional view showing the composition of the semiconductor memory device of the modification of a 2nd embodiment. It is a side sectional view showing the composition of the semiconductor memory device of a 3rd embodiment. It is a sectional side view which shows the structure of the semiconductor memory device of a comparative example. It is a conceptual diagram for demonstrating the state of the cell transistor before writing. It is a conceptual diagram for demonstrating the state of the cell transistor at the time of writing. It is a conceptual diagram for demonstrating the state of the cell transistor at the time of retention. It is a conceptual diagram for demonstrating the effect of 3rd Embodiment. It is a sectional side view which shows the structure of the semiconductor memory device of the modification of 1st to 3rd embodiment. It is a sectional side view which shows the structure of the semiconductor memory device of the modification of 1st to 3rd embodiment.

  Patent Document 1 describes an example of a nonvolatile memory device having a floating gate including two layers. In this device, an insulating film is formed between these layers, and the thickness of the insulating film is such that direct tunneling is possible. Therefore, there is a problem that it is difficult to keep charges in the upper layer constituting the floating gate.

  Patent Document 2 describes an example of a nonvolatile semiconductor memory device having a plurality of floating regions. In this apparatus, the film type and film thickness of the insulating film between the semiconductor substrate and the floating region, and the film type and film thickness of the insulating film between the floating region and the gate electrode (control gate) are the same and similar. It has become. Therefore, when data is written into the memory cell, the same voltage is applied to these insulating films, and there is a problem that charges injected from the substrate to the floating region pass through to the gate electrode.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a plan view schematically showing the configuration of the semiconductor memory device of the first embodiment. The semiconductor memory device of FIG. 1 is a NAND flash memory.

In FIG. 1, the memory cell array region is indicated by R _C and the select transistor region is indicated by R _S. FIG. 1 further shows a plurality of bit lines BL extending in a first direction parallel to the surface of the substrate, a plurality of word lines WL and a plurality of selection lines S extending in a second direction parallel to the surface of the substrate. Has been. The first and second directions are indicated by arrows X and Y, respectively, and are orthogonal to each other.

In the memory cell array region R _C, at each intersection P _C between the bit line BL and a word line WL, a cell transistor (memory cell) is provided. In the selection transistor region R _S , a selection transistor is provided at each intersection P _S between the bit line BL and the selection line S. The cell transistor is electrically connected to the bit line BL and the word line WL, and the selection transistor is electrically connected to the bit line BL and the selection line S.

FIG. 1 further shows an element isolation region R ₁ and an active region (element region) R ₂ . Both the element isolation region R ₁ and the active region R ₂ extend in the X direction, and are alternately provided in the substrate along the Y direction. Cell transistor and select transistor are both formed on the active region R _2.

  FIG. 2 is a side sectional view showing the configuration of the semiconductor memory device of the first embodiment.

2A is a cross-sectional view taken along the I cross section (AA (Active Area) cross section) shown in FIG. 1, and FIG. 2B is a cross-sectional view taken along the II cross section (GC (Gate Conductor) cross section) shown in FIG. It has become. 2A and 2B are cross-sectional views in the memory cell array region R _C , and the cell transistor is indicated by C. FIG.

  Each cell transistor C is formed on a substrate 101. A tunnel insulating film 111, a lower floating gate 112, an IFD (Inter Floating-Gate Dielectric) film 113, and an upper floating gate are sequentially formed on the substrate 101. 114, an IPD (Inter Poly-Si Dielectric) film 115, and a control gate 116.

The substrate 101 is a semiconductor substrate such as a silicon substrate, for example. As shown in FIG. 2A, an element isolation insulating film 121 is formed in the vicinity of the surface of the substrate 101, thereby forming an element isolation region R ₁ and an active region R ₂ in the substrate 101. . In FIG. 2B, an interlayer insulating film 122 formed on the substrate 101 and covering the cell transistor C is formed so as to sandwich the cell transistor C in the substrate 101. The cell transistors C are electrically connected in series. A source / drain diffusion layer 131 to be connected is shown. The element isolation insulating film 121 and the interlayer insulating film 122 are, for example, silicon oxide films.

The tunnel insulating film 111 is formed on the substrate 101 (on the active region R ₂ ) and corresponds to an example of the gate insulating film of the present invention. The tunnel insulating film 111 is, for example, a silicon oxide film formed by thermal oxidation. The tunnel insulating film 111 is appropriately referred to as a _TOX film.

  The tunnel insulating film 111 of this embodiment functions as an FN (Fowler-Nordheim) tunnel film. The FN tunnel film is an insulating film having a thickness in which charge transmission by FN tunneling is dominant. The thickness of the tunnel insulating film 111 is, for example, 3 nm or more, preferably 3 to 5 nm in terms of EOT (Equivalent Oxide Thickness), that is, in terms of silicon oxide film thickness. Details of the FN tunnel film will be described later.

The lower floating gate 112 is formed on the tunnel insulating film 111 and corresponds to an example of the first floating gate of the present invention. The lower floating gate 112 functions as a charge storage film for storing charges. The lower floating gate 112 is, for example, a polysilicon layer. The lower floating gate 112 is appropriately expressed as FG ₁ .

  The IFD film 113 is an insulating film formed on the lower floating gate 112 and corresponds to an example of the first inter-gate insulating film of the present invention. The IFD film 113 is, for example, a silicon oxide film formed by thermal oxidation.

  The IFD film 113 of this embodiment functions as an FN tunnel film, like the tunnel insulating film 111. The thickness of the IFD film 113 is, for example, 3 nm or more, preferably 3 to 5 nm in terms of EOT. Although it is desirable that the thickness of the tunnel insulating film 111 and the thickness of the IFD film 113 are approximately the same in terms of the effective film thickness in terms of EOT, the physical film thickness may not be approximately the same.

The upper floating gate 114 is formed on the IFD film 113 and corresponds to an example of the second floating gate of the present invention. Similar to the lower floating gate 112, the upper floating gate 114 functions as a charge storage film for storing charges. The upper floating gate 114 is a polysilicon layer, for example. The upper floating gate 114 is appropriately expressed as FG ₂ .

  The IPD film 115 is an insulating film formed on the upper floating gate 114, and corresponds to an example of the second inter-gate insulating film of the present invention. The IPD film 115 is, for example, an ONO multilayer film composed of a lower silicon oxide film, a silicon nitride film, and an upper silicon oxide film. The IPD film 115 functions as a charge blocking film that blocks charges injected from the lower floating gate 112 to the upper floating gate 114 from passing to the control gate 116. The thickness of the IPD film 115 of this embodiment is an effective film thickness in terms of EOT, and is larger than the thickness of the tunnel insulating film 111 and the thickness of the IFD film 113.

  The control gate 116 is formed on the IPD film 115 and corresponds to an example of the control gate of the present invention. The control gate 116 functions as a control electrode for controlling the potential of the cell transistor C. The control gate 116 is, for example, a polysilicon layer. The control gate 116 is appropriately expressed as CG.

Note that each of the tunnel insulating film 111, the IFD film 113, and the IPD film 115 may be a single-layer film including only one insulating film or a stacked film including two or more insulating films. Examples of single-layer film, include SiO ₂ film, as an example of a laminated films include the two-layer film including a SiO ₂ film and the high-k insulating film (e.g. _{the Si} 3 _{N 4} film).

  Each cell transistor C includes two layers of floating gates 112 and 114 in this embodiment, but may include three or more layers of floating gates. When each cell transistor C includes a floating gate of N layers (N is an integer of 2 or more), each cell transistor C further includes an N-1 layer IFD film, and the floating gates and the IFD films are alternately stacked. .

  Here, the cross-sectional shapes of the IPD film 115 and the control gate 116 will be described.

As shown in FIG. 2A, the tunnel insulating film 111, the lower floating gate 112, the IFD film 113, and the upper floating gate 114 are divided for each cell transistor C. In FIG. 2A, the tunnel insulating film 111, the lower floating gate 112, the IFD film 113, and the upper floating gate 114 are stacked on the active region R ₂ and sandwiched between the element isolation insulating films 121. ing.

In contrast, the IPD film 115 and the control gate 116 are formed across the cell transistors C adjacent in the Y direction (direction parallel to the word line WL). In FIG. 2A, the height of the upper surface S ₁ of the element isolation insulating film 121 is equal to the height of the upper surface S ₂ of the upper floating gate 114. As a result, the lower surface of the IPD film 115 and the lower surface of the control gate 116 are flat, and the height of the lower surface σ ₁ of the control gate 116 between the cell transistors C is equal to the lower surface σ of the control gate 116 on the cell transistor C. It is equal to the height of ₂ .

  Next, the direct tunnel film and the FN tunnel film will be described.

  FIG. 3 is a conceptual diagram for explaining the direct tunnel film and the FN tunnel film. The horizontal direction in FIG. 3 represents the thickness direction of the insulating film, and the vertical direction in FIG. 3 represents the height direction of the potential inside and outside the insulating film.

  FIG. 3A shows a thin insulating film. The insulating film illustrated in FIG. 3A directly corresponds to a tunnel film. The direct tunnel film is an insulating film having a thickness in which charge transmission by direct tunneling is dominant. As indicated by an arrow A, the charges located in the vicinity of the direct tunnel film cause direct tunneling with a certain probability and directly pass through the tunnel film.

  On the other hand, FIG. 3B shows a thick insulating film. The insulating film illustrated in FIG. 3B corresponds to an FN tunnel film. As described above, the FN tunnel film is an insulating film having a thickness in which charge transmission by FN tunneling is dominant. There is a low probability that charges located in the vicinity of the FN tunnel film pass through the FN tunnel film by direct tunneling. However, when an electric field is applied to the FN tunnel film, the potential barrier of the FN tunnel film is inclined and the barrier becomes thin. As a result, the charges located near the FN tunnel film cause FN tunneling and pass through the FN tunnel film as indicated by an arrow B.

FIG. 4 is a graph showing measured values of the direct tunnel current and the FN tunnel current. The horizontal axis in FIG. 4 represents the gate voltage [V] applied to the nMOSFET by n + poly, and the vertical axis in FIG. 4 represents the current density [μA / cm ² ] of the gate current in the nMOSFET.

4 shows, the effective thickness 2.58nm of T _OX film nMOSFET (tunnel insulating film), 3.65nm, 4.55nm, gate including relates For 5.70Nm, and a direct tunnel current and the FN tunnel current The actual measured value of the current and the theoretical value of the FN tunnel current are shown.

According to FIG. 4, when the effective thickness of the T _OX film is 3.65 nm, 4.55 nm, and 5.70 nm, the gate current is almost in the entire gate voltage region above the gate voltage at which the gate current starts to flow. It almost corresponds to the FN tunnel current. On the other hand, when the effective thickness of the T _OX film is 2.58 nm, the gate current matches the FN tunnel current only in a region having a predetermined voltage or higher in the gate voltage region.

  From this, it can be seen that in an insulating film having an effective film thickness of about 3 nm or more, charge transmission by FN tunneling is dominant. Therefore, an insulating film having an effective film thickness of 3 nm or more can be regarded as an FN tunnel film. Therefore, in this embodiment, the effective film thickness of the tunnel insulating film 111 and the effective film thickness of the IFD film 113 are each set to 3 nm or more. Thereby, the tunnel insulating film 111 and the IFD film 113 become FN tunnel films.

  For details of the graph shown in FIG. 4, refer to “A. Gupta et al., IEEE Trans. Electron Device Lett. 18 (1977) 580.”.

  As described above, in this embodiment, the floating gate of the cell transistor includes the lower floating gate 112 and the upper floating gate 114, and the IFD film 113 is interposed between the lower floating gate 112 and the upper floating gate 114. As a result, the coupling ratio between the upper floating gate 114 and the control gate 116 is improved, and the electric field applied to the tunnel insulating film 111 is increased, so that the writing characteristics of the cell transistor are improved. Furthermore, since the capacity in the cell increases and the coupling ratio increases, the proximity cell interference effect is suppressed.

  In this embodiment, the tunnel insulating film 111 and the IFD film 113 are FN tunnel films. As a result, the charge in the lower floating gate 112 is suppressed from being released to the substrate 101 and the charge in the upper floating gate 114 is suppressed from being released to the lower floating gate 112. As a result, in the present embodiment, with respect to the charges accumulated in these floating gates 112 and 114, the ratio of the charges accumulated in the upper floating gate 114 increases, and the ratio of the charges accumulated in the lower floating gate 112 increases. Less. Thereby, in this embodiment, it becomes possible to keep an electric charge in a cell transistor for a long time.

  In the present embodiment, the IPD film 115 is a charge blocking film. As a result, the charge injected from the substrate 101 to the floating gates 112 and 114 is prevented from passing to the control gate 116.

  In the present embodiment, the IPD film 115 and the control gate 116 are formed across cell transistors adjacent to each other in a direction parallel to the word line. Furthermore, the lower surface of the IPD film 115 and the lower surface of the control gate 116 are flat, and the height of the lower surface of the control gate 116 between the cell transistors is equal to the height of the lower surface of the control gate 116 on the cell transistors. ing. As a result, the capacity between adjacent cells can be reduced, and the occurrence of variations in the drop of the control gate 116 can be avoided.

  In the present embodiment, the thickness of the tunnel insulating film 111 and the IFD film 113 is set to 3 nm or more in terms of EOT. Thereby, these insulating films can be used as FN tunnel films. In the present embodiment, the thickness of the tunnel insulating film 111 and the IFD film 113 may be set to 3 to 5 nm in terms of EOT. As a result, these insulating films can be formed into FN tunnel films that can be easily written by FN tunneling.

  In the present embodiment, the effective film thickness of the IPD film 115 is made larger than the effective film thickness of the tunnel insulating film 111 and the IFD film 113 which are FN tunnel films. As a result, the IPD film 115 can be a charge blocking film.

  The configuration of the semiconductor memory device of this embodiment as described above is suitable for miniaturization of memory cells (cell transistors). According to the present embodiment, it is possible to miniaturize a memory cell while suppressing a decrease in performance of the semiconductor memory device. Specifically, the memory cell can be miniaturized while suppressing deterioration in write characteristics, proximity cell interference effect, charge loss, and the like.

Here, with reference to FIG. 2, the writing operation to the cell transistor and the reading operation from the cell transistor will be described. At the time of writing or reading, a cell transistor (selected cell) to be written or read is selected from the cell transistors arranged in the memory cell array region R _C , and each of the selected cell and the non-selected cell has a predetermined value. Is applied.

  In the present embodiment, when data is written to the selected cell, charges are injected from the substrate 101 into the lower floating gate 112 and the upper floating gate 114 of the selected cell, and the charges are accumulated in these floating gates 112 and 114. In the present embodiment, as described above, charges are mainly accumulated in the upper floating gate 114. When writing data to the selected cell, the write voltage Vpgm is applied to the word line electrically connected to the selected cell.

  On the other hand, when reading data from the selected cell, reading is performed by the read control shown in FIG. FIG. 5 is a timing chart showing the flow of the read operation.

  In the present embodiment, charges are accumulated not only in the upper floating gate 114 but also in the lower floating gate 112. Further, in the present embodiment, there is a possibility that a part of the charge originally stored in the upper floating gate 114 is lost to the lower floating gate 112 by the time of reading. The charge in the lower floating gate 112 may change the threshold voltage of the cell transistor.

  Therefore, in this embodiment, before reading data from the selected cell, a voltage Vrew higher than the read voltage Vread is applied to the word line electrically connected to the selected cell (see FIG. 5). As a result, the charge in the lower floating gate 112 of the selected cell is returned to the upper floating gate 114 of the selected cell.

  Thereafter, in this embodiment, a read voltage Vread is applied to the word line electrically connected to the selected cell, and a sense smaller than the read voltage Vread is applied to the bit line electrically connected to the selected cell. Reading is performed by applying the voltage Vsence (see FIG. 5). As a result, data can be read from the selected cell under an accurate threshold voltage.

  In the present embodiment, the voltage Vrew (rewrite voltage) is set to a voltage that is higher than the read voltage Vread and lower than the write voltage Vpgm.

  Hereinafter, a method for manufacturing the semiconductor memory device of this embodiment will be described.

  6 and 7 are side sectional views for explaining the method for manufacturing the semiconductor memory device of the first embodiment.

  First, as shown in FIG. 6A, on the substrate 101, a first insulating film 211 that is a material of the tunnel insulating film 111, a first electrode layer 212 that is a material of the lower floating gate 112, and a material of the IFD film 113. The second insulating film 213 to be, the second electrode layer 214 to be the material of the upper floating gate 114, and the first mask layer 301 are sequentially formed. The first and second insulating films 211 and 213 are, for example, silicon oxide films formed by thermal oxidation, the first and second electrode layers 212 and 214 are, for example, polysilicon layers, and the first mask layer 301 is, for example, a silicon oxide film.

Next, the first mask layer 301 is patterned by lithography and etching (FIG. 6B). Next, a plurality of first grooves T ₁ corresponding to element isolation grooves are formed by etching using the first mask layer 301. The first trench T ₁ extends in the X direction (a direction parallel to the bit line BL) and penetrates the second electrode layer 214, the second insulating film 213, the first electrode layer 212, and the first insulating film 211. is doing. Further, the first groove T ₁ reaches the inside of the substrate 101, and the bottom surface of the first groove T ₁ is lower than the top surface of the substrate 101.

Next, as shown in FIG. 6 (C), fill the device isolation insulating film 121 to the first groove T _1. The material of the element isolation insulating film 121 is, for example, a silicon oxide film. The element isolation insulating film 121 is embedded in the first trench T ₁ by depositing the material of the element isolation insulating film 121 on the entire surface of the substrate 101 and planarizing the surface of the material by CMP (chemical mechanical polishing). Done. The CMP is performed until the height of the upper surface S ₁ of the element isolation insulating film 121 is the same as the height of the upper surface S ₂ of the second electrode layer 214.

Next, as shown in FIG. 7A, on the second electrode layer 214 and the element isolation insulating film 121, a third insulating film 215 that is a material of the IPD film 115 and a third electrode that is a material of the control gate 116. A layer 216 and a second mask layer 302 are formed in this order. The third insulating film 215 is, for example, an ONO stacked film, the third electrode layer 216 is, for example, a polysilicon layer, and the second mask layer 302 is, for example, a silicon oxide film. In FIG. 7A, due to the fact that the height of S ₁ is equal to the height of S ₂ , the height of the lower surface σ ₁ of the third electrode layer 216 between the cell transistors is the third electrode on the cell transistor. It is equal to the height of the lower surface σ ₂ of the layer 216.

Next, the second mask layer 302 is patterned by lithography and etching (FIG. 7B). Next, a plurality of second grooves T ₂ are formed by etching using the second mask layer 302. Second groove T ₂ are, Y extends in a direction (direction parallel to the word lines WL), the third electrode layer 216, the third insulating film 215, the second electrode layer 214, the second insulating film 213, the first It penetrates through the electrode layer 212 and the first insulating film 211. In the present embodiment, the bottom surface of the second groove T ₂ has the same height as the top surface of the substrate 101.

  As described above, the cell transistor including the tunnel insulating film 111, the lower floating gate 112, the IFD film 113, the upper floating gate 114, the IPD film 115, and the control gate 116 is formed on the substrate 101. Thereafter, a source / drain diffusion layer 131 is formed in the substrate 101, and an interlayer insulating film 122 is formed on the substrate 101 so as to cover the cell transistors (FIG. 7C). Furthermore, contact plugs, via plugs, various wiring layers, and the like are formed on the substrate 101.

  As described above, in this embodiment, the floating gate of the cell transistor includes the lower floating gate 112 and the upper floating gate 114, and the IFD film 113 is interposed between the lower floating gate 112 and the upper floating gate 114. Further, the tunnel insulating film 111 and the IFD film 113 are FN tunnel films, and the IPD film 115 is a charge blocking film. Thereby, in this embodiment, it becomes possible to miniaturize a memory cell, suppressing the fall of the performance of a semiconductor memory device. For example, it is possible to miniaturize the memory cell while suppressing deterioration of write characteristics, proximity cell interference effect, charge loss, and the like. Regarding the write characteristics, according to the present embodiment, the coupling ratio between the upper floating gate 114 and the control gate 116 is improved and the electric field applied to the tunnel insulating film 111 is increased, so that the write characteristics of the cell transistor are improved. In addition, with respect to the neighbor cell interference effect, the capacity in the cell increases and the coupling ratio increases, so that the neighbor cell interference effect is suppressed.

  Hereinafter, second and third embodiments of the present invention will be described. These embodiments are modifications of the first embodiment, and these embodiments will be described with a focus on differences from the first embodiment.

(Second Embodiment)
FIG. 8 is a side sectional view showing the configuration of the semiconductor memory device according to the second embodiment.

In FIG. 8A, as in FIG. 2A, the IPD film 115 and the control gate 116 are formed across the cell transistors C adjacent in the Y direction (direction parallel to the word line WL). However, in FIG. 8A, unlike FIG. 2A, the height of the upper surface S ₁ of the element isolation insulating film 121 is lower than the height of the upper surface S ₂ of the upper floating gate 114. As a result, in FIG. 8A, the height of the lower surface σ ₁ of the control gate 116 between the cell transistors C is lower than the height of the lower surface σ ₂ of the control gate 116 on the cell transistor C.

  In the present embodiment, the height of the upper surface of the element isolation insulating film 121 is equal to the height of the upper surface of the IFD film 113. However, the height of the upper surface of the element isolation insulating film 121 may be a height between the upper surface of the upper floating gate 114 and the upper surface of the IFD film 113.

  In the present embodiment, the thickness of the IPD film 115 between the cell transistors C may be equal to or different from the thickness of the IPD film 115 on the cell transistors C. In the present embodiment, the thickness of the IPD film 115 between the cell transistors C and the thickness of the IPD film 115 on the cell transistor C are effective film thicknesses in terms of EOT, both of which are the thickness of the tunnel insulating film 111 and the IFD film It is set to be thicker than the thickness of 113.

  As described above, in this embodiment, the IPD film 115 and the control gate 116 are formed across the cell transistors adjacent in the direction parallel to the word line. Furthermore, the height of the lower surface of the control gate 116 between the cell transistors is lower than the height of the lower surface of the control gate 116 on the cell transistor, and the control gate 116 is dropped between the cell transistors. As a result, the capacitance between the upper floating gate 114 and the control gate 116 can be increased and the capacitive coupling can be strengthened. As a result, in this embodiment, the write characteristics of the cell transistor are improved.

  Hereinafter, a method for manufacturing the semiconductor memory device of this embodiment will be described.

  9 and 10 are side sectional views for explaining the method for manufacturing the semiconductor memory device of the second embodiment.

  First, as shown in FIG. 9A, on the substrate 101, a first insulating film 211 that is a material of the tunnel insulating film 111, a first electrode layer 212 that is a material of the lower floating gate 112, and a material of the IFD film 113. The second insulating film 213 to be, the second electrode layer 214 to be the material of the upper floating gate 114, and the first mask layer 301 are sequentially formed.

Next, the first mask layer 301 is patterned by lithography and etching (FIG. 9B). Next, a plurality of first grooves T ₁ corresponding to element isolation grooves are formed by etching using the first mask layer 301.

Next, as shown in FIG. 9 (C), fill the device isolation insulating film 121 to the first groove T _1. The element isolation insulating film 121 is embedded in the first trench T ₁ by depositing the material of the element isolation insulating film 121 on the entire surface of the substrate 101 and planarizing the surface of the material by CMP (chemical mechanical polishing). Done. The CMP is performed until the height of the upper surface S ₁ of the element isolation insulating film 121 is the same as the height of the upper surface S ₂ of the second electrode layer 214.

Next, in the present embodiment, the element isolation insulating film 121 is etched to make the height of the upper surface S ₁ of the element isolation insulating film 121 lower than the height of the upper surface S ₂ of the second electrode layer 214 (FIG. 9). (C)). In this embodiment, the etching is performed until the height of the upper surface of the element isolation insulating film 121 becomes equal to the height of the upper surface of the second insulating film 213.

Next, as shown in FIG. 10A, on the second electrode layer 214 and the element isolation insulating film 121, a third insulating film 215 that is a material of the IPD film 115 and a third electrode that is a material of the control gate 116. A layer 216 and a second mask layer 302 are formed in this order. In FIG. 10A, due to the fact that the height of S ₁ is lower than the height of S ₂ , the height of the lower surface σ ₁ of the third electrode layer 216 between the cell transistors is the third height on the cell transistor. The height of the lower surface σ ₂ of the electrode layer 216 is lower.

Next, the second mask layer 302 is patterned by lithography and etching (FIG. 10B). Next, a plurality of second grooves T ₂ are formed by etching using the second mask layer 302.

  As described above, the cell transistor including the tunnel insulating film 111, the lower floating gate 112, the IFD film 113, the upper floating gate 114, the IPD film 115, and the control gate 116 is formed on the substrate 101. Thereafter, a source / drain diffusion layer 131 is formed in the substrate 101, and an interlayer insulating film 122 is formed on the substrate 101 so as to cover the cell transistors (FIG. 10C). Furthermore, contact plugs, via plugs, various wiring layers, and the like are formed on the substrate 101.

  Hereinafter, a semiconductor memory device according to a modification of the second embodiment will be described.

  FIG. 11 is a side sectional view showing a configuration of a semiconductor memory device according to a modification of the second embodiment.

11A to 11C, the IPD film 115 and the control gate 116 are formed across the cell transistors C adjacent in the Y direction. Further, the height of the lower surface σ ₁ of the control gate 116 between the cell transistors C is lower than the height of the lower surface σ ₂ of the control gate 116 on the cell transistor C.

In FIG. 11A, the thickness t ₂ of the upper floating gate 114 is larger than the thickness t ₁ of the lower floating gate 112. According to such a structure, since the capacitance between the upper floating gate 114 and the control gate 116 can be increased and the capacitive coupling can be strengthened, the write characteristics of the cell transistor C are improved.

In FIG. 11B, the thickness t ₃ of the IFD film 113 is an effective thickness in terms of EOT and is thinner than the thickness t ₄ of the tunnel insulating film 111. According to such a structure, charges can be easily stored in the upper floating gate 114, so that a large amount of stored charges can be prevented from existing near the substrate 101.

In FIG. 11C, the thickness t ₃ of the IFD film 113 is an effective film thickness in terms of EOT, and is thinner than the thickness t ₅ of the IPD film 115. According to such a structure, it is possible to make it difficult for charges to escape from the upper floating gate 114 to the control gate 116.

  In FIG. 11C, the thickness of the IFD film 113 is an effective film thickness in terms of EOT, and is set smaller than the thickness of the IPD film 115 between the cell transistors C, and the IPD film on the cell transistor C. The thickness is set to be thinner than 115.

  Note that the modifications shown in FIGS. 11A to 11C are also applicable to the first embodiment and the third embodiment described later.

  As described above, in this embodiment, as in the first embodiment, the floating gate of the cell transistor is configured by the lower floating gate 112 and the upper floating gate 114, and between the lower floating gate 112 and the upper floating gate 114. An IFD film 113 is interposed. Further, the tunnel insulating film 111 and the IFD film 113 are FN tunnel films, and the IPD film 115 is a charge blocking film. As a result, in the present embodiment, as in the first embodiment, the memory cell can be miniaturized while suppressing a decrease in performance of the semiconductor memory device. For example, it is possible to miniaturize the memory cell while suppressing deterioration of write characteristics, proximity cell interference effect, charge loss, and the like. Regarding the write characteristics, according to the present embodiment, the coupling ratio between the upper floating gate 114 and the control gate 116 is improved and the electric field applied to the tunnel insulating film 111 is increased, so that the write characteristics of the cell transistor are improved. In addition, with respect to the neighbor cell interference effect, the capacity in the cell increases and the coupling ratio increases, so that the neighbor cell interference effect is suppressed.

(Third embodiment)
FIG. 12 is a side sectional view showing the configuration of the semiconductor memory device of the third embodiment, and FIG. 13 is a side sectional view showing the configuration of the semiconductor memory device of the comparative example. 12 and 13 are cross-sectional views taken along the I cross section (AA cross section) shown in FIG. 1, and FIGS. 12 and 13 show a cross section of the cell transistor C. FIG.

  In the comparative example, the lower floating gate 112 and the upper floating gate 114 are both N-type polysilicon layers. However, the cell transistor C having such a structure has a drawback of poor data retention.

  Therefore, in this embodiment, the lower floating gate 112 and the upper floating gate 114 are a P-type polysilicon layer and an N-type polysilicon layer, respectively. Thereby, in this embodiment, data retention can be improved by a work function.

  In the first and second embodiments, the lower floating gate 112 and the upper floating gate 114 may both be an N-type polysilicon layer or a P-type polysilicon layer and an N-type polysilicon layer, respectively.

  Furthermore, in the first and second embodiments, the lower floating gate 112 and the upper floating gate 114 may both be a P-type polysilicon layer or an N-type polysilicon layer and a P-type polysilicon layer, respectively.

  Thus, in the first and second embodiments, the lower floating gate 112 and the upper floating gate 114 may be the same conductivity type semiconductor layer or different conductivity type semiconductor layers.

  The operation of the semiconductor memory device of this embodiment (FIG. 12) will be described below.

  FIG. 14 is a conceptual diagram for explaining the state of the cell transistor before writing. As in FIG. 3, the horizontal direction in FIG. 14 represents the height direction of the cell transistor, and the vertical direction in FIG. 14 represents the height direction of the potential inside and outside the cell transistor.

FIG. 14 shows potential barriers of the _TOX film (tunnel insulating film) 111, the IFD film 113, and the IPD film 115.

Further, in FIG. 14, regarding the potentials in the substrate (Sub) 101, the lower floating gate (FG ₁ ) 112, the upper floating gate (FG ₂ ) 114, and the control gate (CG) 116, the lower end of the conduction band and the upper end of the valence band. Is indicated by a solid line, and the Fermi level is indicated by a broken line.

  In FIG. 14, by replacing the lower floating gate 112 from the N-type layer to the P-type layer, the lower end of the conduction band and the upper end of the valence band in the lower floating gate 112 are from the same potential as the upper floating gate 114. A state in which the potential is raised to the same potential as 101 is shown.

  FIG. 15 is a conceptual diagram for explaining the state of the cell transistor at the time of writing.

FIG. 15A shows the state of the cell transistor before writing, as in FIG. At the time of writing, as shown in FIG. 15B, the voltage of the control gate 116 is set to Vpgm. In this embodiment, by replacing the lower floating gate 112 from the N-type layer to the P-type layer, the potential difference E _IFD between the upper surface and the lower surface of the _IFD 113 is increased, so that electrons are easily injected into the upper floating gate 114. Become.

  FIG. 16 is a conceptual diagram for explaining the state of the cell transistor during retention.

FIGS. 16A and 16B respectively show the state of the cell transistor during retention when the lower floating gate 112 is a P-type layer and when the lower floating gate 112 is an N-type layer. In this embodiment, as shown in FIG. 16A, the potential difference E _IFD is relaxed by replacing the lower floating gate 112 from the N-type layer to the P-type layer, so that it is injected into the upper floating gate 114. It becomes difficult to remove electrons. On the other hand, FIG. 16B shows a state where electrons easily escape from the upper floating gate 114 to the lower floating gate 112 and from the lower floating gate 112 to the substrate 101.

  FIG. 17 is a conceptual diagram for explaining the effect of the third embodiment.

In the present embodiment, first, since the potential difference E _IFD is relaxed, there is an effect that electrons injected into the upper floating gate 114 are difficult to escape to the lower floating gate 112. Second, when electrons are accumulated in the lower floating gate 112, the electrons are combined with holes, so that free electrons disappear and polarized electrons are generated. There is an effect that it is difficult to remove the substrate 101. Third, the depletion of the lower portion of the lower floating gate 112, a potential difference Etox is relaxed between the upper and lower surfaces of the T _OX film 111, that the electrons in the lower floating gate 112 is less likely to escape into the substrate 101 effective.

  As described above, in the present embodiment, the lower floating gate 112 and the upper floating gate 114 are semiconductor layers of different conductivity types. Thereby, in this embodiment, the data retention of the cell transistor can be improved.

(Modification)
Hereinafter, modifications of the semiconductor memory device according to the first to third embodiments will be described.

In the first to third embodiments, the active region R ₂ , the tunnel insulating film 111, the lower floating gate 112, the IFD film 113, and the upper floating gate 114 have the same width in the Y direction (direction parallel to the word line). (Refer to FIG. 2 (A), FIG. 8 (A), FIG. 12 (A)). However, the widths of these layers may be set to different widths as shown in FIG.

  FIG. 18 is a side sectional view showing a configuration of a semiconductor memory device according to a modification of the first to third embodiments. 18 is a cross-sectional view taken along the I cross section (AA cross section) shown in FIG. 1. FIG. 18 shows a cross section of the cell transistor C.

18A to _18D , the widths of the active region R ₂ , the lower floating gate 112, and the upper floating gate 114 in the Y direction are indicated by W _Y1 , W _Y2 , and W _Y3 , respectively.

In FIG. 18A, the widths W _Y2 and W _{Y3 in} the Y direction of the lower floating gate 112 and the upper floating gate 114 are set wider than the width W _{Y1 in} the Y direction of the active region R ₂ . On the other hand, in FIG. _18D , the widths W _Y2 and W _{Y3 in} the Y direction of the lower floating gate 112 and the upper floating gate 114 are set to be narrower than the width W _{Y1 in} the Y direction of the active region R ₂ .

In FIG. 18B, the width W _{Y3 of the} upper floating gate 114 in the Y direction is set wider than the width W _{Y2 of the} lower floating gate 112 in the Y direction. In FIG. _18C , the width W _{Y3 of the} upper floating gate 114 in the Y direction is set to be narrower than the width W _{Y2 of the} lower floating gate 112 in the Y direction.

As described above, in the modification shown in FIG. 18, the active region R ₂ , the tunnel insulating film 111, the lower floating gate 112, the IFD film 113, and the Y of the upper floating gate 114 are changed depending on the design convenience of the semiconductor memory device. The direction width can be set to various values.

  Similarly, in the first to third embodiments, the X direction (direction parallel to the bit line) of the tunnel insulating film 111, the lower floating gate 112, the IFD film 113, the upper floating gate 114, the IPD film 115, and the control gate 116. Are the same width (see FIGS. 2B and 8B). However, the widths of these layers may be set to different widths as shown in FIG.

  FIG. 19 is a side sectional view showing a configuration of a semiconductor memory device according to a modification of the first to third embodiments. 19 is a cross-sectional view taken along the II cross section (GC cross section) shown in FIG. 1, and FIG. 19 shows a cross section of the cell transistor C.

19A to 19D, the widths in the X direction of the lower floating gate 112, the upper floating gate 114, and the control gate 116 are indicated by W _X1 , W _X2 , and W _X3 , respectively.

In FIG. _19C , the widths W _X1 and W _{X2 in} the X direction of the lower floating gate 112 and the upper floating gate 114 are set wider than the width W _{X3 in} the X direction of the control gate 116. On the other hand, in FIG. _19D , the widths W _X1 and W _{X2 in} the X direction of the lower floating gate 112 and the upper floating gate 114 are set narrower than the width W _{X3 in} the X direction of the control gate 116.

In FIG. 19A, the width W _{X2 of the} upper floating gate 114 in the X direction is set wider than the width W _{X1 of the} lower floating gate 112 in the X direction. In FIG. 19B, the width W _{X2 of the} upper floating gate 114 in the X direction is set smaller than the width W _{X1 of the} lower floating gate 112 in the X direction.

  As described above, in the modification shown in FIG. 19, the tunnel insulating film 111, the lower floating gate 112, the IFD film 113, the upper floating gate 114, the IPD film 115, and the control gate are selected in accordance with the design convenience of the semiconductor memory device. The width of 116 in the X direction can be set to various values.

  Note that the arbitrary modification shown in FIG. 18 and the arbitrary modification shown in FIG. 19 may be used in combination.

  As mentioned above, although the example of the specific aspect of this invention was demonstrated by 1st to 3rd embodiment, this invention is not limited to these embodiment.

101 Substrate 111 Tunnel insulating film 112 Lower floating gate 113 IFD film 114 Upper floating gate 115 IPD film 116 Control gate 121 Element isolation insulating film 122 Interlayer insulating film 131 Source / drain diffusion layer 211 First insulating film 212 First electrode layer 213 Second Insulating film 214 Second electrode layer 215 Third insulating film 216 Third electrode layer 301 First mask layer 302 Second mask layer

Claims (5)

A substrate,
A gate insulating film formed on the substrate and functioning as an FN (Fowler-Nordheim) tunnel film;
A first floating gate formed on the gate insulating film;
A first inter-gate insulating film formed on the first floating gate and functioning as an FN tunnel film;
A second floating gate formed on the first inter-gate insulating film;
A second inter-gate insulating film formed on the second floating gate and functioning as a charge blocking film;
A control gate formed on the second inter-gate insulating film;
A semiconductor memory device comprising: The semiconductor memory device
A plurality of bit lines extending in a first direction parallel to the surface of the substrate;
A plurality of word lines extending in a second direction parallel to the surface of the substrate;
The bit line and the word including the gate insulating film, the first floating gate, the first inter-gate insulating film, the second floating gate, the second inter-gate insulating film, and the control gate. A plurality of cell transistors electrically connected to the line;
The semiconductor memory device according to claim 1, comprising:   When reading data from a selected cell selected from the cell transistors, a voltage higher than a read voltage is applied to a word line electrically connected to the selected cell before reading. Item 3. The semiconductor memory device according to Item 2.   When reading the data from the selected cell, the read voltage is applied to the word line electrically connected to the selected cell, and the read is applied to the bit line electrically connected to the selected cell. 4. The semiconductor memory device according to claim 3, wherein a sense voltage smaller than the voltage is applied.   4. The semiconductor according to claim 3, wherein the voltage applied to the word line electrically connected to the selected cell before reading is lower than a write voltage when data is written to the selected cell. Storage device.

Images