JPH10233458A - Manufacture of nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of damage of a gate oxide film due to a channeling, by a method wherein first and second semiconductor polycrystalline thin films are formed in order on a semiconductor substrate and after the laminated structure consisting of the first and the second semiconductor polycrystalline thin films is processed into a a two-layer gate electrode, impurities are implanted in the substrate using the gate electrode as a mask and source-drain diffused layers are formed. SOLUTION: A silicon oxide film 2 is formed on the surface of a silicon substrate 1 and a gate oxide film 3 is formed at an element region, which is sectioned by the film 2, on the substrate 1. After that, a polycrystalline silicon film 4 is formed by a CVD method and a very thin oxide layer 5 is formed in this film 4. Then, an ONO film 7, which is used as an insulating film between a floating gate and a control gate, and a polycrystalline silicon film 8 are formed, this film 8 and the films 7 and 4 are processed into the shape of a laminated gate electrode, phosphorus, arsenic and the like are ion-implanted in the substrate 1 using this laminated gate electrode as a mask and source and drain diffused layers 9 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a memory cell in a nonvolatile semiconductor memory device, particularly, a flash memory.

[0002]

2. Description of the Related Art As a nonvolatile semiconductor memory device, an EPROM and a flash memory capable of erasing and writing information are known. However, these nonvolatile semiconductor memory devices have conventionally employed a gate oxide film on the surface of a silicon substrate. After forming a floating gate electrode layer for charge storage, an inter-electrode insulating film, and a control gate electrode layer serving as a word line of each memory cell, and processing into a stacked gate electrode, a source / drain diffusion layer and a channel are formed. A region was formed, and then metal wiring to each electrode was formed.

In such a semiconductor memory device, a polycrystalline silicon thin film is generally used as a floating gate electrode layer. A method of electrically activating the floating gate electrode layer is described in, for example, Ron Muramatsu et al. In Digest of 1994 IEDM, 847-850.
Page (Digest of 1994 IEDM, p
age 847-850).

[0004] In the report and in the conventional method of manufacturing a general flash memory cell, first, as shown in FIG.
OS (Local Oxidation of Sil)
A silicon oxide film 32 for element isolation of a memory cell or the like is formed by an icon method. Thereafter, a tunnel gate oxide film 33 having a thickness of about 100 ° and a polysilicon film 34 for a floating gate electrode having a thickness of about 1500 ° are formed.

Further, as shown in FIG. 4 (b), after an ion implantation of phosphorus, which is an N-type impurity for the purpose of electrically activating the floating gate electrode, an ONO film is formed as an insulating film between gate electrodes. 35 (equivalent oxide film thickness: about 180 °) and a control gate electrode polycrystalline silicon film 36 are sequentially formed.

Subsequently, as shown in FIG. 4C, the polycrystalline silicon film 36, the ONO film 35, and the polycrystalline silicon film 34 are processed into a stacked gate electrode shape using photolithography and dry etching techniques. Then, arsenic, which is an N-type impurity, is implanted into silicon substrate 31 using the gate electrode of the laminated structure as a mask, and source / drain diffusion layers 37 are formed.

Thereafter, a subsequent process for forming metal wiring to the source / drain diffusion layer 37, the control gate electrode 36, and the like is performed to complete a flash memory cell.

[0008]

However, in the above-described manufacturing process, when phosphorus is ion-implanted into the polysilicon film 34 in order to make the polysilicon film 34 for the floating gate electrically active. In some cases, the gate oxide film 34 may be damaged. That is, since the orientation of silicon microcrystals existing in the polycrystalline silicon film 34 is not controlled, various crystal planes are exposed on the upper surface of the polycrystalline silicon film 34, and some of them are exposed. And the so-called channeling surface during ion implantation. Therefore, channeling is likely to occur when phosphorus is ion-implanted. When channeling occurs, as shown in page 104 of the IEICE series “Electronic Device Process”, accelerated ions of phosphorus pass through the polycrystalline silicon film and form a gate oxide film 33 located thereunder. And moves in the gate oxide film 33 with high energy. As a result, the gate oxide film 34 is damaged.

As a method for preventing channeling at the time of implanting phosphorus ions into the floating gate electrode, Japanese Patent Laid-Open No.
As disclosed in Japanese Patent Publication No. 196673, before the silicon film for the floating gate electrode is formed, a part of the gate oxide film is opened, and the opening portion serves as a nucleus for crystal growth. A method in which a film is crystal-grown and made into a single crystal is used.

However, in this method, it is necessary to form a region for crystal growth nuclei in the memory cell array region. For this reason, as memory cells are miniaturized, the ratio of regions for crystal growth nuclei in the memory cells increases, and as a result, the occupied area of the memory cells increases, making it difficult to achieve high memory integration.

An object of the present invention is to improve the characteristics of a gate oxide film for a memory cell by preventing the occurrence of damage to the gate oxide film due to channeling, to improve the reliability of a memory cell due to the improved characteristics of the gate oxide film, It is an object of the present invention to provide a method of manufacturing a nonvolatile semiconductor memory device that realizes high integration of a memory cell because each region for crystal growth is unnecessary in the memory cell.

[0012]

In order to achieve the above object, a method for manufacturing a nonvolatile semiconductor memory device according to the present invention comprises a first polycrystalline film forming step, a second polycrystalline film forming step, and a diffusion layer. Forming a first gate insulating film in an element region on a semiconductor substrate, wherein the first polycrystalline film forming step includes:
Forming a first semiconductor polycrystalline thin film having an extremely thin semiconductor oxide film in the film on the surface of the semiconductor substrate; and forming a second polycrystalline film in the first conductive thin film using a first conductive type thin film. After ion-implanting an impurity for forming a semiconductor film, a second gate insulating film and a second semiconductor polycrystalline thin film are sequentially formed on the semiconductor substrate. This is a process of forming a source / drain diffusion layer after processing into a shape of a two-layer gate electrode and then implanting impurities using the gate electrode as a mask.

A method of manufacturing a nonvolatile semiconductor memory device having a first semiconductor thin film forming step, a second polycrystalline forming step, and a diffusion layer forming step, wherein the first semiconductor thin film forming step is performed on a semiconductor substrate. After forming the first gate insulating film in the element region, the first semiconductor thin film in the amorphous state is formed. The second polycrystalline forming step is performed so that the amorphous semiconductor thin film is polycrystallized. Before the heat treatment is performed, ion implantation of impurities for converting the first semiconductor thin film into a first conductive type semiconductor film is performed, and then a second gate insulating film and a second gate insulating film are formed on the semiconductor substrate. This is a process for sequentially forming a semiconductor polycrystalline thin film. In the diffusion layer forming step, after processing the laminated structure into a shape of a two-layer gate electrode, impurities are implanted using the gate electrode as a mask, and a source / drain diffusion is performed. A process of forming a.

A method for manufacturing a non-volatile semiconductor memory device comprising a first polycrystal forming step, an ion implantation step, a second thin film forming step, and a diffusion layer forming step, wherein the first polycrystal forming step Forming a first gate insulating film in a device region on a semiconductor substrate to form a first semiconductor polycrystalline thin film; and performing the ion implantation step by removing the first semiconductor thin film from a first conductive type. When ion implantation of impurities for forming a semiconductor film is performed, a normal direction of the substrate is set so that the implanted impurities can cross two or more crystal grains in the first semiconductor thin film. Ion implantation of impurities with a sufficiently large angle set, and then a second gate insulating film and a second semiconductor thin film are sequentially formed on the semiconductor substrate. After processing into the shape of the layer gate electrode, Impurities are implanted using the gate electrode as a mask, a process of forming the source and drain diffusion layers.

A non-volatile semiconductor memory device having a first semiconductor single crystal thin film forming step, a second semiconductor thin film forming step, and a diffusion formation, wherein the first semiconductor single crystal thin film forming step includes the steps of: This is a process of forming a first gate insulating film in the formed element region, forming a first semiconductor thin film by a graphoepitaxy method, and irradiating a laser beam or the like to single crystallize the first semiconductor thin film. , Second
The semiconductor thin film forming step is a step of performing ion implantation of a first conductive impurity, and thereafter sequentially forming a second gate insulating film and a second semiconductor thin film on a semiconductor substrate. After processing the structure into the shape of a two-layer gate electrode, impurities are implanted using the gate electrode as a mask,
This is a process for forming a source / drain diffusion layer.

[0016]

In the memory cell of the present invention, a polycrystalline silicon thin film having an extremely thin semiconductor oxide film in the film is used as the silicon film for the floating gate electrode. Performing implantation, using a single-crystal silicon film formed using a graphoepitaxy technique for a silicon film in a region to be a floating gate electrode, and being implanted when phosphorus is ion-implanted into a silicon film for a floating gate electrode. By setting the implantation angle to have a sufficiently large angle with respect to the normal direction of the substrate so that the ions of phosphorus can cross two or more crystal grains in the polysilicon film for the floating gate electrode, Channeling at the time of ion implantation can be prevented, and damage to the gate oxide film can be prevented.

Compared with the conventional method using crystal nuclei, when a silicon film in a region to be a floating gate electrode is monocrystallized by using graphoepitaxy technology or the like,
The area occupied by the memory cell can be reduced, and as a result, high integration of the memory cell can be realized.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. In the memory cell used in the embodiment of the present invention, a silicon film as a semiconductor film, a silicon oxide film as a gate oxide film, and a stacked film (ONO) of a silicon oxide film / silicon nitride film / silicon oxide film as an insulating film.
Film), and a silicon substrate is used as a semiconductor substrate.

[0019]

Embodiment 1 Embodiment 1 of the present invention will be described with reference to FIG.

First, as shown in FIG. 1A, a silicon oxide film 2 having a thickness of 6000.degree. Is formed on the surface of a silicon substrate 1 by the LOCOS separation method. A gate oxide film 3 having a thickness of 100 ° is formed in the element region by thermal oxidation.

Thereafter, a polycrystalline silicon film 4 having a thickness of 1500 ° is formed by the CVD method. In the CVD method of the polycrystalline silicon film 4, a method such as oxygen leak during formation is used.
An extremely thin oxide layer 5 is formed in the polycrystalline silicon film 4. As a result, the microcrystals in the polycrystalline silicon film 4 are separated from each other with the ultrathin oxide layer 5 as a boundary, and have different crystal plane orientations.

That is, the polycrystalline silicon film 4 is composed of a two-layer film of microcrystalline layers having different crystal plane orientations. Thereafter, phosphorus ions are implanted to convert the polycrystalline silicon film 4 into an N-type conductive semiconductor film. At this time, as described above, the polycrystalline silicon film 4 is composed of a two-layer film of microcrystalline layers having different crystal plane orientations.
The upper microcrystal exposes the channeling surface for ion implantation, and even if phosphorus passes through the microcrystal, if the crystal orientation of the microcrystal under oxide film 5 does not match the channeling surface,
Phosphorus ions can be stopped in this microcrystalline region.

As a result, even if phosphorus ions are implanted into the polycrystalline silicon film 4, phosphorus ions pass through the polycrystalline silicon film 4 and directly reach the gate oxide film 3 due to channeling, and No damage to 3

Next, as shown in FIG. 1B, an ONO film 7 (180 equivalent oxide film thickness) serving as an insulating film between the floating gate and the control gate and a polycrystalline silicon film 8 serving as the control gate
(Film thickness: 1500 °) are sequentially formed by the CVD method.

Further, as shown in FIG. 1C, the polycrystalline silicon film 8, the ONO film 7, and the polycrystalline silicon film 4 are formed by photolithography and dry etching techniques to form a stacked gate electrode comprising a control gate and a floating gate. The source / drain diffusion layer 9 is formed by ion-implanting phosphorus, arsenic, and the like using the laminated gate electrode as a mask.

Finally, a non-volatile memory is completed by forming an interlayer insulating film, forming a contact hole, forming a metal wiring to each electrode, and the like.

[0027]

Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIG. First, as shown in FIG. 2A, a film thickness of 600 is formed on the surface of the silicon substrate 11 by the LOCOS separation method.
A silicon oxide film 12 of 0 ° is formed, and a silicon oxide film 1 is formed.
2 in the element region on the silicon substrate 11 partitioned by
A gate oxide film 13 having a thickness of 100 ° is formed by a thermal oxidation method.

Thereafter, an amorphous silicon film 14 having a thickness of 1500 ° is formed. After that, before performing a heat treatment for polycrystallizing the amorphous silicon film 14, phosphorus ions are implanted to turn the silicon film 14 into an N-type conductive semiconductor film. At this time, the silicon film 14
Is in an amorphous state, the channeling surface of the ion implantation is not exposed on the surface of the silicon film 14, no channeling occurs during the ion implantation, and the phosphorus ions stop in the silicon film 14. As a result, even if phosphorus ions are implanted into the amorphous silicon film 14, phosphorus ions pass through the amorphous silicon film 14 and directly reach the gate oxide film 13 due to channeling, and damage the gate oxide film 13. Will not give.

Next, as shown in FIG. 2 (b), an ONO film 15 (equivalent to an oxide film thickness of 180 °) serving as an insulating film between the floating gate and the control gate, and a polycrystalline silicon film 16 (film thickness serving as the control gate) 1500 °) are sequentially formed by the CVD method.

Further, as shown in FIG. 2C, the silicon film 16, the ONO film 15, and the silicon film 14 are processed by photolithography and dry etching into a shape of a laminated gate electrode including a control gate and a floating gate. Using the stacked gate electrode as a mask, phosphorus and arsenic are ion-implanted to form source / drain diffusion layers 17.

Finally, a non-volatile memory is completed by forming an interlayer insulating film, forming a contact hole, and forming a metal wiring on each electrode.

[0032]

Third Embodiment A third embodiment of the present invention will be described with reference to FIG. First, as shown in FIG. 3A, a 6000 ° -thick silicon oxide film 22 is formed on the surface of a silicon substrate 21 by a CVD method, and then, as shown in FIG. The oxide film 22 is removed by photolithography and dry etching of a silicon oxide film. At this time, the mask layout is devised so that the width of the region where the silicon substrate 21 is exposed as the element region is several μm.

Next, as shown in FIG. 3C, a gate oxide film 2 having a thickness of 100.degree.
4 is formed by a thermal oxidation method. After that, the film thickness is 1500 °
Is formed on the entire surface of the substrate by a graphoepitaxy method, and the silicon film 25 is monocrystallized by recrystallization by laser beam heating. The graphoepitaxy method and recrystallization by laser beam heating are described in 1979 IEDM technical dig.
As described in detail on page 210 of est, using this method, the [100] crystal plane orientation of the silicon film was exposed to the surface in a concave region having a width of several μm surrounded by the silicon oxide film 22. A silicon single crystal film can be formed.

Thereafter, as shown in FIG. 3D, phosphorus ions are implanted to convert the single crystal silicon film 25 into an N-type conductive semiconductor film. At this time, as described above, since the [100] crystal plane exposed on the substrate surface causes channeling at the time of ion implantation, the ion implantation angle is set to, for example, 8 degrees from the normal direction of the substrate surface. Do it at an angle. If the crystal orientation does not match the channeling plane, phosphorus ions can be stopped in this single crystal silicon film 25 region. As a result, even if phosphorus is ion-implanted into single crystal silicon film 25, phosphorus ions pass through single crystal silicon film 25 and directly reach gate oxide film 24 due to channeling, so that gate oxide film 2 is formed.
No damage to 4

Next, as shown in FIG. 3E, an ONO film 26 (an oxide film equivalent thickness of 180 °) serving as an insulating film between the floating gate and the control gate and a polycrystalline silicon film 27 (film thickness equivalent to the oxide film) serve as a control gate. 1500 °) are sequentially formed by the CVD method.

Further, as shown in FIG. 3 (f), the polycrystalline silicon film 27, the ONO film 26, the single crystal silicon film 2
5 is processed by photolithography and dry etching into a laminated gate electrode composed of a control gate and a floating gate, and phosphorus and arsenic are ion-implanted using the laminated gate electrode as a mask.
8 is formed.

Finally, a non-volatile memory is completed by forming an interlayer insulating film, forming a contact hole, forming a metal wiring to each electrode, and the like.

[0038]

As described above, according to the present invention, when phosphorus ions are implanted, phosphorus ions pass through the silicon film for the floating gate, reach the gate oxide film thereunder, and damage the gate oxide film. By suppressing the applied channeling phenomenon, the reliability of the gate oxide film can be improved. As a result, it is possible to improve the reliability of the nonvolatile semiconductor memory device, and in particular, to improve the data holding characteristic of keeping the charge accumulated in the floating gate electrode.

Further, it is not necessary to set specially each crystal region for floating gate silicon single crystallization, which is required in the conventional example, and it is possible to suppress channeling. Therefore, the occupied area of the memory cell can be reduced by the amount of no extra crystal regions, and high integration of the memory can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in the order of steps.

FIG. 2 is a sectional view showing Embodiment 2 of the present invention in the order of steps.

FIG. 3 is a sectional view showing a third embodiment of the present invention in the order of steps.

FIG. 4 is a sectional view showing a conventional example in the order of steps.

[Explanation of symbols]

 1,11,21 silicon substrate 2,12,22 silicon oxide film 3,13,24 gate oxide film 4,14,25 floating gate silicon film 5 silicon oxide layer 7,15,26 ONO film 8,16,27 control Gate / silicon film 9, 17, 28 Source / drain diffusion layer 23 Photoresist

Continuation of front page (72) Inventor Makoto Matsuo 5-7-1 Shiba, Minato-ku, Tokyo Within NEC Corporation

Claims (4)

[Claims] 1. A method for manufacturing a non-volatile semiconductor memory device, comprising: a first polycrystalline film forming step, a second polycrystalline film forming step, and a diffusion layer forming step, wherein the first polycrystalline film forming step is Forming a first gate insulating film in an element region on a semiconductor substrate, and then forming a first semiconductor polycrystalline thin film having an extremely thin semiconductor oxide film in the film on the surface of the semiconductor substrate; The polycrystalline film forming step includes the step of:
The step of forming a second gate insulating film and a second semiconductor polycrystalline thin film sequentially on the semiconductor substrate after ion-implanting an impurity for forming a conductive semiconductor film. A method of forming a source / drain diffusion layer by processing a stacked structure into a two-layer gate electrode shape and then implanting impurities using the gate electrode as a mask. . 2. A method for manufacturing a non-volatile semiconductor memory device, comprising: a first semiconductor thin film forming step, a second polycrystalline forming step, and a diffusion layer forming step, wherein the first semiconductor thin film forming step includes: After the first gate insulating film is formed in the upper element region, the first semiconductor thin film in an amorphous state is formed. The second polycrystalline forming step involves polycrystallization of the semiconductor thin film in the amorphous state. Before such a heat treatment is performed, ion implantation of impurities for converting the first semiconductor thin film into a first conductive type semiconductor film is performed, and then a second gate insulating film and a second gate insulating film are formed on the semiconductor substrate. The diffusion layer forming step is to process the laminated structure into the shape of a two-layer gate electrode, implant impurities using the gate electrode as a mask, and perform source / drain diffusion. layer A method for manufacturing a nonvolatile semiconductor memory device, characterized by forming a semiconductor device. 3. A method for manufacturing a non-volatile semiconductor memory device, comprising: a first polycrystal forming step; an ion implantation step; a second thin film forming step; and a diffusion layer forming step. Forming a first gate insulating film in a device region on a semiconductor substrate to form a first semiconductor polycrystalline thin film; and ion-implanting the first semiconductor thin film in a first conductive type. When performing ion implantation of impurities for forming the semiconductor film of the first embodiment, the impurities are implanted in a direction normal to the substrate so that the implanted impurities can cross two or more crystal grains in the first semiconductor thin film. Impurity ion implantation is performed at a sufficiently large angle with respect to the semiconductor substrate, and then a second gate insulating film and a second semiconductor thin film are sequentially formed on the semiconductor substrate. After processing into the shape of a two-layer gate electrode, A method for manufacturing a non-volatile semiconductor storage device, comprising a step of implanting impurities using a gate electrode as a mask to form source / drain diffusion layers. 4. A method for forming a first semiconductor single crystal thin film, comprising:
A non-volatile semiconductor storage device having a semiconductor thin film forming step and a diffusion forming, wherein the first semiconductor single crystal thin film forming step forms a first gate insulating film in an element region formed on a surface of a semiconductor substrate, Forming a first semiconductor thin film by a graphoepitaxy method, and irradiating a laser beam or the like to single crystallize the first semiconductor thin film. The second semiconductor thin film forming step includes the step of ionizing a first conductive impurity. Injection is performed, and then a second gate insulating film and a second semiconductor thin film are sequentially formed on the semiconductor substrate. The diffusion layer forming step includes: after processing the laminated structure into a shape of a two-layer gate electrode; A method of forming a source / drain diffusion layer by implanting impurities using the gate electrode as a mask.