JP2011109535A - Redundant pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress deviation of an output phase generated between a main line system and a redundant system, and to suppress change of the output phase in output changeover. <P>SOLUTION: The redundant PLL circuit includes: an 1/n frequency divider 11 for generating a 1/n (n is an optional natural number) times first frequency signal from a reference signal by a reference clock; PLL circuits 11, 12 for generating 1/m (m is an optional natural number) times second frequency signals from output signals of VCXO 121, 131 to be subjected to phase comparison with the first frequency signal generated by the 1/n frequency divider 11, and controlling the output frequencies of the VCXO 121, 131 based on the phase comparison results; and an output selection switch 14 for selectively deriving the outputs of the PLL circuits 11, 12. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a PLL (Phase Locked Loop) circuit that locks an oscillation output frequency at a frequency n / m (n and m are arbitrary numbers) times that of a reference signal based on a reference clock. About what to do.

  In an electronic device such as a communication device, a PLL circuit that locks an oscillation output frequency to a frequency n / m times a reference signal based on a reference clock is often used. In such a PLL circuit, the reference signal is multiplied by 1 / n with a 1 / n divider and the oscillator output signal is multiplied by 1 / m with a 1 / m divider to control the oscillator so that both are synchronized. .

  By the way, in the electronic device as described above, a redundant configuration of the PLL circuit is taken in order to avoid interruption of operation (see, for example, Patent Document 1). However, when the redundant configuration is formed by using two PLL circuits, the output phase Is synchronized with the phase of the 1 / n frequency divider that divides the reference frequency, so that a deviation occurs in the output phase of each oscillator due to the performance difference of each 1 / n frequency divider. If the output phase has a deviation in the redundant configuration as described above, the output phase changes abruptly when the output of the PLL circuit is switched, resulting in a great adverse effect on the supply destination circuit.

JP 2001-060864 A

  As described above, in a conventional PLL circuit having a redundant configuration, a deviation occurs in the output phase between the main line system and the redundant system, and the output phase changes abruptly when the output of the PLL circuit is switched.

  The object of the present invention is to solve the above problems, suppress the deviation of the output phase generated between the main system and the redundant system with a relatively simple circuit configuration, and suppress the change of the output phase at the time of output switching. An object of the present invention is to provide a redundant PLL circuit that can be used.

  In order to achieve the above object, the redundant PLL circuit according to the present invention includes a frequency divider that generates a first frequency signal 1 / n (n is an arbitrary natural number) times from a reference signal based on a reference clock, A second frequency signal of 1 / m (m is an arbitrary natural number) times is generated from the output signal and phase-compared with the first frequency signal generated by the frequency divider, and based on the phase comparison result, A plurality of PLL circuit units for controlling the output frequency of the oscillator, and an output selection unit for selectively deriving outputs of the plurality of PLL circuit units.

  In the redundant PLL circuit configured as described above, the reference signal is multiplied by 1 / n and then supplied to a plurality of PLL circuit units, so that no deviation occurs in the output phase of each PLL circuit unit.

  With the configuration as described above, according to the present invention, the output phase deviation between the main line system and the redundant system is suppressed with a relatively simple circuit configuration, and the change in the output phase is suppressed at the time of output switching. It is possible to provide a redundant PLL circuit.

1 is a block circuit diagram showing an embodiment of a redundant PLL circuit according to the present invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a specific configuration of an embodiment of a redundant PLL circuit according to the present invention. The redundant PLL circuit shown in FIG. 1 includes a 1 / n frequency divider 11 that generates a 1 / n times frequency signal from a reference signal (reference clock CKref). The 1 / n frequency divider 11 is shared by the two PLL circuit units 12 and 13 in a redundant configuration, and the 1 / n times frequency signal is sent to the first and second PLL circuit units 12 and 13. Supplied.

  The first PLL circuit section 12 has a 1 / m-fold clock of a PLL output clock CKout1 generated by an internal voltage controlled crystal oscillator (VCXO) 121 that is 1 / m times the reference clock CKref given from the outside. It has a speed change function that is synchronized with the n-times clock.

  Specifically, the signal S1 obtained by multiplying the reference clock CKref by 1 / n by the 1 / n frequency divider 11 is captured. On the other hand, the oscillation clock CKout1 generated by the VCXO 121 is multiplied by 1 / m by the 1 / m divider 122 (signal S2), and sent to the phase comparator 123 together with the signal S1 obtained by multiplying the reference clock CKref by 1 / n. The phase comparator 123 obtains the phase difference δ1 between the signal S1 obtained by dividing the reference clock CKref by 1 / n and the signal S2 obtained by dividing the output clock CKout1 by 1 / m at a constant period. The phase difference δ1 is sent to the signal processing unit 124. The signal processing unit 124 samples the input phase difference δ 1 at a predetermined interval and obtains a control voltage value corresponding to the phase difference by digital processing. The output is converted to an analog voltage by a D / A (digital / analog) conversion unit 125. This is converted and applied to the VCXO 121 as a control voltage of the oscillation frequency.

  The second PLL circuit unit 13 has a speed changing function that synchronizes a 1 / m-times clock of the PLL output clock CKout2 generated by the internal VCXO 131 with a 1 / n-times clock of a reference clock CKref given from the outside. Is provided.

  Specifically, the signal S1 obtained by multiplying the reference clock CKref by 1 / n by the 1 / n frequency divider 11 is captured. On the other hand, the oscillation clock CKout2 generated by the VCXO 131 is multiplied by 1 / m by the 1 / m frequency divider 132 (signal S2 ') and sent to the phase comparator 133 together with the signal S1 obtained by multiplying the reference clock CKref by 1 / n. The phase comparator 133 obtains the phase difference δ2 between the signal S1 obtained by dividing the reference clock CKref by 1 / n and the signal S2 ′ obtained by dividing the output clock CKout2 by 1 / m at a constant period. The phase difference δ 2 is sent to the signal processing unit 134. This signal processing unit 134 samples the input phase difference δ2 at regular intervals and obtains a control voltage value corresponding to the phase difference by digital processing. The output is converted to an analog voltage by a D / A (digital / analog) conversion unit 135. It is converted and applied to the VCXO 131 as a control voltage of the oscillation frequency.

  The VCXO outputs of the first and second PLL circuit units 12 and 13 can be selectively output by the output selection switch 14 at an arbitrary timing.

  The operation of the redundant PLL circuit having the above configuration will be described.

  First, in the redundant configuration in the conventional PLL circuit, since the 1 / n times signal of the reference clock CKref is individually generated in each PLL circuit unit, the period position of the 1 / n divided output between the PLL circuit units is When the PLL circuit output is switched, a phase difference of ± π radians of the PLL output frequency is generated at the maximum.

  On the other hand, in the redundant PLL circuit shown in FIG. 1, the 1 / n frequency divider 11 is shared and arranged outside the redundant configuration. In this case, since the circuit scale of the 1 / n frequency divider is small, reliability can be maintained as a common element. According to this configuration, since both the first PLL circuit unit 12 and the second PLL circuit unit 13 are locked to the output of the 1 / n frequency divider 11, the frequency division of the 1 / m frequency dividers 122 and 132 is performed. The output phase matches regardless of the phase. For this reason, even if redundant switching is performed, phase fluctuation due to switching can be prevented.

  Therefore, according to the redundant PLL circuit having the above-described configuration, it is possible to suppress the deviation of the output phase generated between the main line system and the redundant system with a relatively simple circuit configuration, and to suppress the change of the output phase at the time of output switching. .

  The present invention suppresses phase fluctuations caused by redundant switching in order to realize a redundant configuration, particularly in an electronic device using a PLL circuit that converts the speed of a high-precision reference signal such as a ruby resume signal source to n / m times. Can be used, so the utility value is very high. In principle, since the transmission path length between the 1 / n frequency divider 11 and the PLL circuit units 12 and 13 is affected, the mounting position should be considered.

  In addition, you may implement each embodiment suitably combining as much as possible, and the combination effect is acquired in that case. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be obtained as an invention.

  DESCRIPTION OF SYMBOLS 11 ... 1 / n frequency divider, 12 ... 1st PLL circuit part, 121 ... Voltage controlled crystal oscillator (VCXO), 122 ... 1 / m frequency divider, 123 ... Phase comparator, 124 ... Signal processing part, 125 DESCRIPTION OF SYMBOLS ... D / A converter, 13 ... 2nd PLL circuit part, 131 ... Voltage control crystal oscillator (VCXO), 132 ... 1 / m frequency divider, 133 ... Phase comparator, 134 ... Signal processing part, 135 ... D / A converter, 14 ... Output selection switch.

Claims (1)

A frequency divider that generates a first frequency signal that is 1 / n (n is an arbitrary natural number) times from a reference signal based on a reference clock, and a first frequency that is 1 / m (m is an arbitrary natural number) times from an output signal of the oscillator. A plurality of PLL circuit units that generate two frequency signals and perform phase comparison with the first frequency signal generated by the divider, and control the output frequency of the oscillator based on the phase comparison result; A redundant PLL circuit comprising: an output selection unit that selectively derives an output of the PLL circuit unit of

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