JP6111739B2 - Clock skew correction circuit, correction method thereof, and clock distribution device - Google Patents

Description

  The present invention relates to a clock skew correction circuit that corrects clock skew between different clock distribution systems.

A logic circuit often performs a synchronous operation using a clock. Since the clock is widely distributed in the logic circuit, a phase difference of the clock, so-called “clock skew” occurs between the distributed clocks. In a synchronous circuit using a clock, it is desirable that the clock skew is as small as possible. Since the clock skew has a greater influence on the operation of the logic circuit as the clock speed increases, it is necessary to reduce the clock skew.
Here, there is a problem that the clock skew increases as the physical scale of the circuit increases. For example, in a semiconductor integrated circuit, when the chip size increases, the difference between the longest wiring length and the shortest wiring length increases in the clock distribution wiring from the clock supply source to the clock supply destination. For this reason, the variation in the transmission delay time from the clock supply source to the clock supply destination increases, and the clock skew increases.

  On the other hand, in a circuit using a high-speed clock, a PLL (Phase Locked Loop) circuit may be used to multiply a low-speed clock to a high-speed clock. The PLL circuit uses a low-speed clock as an input signal and outputs a multiplied high-speed clock. The high-speed clock output from the PLL circuit is distributed to various parts of the logic circuit by the clock distribution circuit, and the clock is fed back to the PLL circuit from the end of the distribution system. In the PLL circuit, the frequency and phase of the high-speed clock that is the output are adjusted so that the phase of the low-speed clock that is the input matches the phase of the feedback clock.

  When a plurality of clock distribution systems are configured using a plurality of PLL circuits, data may be synchronously transferred between different clocks. At this time, the low-speed clock is distributed to each PLL circuit, but the distribution circuit is configured so that the phases at the input points of each PLL circuit are equal. In the PLL circuit, this low-speed clock is used as a reference clock, and the output high-speed clock is controlled so that the feedback clock fed back from the distribution system end matches the phase of the reference clock. With this configuration, the phases of different clocks are matched, so that synchronous transfer is possible.

  In the clock distribution method described in Patent Document 1, the output signal of the phase difference detector arranged at the end of the distribution system is input to the delay circuit on the feedback clock of the PLL circuit that is the clock output circuit, and the output of the PLL circuit Correct the clock. This reduces the clock skew between different clocks.

JP 2010-224717 A

However, in the technique for reducing the clock skew disclosed in Patent Document 1, feedback from the phase difference detection unit at the end of the distribution system is fed back into the loop of the PLL circuit. For this reason, a double loop configuration is formed, and an unstable operation may occur as a clock distribution system.
The present invention has been made in view of such circumstances, and an object of the present invention is to provide a technique for correcting clock skew that works so that a clock distribution system operates stably.

  One aspect of the clock skew correction circuit according to the present invention is a clock skew correction circuit that corrects clock skew between different clock distribution systems, and includes a delay unit, a phase difference detection unit, a control unit, and an oscillation detection unit. The delay unit receives the reference clock signal, adjusts the delay of the reference clock signal, and outputs the adjusted signal to each clock distribution system. The phase difference detection unit detects a phase difference between different clock signals output from the different clock distribution systems and outputs a phase difference signal. The control unit receives the phase difference signal and sets a delay amount for the delay unit to adjust the reference clock signal in accordance with the phase difference signal. The oscillation detection unit receives the phase difference signal and outputs an operation switching signal for adjusting the operation state of the control unit based on the phase difference signal to the control unit.

  The correction method of the clock skew correction circuit according to the present invention is a method of correcting the clock skew between the clock distribution systems, and the clock skew correction circuit performs the following steps. A step of inputting a reference clock signal, adjusting a delay of the reference clock signal using a delay circuit, and outputting the delay to each clock distribution system; Detecting a phase difference between different clock signals output from the different clock distribution systems to generate a phase difference signal. Setting a delay amount for adjusting the reference clock signal in accordance with the phase difference signal; Adjusting an operating frequency for outputting the control signal based on the phase difference signal when outputting a control signal for setting the set delay amount to the delay circuit;

  Furthermore, a clock distribution device according to the present invention includes different clock distribution systems that distribute clock signals to different distribution systems, and the above-described clock skew correction circuit.

  According to the present invention, it is possible to provide a clock skew correction circuit and a method thereof that work so that the clock distribution system operates stably.

It is a block diagram which shows the structural example of the clock skew correction circuit of one Embodiment. 1 is a block diagram illustrating a configuration of a clock distribution system including a clock skew correction circuit according to a first embodiment. 1 is a block diagram illustrating a configuration example of a phase difference detection circuit according to a first embodiment. It is a block diagram which shows the structural example of the phase difference detection circuit of 2nd Embodiment. It is a block diagram which shows the structural example of the clock distribution system containing the clock skew correction circuit of 3rd Embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. In the drawings, components having the same configuration or function and corresponding parts are denoted by the same reference numerals and description thereof is omitted.

FIG. 1 is a block diagram illustrating a configuration example of a clock skew correction circuit 10 according to an embodiment. The clock skew correction circuit 10 includes a delay unit 11, a phase difference detection unit 12, a control unit 13, and an oscillation detection unit 14. The clock skew correction circuit 10 transmits / receives signals to / from different clock distribution systems. Therefore, FIG. 1 shows a different clock distribution system 20, and in the following description, a description will be given using a case where the different clock distribution systems 20 include a first distribution system and a second distribution system.
The delay unit 11 receives the reference clock signal, adjusts the delay of the reference clock signal, and outputs it to each clock distribution system (first and second clock distribution systems).
The phase difference detection unit 12 detects a phase difference between different clock signals output from different clock distribution systems 20 and outputs a phase difference signal.
The control unit 13 receives the phase difference signal, determines a delay amount to be notified to the delay unit 11 according to the phase difference signal, and outputs the control signal to the delay unit 11. The control signal is a signal indicating the delay amount, and is a signal for notifying the delay amount by which the delay unit 11 adjusts the delay of the reference clock signal.
The oscillation detection unit 14 receives the phase difference signal and adjusts the operation state of the control unit 13 based on the phase difference signal. Specifically, the oscillation detection unit 14 switches the operating frequency of the clock used when the control unit 13 outputs a control signal when the phase difference signal from the phase difference detection unit 12 repeats advance and delay.

  In the clock skew correction circuit 10 according to the embodiment, the oscillation detection unit 14 switches the operation frequency of the control unit 13, so that the feedback constant of the PLL circuit included in the different clock distribution system 20 and the reference clock signal are supplied to the delay unit 11. Set a different feedback constant for feedback. This makes it possible to form a loop in which the clock signal output from the end of the clock distribution system to the PLL circuit and the control signal output from the control unit 13 to the delay unit 11 are fed back at different operating frequencies. Become. As a result, different clock distribution systems 20 can operate stably.

As described above, the clock skew correction circuit according to one embodiment is arranged in a semiconductor integrated circuit having at least two clock distribution systems and realizes the following functions.
A phase difference between different clock distribution systems is detected with respect to clock skew between different clock distribution systems, and a phase difference signal is output (phase difference detection unit 12).
The delay of the reference clock signal of each clock distribution system is adjusted by a delay circuit (delay unit 11).
The delay value of the delay circuit is set using the phase difference signal as an input (control unit 13).
• An unstable operation of the entire clock distribution system is detected using the phase difference signal as an input, and the operation (operation frequency) of the control circuit is set (oscillation detector 14).
Each embodiment will be described below using a specific configuration example.

First embodiment.
* Configuration of First Embodiment A configuration of the first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 2 is a block diagram showing an example of the configuration of the clock distribution system (clock distribution device 100) including the clock skew correction circuit of this embodiment. As a basic configuration of the clock distribution system (clock distribution circuit) of this embodiment, a first PLL circuit (first PLL) 105, a first clock distribution circuit 107, and a second PLL circuit (second PLL) 106 are used. , And a second clock distribution circuit 108. The clock skew correction circuit includes a phase difference detection circuit 110, a control circuit 120, an oscillation detection circuit 130, a first delay circuit 103, and a second delay circuit 104.

The first delay circuit 103 has a reference clock (hereinafter referred to as REF0) as an input, delays the phase with respect to REF0, and outputs a clock (hereinafter referred to as REF1) that is input to the first PLL circuit 105. To do.
The first PLL circuit 105 inputs REF1 and one of the end clocks of the first clock distribution circuit 107 (hereinafter referred to as CLK1F) and outputs a first output clock (hereinafter referred to as CLK1). To do.
The first clock distribution circuit 107 receives CLK1 as an input, splits CLK1 a plurality of times, and distributes it to a large number of circuits operating in synchronization with CLK1 with equal delay (small skew).
By feeding back CLK1F to the first PLL circuit 105 among these clocks at the end of the distribution system, the first PLL circuit 105 adjusts the phase of CLK1 so that the phase of REF1 matches the phase of CLK1F. With this function, REF1 and the clock at the end of the first clock distribution circuit 107 are in phase.

The second delay circuit 104 receives the reference clock REF0, delays the phase with respect to REF0, and outputs a clock that is input to the second PLL circuit 106 (hereinafter referred to as REF2).
The second PLL circuit 106 inputs REF2 and one of the end clocks of the second clock distribution circuit 108 (hereinafter referred to as CLK2F) and outputs a second output clock (hereinafter referred to as CLK2). To do.
The second clock distribution circuit 108 receives CLK2 as an input, branches the CLK2 a plurality of times, and distributes it to a large number of circuits operating in synchronization with the CLK2 with equal delay (small skew).
By feeding back CLK2F to the second PLL circuit 106 among these clocks at the end of the distribution system, the second PLL circuit 106 adjusts the phase of CLK2 so that the phase of REF2 matches the phase of CLK2F. With this function, REF2 and the clock at the end of the second clock distribution circuit 108 are in phase.

The phase difference detection circuit 110 receives the clock CLK1P distributed by the first clock distribution circuit 107 and the clock CLK2P distributed by the second clock distribution circuit 108, detects the phase difference between the two clocks, Phase difference signals SKWA and SKWB are output.
The control circuit 120 receives the phase difference signals SKWA and SKWB, and sets a delay amount of the first delay circuit 103 and the second delay circuit 104 according to the values (hereinafter, referred to as CNTDLY as appropriate). Is output.
The oscillation detection circuit 130 receives the phase difference signals SKWA and SKWB, and when the phase difference signals SKWA and SKWB repeat the early phase and the late phase, an operation switching signal (hereinafter referred to as appropriate). Output as OSC).

  2, the basic configuration of the clock distribution system, specifically, the first PLL circuit 105, the first clock distribution circuit 107, the second PLL circuit 106, and the second clock distribution circuit 108 are the same as those in FIG. 2 shows an example of a clock distribution system 20 having different clocks. The phase difference detection circuit 110, the control circuit 120, the oscillation detection circuit 130, the first delay circuit 103, and the second delay circuit 104 in FIG. 2 are examples of the clock skew correction circuit 10 in FIG. The first and second delay circuits 103 and 104 correspond to the delay unit 11 in FIG.

FIG. 3 is a block diagram illustrating a configuration example of the phase difference detection circuit 110 according to the present embodiment. The phase difference detection circuit 110 of this embodiment includes a delay circuit 111 (first delay adjustment circuit) that changes the phase of the input clock CLK1P, a delay circuit 112 (second delay adjustment circuit) that changes the phase of the input clock CLK2P, and 2 Two flip-flops (FF) 113 and 114 are provided.
The delay circuit 111 receives CLK1P and outputs a clock (hereinafter referred to as CLK1D) obtained by delaying CLK1P for a certain time. The delay circuit 112 receives CLK2P and outputs a clock obtained by delaying CLK2P for a certain time (hereinafter referred to as CLK2D). The flip-flop 113 (first flip-flop) receives CLK1D as a data input, receives CLK2P as a clock input, and outputs a phase difference signal SKWA. The flip-flop 114 (second flip-flop) receives CLK2D as a data input, receives CLK1P as a clock input, and outputs a phase difference signal SKWB.

* Description of Operation of First Embodiment The operation of the first embodiment of the present invention will be described. When performing synchronous transfer of data between different clock distribution systems, it is necessary to distribute the reference clock to each PLL circuit in the same phase. That is, REF1 and REF2 are in phase. Further, the terminal clock of the first clock distribution circuit 107 is in phase with REF1 by feeding back CLK1F to the first PLL circuit 105. The terminal clock of the second clock distribution circuit 108 is in phase with REF2 by feeding back CLK2F to the second PLL circuit 106. That is, the terminal clock of the first clock distribution circuit 107 and the terminal clock of the second clock distribution circuit 108 are in phase.
However, accumulation of delay errors in design, delay differences due to manufacturing variations, delay differences caused by temperature changes during system operation, and the like increases the clock skew between different clocks.

The phase difference detection circuit 110 of the present embodiment receives CLK1P and CLK2P and outputs phase difference signals SKWA and SKWB. When the phase of CLK2P is late with respect to the phase of CLK1P, a phase difference signal (SKWA, SKWB) = (1, 0) is output. Conversely, when the phase of CLK2P is earlier than the phase of CLK1P, a phase difference signal (SKWA, SKWB) = (0, 1) is output. When the difference between the phase of CLK1P and the phase of CLK2P is within a certain delay range, a phase difference signal (SKWA, SKWB) = (0, 0) is output. The delay range at this time is the sum of the delay amount of the delay circuit 111 and the delay amount of the delay circuit 112, and this delay range is called a dead zone of the phase difference detection circuit 110.
The clock has jitter whose phase changes dynamically. For this reason, if the dead zone width of the phase difference detection circuit 110 is set to 0, the phase difference signal may become unstable due to the influence of jitter. Therefore, a dead zone is set using a delay circuit.

Next, the control circuit 120 receives the phase difference signals SKWA and SKWB, and increases the delay amount of the first delay circuit 103 when the phase difference signal SKWA is “1” (SKWA = 1). When SKWB is “1” (SKWB = 1), CNTDLY is output so that the delay amount of the second delay circuit 104 is increased. When both the phase difference signal SKWA and the phase difference signal SKWB are “0”, the delay amounts of the first delay circuit 103 and the second delay circuit 104 are not changed.
Here, since the feedback loop to the reference clock and the feedback loop of the PLL circuit have a double loop structure, an unstable operation may occur as a clock distribution system. In order to suppress the unstable operation, it is necessary to make the loop constant of the feedback to the reference clock sufficiently larger than the loop constant of the PLL circuit. Therefore, a frequency switching circuit is provided in the control circuit 120, and the frequency switching circuit holds a mode for switching the operating frequency of the clock signal that outputs the control signal. If the operation is unstable, the mode of the frequency switching circuit is switched to lower the operating frequency of the control signal (CNTLY).
The feedback to the reference clock is feedback from the control circuit 120 to the first delay circuit 103 and the second delay circuit 104. The feedback of the PLL circuit is feedback from the terminal of the distribution circuit to the PLL circuit. Specifically, the feedback from the first clock distribution circuit 107 to the first PLL circuit 105 and the second clock distribution circuit. Feedback from 108 to the second PLL circuit 106 is included.

  The oscillation detection circuit 130 monitors how the phase difference signals SKWA and SKWB change, and when the phase difference signals (SKWA and SKWB) repeat the states of (1, 0) and (0, 1), In other words, it is considered that the operation is not stable when the advance and the delay are repeated. Then, the oscillation detection circuit 130 switches the mode of the frequency switching circuit in the control circuit 120 by the operation switching signal (OSC), and lowers the operating frequency.

* Explanation of effect Regarding the clock skew between multiple clock distribution systems, adjust the phase of the reference clock not only due to the design delay difference, but also the clock skew caused by manufacturing variations and temperature changes during operation. Can be reduced.
In this embodiment, regarding the possibility of unstable operation due to the double loop configuration, the oscillation detection circuit detects the unstable operation and changes the phase adjustment frequency of the feedback loop to the reference clock. As a result, the feedback constant difference between the feedback loop to the reference clock and the feedback loop to the PLL circuit can be increased, and the operation can be stabilized.

As described above, in the first embodiment of the present invention, the clock distribution method realized by the clock distribution apparatus 100 includes the following components shown in FIG. 2 that embody the clock skew correction circuit 10 of FIG.
A phase difference detection circuit 110 that detects a phase difference between different clocks in different clock distribution systems.
A first delay circuit 103 that makes the phase of the clock REF1 input to the first PLL circuit 105, which is a clock output circuit, variable.
A second delay circuit 104 that makes the phase of the clock REF2 input to the second PLL circuit 106, which is a clock output circuit, variable.
A control circuit 120 that receives the output signal of the phase difference detection circuit 110 as an input and sets the delay amounts of the first delay circuit 103 and the second delay circuit 104.
An oscillation detection circuit 130 that adjusts the operating frequency of the control circuit 120 using the output signal of the phase difference detection circuit 110 as an input.

The phase difference detection circuit 110 at the end of the clock distribution system detects a phase difference between CLK1P and CLK2P distributed by different clock distribution systems, and outputs a phase difference signal. In accordance with this phase difference signal, the control circuit 120 sets the delay amounts of the first delay circuit 103 and the second delay circuit 104 so that the clock skew between different clocks is reduced.
Here, the loop formed by the feedback from the phase difference detection circuit 110 at the end of the distribution system to the reference clock and the loop of the PLL circuit have a double loop structure. When it is detected that the output signal of the first and second output circuits repeats a state where the phase is early and a phase is late, the operating frequency of the control circuit 120 for setting the first delay circuit 103 and the second delay circuit 104 is lowered to reduce the clock. It is characterized by preventing unstable operation of the distribution system.

Second embodiment.
* Configuration of Second Embodiment A configuration of the second embodiment of the present invention will be described. FIG. 4 is a block diagram illustrating a configuration example of the phase difference detection circuit 210 of the present embodiment. The phase difference detection circuit 210 according to the present embodiment includes a delay adjustment circuit 211 (first delay adjustment circuit) capable of switching the phase of the input clock CLK1P, and a delay adjustment circuit 212 (second delay circuit) capable of switching the phase of the input clock CLK2P. Delay adjustment circuit), and two flip-flops (FF) 113 and 114.

  The delay adjustment circuit 211 receives CLK1P and outputs a clock CLK1D obtained by delaying CLK1P by a value set by a delay switching signal (hereinafter referred to as CNTDZ). The delay adjustment circuit 212 receives CLK2P and outputs a clock CLK2D obtained by delaying CLK2P by a value set by the delay switching signal CNTDZ. The flip-flop 113 receives CLK1D as a data input, receives CLK2P as a clock input, and outputs a phase difference signal SKWA. The flip-flop 114 receives CLK2D as a data input, receives CLK1P as a clock input, and outputs a phase difference signal SKWB.

* Description of Operation of Second Embodiment The operation of the second embodiment of the present invention will be described. The phase matching operation between different clock distribution systems, which is the basic operation as the clock distribution system, is the same as that in the first embodiment, and the description thereof is omitted.
In the phase difference detection circuit 210 of this embodiment, CLK1P and CLK2P are input and phase difference signals SKWA and SKWB are output. When the phase of CLK2P is late with respect to the phase of CLK1P, a phase difference signal (SKWA, SKWB) = (1, 0) is output. Conversely, when the phase of CLK2P is earlier than the phase of CLK1P, a phase difference signal (SKWA, SKWB) = (0, 1) is output. When the phase of CLK1P and the phase of CLK2P are within an arbitrary delay range, a phase difference signal (SKWA, SKWB) = (0, 0) is output. The arbitrary delay range at this time is the dead band width of the phase difference detection circuit 210, and is determined by the sum of the delay amount of the delay adjustment circuit 211 and the delay amount of the delay adjustment circuit 212. The present embodiment is characterized in that the dead band width of the phase difference detection circuit 210 can be adjusted by the delay switching signal CNTDZ.

Next, the control circuit 120 receives the phase difference signals SKWA and SKWB, and when the phase difference signal SKWA is “1” (SKWA = 1), the delay amount of the first delay circuit 103 is increased, and the phase difference signal When SKWB is “1” (SKWB = 1), the delay amount of the second delay circuit 104 is increased.
Here, since the feedback loop to the reference clock and the feedback loop of the PLL circuit have a double loop structure, an unstable operation may occur as a clock distribution system. Therefore, the oscillation detection circuit 130 monitors how the phase difference signals SKWA and SKWB change, and the phase difference signals (SKWA and SKWB) repeat the states of (1, 0) and (0, 1). It is considered that the operation is not stable. The oscillation detection circuit 130 outputs an operation switching signal OSC to the control circuit 120. When the control circuit 120 receives the operation switching signal OSC, in addition to switching the operating frequency, the control circuit 120 outputs a dead band switching signal CNTDZ to widen the dead band of the phase difference detection circuit 210. By widening the dead band width, the event probability that the phase difference signal (SKWA, SKWB) = (0, 0) is increased and the delay value switching operation is reduced, which leads to stabilization of the operation.

  In the above description of the operation, the case where the control circuit 120 outputs the dead band switching signal CNTDZ has been described. However, the present invention is not limited to this. For example, the oscillation detection circuit 130 may output the dead band switching signal CNTDZ in addition to outputting the operation switching signal OSC to the control circuit 120. In other words, based on the phase difference signal (SKWA, SKWB) output from the phase difference detection circuit 210, it is determined whether or not the clock distribution system may cause an unstable operation, and the dead zone is determined according to the determination result. What is necessary is just to be comprised so that the width switching signal CNTDZ may be output.

* Explanation of effect Regarding the clock skew between multiple clock distribution systems, adjust the phase of the reference clock not only due to the design delay difference, but also the clock skew caused by manufacturing variations and temperature changes during operation. Can be reduced.
In the present embodiment, regarding the possibility of unstable operation due to the double loop configuration, the oscillation detection circuit detects the unstable operation and widens the dead band of the phase difference detection circuit. As a result, the operation can be stabilized.

Third embodiment.
* Configuration of Third Embodiment A configuration of the third embodiment of the present invention will be described. FIG. 5 is a block diagram showing an example of the configuration of the clock distribution system (clock distribution device 300) including the clock skew correction circuit of this embodiment. The basic configuration of the clock distribution system of the present embodiment includes a first PLL circuit 305, a first clock distribution circuit 107, a second PLL circuit 306, and a second clock distribution circuit 108. As a clock skew correction circuit, A phase difference detection circuit 110, a control circuit 320, an oscillation detection circuit 130, a first delay circuit 103, a second delay circuit 104, and a lock determination circuit 301 are provided.
The configuration of the present embodiment is characterized in that a lock determination circuit 301 is provided with respect to the configuration of the first embodiment or the second embodiment. FIG. 5 shows a configuration example in which the lock determination circuit 301 is provided in the configuration of the first embodiment, but the configuration of the second embodiment can be similarly provided.

The first PLL circuit 305 outputs a lock signal LCK1 in addition to the function realized by the first PLL circuit 105 of the first embodiment.
The second PLL circuit 306 outputs a lock signal LCK2 in addition to the function realized by the second PLL circuit 106 of the first embodiment.
The lock signals LCK1 and LCK2 are obtained when the first PLL circuit 305 or the second PLL circuit 306 is in a locked state, in other words, the PLL circuit is in a stable state, and two input clock signals (REF1 and CLK1F or REF2) CLK2F) is a signal indicating that the phases are the same.
The lock determination circuit 301 receives the lock signal LCK1 output from the first PLL circuit 105 and the lock signal LCK2 output from the second PLL circuit 106, and determines whether both LCK1 and LCK2 are in the locked state. And a signal for operating the control circuit 120 (hereinafter referred to as CNTLCK) is output based on the determination result.
In addition to the function realized by the control circuit 120 of the first embodiment, the control circuit 320 maintains a stopped state when CNTLCK is output from the lock determination circuit 301, and starts operation when CNTLCK is output. Configured.

* Description of Operation of Third Embodiment The operation of the third embodiment of the present invention will be described. The phase matching operation between different clock distribution systems, which is the basic operation as the clock distribution system, is the same as that in the first embodiment, and the description thereof is omitted.
The lock determination circuit 301 of the present embodiment receives the lock signal LCK1 output from the first PLL circuit 105 and the lock signal LCK2 output from the second PLL circuit 106, and both LCK1 and LCK2 are in the locked state. In this case, CNTLCK is output. That is, when either the first PLL circuit 105 or the second PLL circuit 106 is not locked, the delay adjustment according to the result of the phase difference detection is not performed.
This represents a case where each PLL circuit is being initialized at the time of system startup or a case where the PLL circuit is unlocked during system operation, until all the PLL circuits are in a stable state (locked state). This means that the skew correction function is stopped.

* Explanation of effect Regarding the clock skew between multiple clock distribution systems, adjust the phase of the reference clock not only due to the design delay difference, but also the clock skew caused by manufacturing variations and temperature changes during operation. Can be reduced.

  The clock skew correction circuit of the above-described embodiment can be applied to a system having a plurality of clock distribution systems, and in particular, to a system in which data is synchronously transferred between clocks of different clock distribution systems. Can do.

In addition, this invention is not limited to embodiment shown above. Within the scope of the present invention, it is possible to change, add, or convert each element of the above-described embodiment to a content that can be easily considered by those skilled in the art. For example, the present invention can take the following forms.
(Appendix 1)
A clock skew correction circuit for correcting clock skew between different clock distribution systems,
A delay unit that takes a reference clock signal as input, adjusts the delay of the reference clock signal, and outputs it to each clock distribution system;
A phase difference detector that detects a phase difference between different clock signals output from the different clock distribution systems and outputs a phase difference signal;
A control unit configured to input the phase difference signal and set a delay amount by which the delay unit adjusts the reference clock signal according to the phase difference signal;
A clock skew correction circuit comprising: an oscillation detection unit that receives the phase difference signal and outputs an operation switching signal that adjusts an operation state of the control unit based on the phase difference signal to the control unit.
(Appendix 2)
The phase difference detector
A first flip-flop that delays one of the different clock signals and samples with the other clock signal;
A second flip-flop that delays the other clock signal and samples with the one clock signal;
A first delay adjustment circuit for delaying the one clock signal;
A second delay adjustment circuit for delaying the other clock signal,
The clock skew correction circuit according to appendix 1, wherein the first and second delay adjustment circuits are configured to be able to change a delay amount from the outside in accordance with the phase difference signal.
(Appendix 3)
When the control unit receives the operation switching signal from the oscillation detection unit, the control unit switches an operation frequency for outputting a control signal for setting a delay amount for adjusting the reference clock signal, and the first and second delay adjustments The clock skew correction circuit according to appendix 2, wherein the clock skew correction circuit operates to change a delay amount of the circuit.
(Appendix 4)
4. The clock skew correction circuit according to appendix 3, wherein the control unit increases a delay amount of the first and second delay adjustment circuits when the phase difference signal repeats delay and advance.
(Appendix 5)
5. The clock skew correction circuit according to appendix 4, wherein the oscillation detection unit functions to change a delay amount of the first and second delay adjustment circuits according to the phase difference signal.
(Appendix 6)
6. The clock skew correction circuit according to appendix 5, wherein the oscillation detection unit increases a delay amount of the first and second delay adjustment circuits when the phase difference signal repeats delay and advance.
(Appendix 7)
When different clock signals output from the different clock distribution systems are in a stable state, the controller operates to operate, and at least one of the different clock signals output from the different clock distribution systems is in a stable state. The clock skew correction circuit according to any one of appendices 1 to 6, further comprising: a lock determination unit that operates to stop the operation of the control unit if not reached.
(Appendix 8)
The lock determination unit receives a lock signal indicating a stable state from a PLL circuit included in each clock distribution system, and stops the operation of the control unit until lock signals are received from all of the different clock distribution systems. The clock skew correction circuit according to appendix 7, wherein the control unit is operated when a lock signal is received from all of the different clock distribution systems.
(Appendix 9)
A clock skew correction circuit correction method for correcting clock skew between different clock distribution systems,
The clock skew correction circuit includes:
Using the reference clock signal as input, adjusting the delay of the reference clock signal using a delay circuit and outputting it to each clock distribution system,
Detecting a phase difference between different clock signals output from the different clock distribution systems to generate a phase difference signal;
Set a delay amount to adjust the reference clock signal according to the phase difference signal,
A clock skew correction circuit correction method for adjusting an operating frequency for outputting the control signal based on the phase difference signal when outputting a control signal for setting the set delay amount to the delay circuit.
(Appendix 10)
The clock skew correction circuit has phase difference detection means for outputting a phase difference detection signal,
The phase difference detecting means includes
A first flip-flop that delays one of the different clock signals and samples with the other clock signal;
A second flip-flop that delays the other clock signal and samples with the one clock signal;
A first delay adjustment circuit for delaying the one clock signal;
A second delay adjustment circuit for delaying the other clock signal,
The first and second delay adjustment circuits are configured to be able to change a delay amount from the outside according to the phase difference signal,
The phase difference detection means changes the width of the dead zone generated by the delay amount set in the first and second delay adjustment circuits according to the phase difference signal detected last time, and outputs the phase difference signal. 10. The clock skew correction method according to appendix 9, wherein the clock skew correction method is detected.
(Appendix 11)
Different clock distribution systems that distribute clock signals to different systems;
A delay unit that takes a reference clock signal as input, adjusts the delay of the reference clock signal, and outputs it to each clock distribution system;
A phase difference detector that detects a phase difference between different clock signals output from the different clock distribution systems and outputs a phase difference signal;
A control unit configured to input the phase difference signal and set a delay amount by which the delay unit adjusts the reference clock signal according to the phase difference signal;
A clock distribution device comprising: an oscillation detection unit that receives the phase difference signal as input and adjusts an operation state of the control unit based on the phase difference signal.
(Appendix 12)
The different clock distribution systems are:
A first PLL circuit having the output of the delay unit as one input;
A first distributor for distributing the output of the first PLL and outputting a terminal clock signal to the other input of the first PLL circuit;
A second PLL circuit using the output of the delay unit as one input;
A second distributor for distributing the output of the second PLL and outputting a terminal clock signal to the other input of the second PLL circuit;
The phase difference detection unit detects a phase difference between the output of the first distribution unit and the output of the second distribution unit, and generates the phase difference signal.
When the phase difference signal repeats advance and delay, the oscillation detection unit outputs an operation frequency at which the control unit outputs a control signal for setting a delay amount from an operation frequency of the first and second PLL circuits. The clock distribution device according to appendix 11, wherein the clock distribution device is lowered.
(Appendix 13)
The phase difference detector
A first flip-flop that delays one of the different clock signals and samples with the other clock signal;
A second flip-flop that delays the other clock signal and samples with the one clock signal;
A first delay adjustment circuit for delaying the one clock signal;
A second delay adjustment circuit for delaying the other clock signal,
13. The clock skew correction circuit according to appendix 12, wherein the first and second delay adjustment circuits are configured to be able to change a delay amount from the outside according to the phase difference signal.
(Appendix 14)
When different clock signals output from the different clock distribution systems are in a stable state, the controller operates to operate, and at least one of the different clock signals output from the different clock distribution systems is in a stable state. The clock skew correction circuit according to any one of Supplementary Note 11 to Supplementary Note 13, further comprising: a lock determination unit that operates to stop the operation of the control unit when not reached.

DESCRIPTION OF SYMBOLS 10 Clock skew correction circuit 11 Delay part 12 Phase difference detection part 13 Control part 14 Oscillation detection part 20 Different clock distribution system 100, 300 Clock distribution apparatus 103 1st delay circuit 104 2nd delay circuit 105, 305 1st PLL Circuits 106 and 306 Second PLL circuit 107 First clock distribution circuit 108 Second clock distribution circuit 110 and 210 Phase difference detection circuit 111 and 112 Delay circuit 113 and 114 Flip-flop 120 and 320 Control circuit 130 Oscillation detection circuit 211 212 Delay adjustment circuit 301 Lock determination circuit

Claims (10)

A clock skew correction circuit for correcting clock skew between different clock distribution systems,
A delay unit that takes a reference clock signal as input, adjusts the delay of the reference clock signal, and outputs it to each clock distribution system;
Phase difference detection means for detecting a phase difference between different clock signals output from the different clock distribution systems and outputting a phase difference signal;
Control means for setting the delay amount by which the delay means adjusts the reference clock signal according to the phase difference signal, the phase difference signal as an input;
A clock skew correction comprising: an oscillation detection means for receiving the phase difference signal as an input and outputting an operation switching signal for adjusting an operating frequency of the control means to the control means when the phase difference signal repeats delay and advance. circuit. The phase difference detecting means includes
A first flip-flop that delays one of the different clock signals and samples with the other clock signal;
A second flip-flop that delays the other clock signal and samples with the one clock signal;
A first delay adjustment circuit for delaying the one clock signal;
A second delay adjustment circuit for delaying the other clock signal,
2. The clock skew correction circuit according to claim 1, wherein the first and second delay adjustment circuits are configured to be able to change a delay amount from the outside in accordance with the phase difference signal.   When the control means receives the operation switching signal from the oscillation detection means, the control means switches an operating frequency for outputting a control signal for setting a delay amount for adjusting the reference clock signal, and the first and second delay adjustments. 3. The clock skew correction circuit according to claim 2, wherein the clock skew correction circuit functions to change a delay amount of the circuit.   4. The clock skew correction circuit according to claim 3, wherein said control means increases the delay amount of said first and second delay adjustment circuits when said phase difference signal repeats delay and advance.   5. The clock skew correction circuit according to claim 4, wherein the oscillation detection means functions to change a delay amount of the first and second delay adjustment circuits in accordance with the phase difference signal.   6. The clock skew correction circuit according to claim 5, wherein the oscillation detection means increases the delay amount of the first and second delay adjustment circuits when the phase difference signal repeats delay and advance.   When different clock signals output from the different clock distribution systems are in a stable state, the control means is operated to operate, and at least one of the different clock signals output from the different clock distribution systems is in a stable state. The clock skew correction circuit according to any one of claims 1 to 6, further comprising a lock determination unit that operates to stop the operation of the control unit when not reached.   The lock determination unit receives a lock signal indicating a stable state from a PLL circuit included in each clock distribution system, and stops the operation of the control unit until lock signals are received from all of the different clock distribution systems. 8. The clock skew correction circuit according to claim 7, wherein said control means is operated when a lock signal is received from all of said different clock distribution systems. A clock skew correction circuit correction method for correcting clock skew between different clock distribution systems,
The clock skew correction circuit includes:
Using the reference clock signal as input, adjusting the delay of the reference clock signal using a delay circuit and outputting it to each clock distribution system,
Detecting a phase difference between different clock signals output from the different clock distribution systems to generate a phase difference signal;
Set a delay amount to adjust the reference clock signal according to the phase difference signal,
When outputting a control signal for setting the set delay amount to the delay circuit, if the phase difference signal repeats delay and advance, correction of a clock skew correction circuit that adjusts an operating frequency for outputting the control signal Method. Different clock distribution systems that distribute clock signals to different systems;
A delay unit that takes a reference clock signal as input, adjusts the delay of the reference clock signal, and outputs it to each clock distribution system;
Phase difference detection means for detecting a phase difference between different clock signals output from the different clock distribution systems and outputting a phase difference signal;
Control means for setting the amount of delay by which the delay means adjusts the reference clock signal according to the phase difference signal, with the phase difference signal as an input;
A clock distribution apparatus comprising: an oscillation detection unit that receives the phase difference signal as input and adjusts an operating frequency of the control unit when the phase difference signal repeats delay and advance .

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