JP2011103133A5 - - Google Patents
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- Publication number
- JP2011103133A5 JP2011103133A5 JP2011002374A JP2011002374A JP2011103133A5 JP 2011103133 A5 JP2011103133 A5 JP 2011103133A5 JP 2011002374 A JP2011002374 A JP 2011002374A JP 2011002374 A JP2011002374 A JP 2011002374A JP 2011103133 A5 JP2011103133 A5 JP 2011103133A5
- Authority
- JP
- Japan
- Prior art keywords
- tool
- circuit design
- design
- implementation
- probability distribution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 230000035945 sensitivity Effects 0.000 claims 4
- 238000012986 modification Methods 0.000 claims 3
- 230000004048 modification Effects 0.000 claims 3
- 230000003139 buffering effect Effects 0.000 claims 1
- 238000004590 computer program Methods 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 230000003362 replicative effect Effects 0.000 claims 1
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US47505903P | 2003-05-30 | 2003-05-30 | |
| US60/475,059 | 2003-05-30 | ||
| US10/850,808 US7178118B2 (en) | 2003-05-30 | 2004-05-21 | Method and apparatus for automated circuit design |
| US10/850,808 | 2004-05-21 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006515054A Division JP2006527429A (ja) | 2003-05-30 | 2004-05-28 | 自動回路設計のための方法および装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011103133A JP2011103133A (ja) | 2011-05-26 |
| JP2011103133A5 true JP2011103133A5 (enExample) | 2012-03-15 |
| JP5197770B2 JP5197770B2 (ja) | 2013-05-15 |
Family
ID=33457661
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006515054A Pending JP2006527429A (ja) | 2003-05-30 | 2004-05-28 | 自動回路設計のための方法および装置 |
| JP2011002374A Expired - Lifetime JP5197770B2 (ja) | 2003-05-30 | 2011-01-07 | 回路設計ツール |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006515054A Pending JP2006527429A (ja) | 2003-05-30 | 2004-05-28 | 自動回路設計のための方法および装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (3) | US7178118B2 (enExample) |
| EP (2) | EP1629409A1 (enExample) |
| JP (2) | JP2006527429A (enExample) |
| WO (1) | WO2004109562A1 (enExample) |
Families Citing this family (45)
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| KR100855434B1 (ko) * | 2003-11-06 | 2008-09-01 | 클리어 쉐이프 테크날러지즈, 인크. | 델타 정보를 이용한 회로 설계 특성화 프로그램을 기록한컴퓨터로 읽을 수 있는 매체 |
| US7356784B1 (en) * | 2003-12-05 | 2008-04-08 | Cadence Design Systems, Inc. | Integrated synthesis placement and routing for integrated circuits |
| WO2005119441A2 (en) * | 2004-06-01 | 2005-12-15 | Tera Systems, Inc. | Methods and systems for structured asic eletronic design automation |
| US7487486B2 (en) * | 2004-06-17 | 2009-02-03 | Mustafa Celik | Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations |
| US7401307B2 (en) * | 2004-11-03 | 2008-07-15 | International Business Machines Corporation | Slack sensitivity to parameter variation based timing analysis |
| JP2006268479A (ja) * | 2005-03-24 | 2006-10-05 | Fujitsu Ltd | 設計支援装置、設計支援方法、設計支援プログラム、および記録媒体 |
| WO2007002799A1 (en) * | 2005-06-29 | 2007-01-04 | Lightspeed Logic, Inc. | Methods and systems for placement |
| US7752588B2 (en) * | 2005-06-29 | 2010-07-06 | Subhasis Bose | Timing driven force directed placement flow |
| US7325215B2 (en) * | 2005-08-31 | 2008-01-29 | Lsi Logic Corporation | Timing violation debugging inside place and route tool |
| JP4275659B2 (ja) * | 2005-09-26 | 2009-06-10 | 富士通株式会社 | 遅延解析プログラム、遅延解析装置、および遅延解析方法 |
| US7657859B2 (en) * | 2005-12-08 | 2010-02-02 | International Business Machines Corporation | Method for IC wiring yield optimization, including wire widening during and after routing |
| US8332793B2 (en) * | 2006-05-18 | 2012-12-11 | Otrsotech, Llc | Methods and systems for placement and routing |
| US7996797B1 (en) | 2006-08-16 | 2011-08-09 | Altera Corporation | Method and apparatus for performing multiple stage physical synthesis |
| US8127260B1 (en) | 2006-11-22 | 2012-02-28 | Cadence Design Systems, Inc. | Physical layout estimator |
| KR20090068569A (ko) * | 2007-12-24 | 2009-06-29 | 주식회사 동부하이텍 | 반도체 소자의 테스트 패턴 및 테스트 패턴 형성 방법 |
| US7996812B2 (en) * | 2008-08-14 | 2011-08-09 | International Business Machines Corporation | Method of minimizing early-mode violations causing minimum impact to a chip design |
| US8024693B2 (en) * | 2008-11-04 | 2011-09-20 | Synopsys, Inc. | Congestion optimization during synthesis |
| US20100257499A1 (en) * | 2009-04-02 | 2010-10-07 | International Business Machines Corporation | Techniques for fast area-efficient incremental physical synthesis |
| JP5397083B2 (ja) * | 2009-08-17 | 2014-01-22 | 富士通株式会社 | 回路設計支援方法、回路設計支援装置および回路設計支援プログラム |
| US8336015B2 (en) * | 2009-09-08 | 2012-12-18 | Synopsys, Inc. | Pre-route and post-route net correlation with defined patterns |
| US8429589B2 (en) * | 2009-09-08 | 2013-04-23 | Synopsys, Inc. | Generating net routing constraints for place and route |
| US8108821B2 (en) * | 2010-01-12 | 2012-01-31 | International Business Machines Corporation | Reduction of logic and delay through latch polarity inversion |
| US8782577B2 (en) | 2010-07-24 | 2014-07-15 | Cadence Design Systems, Inc. | Method, apparatus, and article of manufacture for providing in situ, customizable information in designing electronic circuits with electrical awareness |
| US8694933B2 (en) | 2010-07-24 | 2014-04-08 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for implementing electronic circuit designs with simulation awareness |
| JP5541011B2 (ja) * | 2010-09-01 | 2014-07-09 | 富士通株式会社 | 最適化ネットリスト作成プログラム、最適化ネットリスト作成装置および最適化ネットリスト作成方法 |
| US8386985B2 (en) | 2011-05-06 | 2013-02-26 | International Business Machines Corporation | Timing driven routing in integrated circuit design |
| US8584070B2 (en) * | 2011-10-04 | 2013-11-12 | International Business Machines Corporation | Evaluating routing congestion based on average global edge congestion histograms |
| US8595662B1 (en) | 2011-12-30 | 2013-11-26 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for implementing a physical design of an electronic circuit with automatic snapping |
| US9064063B1 (en) * | 2011-12-30 | 2015-06-23 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for implementing interactive, real-time checking or verification of complex constraints |
| US8645902B1 (en) | 2011-12-30 | 2014-02-04 | Cadence Design Systems, Inc. | Methods, systems, and computer program products for implementing interactive coloring of physical design components in a physical electronic design with multiple-patterning techniques awareness |
| US8694943B1 (en) | 2011-12-30 | 2014-04-08 | Cadence Design Systems, Inc. | Methods, systems, and computer program product for implementing electronic designs with connectivity and constraint awareness |
| US9053289B1 (en) | 2012-04-12 | 2015-06-09 | Cadence Design Systems, Inc. | Method and system for implementing an improved interface for designing electronic layouts |
| US8640075B2 (en) | 2012-06-01 | 2014-01-28 | International Business Machines Corporation | Early design cycle optimzation |
| WO2014064650A2 (en) * | 2012-10-25 | 2014-05-01 | Tiwari Satish Chandra | Method and system for automated design of an integrated circuit using configurable cells |
| US8959467B2 (en) * | 2012-11-07 | 2015-02-17 | Lsi Corporation | Structural rule analysis with TCL scripts in synthesis or STA tools and integrated circuit design tools |
| US9087172B2 (en) | 2013-10-07 | 2015-07-21 | International Business Machines Corporation | Implementing enhanced net routing congestion resolution of non-rectangular or rectangular hierarchical macros |
| US9483597B1 (en) * | 2015-03-24 | 2016-11-01 | Xilinx, Inc. | Opportunistic candidate path selection during physical optimization of a circuit design for an IC |
| US10169517B2 (en) | 2016-03-29 | 2019-01-01 | Wipro Limited | Methods and systems for reducing congestion in very large scale integrated (VLSI) chip design |
| US10970445B2 (en) * | 2017-06-28 | 2021-04-06 | Intel Corporation | Methods and apparatus for performing timing driven hardware emulation |
| SG11202004147RA (en) * | 2017-11-09 | 2020-06-29 | Nchain Holdings Ltd | System for securing verification key from alteration and verifying validity of a proof of correctness |
| US10586005B1 (en) | 2018-03-21 | 2020-03-10 | Xilinx, Inc. | Incremental synthesis for changes to a circuit design |
| US10831971B1 (en) * | 2019-06-05 | 2020-11-10 | International Business Machines Corporation | Net layer promotion with swap capability in electronic design |
| US12175176B2 (en) * | 2021-03-17 | 2024-12-24 | Synopsys, Inc. | Fast synthesis of logical circuit design with predictive timing |
| CN114118358B (zh) * | 2021-10-15 | 2025-10-21 | 阿里巴巴(中国)有限公司 | 图像处理方法、装置、电子设备、介质及程序产品 |
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| US5257201A (en) * | 1987-03-20 | 1993-10-26 | International Business Machines Corporation | Method to efficiently reduce the number of connections in a circuit |
| JPH04104374A (ja) * | 1990-08-24 | 1992-04-06 | Hitachi Ltd | 実装設計チェック方法 |
| JP2679500B2 (ja) * | 1990-12-17 | 1997-11-19 | モトローラ・インコーポレイテッド | 総合的なシステム歩留りを計算するための方法 |
| US5381524B2 (en) * | 1991-11-12 | 1997-07-08 | Chronology Corp | Automated development of timing diagrams for electrical circuits |
| US5301118A (en) * | 1991-11-18 | 1994-04-05 | International Business Machines Corporation | Monte carlo simulation design methodology |
| JP3219500B2 (ja) * | 1991-12-27 | 2001-10-15 | 株式会社東芝 | 自動配線方法 |
| US5418974A (en) * | 1992-10-08 | 1995-05-23 | International Business Machines Corporation | Circuit design method and system therefor |
| JP3193167B2 (ja) * | 1992-12-11 | 2001-07-30 | 株式会社東芝 | 論理合成システム |
| US5666290A (en) | 1995-12-27 | 1997-09-09 | Vlsi Technology, Inc. | Interactive time-driven method of component placement that more directly constrains critical paths using net-based constraints |
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-
2004
- 2004-05-21 US US10/850,808 patent/US7178118B2/en not_active Expired - Lifetime
- 2004-05-28 EP EP04753928A patent/EP1629409A1/en not_active Ceased
- 2004-05-28 EP EP10181410A patent/EP2275958A3/en not_active Withdrawn
- 2004-05-28 JP JP2006515054A patent/JP2006527429A/ja active Pending
- 2004-05-28 WO PCT/US2004/017207 patent/WO2004109562A1/en not_active Ceased
-
2006
- 2006-12-11 US US11/637,360 patent/US8151228B2/en not_active Expired - Lifetime
-
2011
- 2011-01-07 JP JP2011002374A patent/JP5197770B2/ja not_active Expired - Lifetime
-
2012
- 2012-03-29 US US13/434,755 patent/US8990743B2/en not_active Expired - Lifetime
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