JP2011097065A - Nitride semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device fabricated by a nitride semiconductor device fabricating method, capable of decreasing steps for polishing, cutting, etc., when element units manufactured on a substrate in a wafer process are chip-separated, and can repeatedly use the substrate. <P>SOLUTION: A nitride semiconductor defect position control substrate S is used such that the position of a defect gathering region H where defects having a slow crystal growing speed forming a closed curve gather and the position of a low-defect region ZY having a fast crystal growing speed are predetermined. A nitride semiconductor layer (upper layer part B) is epitaxially grown on a gallium nitride substrate so that the inside of the device may be in the low-defect region ZY and a border may be in the defect gathering region H. The defect position control substrate S and the grown layer (upper layer part B) are separated in an up-down direction and in a lateral direction simultaneously by a laser irradiation or mechanical means, and the substrate is repeatedly used. The fabricated device has an end surface formed of a facet by the growth. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

The present invention relates to a method of manufacturing a good nitride semiconductor device having a low defect density with a small number of steps and a nitride semiconductor device manufactured by the method.

In Patent Document 1, an InGaN buffer layer having a thickness of 0.3 μm or less and a GaN crystal having a thickness of 100 μm or more are grown on a base substrate (sapphire) having a thickness of 3 mm or more, which is different from a nitride semiconductor, and the base substrate is polished by polishing. A method is described in which an LD is manufactured by removing a GaN substrate, polishing and flattening the GaN substrate, and laminating a nitride semiconductor thin film thereon.

In this method, a thick GaN film is formed on a different kind of underlying substrate such as sapphire (Al ₂ O ₃ ), spinel (MgAl ₂ O ₄ ) through a buffer layer, and the sapphire underlying substrate is removed by polishing to separate the GaN independent substrate. GaN buffer layer, crack prevention layer, n-side cladding layer, n-side light guide layer, active layer, p-side cap layer, p-side light guide layer, p-side cladding layer, p-side contact layer, etc. An epitaxial substrate having a stacked semiconductor thin film is produced. The p-side is etched away to form a ridge type, and an n-side electrode and a p-side electrode are formed. Since it is a substrate on which a large number of devices are formed, it is cut out along a boundary line by mechanical means and separated into individual chips. This requires two polishing steps and one mechanical element separation step.

  In Patent Document 2, a GaN crystal is grown on an oxide substrate (sapphire), the oxide substrate is removed to obtain a GaN crystal substrate, and a GaN crystal is further grown thereon to obtain a sufficient thickness. Describes a method of manufacturing a GaN substrate, in which a GaN wafer is obtained by polishing the surface of the GaN crystal smoothly to obtain a GaN wafer. This must be done twice: polishing to remove the sapphire substrate and polishing the GaN crystal. When a p-type, n-type InGaN, AlGaN, or GaN thin film is grown on the GaN substrate thus obtained to produce a device, the GaN substrate must be cut by mechanical means and separated into individual elements. The following Patent Documents 3 and 4 are not directly related to the nitride semiconductor device fabrication method. Therefore, it is not the closest prior art to the present invention. However, since it plays an important role in the present invention, it will be described in advance.

Patent Document 3 describes a novel method for manufacturing a gallium nitride substrate by the present applicant. They are listed because they are the basic technology for manufacturing substrates that play an important role in the present invention. This will be described with reference to FIGS. As shown in FIG. 1, an isolated dot-like (dot-like) mask M (SiO ₂ , SiN, W, Pt, etc.) is attached on a base substrate (GaAs, SiC, sapphire, spinel single crystal) US. In the longitudinal sectional view, the state is as shown in FIG. Then, gallium nitride is vapor-phase grown. It is difficult to grow on the mask M, and the growth is delayed, resulting in a hole. In this way, holes (pits) made of facets F are created on the mask M as shown in FIGS.

  FIG. 8 is a longitudinal sectional view. Facet F forms hexagonal pyramid and 12 pyramid pits. Here, for the sake of simplicity, a facet pit including a facet F of a hexagonal pyramid is shown. You can not pit other than the mask. The gallium nitride crystal is grown while adjusting the growth conditions and maintaining the facets on the mask M as shown in FIGS. 2 and 3 differ in the orientation of the facets of the pyramid. If the base substrate and the mask arrangement are determined, facet pits in any direction of FIGS. 2 and 3 can be generated. Since the dislocation D extends at right angles to the growth surface, the dislocation D moves inward, and the dislocation D concentrates on the bottom of the facet pit. Dislocation D is captured at the bottom of the pit. In the longitudinal sectional view, the state is as shown in FIG. A portion where dislocations concentrated on the position on the mask M is called a defect gathering region H.

  In other parts, dislocations are reduced and single crystals with low dislocations are formed. The portion immediately below the facet F becomes a low defect single crystal region Z. This is a single crystal low dislocation and high conductivity. When the C-plane is grown without being covered by the facet, the portion grown immediately below the C-plane is called a C-plane growth region Y and has low single crystal dislocations and low conductivity. The mask M is also covered with the defect gathering region H. The facet pits as shown in FIG.

  When the crystal becomes quite thick, the upper surface is polished to remove facet pits, and the underlying substrate is removed by grinding, etching, or the like to obtain a gallium nitride free-standing substrate. This is shown in FIG. FIG. 10 is a longitudinal sectional view. This gallium nitride substrate is made of H, Z, and Y. Since it is transparent, it cannot be distinguished with the naked eye. A distinction can be seen by CL (cathodoluminescence). This growth method is called a dot type because the mask arrangement and the defect collection region H arrangement are dot-like, and are distinguished from other types. The defect accumulation region H is an isolated point and does not form a closed curve.

  Since both the low-defect single crystal region Z and the C-plane growth region Y are low-dislocation single crystals (having a common crystal orientation), they are referred to as the low-defect region ZY including both of them. When there is no C-plane growth region Y, a gallium nitride substrate consisting only of a defect assembly region H and a low defect single crystal region Z as shown in FIG. In this case, the low defect single crystal region Z is referred to as a low defect region ZY.

  Patent Document 4 describes a novel method for manufacturing a gallium nitride substrate by the present applicant. A parallel line (striped) mask M is attached on the base substrate (FIG. 11), and gallium nitride is vapor-phase grown thereon. It is difficult to grow on the mask M. Dislocations are concentrated and captured at the bottom of the facet grooves by creating facet grooves facing the facets F and F on the mask M and growing a gallium nitride crystal while maintaining the facets F on the mask M.

  FIG. 12 shows such a state. As the growth proceeds, the top of the mask M is covered with crystals with concentrated dislocations. A portion where dislocations concentrated at the mask position is called a defect assembly region H. In other parts, dislocations are reduced and single crystals with low dislocations are formed. The portion immediately below the facets F and F in parallel is called a low defect single crystal region Z and has high conductivity. When the C-plane is grown without being covered by the facet F, the portion grown immediately below the C-plane is called a C-plane growth region Y and has a low conductivity. When the thickness reaches a certain level, the facet surface is flattened by polishing or the like, and the base substrate is removed to form a self-supporting substrate made of only gallium nitride.

  FIG. 13 and FIG. 14 show this. FIG. 13 shows the case where the C-plane growth region Y is present. FIG. 14 shows the case where there is no C-plane growth region Y. The size of the facet F can be controlled to generate or eliminate the C-plane growth region Y. This growth method is called a stripe type and is distinguished from the others because the arrangement of the mask and the arrangement of the defect collecting regions H are parallel lines. The defect accumulation region H is an isolated parallel line and an open straight line. The closed curve is not made as in the present invention.

  Since both the low defect single crystal region Z and the C-plane growth region Y are low dislocation single crystals (having a common crystal orientation), in the present invention, both the Z and Y are referred to as the low defect region ZY. To do. The dot-type defect accumulation region H is an isolated point and not a closed curve. The stripe-type defect accumulation region H is also an open line and not a closed curve. Neither the dot type nor the stripe type has a defect gathering region H having an isolated point or an open curve, and cannot be a substrate to which the present invention is applied. However, it has been described because it is the basis of the substrate manufacturing technology of the present invention.

JP 2002-261014 “Method of manufacturing nitride semiconductor device”

JP-A-11-001399 “Gallium nitride semiconductor single crystal substrate manufacturing method and gallium nitride diode using the substrate”

Japanese Patent Application Laid-Open No. 2003-165799 (Japanese Patent Application Nos. 2001-284324 and 2002-230925) “Single Crystal Gallium Nitride Substrate, Growth Method, and Manufacturing Method”

Japanese Patent Application Laid-Open No. 2003-183100 (Japanese Patent Application Nos. 2001-311018 and 2002-269387) “Single Crystal Gallium Nitride Substrate, Single Crystal Gallium Nitride Crystal Growth Method, and Single Crystal Gallium Nitride Substrate Manufacturing Method”

  It is a first object of the present invention to provide a nitride semiconductor device manufacturing method capable of reducing the number of steps such as polishing and cutting. It is a second object of the present invention to provide a nitride semiconductor device having a semiconductor layer with a low defect density. It is a third object of the present invention to provide a method of manufacturing a nitride semiconductor device that can repeatedly use a substrate and reduce the consumption of an expensive nitride semiconductor substrate.

A nitride semiconductor defect position control substrate S (Al _x In _y Ga _{1-x) in} which the positions of a defect assembly region H in which defects having a slow crystal growth rate form a closed curve and a low defect region ZY in which the crystal growth rate is high are predetermined are predetermined. _-Y N: 0 ≦ x ≦ 1, 0 ≦ y ≦ 1), and the nitride semiconductor layer is formed on the gallium nitride substrate so that the inside of the device is in the low defect region ZY and the boundary line is in the defect assembly region H The (upper layer portion B) is epitaxially grown, and the defect position control substrate S and the growth layer (upper layer portion B) are separated by laser irradiation or mechanical means. Since the portion grown on the defect gathering region H of the upper layer portion B is thin, it is naturally cut and separated into individual chips. That is, vertical separation and horizontal separation are performed simultaneously. The defect position control substrate S is repeatedly used. “The crystal growth rate is fast” or “the crystal growth rate is slow” means that the growth rate is fast or slow when a nitride semiconductor thin film is grown thereon. It does not mean that the growth rate is slow or fast.

  It is redundant to say that “the substrate in which the positions of a defect assembly region forming a closed curve in which defects with a slow crystal growth rate are aggregated and a low defect region with a high crystal growth rate is determined in advance” is determined. Therefore, it is simply referred to as a “defect position control board” by the symbol S. This is made by the method presented in Patent Documents 3 and 4 mentioned above. The defect area corresponds to the defect gathering area H, and the low defect area corresponds to the low defect area ZY. Even if it is called the defect position control board | substrate S, it means that not only the position of the area | region where the defect gathered is clear but the position of the area | region with few defects is also clear. Moreover, the growth of nitride semiconductor crystals (GaN, InGaN, AlGaN, InN, AlN, AlInGaN) is slow in the defect assembly region, and the growth of nitride semiconductor crystals is fast in the low defect region.

  Furthermore, it is important that the defect accumulation region H forms a closed loop. A closed curve is a curve that starts from an arbitrary point on the curve and always moves back along the curve and moves back a finite length before returning to the original position. A closed curve defect collecting region H surrounds the low defect region ZY. The low defect area ZY is surrounded by a closed curve and becomes an isolated shape, which matches the specific shape of the device. In Patent Documents 3 and 4, the defect gathering region H is an isolated point or an open line. In the present invention, the defect accumulation region H must be a closed curve. The defect gathering region H can have any shape depending on the shape of the mask formed on the base substrate. The defect accumulation region H can be an arbitrary closed curve.

  A large number of layers grown on the defect position control substrate S are collectively referred to as an “upper layer portion” and represented by B. The upper layer portion B has a different structure depending on the type of device, but is a laminated body of thin films of n-type, p-type GaN, AlGaN, and InGaN. The defect position control substrate S is composed of a defect gathering region H which is not uniform and grows slowly and a low defect region ZY which grows quickly. When a nitride semiconductor is grown on the same conditions, a nitride semiconductor crystal grows sufficiently in the low defect region ZY, but almost no crystal grows on the defect assembly region H and almost no defect assembly region H exists. It remains exposed.

  Therefore, the upper layer portion B is thick in the low defect region ZY of the defect position control substrate S and thin in the defect assembly region H. The upper layer portion B grows unevenly as such. Since the growth rate changes depending on the location, it can also be called selective growth. Therefore, the device boundary line is made to correspond to the defect gathering region H having a low growth rate, and the inside of the device is made to correspond to the low defect region ZY having a high growth rate. A defect gathering region H formed of a closed curve becomes a boundary line for each element. The element unit becomes one device. Therefore, the upper layer portion includes a stacked body corresponding to a plurality of devices. The upper layer portion may include an electrode or may not include an electrode.

  Further, a method of separating the chips C from each other by providing a separation layer Q made of a crystal having a narrow band gap between the defect position control substrate S and the upper layer portion B and evaporating the separation layer Q by laser irradiation is also possible. The separation layer Q has a narrow band gap, and when the laser light is applied, the separation layer Q is decomposed and disappears. For this reason, the defect position control substrate S and the upper layer part B are separated vertically.

  The band gap of the separation layer Q is defined as Egq, the band gap of the defect position control substrate S is defined as Egs, and the band gap of the jth surface layer of the upper layer portion B is defined as Egj. The conditions imposed on the laser light wavelength λ and the separation layer Q, the upper layer B, and the defect position control substrate S are Egq <hc / λ <Egs and Egq <hc / λ <min {Egj}. min {...} is a symbol that means the minimum value of {...}. Hereinafter, it may be written as min {Egj} = Egb. It means the smallest band gap among the semiconductor layers constituting the upper layer portion B. h is Planck's constant, and c is the speed of light in vacuum.

  Semiconductors and insulators transmit light with energy smaller than the band gap and absorb light with energy larger than the band gap. Therefore, when laser light satisfying the above inequality is applied, the separation layer Q emits laser light. Absorbs, heats, decomposes and disappears. Therefore, the upper layer part B and the defect position control substrate S are instantaneously separated in the vertical direction.

  In the upper layer portion B, since the growth layer is thin and weak in the defect gathering region H, the chips can be naturally separated using the defect gathering region H as a boundary line.

  The crystals in the upper layer B are separated from each other in the lateral direction as soon as they are separated from the substrate in the vertical direction. Therefore, the chip separation process is omitted. This is the greatest advantage of the present invention.

  The defect position control substrate (AlInGaN) S itself remains separated. Therefore, the defect position control board can be used again as a board. That is, the defect position control substrate S can be used repeatedly because it is not damaged by the formation of the nitride semiconductor of the upper layer portion B. This is also a great advantage of the present invention.

  The present invention provides an upper layer made of a nitride semiconductor on a defect position control substrate S that has a defect gathering region H having a closed curve and a slow growth rate and a low defect region ZY having a fast growth rate and whose position is predetermined. The portion B is epitaxially grown, and the electrode E is provided or not provided on the upper layer portion B, and the upper layer portion B is vertically separated from the defect position control substrate S by laser irradiation so that the upper layer portion B is simultaneously separated into the chips C. It has become.

  Alternatively, a separation layer Q is provided on a defect position control substrate S having a defect gathering region H having a slow growth rate and a low defect region ZY having a high growth rate that form a closed curve, and the position thereof is determined in advance. The upper layer portion B made of a nitride semiconductor is epitaxially grown on the upper layer portion B, and the electrode E is provided or not provided on the upper layer portion B, and the defect position control substrate S and the upper layer portion B are formed from the separation layer Q by laser irradiation or mechanical means. The upper layer part B is separated into chips C at the same time by separating the upper and lower parts.

  After the chip separation, the bottom electrode is formed for each chip. The top electrode may be fabricated at the wafer stage, or the top electrode may be fabricated after chip separation.

  Since the upper layer portion B is removed from the defect position control substrate S and the chip can be separated at the same time, the chip separation process can be omitted. Since the manufacturing process can be greatly reduced, the cost can be reduced.

  The defect position control substrate S remains intact. The defect position control substrate S can be used over and over again. Since the substrate S is also an expensive nitride semiconductor, the effect of cost reduction by repeatedly using it is great.

FIG. 1 shows an example in which an isolated dot-like mask M is formed on a base substrate US proposed by Patent Document 3, a facet pit is formed on the mask M, and a gallium nitride crystal is grown while maintaining the facet F. FIG. 3 is a plan view of a base substrate US in a state where a dot mask is formed on the base substrate US in a facet growth method in which a defect collecting region H is formed at the bottom of the facet pit and other portions are low dislocations.

FIG. 2 shows an example in which an isolated dot-like mask M is formed on the base substrate US proposed by Patent Document 3 and facet pits are formed on the mask M to grow a gallium nitride crystal while maintaining the facet F. In a facet growth method in which a defect gathering region H is formed at the bottom of a facet pit and other portions are low dislocations, a dot mask is formed on the base substrate US, gallium nitride is grown, and facet pits are formed on the mask M to generate facet F The top view of a gallium nitride crystal which shows a mode that the dislocation | rearrangement D is collected to a pit bottom by FIG. Facet ridge lines are generated parallel to the sides of the equilateral triangle connecting the mask M.

FIG. 3 shows an example in which an isolated dot-like mask M is formed on the base substrate US proposed by Patent Document 3 and facet pits are formed on the mask M to grow a gallium nitride crystal while maintaining the facet F. In a facet growth method in which a defect gathering region H is formed at the bottom of a facet pit and other portions are low dislocations, a dot mask is formed on the base substrate US, gallium nitride is grown, and facet pits are formed on the mask M to generate facet F The top view of a gallium nitride crystal which shows a mode that the dislocation | rearrangement D is collected to a pit bottom by FIG. Facet ridge lines are formed at right angles to the sides of the equilateral triangle connecting the masks.

FIG. 4 shows an example in which an isolated point-like mask M is formed on the base substrate US proposed by Patent Document 3 and facet pits are formed on the mask M to grow a gallium nitride crystal while maintaining the facet F. In a facet growth method in which a defect gathering region H is formed at the bottom of a facet pit and other portions are low dislocations, a dot mask is formed on the base substrate US, gallium nitride is grown, and facet pits are formed on the mask M to generate facet F FIG. 5 is a plan view of a gallium nitride crystal in a state where deep facet pits are formed by collecting dislocations D at the bottom of the pits.

FIG. 5 shows an example in which an isolated point-like mask M is formed on the base substrate US proposed by Patent Document 3 and facet pits are formed on the mask M to grow a gallium nitride crystal while maintaining the facet F. A defect gathering region formed on the mask M by forming a defect gathering region H at the bottom of the facet pit and growing the crystal by a facet growth method in which other parts are low dislocations and removing the base substrate US to form a single gallium nitride substrate. FIG. 3 is a plan view of a gallium nitride crystal showing that it consists of a low-defect single crystal region Z formed under H and a facet F and a C-plane growth region Y formed at a facet joint.

FIG. 6 shows an example in which an isolated dot-like mask M is formed on the base substrate US proposed by Patent Document 3 and facet pits are formed on the mask M to grow a gallium nitride crystal while maintaining the facet F. A defect gathering region formed on the mask M by forming a defect gathering region H at the bottom of the facet pit and growing the crystal by a facet growth method in which other parts are low dislocations and removing the base substrate US to form a single gallium nitride substrate. FIG. 3 is a plan view of a gallium nitride crystal showing that it consists of H and a low-defect single crystal region Z formed under facet F.

FIG. 7 shows an example in which an isolated dot-like mask M is formed on the base substrate US proposed by Patent Document 3 and facet pits are formed on the mask M to grow a gallium nitride crystal while maintaining the facet F. FIG. 3 is a longitudinal sectional view of a base substrate US in a state where a dot mask is formed on the base substrate US in a facet growth method in which a defect gathering region H is formed at the bottom of a facet pit and other portions are low dislocations.

FIG. 8 shows an example in which an isolated dot-like mask M is formed on the base substrate US proposed by Patent Document 3 and facet pits are formed on the mask M to grow a gallium nitride crystal while maintaining the facet F. In the facet growth method in which a defect gathering region H is formed at the bottom of the facet pit and other portions are low dislocations, when a dot mask is formed on the base substrate US and gallium nitride is grown, the growth on the mask M is delayed. The longitudinal cross-sectional view of the gallium nitride crystal which shows a mode that the facet pit is produced on it and the dislocation D is collected to the pit bottom by facet F.

FIG. 9 shows an example in which an isolated dot-like mask M is formed on the base substrate US proposed by Patent Document 3 and facet pits are formed on the mask M to grow a gallium nitride crystal while maintaining the facet F. In a facet growth method in which a defect gathering region H is formed at the bottom of a facet pit and other portions are low dislocations, a dot mask is formed on the base substrate US, gallium nitride is grown, and facet pits are formed on the mask M to generate facet F FIG. 4 is a plan view of a gallium nitride crystal that shows dislocations collected at the bottom of the pits, the bottom of the pits becomes a defect gathering region H, the bottom of the facet becomes a low defect single crystal region Z, and the joint of the facet becomes a C-plane growth region Y Facet ridge lines are formed at right angles to the sides of the equilateral triangle connecting the mask M.

FIG. 10 shows an example in which an isolated dot-like mask M is formed on the base substrate US proposed by Patent Document 3, facet pits are formed on the mask M, and a gallium nitride crystal is grown while maintaining the facet F. A defect gathering region formed on the mask M by forming a defect gathering region H at the bottom of the facet pit and growing the crystal by a facet growth method in which other parts are low dislocations and removing the base substrate US to form a single gallium nitride substrate. A plan view of a gallium nitride crystal consisting of a low-defect single crystal region Z formed under H and facet F and a C-plane growth region Y formed at the joint of facet F, or consisting of H and Z.

In FIG. 11, a parallel linear stripe mask is formed on the base substrate US proposed by Patent Document 4, a parallel facet groove is formed on the mask M, and a gallium nitride crystal is grown while maintaining the facet groove. The top view of the base substrate of the state which formed the stripe mask in the base substrate US in the facet growth method which forms the defect gathering area | region H in the facet groove bottom by this, and makes another part low dislocation.

In FIG. 12, a parallel linear stripe mask is formed on the base substrate US proposed by Patent Document 4, a parallel facet groove is formed on the mask M, and a gallium nitride crystal is grown while maintaining the facet groove. Thus, in the facet growth method in which the defect gathering region H is formed at the bottom of the facet groove and the other portions are low dislocations, a stripe mask is formed on the base substrate US to grow gallium nitride to form a facet groove on the mask M. The top view of a gallium nitride crystal which shows a mode that the dislocation D is collected to the bottom of a facet groove | channel by the facet F. FIG.

FIG. 13 shows a method in which a parallel straight mask M is formed on a base substrate US proposed by Patent Document 4, a parallel facet groove is formed on the mask M, and a gallium nitride crystal is grown while maintaining the facet F. In the facet growth method in which the defect gathering region H is formed at the bottom of the facet pit and the other portions are low dislocations, the base substrate US is removed and polished so that the bottom of the facet groove becomes the defect gathering region H and below the facet groove. FIG. 4 is a plan view of a gallium nitride free-standing substrate in which a low-defect single crystal region Z and a facet groove seam become a C-plane growth region Y.

FIG. 14 shows a method in which a parallel linear mask M is formed on the base substrate US proposed by Patent Document 4, a parallel facet groove is formed on the mask M, and a gallium nitride crystal is grown while maintaining the facet F. In the facet growth method in which the defect gathering region H is formed at the bottom of the facet pit and the other portions are low dislocations, the base substrate US is removed and polished so that the bottom of the facet groove becomes the defect gathering region H and below the facet groove. FIG. 3 is a plan view of a gallium nitride free-standing substrate in which is a low-defect single crystal region Z.

FIG. 15 shows a state just before facet growth of an AlInGaN crystal is performed on a base mask US on which a square mask M is attached in order to manufacture a defect position control substrate S having a defect gathering region H having a closed curve necessary for the present invention. The top view of the base substrate US which shows a state.

In FIG. 16, a square mask M is formed on the base substrate US, and an AlInGaN crystal is facet grown thereon, a defect collecting region H is generated on the mask M, and a low defect region ZY is generated in a portion other than the mask M. The top view of the defect position control board | substrate S which has the defect gathering area | region H of the closed curve (square) required for this invention manufactured by doing.

FIG. 17 shows a state immediately before facet growth of an AlInGaN crystal on a regular hexagonal mask M on a base substrate US in order to manufacture a defect position control substrate S having a defect gathering region H having a closed curve necessary for the present invention. The top view of the base substrate which shows the state of.

In FIG. 18, a regular hexagonal mask M is formed on the base substrate US, and an AlInGaN crystal is facet grown thereon, a defect collecting region H is generated on the mask M, and a low defect region ZY is formed on a portion other than the mask M. The top view of the defect position control board | substrate S which has the defect gathering area | region H of the closed curve (regular hexagon) required for this invention manufactured by producing | generating.

In FIG. 19, an equilateral triangular mask M is formed on the base substrate US, and an AlInGaN crystal is facet grown on the mask M, a defect collecting region H is generated on the mask M, and a low defect region ZY is formed on a portion other than the mask M. The top view of the defect position control board | substrate S which has the defect gathering area | region H of the closed curve (regular triangle) required for this invention manufactured by producing | generating.

In FIG. 20, a parallelogram mask M is formed on the base substrate US, and an AlInGaN crystal is facet grown on the mask M to generate a defect accumulation region H on the mask M, and a low defect region ZY is formed on a portion other than the mask M. FIG. 6 is a plan view of a defect position control substrate S having a defect gathering region H having a closed curve (parallelogram) necessary for the present invention, which is manufactured by generating a defect.

FIG. 21 shows a defect set when a separation layer Q is grown on a defect position control substrate S having a predetermined defect position including a defect set area H having a closed curve and a low defect area ZY surrounded by the defect set area H. The longitudinal cross-sectional view of the defect position control board | substrate S and the isolation layer Q for demonstrating growing on the low defect area | region ZY hardly growing on the area | region H. FIG.

FIG. 22 shows a case where a separation layer Q and an upper layer B are grown on a defect position control substrate S having a predetermined defect position including a defect accumulation region H having a closed curve and a low defect region ZY surrounded by the defect accumulation region H. FIG. 4 is a longitudinal sectional view of the defect position control substrate S, the separation layer Q, and the upper layer portion B for explaining that the defect growth region H hardly grows on the defect assembly region H and grows on the low defect region ZY.

FIG. 23 shows the growth of a separation layer Q and an upper layer B on a defect position control substrate S having a predetermined defect position including a defect accumulation region H having a closed curve and a low defect region ZY surrounded by the defect accumulation region H. In this case, the upper layer portion is applied with stress by laser irradiation or mechanical means on the thin film / substrate in which the adjacent element unit grows on the low defect region ZY and grows on the low defect region ZY and is laterally separated. The longitudinal cross-sectional view of the state which isolate | separated B from the defect position control board | substrate S up and down. At the same time as vertical separation, horizontal separation (chip separation) is performed. Chips can be separated at once without cutting the substrate.

FIG. 24 is a chip cross-sectional view showing a state in which an upper electrode P is formed for each unit of elements separated from each other.

FIG. 25 is a chip longitudinal sectional view showing a state in which a lower electrode R is formed for each unit of elements separated from each other.

FIG. 26 is a longitudinal sectional view showing a state in which the upper layer portion B is stacked on the defect position control substrate S as shown in FIG. 22 and the upper electrode P is formed by a wafer process.

FIG. 27 is a longitudinal sectional view showing a state where the upper layer part B having the upper electrode P is vertically separated from the defect position control substrate S by mechanical means or optical means. Chips can be separated at once without cutting the substrate. The substrate can be reused.

In FIG. 28, the nitride semiconductor thin film / substrate is irradiated from above or below with light having an energy (hν) lower than the band gap of the defect position control substrate S and upper layer B with an energy (hν) higher than the band gap of the separation layer Q. However, the light is not absorbed by the substrate S and the upper layer portion B, but is only illustrated by the separation layer Q.

In FIG. 29, a nitride semiconductor is vapor-phase grown on a defect position control substrate S composed of a square defect gathering region H and a low defect region ZY surrounded by the upper layer B. Is a perspective view of a chip C formed of a square mesa-type upper layer B separated from the defect position control substrate S by mechanical or optical means.

30 is a perspective view of a square chip C having an end surface side surface perpendicular to the upper and lower surfaces by polishing the end surface side surface of the chip formed of the square mesa type upper layer portion B of FIG. 29. FIG.

FIG. 31 shows an upper layer portion in which a nitride semiconductor is vapor-phase grown on a defect position control substrate S composed of an equilateral triangular defect gathering region H and a low defect region ZY surrounded by it, with or without an isolation layer Q. The perspective view of the chip | tip C which consists of the equilateral triangle mesa type | mold upper layer part B which formed B and was separated from the defect position control board | substrate S by the mechanical or optical means.

32 is a perspective view of an equilateral triangle chip C having end face sides perpendicular to the upper and lower surfaces by polishing the end face side surface of the chip C composed of the equilateral triangle mesa type upper layer part B of FIG. 31. FIG.

FIG. 33 shows an upper layer formed by vapor-phase growth of a nitride semiconductor on a defect position control substrate S composed of a parallelogram defect gathering region H and a low defect region ZY surrounded by the defect gathering region H with or without an isolation layer Q. The perspective view of the chip | tip C which forms the part B and consists of the parallelogram mesa type | mold upper layer part B isolate | separated from the defect position control board | substrate S by the mechanical or optical means.

FIG. 34 is a perspective view of a parallelogram chip C having an end surface side surface perpendicular to the upper and lower surfaces by polishing the end surface side surface of the chip C composed of the parallelogram mesa type upper layer B of FIG.

FIG. 35 shows an upper layer portion in which a nitride semiconductor is vapor-phase grown on a defect position control substrate S composed of a regular hexagonal defect gathering region H and a low defect region ZY surrounded by the same, with or without an isolation layer Q. The perspective view of the chip | tip C which forms B and forms the regular hexagonal mesa type | mold upper layer part B isolate | separated from the defect position control board | substrate S by mechanical or an optical means.

36 is a perspective view of a regular hexagonal chip C having an end surface side surface perpendicular to the upper and lower surfaces by polishing the end surface side surface of the chip C composed of the regular hexagonal mesa type upper layer portion B of FIG.

FIG. 37 shows an LED element chip in which the upper layer B formed for the LED is separated from the defect position control substrate S by optical or mechanical means, and the upper electrode P and the lower electrode R are attached to the upper layer B. Sectional drawing which shows the structure.

FIG. 38 shows a HEMT element chip in which the upper layer B formed for HEMT is separated from the defect position control substrate S by optical or mechanical means, and the upper electrode P and the lower electrode R are attached to the upper layer B. Sectional drawing which shows the structure.

FIG. 39 shows a shot in a state where the upper layer portion B formed for the Schottky diode is separated from the defect position control substrate S by optical or mechanical means, and the upper electrode P and the lower electrode R are attached to the upper layer portion B. Sectional drawing which shows the structure of a key diode element chip | tip.

In FIG. 40, the upper layer B formed for the vertical transistor is separated from the defect position control substrate S by optical or mechanical means, and the upper electrode P and the lower electrode R are attached to the upper layer B. Sectional drawing which shows the structure of a type transistor element chip.

[1. Defect position control substrate S (FIGS. 16, 18, 19, and 20)]
The composition is Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1), but the distributed positions of the defect assembly region H and the low defect region ZY It is an AlInGaN substrate as determined in advance. It is given for the first time in Patent Documents 3 and 4. Since the mask M is formed on the base substrate US and crystal growth is delayed on the mask M, facet pits and facet grooves are formed on the mask M, and dislocations in other regions are drawn to the facet bottom. The defect gathering region H is concentrated at a high density, and the other part is a low-dislocation single crystal ZY.

  Therefore, the present invention uses the substrates of Patent Documents 3 and 4 as starting materials. The growth of the nitride semiconductor is fast on the low defect region ZY, and the growth of the nitride semiconductor is slow in the defect assembly region H. Moreover, the defect gathering region H is provided so as to form a closed curve. Patent Documents 3 and 4 do not have a defect curve region H as a closed curve. In the dot type of Patent Document 3, the defect collection region H is an isolated point, and in the stripe type of Patent Document 4, the defect collection region H is a parallel straight line group. None of them are closed curves.

  The starting substrate of the present invention is required to be formed so as to include the defect accumulation region H and the low defect region ZY by facet growth of Patent Documents 3 and 4, and that the defect accumulation region H is a closed curve. This is because the elements can be separated from each other when cut along the defect gathering region H. The closed curve is an element unit. Therefore, the defect assembly region H may be formed on the defect position control substrate S so as to have an outline for one unit of the element. The defect gathering region H must be a closed curve because it determines the external shape of the device. Since the defect collecting region H is formed on the mask M, the shape of the defect collecting region H can be freely determined by the shape of the mask M.

  As in Patent Documents 3 and 4, in the defect position control substrate S, the defect assembly region H and the low defect region ZY grow in the vertical direction, and the defect assembly region H is a single crystal whose direction is reversed. This is the case only when the low-defect region ZY grows C-plane, the front surface is the Ga surface, the back surface is the N surface, and the defect assembly region H is the N surface and the back surface is the Ga surface. That is, only when the C-plane is grown on the substrate with mask, the defect accumulation region H and the low defect region ZY are formed. This means that the surface of the defect position control substrate S is a C plane (partially -C plane).

  In addition to the C plane, hexagonal crystals include M plane ({1-100}) and A plane ({11-20}) as representative planes. In many cases, the {1-100} plane is a cleavage plane. is there. However, it is unclear whether the defect gathering region H of the closed curve and the low defect region ZY surrounded by the closed curve can be formed on the {1-100} plane or {11-20}. A large nitride semiconductor crystal having a {1-100} plane or a {11-20} plane has not yet been made. When a nitride semiconductor is grown on the mask M, it is unclear whether the crystal orientation is reversed such as the defect assembly region H and the low defect region ZY. Also, it is not known whether there is growth rate selectivity when a nitride semiconductor is grown thereon. At present, the defect position control substrate S is limited to C-plane grown crystals. Therefore, the cleavage plane does not become a horizontal plane. Therefore, it cannot be separated by natural cleavage.

  Since many nitride semiconductors are trigonal or hexagonal, the chip shape (closed curve shape) is square, regular hexagon, equilateral triangle, parallelogram, rhombus, etc. It becomes the shape of. In this case, the defect collection region H on the defect position control substrate S is a regular hexagon, a regular triangle, a parallelogram, a diamond shape, or the like.

  However, since the present invention is a technique for separating chips without using cleavage, it is not necessary to match the chip outline to the cleavage plane. A chip C having a square rectangular outline may be used. In that case, the defect gathering region H is a square rectangle. The maximum value of the horizontal dimension of a closed curve shape such as a square, a regular hexagon, a regular triangle, a parallelogram, and a diamond shape is about 50 mm, and the minimum value is about 0.2 mm.

  FIG. 15 is a plan view of a part of the base substrate in which a mask M having a square closed curve is formed on the base substrate US. FIG. 16 is a partial plan view of a nitride semiconductor (AlInGaN) self-supporting substrate obtained by growing a facet of a nitride semiconductor (AlInGaN) to an appropriate thickness and polishing the facet portion to remove the base substrate US. It is. In this case, the upper part of the mask M becomes a defect collection region H, which forms a closed curve. A portion surrounded by the closed curve becomes a low defect region ZY having a single crystal and low dislocations. The low defect area ZY is a unit of the semiconductor device. However, both ZY and H are transparent and cannot be distinguished with the naked eye. The distinction can be understood only by observing with CL (cathode luminescence) or a fluorescence microscope.

  FIG. 17 is a plan view of a part of the base substrate in which the mask M having a regular hexagonal closed curve is formed on the base substrate US. FIG. 18 is a partial plan view of a nitride semiconductor (AlInGaN) self-standing substrate obtained by growing a facet of a nitride semiconductor (AlInGaN) thereon and polishing the facet portion to an appropriate thickness to remove the base substrate US. It is. In this case, the upper part of the mask M becomes a defect collection region H, which forms a closed curve. The portion surrounded by the closed curve is the low defect area ZY. The low defect area ZY is a unit of the semiconductor device. If this substrate is used, a regular hexagonal device can be formed. In this case, both ZY and H are transparent and cannot be distinguished with the naked eye. The distinction can be understood only by observing with CL (cathode luminescence) or a fluorescence microscope.

  In addition, a nitride semiconductor defect position control substrate S having a defect collection region H such as an equilateral triangle or a parallelogram can be used. FIG. 19 shows an example of a defect position control substrate S having an equilateral triangle defect gathering region H. As in FIGS. 15 to 18, a defect gathering region H is formed on the mask M, and the mask M position and the defect gathering region H position have a one-to-one correspondence. Therefore, the illustration of the mask M is omitted here, and only the defect position control substrate S is shown. The equilateral triangular defect collection region H forms a closed curve. A low defect region ZY, which is a single crystal of low dislocations, is surrounded by it.

  FIG. 20 is a partial plan view of a nitride semiconductor defect position control substrate S having a parallelogram (diamond-shaped) defect accumulation region H. FIG. The defect accumulation region H exists so as to form a side of the parallelogram. A portion surrounded by the defect accumulation region H of the closed curve is the low defect region ZY.

  The defect position control substrate S can be made by the methods of Patent Documents 3 and 4 described above. A new requirement is a closed curve. In addition, device fabrication is facilitated using the special properties of the defect position control substrate S.

  What is it's nature? That is, the nitride semiconductor crystal is difficult to grow on the defect gathering region H, but the nitride semiconductor crystal grows easily on the low defect region ZY. This is a special property that was not known when Patent Documents 3 and 4 were invented. What is the identity of the defect gathering region H in the first place? This was not known when Patent Documents 3 and 4 were invented. Now, the identity of the defect gathering region H has been considerably understood.

  A base substrate having a three-fold symmetry is used. The nitride semiconductor grown thereon has a C plane on the top surface. However, since facet growth is performed, the flat C-plane does not exist so much during the growth, and the diagonal facet covers almost the entire surface. When the growth is finished and the facet surface is polished, it becomes a flat surface. This flat surface should be a C-plane. In the low defect area ZY, it is certainly the C plane. That is, it has been found that the upper surface of the low defect region ZY is a Ga surface (C surface) and the lower surface is an N surface.

  That is as expected. However, it has been found that the defect collecting region H is a single crystal, but is a single crystal with the c-axis reversed. That is, the upper surface of the defect gathering region H is the N surface, and the lower surface is the Ga surface. The defect position control substrate S is formed by combining a low defect region ZY having a Ga surface on the surface and a defect collecting region H having an N surface on the surface. The opposite is true when viewed from the back. On the back surface, the defect collecting region H is a Ga surface, and the low defect region ZY is an N surface.

If that is the case, the requirement for realizing the present invention does not yet exist, but after that, it is difficult for a nitride semiconductor to grow on the defect gathering region H (N plane), and on the low defect region ZY (Ga plane). It has been found that there is a growth rate selectivity that nitride semiconductors are easy to grow. The discovery of the selectivity of the growth rate of the Ga and N planes is completely new. First, it was described that gallium nitride is difficult to grow on the mask M when a mask (SiO ₂ , SiN, W, Pt) is attached on the base substrate (GaAs, sapphire, SiC). Therefore, the facet F with the mask M as the bottom was easily formed. That was non-uniformity (selectivity) of the growth rate between the base substrate US and the mask M.

  It is not the case that the present invention is newly discovered here, but the growth rate of the nitride semiconductor (AlInGaN) substrate made by the facet growth method is slow on the defect collecting region H and grown on the low defect region ZY. This is the non-uniformity of the growth rate that is high. Such discovery of selectivity is novel. Since the nitride semiconductor substrate itself (defect position control substrate S) composed of repetition of H and ZY is novel, the discovery of the selectivity of the growth rate of the crystal grown thereon is completely new.

The present invention takes advantage of the selectivity of the growth rate of such a nitride semiconductor defect position control substrate S at H and ZY. The growth rates on H and ZY are V _H and V _ZY . The selectivity here means V _H <V _ZY .

  In the present invention, the upper layer portion B may be grown on the defect position control substrate S via the separation layer Q, and the upper layer portion B may be grown without the separation layer Q.

Even when the isolation layer Q is grown, it hardly grows on the defect gathering region H, but grows only on the low defect region ZY. When the upper layer portion B is formed thereon, it does not grow on the defect gathering region H but grows only on the low defect region ZY. That is, the growth rate selectivity property (V _H <V _ZY ) of the defect position control substrate S is inherited by the nitride semiconductor epitaxially grown thereon. This is because the defect gathering region H is not simply because there are many defects, but because the crystal orientation is completely reversed. The isolation layer Q and the upper layer portion B grown on the N surface of the defect collecting region H must also be grown with the N surface as the upper surface. That's what epitaxial growth is all about. However, the N-plane and Ga-plane have selectivity and the crystal orientation is maintained, so that even if the number and thickness of the growth layers increase, it is maintained as an invariant property.

  Ideally, the growth layer is placed only on the low defect region ZY, and the epitaxial growth layer is not placed on the defect assembly region H. Even if the crystal is thinly deposited on the defect gathering region H, it can be easily removed by etching with KOH. As a result, the boundary groove on the defect gathering region H is clear.

  Therefore, when an impact or mechanical stress due to laser irradiation is applied to the epitaxially grown crystal, the upper layer portion B can be easily removed from the defect position control substrate S. Chip separation is performed in the horizontal direction as well as in the vertical direction. As described above, the present invention effectively utilizes the difference in growth rate between H and ZY of the defect position control substrate S.

  The AlInGaN defect position control substrate S including the closed curve defect gathering region H and the low defect region ZY surrounded by the defect gathering region H as shown in FIGS. 16, 18, 19, and 20 can be used as the starting substrate of the present invention.

[2. Separation layer Q (FIG. 21)]
The separation layer Q is between the defect position control substrate S and the upper layer portion B, and disappears or breaks when the separation layer Q is vertically separated. This is advantageous because the isolation layer Q has a selectivity that it is difficult to grow on the defect gathering region H and that it is easy to grow on the low defect region ZY. FIG. 21 shows a state in which the separation layer Q is grown on the defect position control substrate S. Although it grows on the low defect region ZY (AlInGa surface), it hardly grows on the defect assembly region H (N surface). It is desirable that the separation layer Q be sufficiently thin in order to save growth time and material.

  The separation layer Q has a thickness of about 3 nm to 1000 nm, for example. Although it may exceed 1000 nm, the material is wasted. If it is 3 nm or less, laser light is selectively absorbed and separated from the separation layer Q. The separation layer Q can be omitted by the vertical separation means W. The separation layer Q differs depending on the vertical separation means W. In the case of separation by laser irradiation L, there is a condition that the band gap Egq is smaller than the band gap Egs of the defect position control substrate S and the minimum band gap Egb of the upper layer portion B. In addition, the condition that the wavelength λ of the laser has energy in the middle of these band gaps is necessary.

    Egq <hc / λ <Egs, Egq <hc / λ <Egb

A semiconductor cannot absorb light with energy (hc / λ) smaller than the band gap, but can absorb light with energy larger than the band gap. FIG. 28 illustrates this. It is assumed that the separation layer Q and the upper layer part B are grown on the defect position control substrate S. The band gap Eg is written on the right side. The energy of the laser beam is represented by hν (h is Planck's constant, ν is wave number ν = c / λ). The band gap of the separation layer Q is smaller than hν, and the band gap of the upper layer portion B is larger than hν although there is variation. Laser light having a wavelength like the above inequality is transmitted through the upper layer portion B and the defect position control substrate S, but is completely absorbed by the separation layer Q. Since the separation layer Q is rapidly heated and decomposed, the upper layer portion B and the defect position control substrate S are vertically separated using the separation layer Q as a cut surface.

  As a material of the separation layer Q satisfying the above inequality, for example, the InN layer has a small band gap and can be used for any combination of B and S. InN has been used for a long time because it was not very useful and could not produce a good crystal. It turns out that it seems to be about 0.7eV now. Therefore, the band gap of InN is lower than that of GaN and AlN, and the band gap is lower than any of AlInGaN which is a mixed crystal thereof.

  When the upper and lower separation means W is mechanical, the separation layer Q is made of a mechanically fragile material. For example, the separation layer Q is a GaN crystal doped with any of C (carbon), Fe (iron), and Mg (magnesium). GaN doped with C, Fe, Mg or the like forms a brittle and easy-to-peel crystal. A lateral shear stress is applied to the upper and lower layers B and Q, or a tensile stress is applied by adsorbing the upper and lower layers B and Q. As a result, the upper layer portion B is separated from the defect position control substrate S.

[3. Upper layer part B (FIG. 22)]
The upper layer portion B is epitaxially grown on the separation layer Q. It is a laminated body of nitride semiconductor layers having various compositions. It hardly grows on the defect gathering region H and grows only on the low defect region ZY. Therefore, as shown in FIG. 22, a trapezoidal (mesa-type) upper layer portion B grows on the low defect region ZY. FIG. 22 shows a case where the upper surface electrode E is not formed. The portion that hits the defect gathering region H becomes a boundary line. This is an advantage of the defect position control substrate S. One trapezoid corresponds to the device.

  The present invention relates to a light emitting element such as a light emitting diode or a laser diode, a rectifier, a bipolar transistor, a field effect transistor, an electronic element such as a HEMT (High Electron Mobility Transistor), a temperature sensor, a pressure sensor, or a radiation sensor. For semiconductor sensors such as visible / ultraviolet light detectors, SAW devices (Surface Acoustic Wave Devices), vibrators, resonators, oscillators, MEMS (Micro Electro Mechanical System) components, piezoelectric actuators, etc. Widely used as a substrate. The structure of the upper layer portion B varies depending on the purpose of the nitride semiconductor device. In the present invention, the structure of the upper layer portion B is various.

  In the case of a light emitting element, the structure is a substrate portion, a buffer layer, a clad layer, an active layer, a clad layer, and a contact layer. The “substrate portion” is not a part of the defect position control substrate. Since the defect position control substrate S is recovered and reused, it does not become a part of the device. A part that becomes a backbone for maintaining the mechanical strength when the chips are separated is necessary. That portion is the “substrate portion” here. Later, it is simply written as n-GaN substrate or n-GaN, but it should not be interpreted as a part of the defect position control substrate S. 37 to 40 show longitudinal sectional views of the completed device. The upper layer portion B is a layer structure portion obtained by removing the upper electrode and the lower electrode from the completed device.

  In the case of the light receiving element, the substrate portion, the buffer layer, the light receiving layer, the window layer, and the contact layer are used. In the case of a Schottky diode, it means a substrate portion and an n-type layer. In the case of HEMT, the structure is a substrate portion, an i-type layer, and an i-type layer. After separating the upper layer portion B from the defect position control substrate S, an n-side electrode and a p-side electrode are formed. The upper layer part B will be described more specifically.

(In the case of LED: Fig. 37) From top to bottom
p-type GaN layer 65
p-type AlGaN layer 64
GaN / InGaN-MQW63 (GaN / InGaN) ₃
AlGaN layer 62
n-type GaN layer 60
The n-type GaN layer 60 hits the substrate portion. Here, MQW63 is formed by laminating two layers of GaN and InGaN three times.

(In the case of HEMT; Fig. 38) From top to bottom
i-AlGaN73
i-GaN72
GaN substrate 70
The GaN substrate 70 hits the substrate portion.

(In the case of a Schottky diode; Fig. 39) From top to bottom
n ^{― ―} GaN82
n-GaN substrate 80
The n-GaN substrate 80 hits the substrate portion.

(In the case of a vertical MIS transistor; FIG. 40)
N ⁺ type GaN95 from top to bottom
p-type GaN93
n ⁻ −GaN 92
n-GaN substrate 90
The n-GaN substrate 90 hits the substrate portion.

[4. Upper layer B + electrode E (FIG. 26)]
The upper layer part B is a stacked body of epitaxially grown layers. In some cases, the upper layer part B and the defect position control substrate S are separated after the wafer process is performed until the electrode E is formed thereon. If the substrate portion is n-type, the electrode on the upper layer portion B is often a p-side electrode. However, depending on the element structure, both the p-side and n-side electrodes can be provided on the upper surface. By doing so, electrode formation can be performed in the wafer process as in the normal wafer process. In the case of a light emitting device, the upper layer portion B has a structure of a substrate portion, a buffer layer, a cladding layer, an active layer, a cladding layer, a contact layer, and an electrode. In the case of a light receiving element, it has a structure such as a substrate portion, a buffer layer, a light receiving layer, a window layer, a contact layer, and an electrode. In the case of a Schottky diode, it means a substrate portion, an n-type layer, and a Schottky electrode. In the case of HEMT, the structure is a substrate portion, an i-type layer, an i-type layer, and an electrode. After separating the upper layer portion B from the defect position control substrate S, the remaining electrodes are formed on the back surface of the chip C.

(In the case of LED; Fig. 37) From top to bottom
p electrode (nickel Ni) 66
p-type GaN layer 65
p-type AlGaN layer 64
GaN / InGaN-MQW63 (GaN / InGaN) ₃
AlGaN layer 62
n-type GaN layer 60
Here, MQW is obtained by laminating two layers of GaN and InGaN three times.

(In the case of HEMT; Fig. 38) From top to bottom
Source electrode 74, drain electrode (Ti / Al / Ti / Au) 75, gate electrode (Au) 76
i-AlGaN73
i-GaN72
GaN substrate 70

(In the case of a Schottky diode; Fig. 39) From top to bottom
Schottky electrode (Au) 83
n ⁻ −GaN 82
n-GaN substrate 80

(In the case of a vertical MIS transistor; FIG. 40)
Source electrode (Ti / Al / Ti / Au) 97 in order from the top
Gate electrode (Au) 99
n ⁺ type GaN95
p-type GaN93
n ⁻ −GaN 92
n-GaN substrate 90

[5. Vertical separation means (FIGS. 23 and 27)]
Next, the upper layer part B is separated from the defect position control substrate S in the vertical direction. This is shown in FIGS. The part of the separation layer Q is destroyed, and the upper layer part B and the defect position control substrate S are separated vertically. The separation means will be described. Since the upper layer part B is separated in advance in the lateral direction with the defect gathering region H as a boundary, in the case of the present invention, it is separated in the vertical direction and at the same time, in the lateral direction. Therefore, the separation means is the vertical and horizontal separation means. There are means by laser irradiation and mechanical means. In addition, the separation layer Q may be used or the separation layer Q may not be used.

(5A. Separation by laser irradiation using the separation layer Q)
A separation layer Q is formed between the defect position control substrate S and the upper layer part B. The thickness of the separation layer Q is 3 nm to 1000 nm. The isolation layer Q also has a convenient property that it is difficult to grow on the defect gathering region H and easily grows on the low defect region ZY. When only the separation layer Q is decomposed by laser irradiation, the band gap of the separation layer Q is narrower than any of the semiconductor layers, the energy of the semiconductor laser is larger than the band gap of the separation layer Q, and other semiconductor layers Make it smaller than any of them. The band gap of the separation layer Q is defined as Egq, the band gap of the defect position control substrate S is defined as Egs, and the band gap of the jth surface layer of the upper layer portion B is defined as Egj. The conditions imposed on the laser light wavelength λ and the separation layer Q, the upper layer B, and the defect position control substrate S are Egq <hc / λ <Egs and Egq <hc / λ <min {Egj}.

Semiconductors and insulators transmit light having energy smaller than the band gap and absorb light having energy larger than the band gap. This is as shown in FIG. When laser light satisfying the above inequality is applied, the separation layer Q absorbs the laser light and is heated and thermally decomposed and disappears. Therefore, the upper layer part B and the defect position control substrate S are instantaneously separated in the vertical direction. For example, the InN layer is a separation layer Q. Since this has the smallest band gap among AlGaInN crystals, it selectively absorbs laser light and thermally decomposes.
In the upper layer portion B, since the growth layer is thin and weak in the defect gathering region H, the chips can be naturally separated using the defect gathering region H as a boundary line. Simultaneously with vertical separation, horizontal separation is possible, and chip C is cut off. The residue Q ′ of the separation layer Q may remain on the defect position control substrate S. It can be removed by polishing or etching. The defect position control substrate S having a flat and smooth surface can be reused.

(5B. Separation by mechanical means using separation layer Q)
A separation layer Q is formed between the defect position control substrate S and the upper layer part B. The thickness of the separation layer Q is 3 nm to 1000 nm. The upper layer part B and the defect position control substrate S are separated vertically by a mechanical means with the separation layer Q as a boundary. The separation layer Q is required to be a brittle crystal. For example, a GaN film doped with carbon C, magnesium Mg, and iron Fe can be used as the brittle separation layer Q. When the defect position control substrate S is fixed and the upper layer part B is pulled up, it is separated from the brittle separation layer Q.

(5C. When separating by laser irradiation without using the separation layer Q)
The upper and lower layers can be separated without using the separation layer Q. The upper layer portion B is formed directly on the defect position control substrate S. In this case, since there is no portion to be broken at the sacrifice, it cannot be separated vertically by mechanical means. So mechanical separation means cannot be applied. Only light separation by laser irradiation is possible. In this case, the upper layer portion B absorbs the laser light and a part of the laser beam is decomposed to be separated from the defect position control substrate S in the vertical direction. The band gap Egs of the defect position control substrate S, the minimum band gap Egb of the upper layer portion B, and the laser wavelength λ must satisfy the inequality Egb <hc / λ <Egs.

[6. Formation of upper surface electrode (FIG. 24)]
As shown in FIG. 23, the upper layer B is separated into chips. Upper electrodes P and P are formed on the upper surface of each chip C. A chip having an upper electrode can be formed as shown in FIG. This is a case where the upper electrodes P, P are not formed by the wafer process as shown in FIGS. However, as shown in FIGS. 26 and 27, the upper electrodes P and P can be formed by a wafer process. In that case, it is not necessary to form the upper electrodes P and P after separating the chips.

[7. Formation of bottom electrode (FIG. 25)]
Next, the lower electrode R is formed on the back surface of the upper layer portion B for each chip. This makes a device chip. It is a disadvantage of the present invention that the lower electrode R cannot be formed during the wafer process. However, there is a case where the lower electrode R is unnecessary as shown in FIG.

[8. Chip shape shaping (FIGS. 29 to 36)]
The upper layer B that has grown with the defect gathering region H as a boundary often becomes a mesa shape (trapezoid). Even a mesa type may function as a device. However, there are cases where a rectangular parallelepiped chip having the same size on the upper and lower surfaces is preferable. In this case, after separating the chips, the side surfaces and end surfaces are polished to finish the side walls at right angles.

  FIG. 29 shows a mesa chip C having a square bottom surface and a top surface. If it may be a mesa type, the shape is kept as it is. Further, as shown in FIG. 30, a rectangular parallelepiped device in which end faces and side faces are machined to make these faces perpendicular to each other can be obtained. FIG. 31 shows an equilateral triangular mesa chip C separated from the chip. The end face can be processed into a regular triangular chip C having a right end face as shown in FIG. FIG. 33 shows a mesa parallelogram chip C. FIG. This can also be used as it is, or it can be a parallelogram chip C whose end face is perpendicular as shown in FIG. FIG. 35 shows a mesa-shaped regular hexagonal tip C. FIG. This can also be processed into a regular hexagonal tip C having a right end face as shown in FIG.

[9. Final device shape (FIGS. 37 to 40)]
Although it may be a mesa type, here, the state of the chip C to which the electrode of the device with the end face side surface made perpendicular is shown. The laminated structure does not include the defect position control substrate S and consists only of the upper layer portion B. The thickness of the upper layer part B shall be 10 micrometers-600 micrometers. Since a substrate cut out to include a substrate like a normal semiconductor device has a thick substrate, the thickness of the stacked portion of the device is about 300 μm to 600 μm. However, in the present invention, since the semiconductor laminated structure is composed of only the upper layer portion B, the upper layer portion B thickness can be 10 μm to 300 μm.

(In the case of LED; Fig. 37) From top to bottom
p electrode (nickel Ni) 66
p-type GaN layer 65
p-type AlGaN layer 64
GaN / InGaN-MQW63 (GaN / InGaN) ₃
AlGaN layer 62
n-type GaN layer 60
n electrode (Ti / Al / Ti / Au) 67

(In the case of HEMT; Fig. 38) From top to bottom
Source electrode 74, drain electrode (Ti / Al / Ti / Au) 75, gate electrode (Au) 76
i-AlGaN73
i-GaN72
GaN layer 70

(In the case of a Schottky diode; Fig. 39) From top to bottom
Schottky electrode (Au) 83
n ⁻ −GaN 82
n-GaN substrate 80
Ohmic electrode (n electrode: Ti / Al / Ti / Au) 84

(In the case of a vertical MIS transistor; FIG. 40)
Source electrode (Ti / Al / Ti / Au) 97 in order from the top
Gate electrode (Al) 99
n ⁺ type GaN95
p-type GaN93
n ⁻ −GaN 92
n-GaN substrate 90
Drain electrode (Ti / Al / Ti / Au) 94

S Defect position control board
ZY low defect area
H Defect assembly area
B Upper layer
C chip
YC plane growth region
Z Low defect single crystal region
Q separation layer
60 n-type GaN layer
62 AlGaN layer
63 MQW
64 p-type AlGaN layer
65 p-type GaN layer
66 p-electrode
67 n-electrode
70 GaN substrate
72 i-GaN
73 i-AlGaN
74 Source electrode
75 Drain electrode
76 Gate electrode
80 n-GaN substrate
82 n ⁻ −GaN
83 Schottky electrode
84 Ohmic electrode
90 n-GaN substrate
92 n ⁻ -GaN
93 p-GaN
94 Drain electrode
95 n ⁺ -GaN
97 Source electrode
99 Gate electrode

Claims (11)

A plurality of nitride semiconductor layers (Al _uj In _vj Ga _{1 -uj-vj} N: 0 ≦ u _j ≦ 1, 0 ≦ v _j ≦ 1, u _j are formed on the upper surface of a chip which is a semiconductor device. A nitride semiconductor device having an upper layer portion in which + v _j ≦ 1) is laminated, and having a mesa type in which end faces around the chip are all formed by facet by crystal growth.   The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device has a thickness of 10 µm to 600 µm and a horizontal dimension of 0.2 mm to 50 mm. Nitride semiconductor (Al _x In _y Ga _1-xy N: 0 ≦ x ≦ 1, 0 ≦ y) including a defect assembly region H formed in a closed curve shape and a low defect region ZY surrounded by the defect assembly region H ≦ 1, x + y ≦ 1) On the defect position control substrate S, a plurality of silicon nitride semiconductor layers (Al _uj In _vj Ga _{1 -uj-vj} N: 0 ≦ u _j ≦ 1, 0 ≦ v _j ≦ 1, u _j + v _j ≦ 1) and forming the upper layer portion B, and separating the upper layer portion B from the defect position control substrate S up and down. Simultaneously with the separation step, the wafer is separated along the defect collecting region H in the lateral direction and separated into individual chips, the chip end faces are formed by growth facets, have a mesa shape, and have a thickness of 10 μm to 600 μm. And the horizontal dimension is 0.2 mm to 50 mm. Nitride semiconductor device characterized by and. Nitride semiconductor (Al _x In _y Ga _1-xy N: 0 ≦ x ≦ 1, 0 ≦ y) including a defect assembly region H formed in a closed curve shape and a low defect region ZY surrounded by the defect assembly region H ≦ 1, x + y ≦ 1) On the defect position control substrate S, a plurality of nitride semiconductor layers (Al _uj In _vj Ga _1-uj-vj N: 0 ≦ u _j ≦ 1, 0 ≦ v _j ≦ 1, u _j + v _j ≦ 1) to form an upper layer portion B, and a step of separating the upper layer portion B from the defect position control substrate S in the vertical direction. Simultaneously with the separation step, the wafer is separated along the defect collection region H in the lateral direction to be separated into individual chips, the chip end faces are formed by growth facets, the thickness is 10 μm to 600 μm, and the horizontal dimension is 0. Nitride half characterized by being 2 mm to 50 mm Body device. Nitride semiconductor (Al _x In _y Ga _1-xy N: 0 ≦ x ≦ 1, 0 ≦ including defect assembly region H formed in a closed curve and low defect region ZY surrounded by defect assembly region H y ≦ 1, x + y ≦ 1) A nitride semiconductor isolation layer Q having a narrow band gap Egq is grown on a defect position control substrate S, and a plurality of nitride semiconductor layers (Al _uj In _vj Ga _1-uj-vj N: 0 ≦ u _j ≦ 1, 0 ≦ v _j ≦ 1, u _j + v _j ≦ 1) is formed as the upper layer portion B, which is higher than the band gap Egq of the separation layer Q The separation layer Q is decomposed by irradiating a laser beam (Egq <hc / λ <Egb) having an energy lower than the minimum value Egb (min {Egj}) of the band gap of the upper layer portion B, so that the upper layer portion B From the defect position control board S up and down At the same time as separating, along the defect gathering region H in the lateral direction, it is separated into individual chips, the chip end faces are formed by growth facets, have a mesa shape, and have a thickness of 10 μm to 600 μm A nitride semiconductor device having a horizontal dimension of 0.2 mm to 50 mm. Nitride semiconductor (Al _x In _y Ga _1-xy N: 0 ≦ x ≦ 1, 0 ≦ y) including a defect assembly region H formed in a closed curve shape and a low defect region ZY surrounded by the defect assembly region H ≦ 1, x + y ≦ 1) A nitride semiconductor isolation layer Q having a narrow band gap Egq is grown on the defect position control substrate S, and a plurality of nitride semiconductor layers (Al _uj ) for forming a device thereon are formed. In _vj Ga _1-uj-vj N: 0 ≦ u _j ≦ 1, 0 ≦ v _j ≦ 1, u _j + v _j ≦ 1) is formed as an upper layer portion B, which is higher than the band gap Egq of the separation layer Q The separation layer Q is decomposed by irradiating laser light having a lower energy (Egq <hc / λ <Egb) than the minimum band gap Egb (min {Egj}) of the layer B, so that the upper layer B Separated vertically from defect position control board S At the same time, it is separated along the defect gathering region H in the lateral direction and separated into individual chips, the chip end faces are formed by growth facets, the thickness is 10 μm to 600 μm, and the horizontal dimension is 0.2 mm to A nitride semiconductor device having a thickness of 50 mm. Nitride semiconductor (Al _x In _y Ga _1-xy N: 0 ≦ x ≦ 1, 0 ≦ y) including a defect assembly region H formed in a closed curve shape and a low defect region ZY surrounded by the defect assembly region H ≦ 1, x + y ≦ 1) A brittle nitride semiconductor isolation layer Q is grown on the defect position control substrate S, and a plurality of nitride semiconductor layers (Al _uj In _vj Ga) for forming a device thereon are formed. _1-uj-vj N: 0 ≦ u _j ≦ 1, 0 ≦ v _j ≦ 1, u _j + v _j ≦ 1) are stacked to form the upper layer portion B, and the defect position control substrate S and the upper layer portion B are displaced or The separation layer Q is broken by applying a tensile stress, and the upper layer B is separated vertically from the defect position control substrate S, and at the same time, is separated along the defect collection region H in the lateral direction to be separated into individual chips. Is formed by growth facets and has a mesa shape Cage, the thickness was 10Myuemu～600myuemu, nitride semiconductor devices, wherein the horizontal dimension is 0.2Mm～50mm. Nitride semiconductor (Al _x In _y Ga _1-xy N: 0 ≦ x ≦ 1, including defect assembly region H and low defect region ZY, in which defect assembly region H is formed in a closed curve surrounding low defect region ZY 0 ≦ y ≦ 1, x + y ≦ 1) A plurality of nitride semiconductor layers (Al _uj for forming a device having a band gap Egj smaller than the band gap Egs of the defect position control substrate S on the defect position control substrate S In _vj Ga _1-uj-vj N: 0 ≦ u _j ≦ 1, 0 ≦ v _j ≦ 1, u _j + v _j ≦ 1) are formed as the upper layer portion B, and from the band gap Egs of the defect position control substrate S A part of the upper layer part B is decomposed by irradiating laser light having a lower energy (Egq <hc / λ <Egs) than the minimum band gap Egb (min {Egj}) of the upper layer part B. The upper layer B is missing Separated vertically from the recessed position control substrate S along the defect gathering region H in the lateral direction and separated into individual chips, the chip end faces are formed by growth facets, and the thickness is 10 μm to 600 μm. A nitride semiconductor device having a horizontal dimension of 0.2 mm to 50 mm. 4. The nitride-based semiconductor grows at a slow growth rate on the defect gathering region H, and the nitride-based semiconductor grows at a high growth rate on the low-defect region ZY. Nitride semiconductor device in any one of -8.   9. The nitride semiconductor device according to claim 3, wherein an upper electrode is formed following the formation of the upper layer portion B, and only the lower electrode is formed after chip separation.   9. The nitride semiconductor device according to claim 3, wherein an upper electrode and a lower electrode are formed after chip separation without forming an upper electrode following the upper layer portion B.

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