JP2011091102A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that is achieved in the reduction of the opening current. <P>SOLUTION: The semiconductor device includes a plurality of circuit blocks. Operation stop voltages Vstop in a plurality of circuit blocks are equal to each other. A P-type transistor is used in a critical path of operation timing for determining the operation stop voltages Vstop. P-type impurity densities in a semiconductor immediately below a gate electrode of the P-type transistor are equal to each other between the plurality of circuit blocks. N-type impurity densities in a semiconductor immediately below a gate electrode of an N-type transistor used in the critical path are also equal to each other between the plurality of circuit blocks. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a plurality of circuit blocks.

  In recent years, there has been a growing demand for functional operation with a long battery life or a small amount of self-power generation for wristwatches and portable devices, and ultra-low power consumption of semiconductor devices has been energetically promoted. For example, in a low power type semiconductor device using a 32 KHz crystal resonator, 150 nW (1.0 V, 150 nA; see, for example, Patent Document 1) or 25 nW (0.5 V, 50 nA; for example, Patent Document 2) )) Is required. In order to meet these requirements, the drive voltage (Vreg) of the semiconductor device is set to a minimum value that is necessary for the semiconductor device to operate normally (ie, the operation stop voltage (Vstop)). Therefore, it has been attempted to realize low voltage driving of the semiconductor device and reduce power consumption.

JP 2003-134682 A JP 2002-111007 A

  In the above method, Vreg needs to be set to a value larger than Vstop by an amount corresponding to the margin. The largest of the required margins is the margin for the environmental temperature. Conventionally, it has been usual to set Vreg to be about 0.1 to 0.2 V higher than Vstop as a margin for changes in environmental temperature (see, for example, Patent Document 1).

  In addition, in order to reduce the margin for changes in environmental temperature, using the SOI (Silicon On Insulator) structure with low temperature dependence of electrical characteristics, the logic circuit and the analog circuit are separately used as the body tie type and the floating body type. In addition, a proposal has been made to make the threshold voltages of the body tie type and floating body type transistors have the same value (see, for example, Patent Document 2).

However, in the prior art, Vstop of various circuit blocks included in the semiconductor device is different for each circuit block, and Vreg-Vstop (that is, a margin of drive voltage) is different among a plurality of circuit blocks. For example, as shown in FIG. 9, when the operation stop voltage of the first circuit block is Vstop (1) and the operation stop voltage of the second circuit block is Vstop (2), Vstop (1), Vstop ( 2) had different values in the temperature range of −70 ° C. to 20 ° C., and Vreg−Vstop (1) ≠ Vreg−Vstop (2). For this reason, in the conventional technique, there is a tendency that a circuit block having a large drive voltage margin consumes current wastefully, and the current consumption of the entire semiconductor device may not be sufficiently reduced.
Accordingly, some aspects of the present invention have been made in view of such circumstances, and an object thereof is to provide a semiconductor device capable of reducing current consumption of the entire semiconductor device.

  In order to achieve the above object, a semiconductor device according to one embodiment of the present invention is a semiconductor device including a plurality of circuit blocks, and operation stop voltages Vstop in each of the plurality of circuit blocks are equal to each other, and the operation stop is performed. The P-type impurity concentration in the semiconductor immediately under the gate electrode of the P-type transistor used for the critical path of the operation timing for determining the voltage Vstop is equal among the plurality of circuit blocks, and the N-type transistor used for the critical path is the same. The N-type impurity concentration in the semiconductor directly under the gate electrode is also equal among the plurality of circuit blocks.

  Here, the “operation stop voltage Vstop” is, for example, the minimum drive voltage necessary for a circuit block or the like to operate normally. The “critical timing of operation timing for determining the operation stop voltage Vstop” means at least a part of a circuit that requires the highest voltage for the circuit block to operate normally, or It is at least part of a circuit that becomes a bottleneck for voltage reduction. The “semiconductor directly under the gate electrode” is a body region when the transistor is formed on an SOI substrate, and a channel region when the transistor is formed on a bulk silicon substrate.

  With such a configuration, the temperature dependence of the operation stop voltage Vstop in each of the plurality of circuit blocks can be made to substantially coincide with each other between the plurality of circuit blocks. The operation stop voltage Vstop in each can be made substantially equal to the operation stop voltage of the entire semiconductor device including the plurality of circuit blocks (that is, the maximum value of the operation stop voltage: Vstopmax). Thereby, in each of the plurality of circuit blocks, Vreg−Vstop (that is, the margin of the drive voltage) can be reduced, so that the current consumption of the entire semiconductor device can be reduced.

  The semiconductor device includes an oscillation circuit and a frequency dividing circuit as the plurality of circuit blocks, and the oscillation circuit is used for a critical path of an operation timing for determining the operation stop voltage Vstop of the oscillation circuit. A first P-type transistor and a first N-type transistor, and the frequency divider circuit is used for a critical path of an operation timing for determining the operation stop voltage Vstop of the frequency divider circuit. A P-type transistor and a second N-type transistor, wherein the first P-type transistor and the second P-type transistor have the same P-type impurity concentration in the semiconductor immediately under the gate electrode, and In the semiconductor immediately below each gate electrode of the first N-type transistor and the second N-type transistor -Type impurity concentration are equal to each other, it may be characterized in that. With such a configuration, the temperature dependence of Vstop can be substantially matched in each of the oscillation circuit and the frequency dividing circuit. For example, in the oscillation circuit, Vreg−Vstop can be reduced, or the through current of the oscillation inverter can be reduced.

In the semiconductor device, the threshold voltage of each of the P-type transistor and the N-type transistor used for the critical path may be controlled by a work function of the gate electrode. With such a configuration, the threshold voltage of the transistor can be adjusted without affecting the temperature dependence of the operation stop voltage Vstop.
In the semiconductor device, the threshold voltage of each of the P-type transistor and the N-type transistor used for the critical path may be controlled by a fixed charge or work function of the gate insulating film. With such a configuration, the threshold voltage of the transistor can be adjusted without affecting the temperature dependence of the operation stop voltage Vstop.

  The semiconductor device may further include a power supply circuit that supplies a drive voltage Vreg to the oscillation circuit and the frequency divider circuit, and the power supply circuit includes a third P-type transistor that determines the drive voltage Vreg; A third N-type transistor, and a P-type impurity concentration in a semiconductor immediately below the gate electrode of the third P-type transistor is equal to a semiconductor immediately below the gate electrode of the first P-type transistor or the second P-type transistor. The N-type impurity concentration in the semiconductor immediately below the gate electrode of the third N-type transistor is equal to the N-type impurity concentration in the semiconductor immediately below the gate electrode of the first N-type transistor or the second N-type transistor. It may be characterized by being equal to the type impurity concentration. With such a configuration, the temperature dependency of the drive voltage Vreg can be made substantially coincident with the temperature dependency of the operation stop voltage Vstop.

1 is a diagram illustrating a configuration example of a semiconductor device 100 according to an embodiment of the present invention. 2 is a diagram illustrating a configuration example of a frequency divider circuit 10. FIG. The figure which shows the structural example of the FF circuit 10, and the operation example. FIG. 3 is a diagram showing a configuration example of an oscillation circuit 40. FIG. 6 illustrates a configuration example of an SOI substrate. The figure which shows the structural example of the MOS transistor used for each circuit block. The figure which shows the temperature dependence of Vreg and Vstop. The figure which shows reduction of a through current. The figure which shows a prior art example.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and redundant description thereof is omitted.
[Configuration example of the entire semiconductor device]
FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device 100 according to an embodiment of the present invention. A semiconductor device 100 illustrated in FIG. 1 is an example of a semiconductor device including various circuit blocks, and is, for example, an integrated circuit incorporated in a watch. The semiconductor device 100 includes, for example, a frequency divider circuit 10, a control circuit 20, a detection circuit 30, an oscillation circuit 40, and a power supply circuit 50. The frequency dividing circuit 10 and the control circuit 20 are logic circuits, and the detection circuit 30, the oscillation circuit 40, and the power supply circuit 50 are analog circuits. The logic circuit and the analog circuit are formed on the same SOI substrate, for example. Here, the SOI substrate is a substrate having a structure in which an insulating layer 8 is stacked on a support substrate 7 and a semiconductor layer 9 is stacked on the insulating layer 8 as shown in FIG. The insulating layer 8 is, for example, a silicon oxide film, and the semiconductor layer 9 is, for example, a single crystal silicon layer. First, a configuration example of the frequency dividing circuit 10 will be described.

[Configuration example of divider circuit]
FIG. 2 is a diagram illustrating a configuration example of the frequency dividing circuit 10. As shown in FIG. 2, the frequency divider 10 has a structure in which n (n is an integer of 2 or more) FF circuits 10 are connected over n stages (that is, n FF circuits 10 are connected in series in n stages). Structure). The FF circuit 10 is, for example, a quasi-static T flip-flop circuit. In the frequency divider circuit 10, the input terminal C1 of the first stage FF circuit 60 is connected to, for example, the oscillation circuit 40, and the output terminal Q1 of the first stage FF circuit 60 is connected to the input terminal C2 of the second stage FF circuit 60. It is connected to the. Similarly, when n is 3 or more, the output terminal Qn−1 of the (n−1) th FF circuit 60 is connected to the input terminal Cn of the nth FF circuit 60 and the (n−1) th FF circuit 60 is connected. Are connected to the output terminal XQn of the nth FF circuit 60, respectively.

  3A and 3B are a circuit diagram showing a configuration example of the FF circuit 10 and a timing chart showing an operation example thereof. As shown in FIG. 3A, the FF circuit 10 includes clocked inverters 1, 3, 4, and 5 and inverters 2 and 6. Each of the clocked inverters 1, 3, 4, 5 is provided with one or both of a C input terminal and an XC input terminal. Here, a signal input to the C input terminal (that is also referred to as a C input signal) is a clock signal, and is a signal that repeats H and L at regular intervals. A signal (that is, an XC input signal) input to the XC input terminal is a signal obtained by inverting H and L of the C input signal. The inverters 2 and 6 are each provided with a set terminal and a reset terminal (not shown).

  The connection relationship between the clocked inverters 1, 3, 4, 5 and the inverters 2 and 6 will be described. As shown in FIG. 3A, the output terminal of the clocked inverter 1 is connected to the input terminal of the inverter 2, It is connected to the output terminal of the clocked inverter 3. The output terminal of the inverter 2 and the input terminal of the clocked inverter 3 are connected to the input terminal of the clocked inverter 4. Furthermore, the output terminal of the clocked inverter 4 is connected to the output terminal of the clocked inverter 5, the input terminal of the inverter 6, the input terminal of the clocked inverter 1, and the Q output terminal. The input terminal of the clocked inverter 5 and the output terminal of the inverter 6 are connected to the XQ output terminal.

Thus, in synchronization with the C input signal, the Q output signal is output from the Q output terminal, and the XQ output signal is output from the XQ output terminal. As shown in FIG. 3B, the Q output signal is a signal having a period twice that of the C input signal (that is, the frequency is ½), and the XQ output signal is H and L of the Q output signal. Is a signal obtained by inverting.
The frequency dividing circuit 10 having such a structure sequentially divides a high-frequency clock signal by the FF circuit 10 in each stage and converts it to a low-frequency signal. Therefore, the inverter included in the FF circuit 10 on the side closer to the oscillation circuit (that is, the front stage) operates with a clock signal having a higher frequency and is included in the FF circuit 10 on the side farther from the oscillation circuit (that is, the rear stage). The inverter operates with a low frequency clock signal.

  For example, when an input signal of 32 kHz is supplied from the oscillation circuit, the FF circuit 10 divides the input signal by 2 (that is, converts the frequency to 1/2) and outputs it. The 32 kHz signal finally becomes 1 Hz. At this time, the inverter configuring the first stage FF circuit 10 operates with a signal of, for example, 32 KHz, and the inverter configuring the 15th stage FF circuit 10 operates with, for example, a signal of 1 Hz. Next, a configuration example of the oscillation circuit 40 will be described.

[Configuration example of oscillation circuit]
FIG. 4 is a circuit diagram illustrating a configuration example of the oscillation circuit 40. As shown in FIG. 4, the oscillation circuit 40 includes an oscillation inverter 41, a crystal oscillator 42, a resistor 43, and capacitors 44 to 46. In the oscillation circuit 40, a resonance circuit is configured by the crystal oscillator 42 and the capacitors 44 and 45, and an oscillation inverter 41 is connected to the resonance circuit to oscillate a specific frequency (for example, 32 kHz). It is like that. A waveform shaping NAND circuit 90 is connected to the output terminal of the oscillation circuit 40.

[Operation stop voltage Vstop]
By the way, in the semiconductor device 100, in order to realize the low power consumption, each circuit block (that is, the frequency divider circuit 10, the control circuit 20, the detection circuit 30, the oscillation circuit 40, and the power supply circuit 50) is realized. In each case, the value of the operation stop voltage Vstop is set to the value of the operation stop voltage of the entire semiconductor device 100 (that is, the maximum value of the operation stop voltage: Vstopmax). That is, all Vstops of each circuit block are set to Vstopmax.

  More specifically, Vstop in the oscillation circuit 40 is determined by a voltage at which the crystal oscillator 42 cannot supply energy loss for continuing oscillation. Further, Vstop in logic circuits such as the frequency divider circuit 10 and the control circuit 20 is determined by a voltage at which information processing cannot be performed due to an increase in element delay time. Here, in the semiconductor device 100 shown in FIG. 1, since the frequency divider circuit 10 operates normally, other circuit blocks (that is, the control circuit 20, the detection circuit 30, the oscillation circuit 40, and the power supply circuit 50). Higher voltage than each).

  Further, at least in the logic circuit, the frequency divider circuit 10 operates at the highest frequency (for example, 32 kHz) and has a critical path of operation timing for determining the operation stop voltage Vstopmax of the entire semiconductor device 100. For example, if the threshold voltage is set so that the off-leak current of the MOS transistor constituting the frequency divider circuit 10 is about 1 nA, the 32 kHz logic function stops when the drive voltage becomes less than 0.3 V. .

  On the other hand, most of the MOS transistors constituting the control circuit 20 operate at a low frequency (for example, 8 Hz). For this reason, when the threshold voltage of the MOS transistor constituting the control circuit 20 is set so that the off-leakage current is about 1 nA, even if the driving voltage is lower than 0.3 V (for example, 0.25 V). Its logic function works correctly. Thus, the frequency divider circuit 10 requires a higher voltage than other circuit blocks in order to operate normally. From the viewpoint of lowering the voltage of the entire semiconductor device, the frequency dividing circuit is a bottleneck.

  Therefore, in this semiconductor device 100, the operation stop voltage Vstop of the frequency dividing circuit 10 is set to Vstopmax, and all Vstops of other circuit blocks (that is, the control circuit 20, the detection circuit 30, the oscillation circuit 40, and the power supply circuit 50) are all Vstopmax. (Ideally match). That is, all Vstops of other circuit blocks are raised to Vstopmax. Such adjustment of Vstop in each circuit block is performed by adjusting the threshold voltage of the MOS transistor used in the critical path of the operation timing for determining the operation stop voltage Vstop in each circuit block.

Here, the critical path of the operation timing for determining Vstop of the frequency divider circuit 10 is the FF circuit 10, and particularly, the FF circuit 10 in the previous stage (including at least the first stage) operating at a high frequency. As described above, most of the control circuit 20 operates at a low frequency (for example, 8 Hz). Since the operation frequency of the control circuit 20 is substantially uniform, the critical path of the operation timing for determining the Vstop of the control circuit 20 can be regarded as the entire control circuit 20. The critical path of the operation timing for determining Vstop of the oscillation circuit 40 is the oscillation inverter 41 and the NAND circuit 90.
As will be described later, the threshold voltage of the MOS transistor in each circuit block is controlled by controlling the work function of the gate electrode or the fixed charge or work function of the gate insulating film in order to eliminate the temperature dependence of the threshold voltage. To do.

[Body region impurity concentration]
Further, in this semiconductor device 100, the impurity concentration in the body region (that is, the semiconductor layer directly under the gate electrode) of the MOS transistor used for the critical path of the operation timing for determining the operation stop voltage Vstop in each circuit block is P channel type. Each N-channel type is the same between each circuit block.

  6A to 6C are cross-sectional views showing a configuration example of a MOS transistor used in each circuit block. FIG. 6A shows a P-type MOS transistor 51 and an N-type MOS transistor 56 used for the critical path of the frequency divider circuit 10, and FIG. 6B shows a P-type MOS used for the critical path of the oscillation circuit 40. A transistor 61 and an N-type MOS transistor 66 are shown. FIG. 6C shows a P-type MOS transistor 71 and an N-type MOS transistor 76 that determine the drive voltage Vreg of the power supply circuit 50.

  As shown in FIGS. 6A to 6C, in this semiconductor device 100, the N-type impurity concentration (that is, the donor concentration) in the body region 52 of the P-type MOS transistor 51 is Nd1, and the P-type MOS transistor 61 When the donor concentration in the body region 62 is Nd2 and the donor concentration in the body region 72 of the P-type MOS transistor 71 is Nd3, these respective concentrations are Nd1 = Nd2 = Nd3.

Further, the P-type impurity concentration (that is, the acceptor concentration) in the body region 57 of the N-type MOS transistor 56 is Na1, the acceptor concentration in the body region 67 of the N-type MOS transistor 66 is Na2, and the body region of the N-type MOS transistor 76. When the acceptor concentration in 77 is Na3, these concentrations are Na1 = Na2 = Na3.
Thereby, the temperature dependence of the threshold voltages of the P-type MOS transistors 51, 61, 71 is substantially the same between the P-type MOS transistors 51, 61, 71. The temperature dependence of the threshold voltage of the N-type MOS transistors 56, 66, and 76 is also the same between the N-type MOS transistors 56, 66, and 76.

[Control of threshold voltage]
In the semiconductor device 100, the threshold voltages of the MOS transistors 51, 56, 61, 66, 71, and 77 shown in FIGS. 6A to 6C are the work function of the gate electrode or the gate insulating film. It is controlled by a fixed charge or a work function of the gate insulating film.
That is, the threshold voltages of the MOS transistors 51, 56, 61, 66, 71, and 77 change the work function by using silicide, metal, and alloy for the gate electrodes 53, 58, 63, 68, 73, and 78, respectively. Thus, the optimum threshold voltage required to make the Vstops of the circuit blocks coincide with each other is set. Alternatively, the threshold voltages of the MOS transistors 51, 56, 61, 66, 71, 77 change the fixed charges of the gate insulating films 54, 59, 64, 69, 74, 79 or their work functions, respectively. It is set to an optimum threshold voltage required to make the Vstops of the circuit blocks coincide.

Here, the threshold voltage Vth of the MOS transistor is expressed by the following equation (i). The temperature dependence of Vth is expressed by the following equation (ii).
Vth = Φms−Qi / Ci + 2ψB + √ (4εs · q · NA · ψB) / Ci (i)
dVth / dT = dψB / dT · (2 + 1 / Ci · √ (εsqNA / ψB) (ii)
In the above equations (i) and (ii), Φms is the work function difference between the gate electrode and silicon, Qi is the fixed charge of the gate insulating film, Ci is the capacitance of the gate insulating film, and ψB is the Fermi of the body and the intrinsic semiconductor. The level difference, εs is the dielectric constant of Si, q is the charge, NA is the impurity concentration of the body, and T is the temperature.

  As can be seen from the equation (i), the threshold voltage Vth of the MOS transistor can be adjusted to an arbitrary value by controlling the work function of the gate electrode, the fixed charge of the gate insulating film, or the work function thereof. . That is, in the MOS transistor, even if the impurity concentration in the body region is the same, the threshold voltage Vth is set to a different value by controlling the work function of the gate electrode or the fixed charge of the gate insulating film or the work function thereof. Can be set to

  For silicide, the work function can be controlled by using different materials such as TiSi2, CoSi2, PtSi, and NiSi, or by doping impurities such as As, Sb, and BF2 into the same silicide. For alloys, the work function can be controlled by changing the composition ratio, such as RuMo. Alternatively, a high-K material such as HfO may be used for the gate insulating film, and the work function and the oxide film charge may be controlled by controlling the doping amount of Al or the like.

  As can be seen from the equation (ii), the temperature dependence of the threshold voltage Vth of the MOS transistor depends on φB and NA, that is, the impurity concentration of the body region. The temperature dependence of the threshold voltage Vth is not affected by the work function of the gate electrode, the fixed charge of the gate insulating film, or the work function thereof. In the semiconductor device 100 described above, the threshold voltages Vth of the MOS transistors 51, 56, 61, 66, 71, and 77 are set to different (that is, optimized) values, and the P channel is related to the temperature dependency thereof. Each type and N channel type can be substantially the same.

[About reduction of current consumption]
FIG. 7 is a diagram illustrating the temperature dependence of Vreg and Vstop in the semiconductor device 100. The horizontal axis in FIG. 7 is temperature (° C.), and the vertical axis is voltage (V).
As shown in FIG. 7, in this semiconductor device 100, the operation stop voltage Vstop of the frequency divider circuit 10 is set to Vstopmax, and other circuit blocks (that is, the control circuit 20, the detection circuit 30, the oscillation circuit 40, and the power supply circuit 50). All Vstops are raised to Vstopmax. That is, Vstop of each circuit block is substantially equal to Vstopmax. As described above, the Vstop control in each circuit block is performed by parameters that do not affect the temperature dependence of the threshold voltage Vth, such as the work function of the gate electrode, the fixed charge of the gate insulating film, or the work function thereof. This is achieved by adjusting the threshold voltage Vth.

  Further, as described above, the MOS transistors 51 and 58 that constitute the critical path of the frequency dividing circuit 10, the MOS transistors 61 and 68 that constitute the critical path of the oscillation circuit 40, and the MOS transistor that determines the Vreg of the power supply circuit The impurity concentrations of the body regions 71 and 76 are substantially the same for each P channel and each N channel. As a result, the temperature dependence of Vstop (= Vstopmax) of each circuit block and the temperature dependence of Vreg are almost the same.

Thus, in an arbitrary temperature range (for example, a temperature range of −20 to 70 ° C.), Vstop of each circuit block substantially matches Vstopmax, and the temperature dependence of Vstop (= Vstopmax) and the temperature dependence of Vreg. Therefore, Vreg-Vstop need not take into account variations between circuit blocks and margins for environmental temperature, and Vreg-Vstop can be reduced (ideally minimized). it can. Thereby, it is possible to reduce waste of current consumption in each circuit block.
In addition, in the control circuit 20, the detection circuit 30, the oscillation circuit 40, the power supply circuit 50, and the like, the absolute value of the threshold voltage of the MOS transistor is set higher with the adjustment of Vstop to Vstopmax. Therefore, for example, a reduction in off-leakage current can be expected for MOS transistors that are normally off in these circuit blocks.

  Further, even in an inverter operating at a relatively high frequency such as the oscillation inverter 41 included in the oscillation circuit 40, both the absolute value of the threshold voltage of the P-type MOS transistor and the threshold voltage of the N-type MOS transistor are set higher. The As a result, for example, as shown in FIG. 8, the transfer characteristics (that is, the Vg-Ig characteristics) of the P-type MOS transistor and the N-type transistor are shifted from the broken line to the solid line to the high voltage side. Can be expected to be reduced. Here, the through current flows from the power supply potential to the ground potential through the P-type MOS transistor and the N-type MOS transistor when the P-type MOS transistor and the N-type MOS transistor are simultaneously turned on for an instant. It is the current that ends up.

  As described above, according to the semiconductor device 100 according to the embodiment of the present invention, the temperature dependence of Vstop in each of the plurality of circuit blocks is substantially the same between the plurality of circuit blocks, and is in an arbitrary temperature range ( For example, in the temperature range of −20 to 70 ° C., Vstop in each of the plurality of circuit blocks substantially matches Vstopmax. Also, the temperature dependence of Vstop and the temperature dependence of Vreg are almost the same. Accordingly, Vreg−Vstop (that is, the margin of the driving voltage) can be reduced in an arbitrary temperature range, so that the current consumption of the entire semiconductor device can be reduced.

That is, in the semiconductor device 100 described above, the impurity concentration in the body region of the MOS transistor used in the critical path of each circuit block and the MOS transistor constituting the power supply circuit that is a constant voltage source is the same. The temperature dependence of Vth is the same. For this reason, for example, if the Vstop of each circuit block is set to be the same at room temperature, a large difference in Vstop between the circuit blocks does not occur even if the temperature rises and falls. Further, Vreg having a value close to Vstop at room temperature has almost the same temperature dependency as Vstop, and Vreg takes a value close to Vstop at each temperature even if the temperature rises and falls. Therefore, for example, the operation can be continued with a small current consumption in the temperature range to be used (for example, room temperature ± 40 ° C.) only by taking Vreg about 0.03 V larger than Vstop.
Thus, by arranging the Vstops for each circuit block, it is possible to optimize the current consumption reduction as a whole and to minimize the operating voltage margin with respect to changes in the environmental temperature. Thus, a semiconductor device with low voltage drive and low current consumption can be provided.

  In the above-described embodiment, the case where the circuit blocks of the frequency divider circuit 10, the control circuit 20, the detection circuit 30, the oscillation circuit 40, and the power supply circuit 50 are formed on the same SOI substrate has been described. It is not limited to this. For example, the above circuit blocks may be formed on the same bulk silicon substrate. Even in such a configuration, the impurity concentration in the silicon substrate (that is, the channel region) immediately below the gate electrode of the MOS transistor used for the critical path is the same between the circuit blocks for each P channel and each N channel. By doing so, it is possible to achieve the same effects as in the above embodiment.

  1, 3, 4, 5 clocked inverter, 2, 6 inverter, 7 support substrate, 8 insulating layer, 9 semiconductor layer, 10 oscillation circuit, 20 control circuit, 30 detection circuit, 40 oscillation circuit, 41 oscillation inverter, 42 crystal Oscillator, 43 Resistor, 44-46 Capacitor, 50 Power supply circuit, 51, 58, 61, 68, 71, 78 MOS transistor, 52, 57, 62, 67, 72, 77 Body region, 53, 58, 63, 68, 73, 78 Gate electrode, 54, 59, 64, 69, 74, 79 Gate insulating film, 60 FF circuit, 90 NAND circuit, 100 Semiconductor device

Claims (5)

A semiconductor device comprising a plurality of circuit blocks,
The operation stop voltages Vstop in each of the plurality of circuit blocks are equal to each other,
The P-type impurity concentrations in the semiconductor immediately below the gate electrode of the P-type transistor used for the critical path of the operation timing for determining the operation stop voltage Vstop are equal to each other among the plurality of circuit blocks, and
A semiconductor device characterized in that N-type impurity concentrations in a semiconductor immediately below a gate electrode of an N-type transistor used for the critical path are also equal among the plurality of circuit blocks. As the plurality of circuit blocks, an oscillation circuit and a frequency divider circuit are provided,
The oscillation circuit includes a first P-type transistor and a first N-type transistor that are used in a critical path of operation timing for determining the operation stop voltage Vstop of the oscillation circuit.
The frequency divider circuit includes a second P-type transistor and a second N-type transistor that are used in a critical path of operation timing for determining the operation stop voltage Vstop of the frequency divider circuit.
The P-type impurity concentrations of the first P-type transistor and the second P-type transistor in the semiconductor immediately below each gate electrode are equal to each other, and
2. The semiconductor device according to claim 1, wherein the first N-type transistor and the second N-type transistor have the same N-type impurity concentration in the semiconductor immediately under the gate electrode.   3. The semiconductor device according to claim 1, wherein a threshold voltage of each of the P-type transistor and the N-type transistor used in the critical path is controlled by a work function of a gate electrode.   3. The semiconductor according to claim 1, wherein a threshold voltage of each of the P-type transistor and the N-type transistor used in the critical path is controlled by a fixed charge or a work function of the gate insulating film. apparatus. A power supply circuit for supplying a drive voltage Vreg to the oscillation circuit and the frequency divider circuit;
The power supply circuit includes a third P-type transistor and a third N-type transistor that determine the driving voltage Vreg.
The P-type impurity concentration in the semiconductor immediately under the gate electrode of the third P-type transistor is equal to the P-type impurity concentration in the semiconductor immediately under the gate electrode of the first P-type transistor or the second P-type transistor,
The N-type impurity concentration in the semiconductor immediately below the gate electrode of the third N-type transistor is equal to the N-type impurity concentration in the semiconductor immediately below the gate electrode of the first N-type transistor or the second N-type transistor. The semiconductor device according to claim 2.

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