JP2010273044A - Frequency-divider circuit, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frequency-divider circuit capable of balancing improvement of stability of circuit operation with reduction of power consumption, and to provide a semiconductor device. <P>SOLUTION: This frequency-divider circuit: includes an FF circuit 10 located on an anterior stage side close to an oscillation circuit and operating at a high frequency, and an FF circuit 10 located on a posterior stage side distant from the oscillation circuit and operating at a low frequency, wherein the respective FF circuits 10 at the anterior and posterior stages have each FB-SOI-MOSFETs 11-14, 21, 25 normally repeating turning on/off in operation of the frequency-divider circuit; and are set to satisfy ¾Vth1¾<¾Vth2¾, when an absolute value of a threshold voltage of the MOSFETs 11-14, 21, 25 possessed by each FF circuit 10 at the anterior stage and that of the MOSFETs 11-14, 21, 25 possessed by each FF circuit 10 at the posterior stage are denoted by ¾Vth1¾ and ¾Vth2¾, respectively. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a frequency dividing circuit and a semiconductor device.

  Conventionally, a MOSFET having an SOI structure (Silicon on Insulator) is known (see, for example, Patent Document 1). Here, the SOI structure is a structure in which a silicon thin film (SOI layer) is stacked on an insulating film, and a MOSFET having an SOI structure (hereinafter also referred to as SOI-MOSFET) is formed in this SOI layer. It is a MOSFET. The SOI-MOSFET has a feature that enables a reduction in junction capacitance and a reduction in operating voltage due to a low threshold voltage, and has attracted attention as a technique for realizing various circuits that require operation with low power consumption. . In such an SOI-MOSFET, a body region made of a silicon layer is formed as a region corresponding to a channel. Depending on whether or not there is a neutral region where majority carriers exist in this body region, the characteristics of the SOI-MOSFET differ. Here, the case where the neutral region exists in the body region is called a partially depleted type (PD), and the case where the neutral region does not exist is called a fully depleted type (FD).

  A fully-depleted SOI-MOSFET (hereinafter also referred to as FD-SOI-MOSFET) has a smaller S value than a bulk type, and therefore, a threshold voltage is set low without increasing off-leakage current (leakage current). Suitable for low power consumption. On the other hand, since the thinning required for the SOI layer is severe and it is difficult to make the film thickness uniform, there is a demerit that the threshold voltage tends to vary. On the other hand, a partially depleted SOI-MOSFET (hereinafter also referred to as PD-SOI-MOSFET) can easily secure a manufacturing margin with respect to the thickness of the SOI layer, and is the same process as the bulk type. There is a great advantage that it can be formed using. Further, like the fully depleted type, the junction capacitance is low, so that high speed operation and low power consumption are possible.

  Further, in the PD-SOI-MOSFET, the body region is electrically connected to the source region and the potential is fixed (so-called body tie type), and the body region is not electrically connected to other regions. There is a floating type (so-called floating body type). The body tie type has a carrier escape area, so that the depletion layer easily spreads, and its characteristics are close to those of the bulk type. On the other hand, since the floating body type (hereinafter also referred to as FB type) has no escape space for carriers, the depletion layer is difficult to expand, and its characteristics are close to those of the complete depletion type. Furthermore, since the FB type has a small number of element terminals and a small occupation area, the MOSFET can be reduced in size and cost.

  In addition, it is known that an FB type PD-SOI-MOSFET (hereinafter also referred to as an FB-PD-SOI-MOSFET) is applied to a digital circuit including a frequency divider (for example, Patent Documents 1 and 2). reference.). Here, the frequency dividing circuit is a circuit that divides a frequency, for example, a circuit that divides a high-frequency clock signal generated by an oscillation circuit into an integer and converts it to a low-frequency clock signal. . In such a frequency dividing circuit, a plurality of flip-flop circuits (hereinafter also referred to as FF circuits) are usually used to lower the frequency.

  For example, in a watch IC, a 32 kHz clock signal is generated from a crystal oscillator, and in a frequency dividing circuit, the frequency is halved by one FF circuit. In this case, by connecting the FF circuits in 15 stages, a 1 Hz clock signal can be obtained from a 32 kHz clock signal, and a time interval of 1 second is created (for example, see Patent Document 3). Here, since a portable device such as a watch cannot be directly connected to an AC power supply, the IC operates with a button battery or natural energy. For this reason, it is important to reduce power consumption as much as possible in order to maintain long-term operation. In the frequency dividing circuit, the front FF circuit close to the oscillation circuit operates at a high frequency (for example, 32 kHz), and the rear FF circuit and the control circuit that performs time control of the second hand have a low frequency (for example, 1 to 1). 8 Hz).

  If an FB-PD-SOI-MOSFET is employed in such a frequency dividing circuit, the smallest MOSFET can be realized in terms of design rules, and the junction capacitance can be ideally reduced. In other words, the FB-PD-SOI-MOSFET has a small number of element terminals, a small MOSFET area, can be manufactured at low cost, has a large driving current on / off ratio, and has a small diffusion capacitance. Therefore, the integrated circuit is excellent in speeding up and low power.

JP 2002-111005 A JP 2002-111006 A JP 2001-235567 A JP 2001-44440 A

  By the way, the FB-PD-SOI-MOSFET has instability in its electrical characteristics due to the substrate floating effect of the SOI layer. That is, in the PD-SOI-MOSFET, the body tie type Id-Vg characteristic does not show hysteresis, but the floating body type Id-Vg characteristic shows hysteresis. Here, Id is a current (ie, drain current) flowing between the source region and the drain region, and Vg is a voltage applied to the gate electrode (ie, gate voltage). The Id-Vg characteristic is also called a current-voltage characteristic or a transfer characteristic. The hysteresis (that is, the history effect) is a property that the state of the MOSFET changes depending on not only the currently applied voltage but also the voltage applied in the past.

  As described above, the FB-PD-SOI-MOSFET showing the hysteresis has been conventionally applied to a logic circuit such as a frequency divider circuit, but in each FB-PD-SOI-MOSFET constituting the circuit, A circuit design that takes into account the difference in the floating state of the SOI layer substrate has not been made. In other words, in the frequency divider circuit in which the FF circuits are connected over a plurality of stages, all the FB-PD-SOI-MOSFETs are designed in the same condition and in the same pattern for each P channel and each N channel. Therefore, the circuit design has been made on the assumption that the instability of the electrical characteristics of the FB-PD-SOI-MOSFET is the same regardless of the position in the frequency divider circuit.

For example, the FF-PD-SOI-MOSFET included in the FF-PD-SOI-MOSFET included in the FF-PD-SOI-MOSFET included in the first stage FF circuit that operates at a high frequency in the frequency divider circuit, the subsequent FF circuit that operates at a low frequency, or the control circuit that performs time control of the second hand. Each of the P channel type and the N channel type is designed in the same condition and in the same pattern.
In the conventional technique, for example, in all the FB-PD-SOI-MOSFETs included in the frequency divider circuit, on the premise that the body potential becomes unstable, when the hysteresis characteristic becomes the worst case, The circuit was designed to ensure a large drive voltage and current consumption margin (see, for example, Patent Document 4). For example, when it is desired to reduce the standby current of the frequency divider circuit, the worst case, i.e., all of the frequency divider circuits that constitute the frequency divider circuit on the premise of the IV characteristics when the off-leakage current is maximized within the range that can be assumed. The absolute value of the threshold voltage of the FB-PD-SOI-MOSFET is set to a higher value.

However, in this case, the FB-PDs formed under the same conditions and in the same pattern are different when the initial value until the start of oscillation is set and when the subsequent oscillation is continued, because the floating state of each SOI layer substrate is different. Even in the case of -SOI-MOSFET, the electrical characteristics show different values. For this reason, if the drive voltage is lowered for the purpose of reducing power consumption, etc., the operating margin of the frequency divider circuit will be insufficient, and especially in the FF circuit operating at a high frequency, the frequency division at the start of oscillation or at the time of oscillation continuation. There is a possibility that a dropout or the like may occur. On the other hand, if the absolute value of the threshold voltage of the FB-PD-SOI-MOSFET that constitutes the frequency divider circuit is set to a low value so that it can operate even at a low voltage, the off-leakage current increases and the current consumption of the entire frequency divider circuit is reduced. There was a possibility that it would increase.
Accordingly, some aspects of the present invention have been made in view of such circumstances, and a frequency dividing circuit and a semiconductor device that are capable of both improving the stability of circuit operation and reducing power consumption. The purpose is to provide.

  In order to achieve the above object, a divider circuit according to one embodiment of the present invention is a divider circuit in which a plurality of flip-flop circuits are connected to an oscillator circuit in a plurality of stages, and is close to the oscillator circuit. A first flip-flop circuit operating at a high frequency on the front stage side, and a second flip-flop circuit operating on a low frequency side on the rear stage far from the oscillation circuit. The flip-flop circuit has a first transistor formed in a semiconductor layer on an insulating layer, and the first transistor is a floating body type partially depleted transistor, which is normally used when the frequency divider circuit operates. The second flip-flop circuit has a second transistor formed in the semiconductor layer on the insulating layer. The second transistor is a floating body type partially depleted transistor, and is normally a transistor that repeatedly turns on and off during the operation of the frequency dividing circuit. The absolute value of the threshold voltage of the first transistor is expressed as | Vth1 It is characterized in that | Vth1 | <| Vth2 | is set, where | is the absolute value of the threshold voltage of the second transistor | Vth2 |.

  Here, the “insulating layer” is also called a BOX layer, for example, and the “semiconductor layer” is also called an SOI layer, for example. In addition, the “floating body type partially depleted transistor” means that the semiconductor layer (that is, the body region) immediately below the gate electrode is electrically floated and the body voltage is applied when a threshold voltage is applied to the gate electrode. A transistor in which a region is partially depleted (that is, a neutral region remains without a depletion layer reaching an insulating layer). The threshold voltage of the transistor is set (adjusted) by introducing impurities into the body region, for example. Such introduction of impurities is also called channel doping, for example.

  With such a configuration, in the first flip-flop circuit on the upstream side close to the oscillation circuit, the absolute value | Vth1 | of the threshold voltage of the first transistor is low, so that a large on (On) even at a low voltage. A current can be obtained. Accordingly, in the first flip-flop circuit, for example, the operation speed of the inverter can be increased (that is, the delay time can be reduced), so that it is possible to avoid malfunction such as missing frequency division, and stability of circuit operation. Can be increased. Further, in the second flip-flop circuit, since the absolute value | Vth2 | of the threshold voltage of the second transistor on the rear stage side far from the oscillation circuit is high, the off-leak current can be reduced. Here, in the second flip-flop circuit, not only the off-leak current but also the on-current is reduced. However, since the second flip-flop circuit operates at a low frequency, the second flip-flop circuit operates at a lower frequency than in the case of operating at a higher frequency. Malfunctions such as loop-through are unlikely to occur. Therefore, it is possible to improve the stability of the circuit operation and reduce power consumption.

  In the frequency divider circuit, the first transistor includes a first N-type transistor and a first P-type transistor, and the gate length of the first N-type transistor is L1 (N). The gate width of the first N-type transistor is W1 (N), the threshold voltage of the first N-type transistor is Vth1 (N), and the gate length of the first P-type transistor is L1. (P), where the gate width of the first P-type transistor is W1 (P) and the threshold voltage of the first P-type transistor is Vth1 (P), L1 (N) = L1 (P) , W1 (N) = W1 (P) and Vth1 (N) = − Vth1 (P).

  In the frequency divider circuit, the second transistor includes a second N-type transistor and a second P-type transistor, and the gate length of the second N-type transistor is L2 (N). The gate width of the second N-type transistor is W2 (N), the threshold voltage of the second N-type transistor is Vth2 (N), while the gate length of the second P-type transistor is L2 (P), where the gate width of the second P-type transistor is W2 (P) and the threshold voltage of the second P-type transistor is Vth2 (P), L2 (N) = L2 (P) , W2 (N) = W2 (P) and Vth2 (N) = − Vth2 (P).

  In the frequency divider circuit, at least one of the first flip-flop circuit or the second flip-flop circuit includes a third transistor formed in the semiconductor layer on the insulating layer, The third transistor is a floating body type partially depleted transistor, which is normally turned off during the operation of the frequency divider, and when the absolute value of the threshold voltage of the third transistor is | Vth3 | , | Vth2 | ≦ | Vth3 | is set. With such a structure, the resistance component of the third transistor can be increased in the first flip-flop circuit or the second flip-flop circuit. Accordingly, the off-leakage current in the flip-flop can be further reduced, so that the power consumption of the frequency divider circuit can be further reduced.

  Further, in the above frequency divider circuit, at least one of the first flip-flop circuit or the second flip-flop circuit includes a fourth transistor formed in the semiconductor layer on the insulating layer, The fourth transistor is a floating body type partially depleted transistor, which is a normally-on transistor during the operation of the frequency divider, and when the absolute value of the threshold voltage of the fourth transistor is | Vth4 | , | Vth4 | ≦ | Vth1 | is set. With such a structure, the resistance component of the fourth transistor can be reduced in the first flip-flop circuit or the second flip-flop circuit. Accordingly, the on-current in the flip-flop can be further increased, so that the operation stability of the frequency divider circuit can be further improved.

  A semiconductor device according to another aspect of the present invention is disposed between the frequency divider circuit, the oscillation circuit, and the frequency divider circuit, and shapes the amplitude voltage output from the oscillation circuit by shaping the waveform. A waveform shaping circuit for supplying to a peripheral circuit, wherein the waveform shaping circuit has a fifth transistor formed in the semiconductor layer on the insulating layer, and the fifth transistor is a floating body type Is a transistor that normally repeats on and off during the operation of the waveform shaping circuit, and when the absolute value of the threshold voltage of the fifth transistor is | Vth5 | It is characterized by being set to │Vth1│.

  With such a configuration, it is possible to improve the stability of the circuit operation of the semiconductor device and reduce power consumption. In particular, in the waveform shaping circuit, since the absolute value | Vth5 | of the threshold voltage of the fifth transistor is low, a large on-current can be obtained even at a low voltage. Thereby, even in the waveform shaping circuit, for example, the operation speed of the inverter can be increased (that is, the delay time can be reduced).

  In the above semiconductor device, the fifth transistor includes a fifth N-type transistor and a fifth P-type transistor, and the gate length of the fifth N-type transistor is L5 (N). The gate width of the fifth N-type transistor is W5 (N), the absolute value of the threshold voltage of the fifth N-type transistor is Vth5 (N), while the gate length of the fifth P-type transistor is Is L5 (P), the gate width of the fifth P-type transistor is W5 (P), and the threshold voltage of the fifth P-type transistor is Vth5 (P), L5 (N) = L5 ( P), W5 (N) = W5 (P), and Vth5 (N) = − Vth5 (P).

In the above semiconductor device, the waveform shaping circuit includes a sixth transistor formed in the semiconductor layer on the insulating layer, and the sixth transistor is a floating body type partially depleted transistor. When the waveform shaping circuit is in operation, the transistor is normally off. When the absolute value of the threshold voltage of the sixth transistor is | Vth6 |, | Vth2 | ≦ | Vth6 | It is a feature.
With such a configuration, the resistance component of the sixth transistor can be increased in the waveform shaping circuit. Thereby, the off-leak current of the waveform shaping circuit can be further reduced, so that the power consumption of the semiconductor device can be further reduced.

Further, in the above semiconductor device, the waveform shaping circuit includes a seventh transistor formed in the semiconductor layer on the insulating layer, and the seventh transistor is a floating body type partially depleted transistor. When the waveform shaping circuit is in operation, the transistor is normally on, and when the absolute value of the threshold voltage of the seventh transistor is | Vth7 |, | Vth7 | ≦ | Vth1 | It is a feature. With such a configuration, the resistance component of the seventh transistor can be lowered in the waveform shaping circuit. As a result, the on-current in the waveform forming circuit can be further increased, so that the operational stability of the semiconductor device can be further increased.
Note that the above-described frequency dividing circuit or semiconductor device is extremely suitable for application to portable electronic devices such as a watch, a mobile phone, and a mobile personal computer that require a long-time operation with a small and light battery, for example. It is.

The figure which shows the structural example of the frequency divider circuit 50 which concerns on 1st Embodiment. FIG. 3 is a diagram illustrating a configuration example and an operation example of the FF circuit 10 according to the first embodiment. The figure which showed FF circuit 10 using the code | symbol of a logic circuit. The figure which shows the structural example of the clocked inverter 1, and its operation example. The figure which shows the structural example of the inverter. The figure which shows the other structural example of the inverter. The figure which shows the structural example of the semiconductor device 100 which concerns on 2nd Embodiment. FIG. 3 is a diagram showing a configuration example of an oscillation circuit 40. FIG. 3 is a diagram showing a configuration example of a NAND circuit 90. The figure which shows the magnitude relationship of the absolute value of the threshold voltage which concerns on 1st-3rd embodiment. The figure which shows the state change of the body area | region 66 (the 1). The figure which shows the state change of the body area | region 66 (the 2). The figure which shows the measurement result when MOSFET21 is turned on / off.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and redundant description thereof is omitted.
(1) First Embodiment FIG. 1 is a diagram illustrating a configuration example of a frequency divider circuit 50 according to a first embodiment of the present invention.
As shown in FIG. 1, the frequency dividing circuit 50 has a structure in which n flip-flop circuits 10 are connected over n stages (that is, a structure in which n flip-flop circuits 10 are connected in n stages in series). . The flip-flop circuit 10 is, for example, a quasi-static T flip-flop circuit. In this frequency dividing circuit 50, the input terminal C1 of the first-stage flip-flop circuit (FF circuit) 10 is connected to, for example, an oscillation circuit, and the output terminal Q1 of the first-stage FF circuit 10 is connected to the second-stage FF circuit 10. Are connected to the input terminal C2. Similarly, when n is 3 or more, the output terminal Q _n−1 of the ( _n−1 ) th stage FF circuit 10 is connected to the input terminal C _n of the _nth FF circuit 10 and the (n−1) th stage FF. The output terminal XQ _n−1 of the circuit 10 is connected to the output terminal XQ _n of the _nth FF circuit 10.

Thus, for example, in synchronization with a clock signal supplied from the oscillation circuit, the Q _n output signals from the output terminals Q _n of the frequency dividing circuit 50 is output, XQ _n output signal from the output terminal XQ _n is outputted. Here, the Q _n output signal is a signal whose period is 2 ⁿ times (that is, the frequency is ½) compared to the C ₁ input signal, which is a clock signal, and the XQ _n output signal is the high ( A signal obtained by inverting High (hereinafter also simply referred to as H) and Low (hereinafter also simply referred to as L).

2A and 2B are a circuit diagram showing a configuration example of the FF circuit 10 according to the first embodiment of the present invention and a timing chart showing an operation example thereof.
As shown in FIG. 2A, the FF circuit 10 includes clocked inverters 1, 3, 4, and 5 and inverters 2 and 6. Each of the clocked inverters 1, 3, 4, 5 is provided with one or both of a C input terminal and an XC input terminal. Here, a signal input to the C input terminal (that is also referred to as a C input signal) is a clock signal, and is a signal that repeats H and L at regular intervals. A signal (that is, an XC input signal) input to the XC input terminal is a signal obtained by inverting H and L of the C input signal. The inverters 2 and 6 are each provided with a set terminal and a reset terminal (not shown).

  The connection relationship between the clocked inverters 1, 3, 4, 5 and the inverters 2 and 6 will be described. As shown in FIG. 2A, the output terminal of the clocked inverter 1 is connected to the input terminal of the inverter 2, It is connected to the output terminal of the clocked inverter 3. The output terminal of the inverter 2 and the input terminal of the clocked inverter 3 are connected to the input terminal of the clocked inverter 4. Furthermore, the output terminal of the clocked inverter 4 is connected to the output terminal of the clocked inverter 5, the input terminal of the inverter 6, the input terminal of the clocked inverter 1, and the Q output terminal. The input terminal of the clocked inverter 5 and the output terminal of the inverter 6 are connected to the XQ output terminal.

Thus, in synchronization with the C input signal, the Q output signal is output from the Q output terminal, and the XQ output signal is output from the XQ output terminal. As shown in FIG. 2B, the Q output signal is a signal having a cycle twice that of the C input signal (that is, the frequency is ½), and the XQ output signal is the H and L of the Q output signal. Is a signal obtained by inverting.
FIG. 3 is a diagram showing the FF circuit 10 shown in FIGS. 2A and 2B by using logic circuit symbols. As shown in FIG. 3, the FF circuit 10 includes, for example, clocked inverters 1, 3, 4, and 5 and inverters 2 and 6. Among these, the inverters 2 and 6 are each composed of, for example, a combination of one AND circuit and one NOR circuit, and a reset (XR) terminal is connected to the input terminal of the AND circuit, and the input of the NOR circuit A set (S) terminal is connected to the terminal. In the present invention, each of the transistors constituting the inverters 1 to 6 is formed of a floating body type partially depleted SOI-MOSFET (ie, FB-PD-SOI-MOSFET).

  By the way, as shown in FIGS. 2A and 2B, the frequency dividing circuit 50 sequentially divides the high-frequency clock signal by the FF circuit 10 in each stage and converts it into a low-frequency signal. For this reason, the FB-PD-SOI-MOSFET included in the FF circuit 10 on the side closer to the oscillation circuit (that is, the front stage) operates with a clock signal having a higher frequency and is located on the side farther from the oscillation circuit (that is, the rear stage). The FB-PD-SOI-MOSFET included in the FF circuit 10 operates with a low-frequency clock signal.

  For example, an input signal of 32 kHz is supplied from the oscillation circuit, and each FF circuit 10 divides the input signal by two (that is, converts the frequency to ½) and outputs it. For example, when 15 stages of FF circuits 10 are connected, the 32 kHz signal finally becomes 1 Hz. At this time, the FB-PD-SOI-MOSFET constituting the first stage FF circuit 10 operates with a signal of, for example, 32 KHz, and the FB-PD-SOI-MOSFET constituting the 15th stage FF circuit 10 has, for example, 1 Hz. Operates with signals.

  4A and 4B are a circuit diagram showing a configuration example of the clocked inverter 1 and a timing chart showing an operation example thereof. As shown in FIG. 4A, the clocked inverter 1 includes N-channel type FB-PD-SOI-MOSFETs 11 and 12 and P-channel type FB-PD-SOI-MOSFETs 13 and 14. Among these, the MOSFETs 11 and 13 constitute an inverter main body, the source of the MOSFET 11 is connected to, for example, the ground potential (or the regulator potential Vreg), and the drain of the MOSFET 13 is connected to, for example, the power supply potential Vdd. The gates of these MOSFETs 11 and 13 are connected to the input terminal A of the clocked inverter 1. Further, the MOSFET 12 is connected between the MOSFET 11 and the output terminal B, and the MOSFET 14 is connected between the MOSFET 13 and the output terminal B. The gate of the MOSFET 12 is connected to the C input terminal, and the gate of the MOSFET 14 is connected to the XC input terminal.

  As shown in FIGS. 4A and 4B, in this clocked inverter 1, when the C input signal is H (that is, the XC input signal is L), the MOSFETs 12 and 14 are both turned on. As the name suggests, the inverter 1 functions as an inverter (ie, an element that outputs L if the input signal is H and outputs H if the input signal is L). On the other hand, when the C input signal is L (that is, the XC input signal is H), both the MOSFETs 12 and 14 are turned off, so that the drain of the MOSFET 11 and the output terminal B are electrically separated, and the MOSFET 13 The source and the output terminal B are electrically separated. Therefore, the potential of the output terminal B is maintained as it is.

  Here, during the operation of the frequency dividing circuit 50, the MOSFETs 11 to 14 normally operate at a high frequency (that is, turn on and off in synchronization with the high frequency) in the FF circuit 10 in the previous stage. In the FF circuit 10 at the subsequent stage, the MOSFETs 11 to 14 operate at a low frequency. The other clocked inverters 3, 4, and 5 shown in FIG. 1 also have the same configuration as the clocked inverter 1 shown in FIGS. 4 (a) and 4 (b), for example.

  FIG. 5 is a circuit diagram illustrating a configuration example of the inverter 2. As shown in FIG. 5, the inverter 2 includes N-channel type FB-PD-SOI-MOSFETs 21 to 23 and P-channel type FB-PD-SOI-MOSFETs 24 to 26. Among these, the MOSFETs 21 and 25 constitute an inverter body, the source of the MOSFET 21 is connected to, for example, the ground potential (or Vreg), and the drain of the MOSFET 25 is connected to, for example, the power supply potential Vdd. The gates of the MOSFETs 21 and 25 are connected to the input terminal A of the inverter 2, respectively. Further, the MOSFET 22 is connected between the MOSFET 21 and the output terminal B, and the MOSFET 24 is connected between the MOSFET 25 and the output terminal B. The gate of the MOSFET 22 is connected to the reset (XR) terminal, and the gate of the MOSFET 24 is connected to the set (S) terminal. Further, the MOSFET 23 is connected between the ground potential (or Vreg) and the output terminal B, and the MOSFET 26 is connected between the power supply potential Vdd and the MOSFET 24 (that is, connected in parallel with the MOSFET 25). . The gate of the MOSFET 23 is connected to the S input terminal, and the gate of the MOSFET 26 is connected to the XR input terminal.

  As shown in FIG. 5, in the inverter 2, when the signal input to the S input terminal is L and the signal input to the XR input terminal is H, the MOSFETs 22 and 24 are turned on and the MOSFETs 23 and 26 are turned on. Therefore, the inverter 2 functions as an inverter as the name suggests. On the other hand, when the signal input to the S input terminal is H and the signal input to the XR input terminal is L, the MOSFETs 22 and 24 are turned off and the MOSFETs 23 and 26 are turned on. Becomes the ground potential (or Vreg) without depending on H and L of the signal input to the input terminal A. Therefore, the initial setting of the B potential is possible.

  Here, during the operation of the frequency dividing circuit 50, normally, in the FF circuit 10 in the previous stage, the MOSFETs 21 and 25 operate at a high frequency (that is, on and off in synchronization with the high frequency), and the MOSFETs 22 and 24 are turned on. MOSFETs 23 and 26 are turned off. In the FF circuit 10 at the subsequent stage, the MOSFETs 21 and 25 operate at a low frequency, the MOSFETs 22 and 24 are turned on, and the MOSFETs 23 and 26 are turned off.

  That is, after an oscillation circuit (not shown) starts its oscillation operation, in the FF circuit 10 in the frequency dividing circuit 50 connected to this oscillation circuit, the potential of the set (S) terminal connected to the inverter 2 is fixed to L, The potential of the reset (XR) terminal is fixed to H. As a result, the N-channel MOSFET 23 and the P-channel MOSFET 26 shown in FIG. 5 are turned off, and the N-channel MOSFET 22 and the P-channel MOSFET 24 are turned on. The N-channel MOSFET 21 and the P-channel MOSFET 25 constitute an inverter body. In the front-stage FF circuit 10, these MOSFETs 21 and 25 are repeatedly turned on / off at a high frequency, and in the rear-stage FF circuit 10, these MOSFETs 21 and 25 are repeatedly turned on / off at a low frequency.

By the way, when an input signal (that is, an amplitude voltage) in which H and L are switched at regular intervals is repeatedly applied to the gate electrode of the FB-PD-SOI-MOSFET, after a few seconds, the on-current and off-leakage current are changed in operation. It takes a stable value regardless of the frequency. That is, the body potentials of the individual MOSFETs constituting the frequency divider circuit 50 each have a stable state.
This will be described using the inverter 2 shown in FIG. 5 as an example. In FIG. 5, when the potential of the set (S) terminal is fixed to L and the potential of the reset (XR) terminal is fixed to H, the potentials of the body regions (neutral regions) of the MOSFETs 22, 23, 24, and 26. (That is, the body potential) becomes stable at the potential of each source region (hereinafter also referred to as source potential) (see, for example, steps I and II in FIG. 11B described later). That is, the body potentials of the N-channel type MOSFETs 22 and 23 are fixed to L, and the body potentials of the P-channel type MOSFETs 24 and 26 are fixed to H and stabilized.

  On the other hand, the body potentials of the N-channel MOSFET 21 and the P-channel MOSFET 25 constituting the inverter oscillate with the amplitude of the input signal (amplitude voltage) applied to the input terminal A, but the N-channel MOSFET The body potential of the MOSFET 21 stably oscillates between the source potential (L) and a potential lower than the source potential by the threshold voltage, and the body potential of the P-channel MOSFET 25 is changed from the source potential (H) and the source potential to the threshold voltage. Oscillates stably with a potential higher by that amount (for example, see steps III and IV in FIG. 12B described later). That is, the body potential of the N-channel MOSFET 21 stably oscillates between the fixed potential differences in a region lower than the source potential, and the body potential of the P-channel MOSFET 25 is fixed in the region higher than the source potential. It vibrates stably between.

  As described above, even in the same channel type MOSFET, the body potential of the MOSFET 21 oscillates and the body potentials of the MOSFETs 22 and 23 are fixed. Therefore, the MOSFET 21 and the MOSFETs 22 and 23 exhibit different electrical characteristics. Similarly, even in the P-channel type, the body potential of the MOSFET 25 oscillates and the body potential of the MOSFETs 24 and 26 is fixed. Therefore, the MOSFET 25 and the MOSFETs 24 and 26 exhibit different electrical characteristics.

  For example, as shown in FIGS. 13A and 13B described later, in the N-channel MOSFET 21, when the gate electrode potential (hereinafter also referred to as the gate potential) swings and the on / off drive is started, The on-current / off-leakage current gradually decreases, but after a few seconds, the on-current / off-leakage current becomes stable values, and a stable transfer characteristic is exhibited. On the other hand, in the N-channel MOSFET 22, since the gate potential is fixed, the body potential is stabilized in a state where it matches the source potential. At this time, due to the difference in body potential, the threshold voltage of the MOSFET 22 is apparently smaller than the threshold voltage of the MOSFET 21, and the on-current value of the MOSFET 22 increases compared to the on-current value of the MOSFET 21. Similarly, even in the P-channel type, the absolute value of the threshold voltage of the MOSFET 24 is apparently smaller than the absolute value of the threshold voltage of the MOSFET 25 due to the difference in body potential, and the on-current value of the MOSFET 24 is the same as the on-current value of the MOSFET 25. Compared to increase.

Therefore, in the present invention, the threshold voltage of each MOSFET included in the frequency divider circuit 50 is optimized in consideration of the difference in the stable state of the body potential and the positioning of each MOSFET in the frequency divider circuit 50. Perform circuit design.
Specifically, among the MOSFETs included in the FF circuit 10 in the preceding stage (including at least the first stage) close to the oscillation circuit, the MOSFETs 11 to 14, 21, and 25 that repeatedly turn on and off at a high frequency are absolute threshold voltages. It is composed of FB-PD-SOI-MOSFET having a low value. In addition, among the MOSFETs included in the FF circuit 10 in the subsequent stage, the MOSFETs 11 to 14, 21, and 25 that repeatedly turn on and off at a low frequency are configured by FB-PD-SOI-MOSFETs having a high absolute value of the threshold voltage. That is, the absolute value of the threshold voltage of the MOSFETs 11 to 14, 21, and 25 included in the preceding FF circuit 10 is | Vth1 |, and the absolute value of the threshold voltage of the MOSFETs 11 to 14, 21, and 25 included in the subsequent FF circuit 10 is set. When | Vth2 | is set, | Vth1 | <| Vth2 | is set. The difference between | Vth1 | and | Vth2 | is, for example, about 0.05 to 0.1V.

  That is, the threshold voltage of the N-channel MOSFETs 11, 12, and 21 included in the preceding FF circuit 10 operating at a high frequency is set to Vth 1 (N), and the P-channel MOSFETs 13, 14, included in the preceding FF circuit 10 are set. The threshold voltage of 26 is Vth1 (P). Further, the threshold voltage of the N-channel MOSFETs 11, 12, and 21 included in the subsequent FF circuit 10 operating at a low frequency is set to Vth2 (N), and the P-channel MOSFETs 13, 14, The threshold voltage of 26 is Vth2 (P). At this time, Vth1 (N) <Vth2 (N) and | Vth1 (P) | <| Vth2 (P) | are set. As a result, the on-state current can be increased in the front-stage FF circuit 10, and the off-leak current can be reduced in the back-stage FF circuit 10.

  Further, the absolute value of the threshold voltage of the MOSFETs 23 and 26 having a fixed gate voltage that is normally off is assumed to be set and reset in the FF circuit 10 at the front stage and the rear stage (that is, all included in the frequency divider circuit 50). Are all set to the same value and this is defined as | Vth3 |. At this time, it is preferable to set | Vth2 | ≦ | Vth3 |. Thereby, in the front-stage and rear-stage FF circuits 10, the resistance components of the MOSFETs 23 and 26 that are normally off can be increased, and the off-leak current can be further reduced. Similarly, the absolute values of the threshold voltages of the MOSFETs 22 and 24 having a fixed gate voltage that is normally on are set to the same value in the FF circuit 10 in the preceding stage and the succeeding stage, and are set to | Vth4 Let │ be. At this time, it is preferable to set | Vth4 | ≦ | Vth1 |. Thereby, in the front-stage and rear-stage FF circuits 10, the resistance components of the normally-on MOSFETs 22 and 24 can be reduced, and the on-current can be further increased.

Further, in the front-stage and rear-stage FF circuits 10, the absolute values of the threshold voltages of the MOSFETs 23 and 26 are set to | Vth3 |, and the absolute values of the threshold voltages of the MOSFETs 22 and 24 are set to | Vth4 | The circuit 10 and the subsequent FF circuit 10 can be set and reset under the same conditions (for example, the same voltage value).
In the present invention, in addition to the above settings, the absolute values of the threshold voltages of the N-channel MOSFET and the P-channel MOSFET that play the same role in the FF circuits 10 in each stage are set to the same value. It is preferable to set. For example, it is preferable to set Vth1 (N) = − Vth1 (P), and it is preferable to set Vth2 (N) = − Vth2 (P). Thereby, in each FF circuit 10, the N-channel type MOSFET 21 and the P-channel type MOSFET 25 can be turned on and off at the same timing under the same conditions (for example, the same voltage value).

  Further, in the present invention, in addition to the above setting, the sizes of the N-channel type MOSFET and the P-channel type MOSFET that play the same role in the FF circuit 10 in each stage may be set to the same value. preferable. For example, the gate length of the N-channel MOSFET 21 included in the preceding FF circuit 10 operating at a high frequency is L1 (N), the gate width is W1 (N), and the gate lengths of the P-channel MOSFETs 13, 14, 26 are Is L1 (P) and the gate width is W1 (P), it is preferable that L1 (N) = L1 (P) and W1 (N) = W1 (P). Similarly, the gate length of the N-channel MOSFET 21 included in the subsequent FF circuit 10 operating at a low frequency is L2 (N), the gate width is W2 (N), and the gate length of the P-channel MOSFET 26 is L2 (N P) When the gate width is W2 (P), it is preferable that L2 (N) = L2 (P) and W2 (N) = W2 (P). Thereby, in a circuit using a threshold voltage or a subthreshold current equal to or lower than the threshold voltage, the balance of the On / Off currents of the P-channel and N-channel transistors is improved. This is because the swing S value in the sub-threshold region has the same value close to the ideal value for each of the P-channel and N-channel transistors, and the On / Off current ratio of each of the P-channel and N-channel transistors becomes almost equal. Because. Further, if the P-channel and N-channel transistors have the same minimum dimensions, the circuit can be reduced and the elements can be highly integrated.

  As described above, according to the first embodiment of the present invention, the absolute values of the threshold voltages of the MOSFETs 11 to 14, 21, and 25 of the front-stage FF circuit 10 are the same as those of the MOSFETs 11 to 14, 21, and 25 of the rear-stage FF circuit 10. It is set to a value lower than the absolute value of the threshold voltage. As a result, the FF circuit 10 in the previous stage can obtain a large on-current even at a low voltage, and for example, the operation speed of the inverters 1 to 6 can be increased (that is, the delay time can be reduced).

  For this reason, in the preceding stage FF circuit 10 that operates at a high frequency, it is possible to avoid an operation failure such as missing frequency division and to improve the stability of the circuit operation. In the FF circuit 10 in the previous stage, the off-leakage current increases due to a trade-off with an increase in the on-current. However, in a watch or the like, for example, the MOSFET of the first to fifth FF circuits 10 connected to the oscillation circuit The number is as small as several to tens. Therefore, even if, for example, an FB-PD-SOI-MOSFET having an off-leakage current of 0.01 to 0.1 nA is used as the MOSFETs 11 to 14 and 21 to 26 included in the FF circuit 10 in the previous stage, other than the charge / discharge current The quiescent current can be suppressed within 1 to 10 nA. Therefore, it is possible to stably operate the FF circuit 10 in the previous stage without increasing the current consumption.

  On the other hand, in the latter stage FF circuit 10, the absolute value of the threshold voltage of the MOSFETs 11 to 14, 21, and 25 is set to a high value (compared to the previous stage), so that the off-leakage current is set to 0.001 to 0.01 nA or less, for example. Can be suppressed. For this reason, for example, even in a circuit composed of a large number of MOSFETs of several thousand or more, such as when the subsequent stage FF circuit 10 is connected to more than ten stages or when the control circuit is connected after the subsequent stage FF circuit 10, Static currents other than current can be suppressed within 1 to 10 nA. Further, in the FF circuit 10 at the subsequent stage, the on-current becomes low due to the trade-off between the off-leakage current, but since the operation frequency is low in the subsequent stage, it is possible to avoid the malfunction of the FF circuit 10. Thereby, for example, an ultra-low voltage drive of 0.5 V or less becomes possible.

  In the first embodiment, the MOSFETs 11 to 14, 21, and 25 included in the front-stage FF circuit 10 correspond to the “first transistor” of the present invention, and are included in the rear-stage FF circuit 10 to include the MOSFETs 11 to 14, 21, Reference numeral 25 corresponds to the “second transistor” of the present invention. The MOSFETs 23 and 26 correspond to the “third transistor” of the present invention, and the MOSFETs 22 and 24 correspond to the “fourth transistor” of the present invention. The front-stage FF circuit 10 corresponds to the “first flip-flop circuit” of the present invention, and the rear-stage FF circuit 10 corresponds to the “second flip-flop circuit” of the present invention.

  In addition, although this 1st Embodiment demonstrated the case where the inverters 2 and 6 had both a set (S) terminal and a reset (XR) terminal, this invention is not limited to this. For example, as illustrated in FIG. 6, the inverter 2 may include only FB-PD-SOI-MOSFETs 21, 22, 25, 26, a reset (XR) terminal, and input terminals A and B. That is, the set (S) terminal may not be provided. The same applies to the inverter 6. Even in such a configuration, the absolute value of the threshold voltage of the MOSFETs 21 and 25 included in the preceding FF circuit 10 should be lower than the absolute value of the threshold voltage of the MOSFETs 21 and 25 included in the subsequent FF circuit 10. Thus, the same effect as in the first embodiment can be obtained.

(2) Second Embodiment FIG. 7 is a block diagram showing a configuration example of a semiconductor device 100 according to a second embodiment of the present invention. A semiconductor device 100 illustrated in FIG. 7 is, for example, a semiconductor device 100 built in a watch, and includes an oscillation circuit 40, a frequency dividing circuit 50, a control circuit 60, a detection circuit 70, and a power supply circuit 80. The oscillation circuit 40, the power supply circuit 80, and the detection circuit 70 are analog circuits, and the frequency dividing circuit 50 and the control circuit 60 are digital circuits.

  FIG. 8 is a circuit diagram illustrating a configuration example of the oscillation circuit 40. As illustrated in FIG. 8, the oscillation circuit 40 includes an oscillation inverter 41, a crystal oscillator 42, a resistor 43, and capacitors 44 to 46. In the oscillation circuit 40, a resonance circuit is configured by the crystal oscillator 42 and the capacitors 44 and 45, and an oscillation inverter 41 is connected to the resonance circuit to oscillate a specific frequency (for example, 32 kHz). It is like that. A waveform shaping NAND circuit 90 is connected to the output terminal of the oscillation circuit 40.

FIG. 9 is a circuit diagram illustrating a configuration example of the NAND circuit 90.
As shown in FIG. 9, the NAND circuit 90 includes, for example, N-channel MOSFETs 91 and 92 and P-channel MOSFETs 93 and 94. For example, the source of the MOSFET 91 is connected to the ground potential (or Vreg), for example, and the drain of the MOSFET 91 is connected to the source of the MOSFET 92. The drains of the MOSFETs 92 to 94 are connected to the output terminal Y. Further, the sources of the MOSFETs 93 and 94 are connected to the power supply potential VDD. The gates of the MOSFETs 91 and 94 are connected to the input terminal A, and the gates of the MOSFETs 92 and 93 are connected to the input terminal B.

  In this NAND circuit 90, for example, the input terminal A is connected to the output terminal of the oscillation circuit 40 shown in FIG. 8, and an amplitude voltage having a specific frequency (for example, 32 kHz) is applied to the input terminal A. ing. As a result, the MOSFETs 91 and 94 whose gates are connected to the input terminal A operate at a high frequency (that is, turn on and off in synchronization with the high frequency). For example, H is applied as the signal T to the input terminal B, the MOSFET 92 is turned on, and the MOSFET 93 is turned off. That is, MOSFET 92 is normally on and MOSFET 93 is normally off.

  By the way, in this 2nd Embodiment, all MOSFET91-94 contained in the NAND circuit 90 consists of FB-PD-SOI-MOSFET. The absolute value of the threshold voltage of the MOSFETs 91 and 94 operating at a high frequency is | Vth5 |, the absolute value of the threshold voltage of the normally-off MOSFET 93 is | Vth6 |, and the absolute value of the threshold voltage of the normally-on MOSFET 92 is | When Vth7 | is set, each value is set to, for example, | Vth5 | ≦ | Vth1 |, | Vth6 | = | Vth3 |, | Vth7 | = | Vth4 |. Thereby, in the NAND circuit 90, the on-current can be increased and the off-leakage current can be reduced.

  In the present invention, in addition to the above setting, the threshold voltage of the N-channel MOSFET 91 operating at a high frequency and the absolute value of the threshold voltage of the P-channel MOSFET 94 are preferably set to the same value. . That is, when the threshold voltage of the N-channel MOSFET 91 is Vth5 (N) and the threshold voltage of the P-channel MOSFET 94 is Vth5 (P), it is preferable to set Vth5 (N) = − Vth5 (P). . Accordingly, the N-channel MOSFET 91 and the P-channel MOSFET 94 can be turned on and off at the same timing under the same conditions (for example, the same voltage value).

  Further, in the present invention, in addition to the above setting, it is preferable to set the sizes of the MOSFETs 91 and 94 to the same value. That is, when the gate length of the N-channel MOSFET 91 is L5 (N), the gate width is W5 (N), the gate length of the P-channel MOSFET 94 is L5 (P), and the gate width is W5 (P), It is preferable that L1 (N) = L5 (P) and W1 (N) = W1 (P). Thereby, in a circuit using a threshold voltage or a subthreshold current equal to or lower than the threshold voltage, the balance of the On / Off currents of the P-channel and N-channel transistors is improved. This is because the swing S value in the sub-threshold region has the same value close to the ideal value for each of the P-channel and N-channel transistors, and the On / Off current ratio of each of the P-channel and N-channel transistors becomes almost equal. Because. Further, if the P-channel and N-channel transistors have the same minimum dimensions, the circuit can be reduced and the elements can be highly integrated.

As described above, according to the second embodiment of the present invention, in the NAND circuit 90 closest to the oscillation circuit 40, the absolute value of the threshold voltage of the MOSFETs 91 and 94 operating at a high frequency is included in the FF circuit 10 in the previous stage. Since it is set to a value at least equal to or lower than that of the MOSFETs 11 to 14, 21, and 25, a large on-current can be obtained even at a low voltage, and the operation speed of the inverter composed of the MOSFETs 91 and 94 is increased (ie, the delay). Time). Thereby, in the semiconductor device, it is possible to avoid an operation failure such as missing frequency division and to improve the stability of the circuit operation. Moreover, it is possible to achieve both a low standby current and an ultra-low voltage drive of 0.5 V or less, for example.
In the second embodiment, the MOSFETs 91 and 94 correspond to the “fifth transistor” of the present invention, the MOSFET 93 corresponds to the “sixth transistor” of the present invention, and the MOSFET 92 corresponds to the “seventh transistor” of the present invention. It corresponds to. The NAND circuit 90 corresponds to the “waveform shaping circuit” of the present invention. Other correspondences are the same as in the first embodiment.

(3) Third Embodiment In the first and second embodiments described above, for example, as shown in FIG. 10A, the frequency divider circuit 50 is divided into a front stage and a rear stage, and the frequency divider circuit 50 operates. The absolute values of the threshold voltages of the FB-SOI-MOSFETs 11 to 14, 21, and 25 that are repeatedly turned on and off in the normal state are differentiated between the NAND circuit 90, the preceding FF circuit 10, and the subsequent FF circuit 10. Explained what to do. However, the present invention is not limited to this.

For example, as shown in FIG. 10B, the frequency dividing circuit 50 may be divided into a front stage, a middle stage, and a rear stage, and the absolute value of the threshold voltage may be differentiated according to this division. Here, the middle stage is a position where the distance from the oscillation circuit 40 is farther from the previous stage and closer than the rear stage, and is a position between the front stage and the rear stage. In the interrupted FF circuit 10, when the absolute value of the threshold voltage of the MOSFETs 11 to 14, 21 and 25 that repeats on and off is normally | Vth8 | Set to │ <│Vth8│ <│Vth2│.
Alternatively, the frequency dividing circuit 50 is further divided into four or more stages instead of three stages of the preceding stage, the middle stage, and the latter stage, and the threshold voltage of the MOSFETs 11 to 14, 21, 25 increases as the distance from the oscillation circuit 40 increases. You may set so that an absolute value may become high. Thereby, the stability of the circuit operation and the power saving performance in the frequency divider circuit 50 can be finely adjusted.

(4) FB-PD-SOI-MOSFET Next, electrical characteristics of the FB-PD-SOI-MOSFET will be described.
In the FB-PD-SOI-MOSFET, when an input signal (that is, an amplitude voltage) in which H and L are switched at regular intervals, such as an alternating voltage or a pulse voltage, is applied, The absolute value of the threshold voltage is low, and the absolute value of the threshold voltage tends to increase with time. Such threshold voltage fluctuation is caused by a forward bias acting between the neutral region of the body region and the source region for a few seconds at the beginning of the start-up, and majority carriers in the source region move to the neutral region. This is because the majority of the carriers in the neutral region of the body are eliminated, so that the potential of the entire body region becomes unstable. This point will be described using, for example, an N-channel MOSFET 21 as an example.

  11 (a) to 12 (b) are diagrams showing changes in the state of the body region 66. Of these, FIG. 11 (a) is a conceptual diagram showing the extent of expansion of the depletion layer 66a and the neutral region 66b. Each figure (b) is the figure which showed along the depth direction the potential energy distribution in a cut surface when the body region 66 is cut | disconnected from the source end surface in the depth direction. In FIG. 11B and FIG. 12B, the horizontal axis represents potential energy, and the vertical axis represents the depth from the surface of the body region 66. φ0 is the initial surface potential of the MOSFET 21 to which no voltage is applied. φf is a function of the Fermi level Ef of the body region, and q · Φf = Ef−Ei. Here, Ei is an intrinsic silicon Fermi level, and q is a charge amount of electrons. 2φf corresponds to a threshold voltage.

  First, in FIG. 11A, a gate voltage Vg is applied to the gate electrode 63 and a drain voltage Vd is applied between the source region 64 and the drain region 65. Both the gate voltage Vg and the drain voltage Vd are DC voltages (that is, voltages whose directions do not change periodically). As an example, the drain voltage Vd = 0.4 [V] is applied between the source region 64 and the drain region 65, and the gate voltage Vg is changed from, for example, 0 [V] to 0.4 [V] in this state. The drain voltage Vd corresponds to the difference between the power supply potential Vdd shown in FIG. 5 and the ground potential (or Vreg). A case where the threshold voltage is smaller than the gate applied voltage 0.4V will be described.

  Then, as shown in FIG. 11A, the depletion layer 66a gradually expands downward in the body region 66, and the neutral region 66b becomes smaller by that amount (from the broken line region to the solid line region). This is shown in FIG. When Vg is raised from 0 V to 0.4 V, the depletion layer does not spread immediately, so that the potential energy (ie, potential) of the body region 66 also increases as a whole (process I).

  In this process I, the potential of the body region 66 is higher than the potential of the source region 64. Therefore, in FIGS. 11A and 11B, a forward bias acts between the P-type body region 66 and the N-type source region 64, and the source region 64 changes to the neutral region 66b. Electron e flows in. As a result, the holes h and electrons e, which are majority carriers, are recombined in the neutral region 66b to reduce the hole h, and the neutral region 66b becomes smaller (that is, the depletion layer 66a expands). The potential at 66b gradually decreases (process II). The flow of electrons e into the neutral region 66b continues until the potential of the neutral region 66b becomes substantially the same as the potential of the source region 64. When the potential of the neutral region 66b and the potential of the source region 64 become approximately the same level, the forward bias does not work, so the flow of electrons e stops and the reduction of the neutral region 66b also stops. That is, the source region 64 and the body region (depletion layer 66a and neutral region 66b) are in an equilibrium state, and the potential (number of majority carriers) of the body region 66 is stabilized. While the N-channel MOSFET 21 is on for a few seconds at the beginning of startup, the process I and the process II proceed in parallel.

  When the number of majority carriers in the neutral region 66b is stabilized, as shown in FIGS. 12A and 12B, the potential of the body region 66 is shifted as a whole in accordance with the on / off driving of the MOSFET 21. (Process III, IV). In these processes III and IV, the potential of the neutral region 66b is lower than the potential of the source region 64, and a reverse bias acts between the body region 66 and the source region 64. It is difficult for charge to move between the conductive region 66b. Therefore, the size of the neutral region 66b (that is, the number of majority carriers) hardly changes. While the depletion layer 66a and the neutral region 66b are maintained in an equilibrium state, the potential of the body region 66 repeatedly decreases and increases as the MOSFET 21 is turned on / off.

  FIGS. 13A and 13B are diagrams showing results of actually measuring the on-current and off-leakage current when the MOSFET 21 is continuously turned on / off. In FIG. 13A, the horizontal axis indicates time, and the vertical axis indicates on-current. In FIG. 13B, the horizontal axis represents time, and the vertical axis represents off-leakage current. Here, the gate electrode 63 and the drain region 65 are electrically connected (that is, short-circuited), and a voltage Vgs = 0.4 V is applied between the gate and the source at an interval of 500 msec.

  As shown in FIG. 13A, when the application of the voltage Vgs pulse is started, the on-current gradually decreases with the pulse, and after about 10 seconds, the value becomes stable. It was. Also, the hysteresis seen in the on-current almost disappeared after about 10 seconds. Similarly, as shown in FIG. 13B, when the application of the voltage Vgs pulse is started, the off-leakage current gradually decreases in accordance with the pulse, and the value becomes stable after about 10 seconds. It became a thing. That is, when about 10 seconds have elapsed after the on / off drive of the MOSFET 21 is started, the hysteresis disappears and the on / off ratio is close to the ideal characteristics of the FD-SOI-MOSFET.

  As described above, the N-channel FB-PD-SOI-MOSFET 21 allows a larger drain current (that is, an on-current and an off-leakage current) Id to flow at the same gate voltage Vg at the time of start-up than when it is stable. More power can be supplied. At the same time, the leakage current increases. This is because the potential of the neutral region 66b is higher than the potential of the source region 64 at the time of startup, and the absolute value of the apparent threshold voltage is small. In the stable state, the potential of the neutral region 66b is smaller than the potential of the source region 64, and the apparent absolute value of the threshold voltage is increased. In addition, a reverse bias is applied between the source and the body, making it difficult for electrons e to flow from the source region 64 to the neutral region 66b, and the sizes of the neutral region 66b and the depletion layer 66a hardly change. For this reason, the gate potential acts almost 100% on the potential barrier between the source and the channel without expanding the depletion layer, and exhibits a steep subthreshold current characteristic.

  Such characteristics can be seen not only in the N-channel type but also in the P-channel type FB-PD-SOI-MOSFET. That is, the P-channel type FB-PD-SOI-MOSFET can flow a larger drain current (that is, an on-current and an off-leakage current) Id at the same gate voltage Vg at the time of startup than at the time of stabilization. Larger power can be supplied. At the same time, the leakage current increases. Although not shown, when the P-channel type FB-PD-SOI-MOSFET is activated, the potential of the neutral region is lower than the potential of the source region, and a hole h is generated from the source region to the neutral region by a forward bias. It flows in and the neutral area becomes smaller. Further, at the stable time, the potential of the neutral region becomes larger than the potential of the source region, and holes h do not easily flow from the source region to the neutral region due to the reverse bias. Thereby, in the P-channel type FB-PD-SOI-MOSFET, the absolute value of the threshold voltage at the time of activation is lower than the absolute value of the threshold voltage at the time of stabilization.

  In the FB-PD-SOI-MOSFET, the absolute value of the gate voltage Vg, the absolute value of the drain voltage Vd, or the absolute value of the gate-source voltage Vgs is 0.8 [V] or less, more preferably It is preferably set to 0.6 [V] or less. That is, in the MOSFETs 11 to 14 and 21 to 26, the absolute value of the drive voltage is preferably 0.8 [V] or less, more preferably 0.6 [V] or less. Thereby, in the body region, pair creation (ie, generation of electron-hole pairs) due to impact ionization can be suppressed, and the potential of each body region can be prevented from fluctuating in an unintended direction. Therefore, it is possible to contribute to stabilization of the characteristics of the frequency divider circuit. When the absolute value of the drive voltage exceeds 0.8 [V], pair creation tends to occur in the body region.

  Note that the threshold voltage of the floating body type PD-SOI-MOSFET varies depending on the measurement method. For this reason, when comparing the magnitudes of threshold voltages, it is necessary to define the measurement method. That is, it is necessary to determine the measurement method for each of the N channel type and the P channel type. For example, the threshold voltage of an N-channel MOSFET is a current-voltage (DC-I-V) characteristic obtained by gradually reducing the applied voltage after applying a voltage higher than the use (drive) voltage between the gate and source. Can be determined by evaluating. For example, after holding the gate voltage Vg = 0.4 [V] for several to several tens of seconds, the gate voltage is decreased from 0.4 [V] to 0 [V], and the transfer characteristic measured at the time of the decrease. Based on the above, the threshold voltage of the N-channel MOSFET can be determined. At this time, the voltage between the source and the drain is set to a low voltage that does not cause impact ionization. In addition, the threshold voltage of the P-channel MOSFET is set such that, after applying a voltage higher than the absolute value of the use (drive) voltage between the gate and the source, the absolute value of the applied voltage is gradually reduced to obtain a current-voltage (DC -IV) can be determined by evaluating the characteristics. For example, after holding the gate voltage Vg = −0.4 [V] for several to several tens of seconds, the gate voltage is increased from −0.4 [V] to 0 [V], and measured at the time of this increase. Based on the transfer characteristics, the threshold voltage of the P-channel MOSFET can be determined.

  1, 3, 4, 5 clocked inverter, 2, 6 inverter, 10 quasi-static T flip-flop circuit (FF circuit), 11-14, 21-26, 91-94 FB-PD-SOI-MOSFET, 40 oscillation Circuit, 41 oscillating inverter, 42 crystal oscillator, 43 resistor, 44-46 capacitor, 50 frequency dividing circuit, 60 control circuit, 63 gate electrode, 64 source region, 65 drain region, 66 body region, 66a depletion layer, 66b Neutral region, 70 detection circuit, 80 power supply circuit, 90 NAND circuit, 100 frequency dividing circuit

Claims (9)

A frequency dividing circuit in which a plurality of flip-flop circuits are connected to an oscillation circuit over a plurality of stages,
A first flip-flop circuit operating at a high frequency on the front side close to the oscillation circuit;
A second flip-flop circuit operating at a low frequency on the rear stage side far from the oscillation circuit,
The first flip-flop circuit includes a first transistor formed in a semiconductor layer on an insulating layer,
The first transistor is a floating body type partially depleted transistor, which is normally a transistor that repeatedly turns on and off during the operation of the frequency divider.
The second flip-flop circuit includes a second transistor formed in the semiconductor layer on the insulating layer,
The second transistor is a floating body type partially depleted transistor, and is normally a transistor that repeatedly turns on and off during the operation of the frequency divider.
When the absolute value of the threshold voltage of the first transistor is | Vth1 | and the absolute value of the threshold voltage of the second transistor is | Vth2 |
A frequency dividing circuit characterized in that | Vth1 | <| Vth2 | is set. The first transistor includes a first N-type transistor and a first P-type transistor,
The gate length of the first N-type transistor is L1 (N),
The gate width of the first N-type transistor is W1 (N),
The threshold voltage of the first N-type transistor is Vth1 (N),
The gate length of the first P-type transistor is L1 (P),
The gate width of the first P-type transistor is W1 (P),
When the threshold voltage of the first P-type transistor is Vth1 (P),
L1 (N) = L1 (P),
W1 (N) = W1 (P),
2. The frequency dividing circuit according to claim 1, wherein Vth1 (N) = − Vth1 (P) is set. The second transistor includes a second N-type transistor and a second P-type transistor,
The gate length of the second N-type transistor is L2 (N),
The gate width of the second N-type transistor is W2 (N),
The threshold voltage of the second N-type transistor is Vth2 (N),
The gate length of the second P-type transistor is L2 (P),
The gate width of the second P-type transistor is W2 (P),
When the threshold voltage of the second P-type transistor is Vth2 (P),
L2 (N) = L2 (P),
W2 (N) = W2 (P),
3. The frequency dividing circuit according to claim 1, wherein Vth2 (N) = − Vth2 (P) is set. At least one of the first flip-flop circuit or the second flip-flop circuit has a third transistor formed in the semiconductor layer on the insulating layer,
The third transistor is a floating body type partially depleted transistor, and is a normally off transistor during the operation of the frequency divider.
When the absolute value of the threshold voltage of the third transistor is | Vth3 |
The frequency dividing circuit according to claim 1, wherein | Vth2 | ≦ | Vth3 | is set. At least one of the first flip-flop circuit or the second flip-flop circuit has a fourth transistor formed in the semiconductor layer on the insulating layer,
The fourth transistor is a floating body type partially depleted transistor, and is a normally-on transistor during the operation of the frequency divider.
When the absolute value of the threshold voltage of the fourth transistor is | Vth4 |
The frequency dividing circuit according to claim 1, wherein | Vth4 | ≦ | Vth1 | is set. A frequency dividing circuit according to any one of claims 1 to 5,
A waveform shaping circuit that is arranged between the oscillation circuit and the frequency divider circuit and that shapes the amplitude voltage output from the oscillation circuit and supplies the waveform to the frequency divider circuit;
The waveform shaping circuit includes a fifth transistor formed in the semiconductor layer on the insulating layer,
The fifth transistor is a floating body type partially depleted transistor, which is normally a transistor that repeatedly turns on and off when the waveform shaping circuit operates.
When the absolute value of the threshold voltage of the fifth transistor is | Vth5 |
| Vth5 | ≦ | Vth1 | is set. The fifth transistor includes a fifth N-type transistor and a fifth P-type transistor,
The gate length of the fifth N-type transistor is L5 (N),
The gate width of the fifth N-type transistor is W5 (N),
The absolute value of the threshold voltage of the fifth N-type transistor is Vth5 (N),
The gate length of the fifth P-type transistor is L5 (P),
The gate width of the fifth P-type transistor is W5 (P),
When the threshold voltage of the fifth P-type transistor is Vth5 (P),
L5 (N) = L5 (P),
W5 (N) = W5 (P),
The semiconductor device according to claim 6, wherein Vth5 (N) = − Vth5 (P) is set. The waveform shaping circuit includes a sixth transistor formed in the semiconductor layer on the insulating layer,
The sixth transistor is a floating body type partially depleted transistor, which is normally off during operation of the waveform shaping circuit,
When the absolute value of the threshold voltage of the sixth transistor is | Vth6 |
8. The semiconductor device according to claim 6, wherein | Vth2 | ≦ | Vth6 | is set. The waveform shaping circuit includes a seventh transistor formed in the semiconductor layer on the insulating layer;
The seventh transistor is a floating body type partially depleted transistor, and is a normally-on transistor during operation of the waveform shaping circuit.
When the absolute value of the threshold voltage of the seventh transistor is | Vth7 |
The semiconductor device according to claim 6, wherein | Vth7 | ≦ | Vth1 | is set.

Images