JP4115358B2 - Output circuit and level shift circuit - Google Patents

Description

  The present invention relates to an output circuit and a level shifter circuit constituted by transistors, and more particularly to an output circuit and a level shift circuit capable of outputting an output signal having an amplitude exceeding the breakdown voltage of the transistor.

  Currently, CMOS technology is most widely used for the manufacture of semiconductor integrated circuits. A CMOS integrated circuit manufactured on a semiconductor substrate by this CMOS technology is often used with a driving voltage of 5 V or less. However, CMOS integrated circuits are often used to drive and control devices that require larger amplitude voltages as input signals. As such a device, for example, a liquid crystal display used in a notebook personal computer, a cellular phone device, or the like can be cited. In order to drive the liquid crystal display, a signal with a high amplitude of 8V to 20V is required. It becomes. Therefore, a level shift circuit and an output circuit are required to create a high-amplitude signal for driving the liquid crystal display from a low-amplitude signal generated by the signal generation circuit. A high voltage is applied between the terminals of the transistors constituting such a level shift circuit and an output circuit.

  However, when a high voltage transistor for high voltage driving is manufactured on a semiconductor substrate in addition to a low voltage transistor for low voltage driving, the manufacturing process increases as the number of types of transistors increases, and the manufacturing cost increases. Will also increase.

  For this reason, for example, in Patent Document 1 and Patent Document 2, a high voltage transistor is not applied between terminals of each transistor without using a high voltage transistor, and a level shift circuit or an output circuit is formed by a low voltage transistor. Has been proposed.

  The high voltage CMOS logic circuit disclosed in Patent Document 1 will be described below.

  FIG. 8 is a circuit diagram showing a configuration of a high voltage CMOS logic circuit disclosed in Patent Document 1. In FIG. Here, an inverter circuit is shown as a representative example.

  In FIG. 8, this inverter circuit includes an N-channel transistor N11 and a P-channel transistor P11 to which an input signal Vin is input, an N-channel transistor N12 connected in series between a power supply voltage Vdd and a ground potential GND, and N13 and P-channel transistors P12 and P13 are configured, and the substrate terminals of the N-channel transistors N11 to N13 and the P-channel transistors P11 to P13 are all connected to the source terminal.

  The input signal Vin is applied to the drain terminal of the N-channel transistor N11, the intermediate potential VSHLD is applied to the gate terminal, and the source terminal is connected to the gate terminal of the N-channel transistor N12. The input signal Vin is applied to the drain terminal of the P-channel transistor P11, the intermediate voltage VSHLD is applied to the gate terminal, and the source terminal is connected to the gate terminal of the P-channel transistor P12. The drain terminal of the N-channel transistor N12 is connected to the source terminal of the N-channel transistor N13, and the source terminal is connected to the ground potential GND. The drain terminal of the P-channel transistor P12 is connected to the source terminal of the P-channel transistor P13, and the power supply voltage Vdd is applied to the source terminal. An intermediate potential VSHLD is applied to the gate terminal of the N-channel transistor N13, and the drain terminal is connected to the output terminal Vout. An intermediate potential VSHLD is applied to the gate terminal of the P-channel transistor P13, and the drain terminal is connected to the output terminal Vout. The intermediate potential VSHLD is set to a half potential of the power supply voltage Vdd.

  In a super transistor “Super transistor” composed of two N-channel transistors N11 and N12, the source terminal is connected to the gate terminal of the second transistor N12. Even if the high-amplitude power supply voltage Vdd is applied as the input signal Vin to the drain terminal of the first N-channel transistor N11, the intermediate potential VSHLD = Vdd / 2 is applied to the gate terminal of the first N-channel transistor N11. Therefore, only Vdd / 2, which is half the power supply voltage, is applied between the gate and drain of the first N-channel transistor N11, and the source terminal of the first N-channel transistor N11 is applied. Only outputs a voltage of Vdd−VSHLD−Vtn = Vdd / 2−Vtn. Here, Vtn is a threshold voltage of the N-channel transistor. Therefore, only the voltage of Vdd / 2−Vtn is applied between the gate / source of the second N-channel transistor N12.

  For the P-channel transistor, the voltage applied between the gate / drain and between the gate / source can be reduced to half or less of the power supply voltage by using the same configuration. By using the supertransistor “Supertransistor” thus configured, a logic circuit such as an inverter circuit can be configured.

  However, as the output signal, a signal having the same high amplitude as the power supply voltage Vdd is output. Therefore, when the inverter circuit is configured by only the supertransistor “Supertransistor”, the second N-channel transistor N12 and the second P-channel transistor A voltage higher than the withstand voltage is applied between the gate / drain of the channel type transistor P12.

  Therefore, as shown in FIG. 8, a third N-channel transistor N13 and a third P-channel transistor P13 are inserted between the second N-channel transistor N12 and the second P-channel transistor P12. Thus, by applying the intermediate potential VSHLD = Vdd / 2 to the gate terminals of the transistors N13 and P13, the voltage applied between the gate / drain and between the gate / source of each transistor is suppressed to less than half of the power supply voltage Vdd. Is possible.

  Therefore, a high-amplitude input signal can be output without destroying the transistor by using a low-voltage transistor without using a high-voltage transistor.

  Next, the level shift circuit disclosed in Patent Document 2 will be described.

  In Patent Document 1, as shown in FIG. 8, in the transistors N11 and P11 constituting the output circuit, 0 to Vdd / 2−2 is input from the input signal Vin having the same amplitude as the power supply voltage Vdd by the transistor N11. A signal of Vtn is generated, and a signal of Vdd / 2 + | Vtp | to Vdd is generated by the transistor P11.

  On the other hand, in Patent Document 2, the transistors N11 and P11 are not provided, and the signals Vin1 and Vin2 having half the amplitude of the power supply voltage are input to the transistors N13 and P13, so that the amplitude has the same magnitude as the power supply voltage. Is output.

  Also in this level shift circuit, the voltage applied to the gate terminals of the transistors N13 and P13 is set to Vdd / 2, which is half the power supply voltage, thereby connecting the drain terminal of the transistor N12 and the source terminal of the N13. A voltage Vb = Vdd / 2−Vtn is output at the point B, and a voltage Vc = Vdd / 2 + | Vtp | is output at a connection point C between the drain terminal of the transistor P12 and the source terminal of P13. Therefore, the voltage applied between the gate / drain and between the gate / source of each transistor can be suppressed to half or less of the power supply voltage Vdd.

Therefore, a high-amplitude input signal can be output without destroying the transistor by using a low-voltage transistor without using a high-voltage transistor.
U. S. Patent 5,465,054 JP 2001-102915 A

  In the output circuit disclosed in Patent Document 1 and the level shift circuit disclosed in Patent Document 2, even when a transistor having a breakdown voltage between the gate / drain and between the gate / source of only about half of the power supply voltage is used, The transistor can be operated normally without being destroyed. However, these output circuits and level shift circuits have the following problems.

  9A to 9E are waveform diagrams when the inverter circuit shown in FIG. 8 is operated.

  FIG. 9A shows the waveforms of the input signal Vin and the output signal Vout.

  FIG. 9B shows waveforms of the voltage Va at the connection point A between the transistors N11 and N12 and the voltage Vd at the connection point D between the transistors P11 and P12.

  FIG. 9C shows waveforms of the voltage Vb at the connection point B between the transistors N12 and N13 and the voltage Vc at the connection point C between the transistors P12 and P13.

  FIG. 9D shows the voltage differences Vin−Va and Vd−Vin between the source / drain of the transistor N11 and the transistor P11.

  FIG. 9E shows the voltage differences Vout−Vb and Vc−Vout between the source / drain of the transistor N13 and the transistor P13.

  Looking at the first N-channel transistor N11, half of the power supply voltage Vdd / 2 is applied to the gate terminal, and the drain terminal has the same amplitude as the power supply voltage as shown in FIG. Since the signal is input, as shown in FIG. 9B, the source terminal (connection point A) is charged only to Vdd / 2−Vtn, which is a voltage lower than the half of the power supply voltage by the threshold voltage. . Therefore, as shown in FIG. 9D, a voltage of Vdd / 2 + Vtn, which is a voltage higher than the half of the power supply voltage by the threshold voltage, is applied between the source and drain.

  As for the third N-channel transistor N13, half of the power supply voltage Vdd / 2 is applied to the gate terminal, and the amplitude from the drain terminal is the same as the power supply voltage as shown in FIG. Therefore, as shown in FIG. 9C, the source terminal (connection point B) is charged only to Vdd / 2−Vtn, which is a voltage lower than the half of the power supply voltage by the threshold voltage. Not. Therefore, as shown in FIG. 9E, a voltage of Vdd / 2 + Vtn, which is a voltage higher than the half of the power supply voltage by the threshold voltage, is applied between the source and drain.

  Further, the first transistor N11 functions as a transfer gate, and as shown in FIG. 9B, the rise delay time becomes longer than that at the fall time. Thus, a large voltage is applied.

  Looking at the first P-channel transistor P11, half of the power supply voltage Vdd / 2 is applied to the gate terminal, and the drain terminal has the same amplitude as the power supply voltage, as shown in FIG. Since the signal is input, as shown in FIG. 9B, the source terminal (connection point D) is discharged only to Vdd / 2 + | Vtp | which is a voltage higher than the half of the power supply voltage by the threshold voltage. . Therefore, as shown in FIG. 9D, a voltage of Vdd / 2 + | Vtp |, which is a voltage higher than the half of the power supply voltage by the threshold voltage, is applied between the source and drain.

  Further, regarding the third P-channel transistor P13, half of the power supply voltage Vdd / 2 is applied to the gate terminal, and as shown in FIG. 9A, the amplitude is the same as the power supply voltage at the drain terminal. Therefore, as shown in FIG. 9C, the source terminal (connection point C) is only up to Vdd / 2 + | Vtp |, which is higher than the half of the power supply voltage by the threshold voltage. Does not discharge. Therefore, as shown in FIG. 9E, a voltage of Vdd / 2 + | Vtp |, which is a voltage higher than the half of the power supply voltage by the threshold voltage, is applied between the source and drain.

  Further, the first transistor P11 functions as a transfer gate, and as shown in FIG. 9B, the delay time of the fall is longer than that at the time of rise. Thus, a large voltage is applied.

  Therefore, when a transistor having a source / drain breakdown voltage of only about half of the power supply voltage is used, the transistor is deteriorated or destroyed. The same applies to the level shift circuit disclosed in Patent Document 2.

  By the way, CMOS LSI is suitable for devices that require low power consumption, and has achieved remarkable performance improvement. However, the power consumption of the LSI chip increases with its increase in scale and operation speed. Even in CMOS LSIs, further reduction in power consumption has become necessary. Therefore, an SOI (Silicon On Insulator) structure suitable for reducing parasitic capacitance and power supply voltage is used as means for reducing the power consumption of the CMOS LSI.

  In recent years, polysilicon thin film transistors have been used not only as switching elements for pixels formed on an active matrix substrate of a liquid crystal display but also for peripheral drive circuits by utilizing their high mobility characteristics. A circuit-integrated liquid crystal display device is realized. In such a transistor manufactured over an insulating substrate, the body potential is not fixed, and the dynamic substrate floating effect caused by the fluctuation of the body potential is the biggest problem of the SOI device.

  In order to suppress such a dynamic substrate floating effect, there is a method of providing a body contact (substrate terminal) for fixing a body potential. There is a drawback that the layout is severely restricted. Even without providing a body contact, it is possible to suppress the dynamic substrate floating effect by reducing the thickness of the body region and completely depleting it. As a result, the parasitic bipolar effect with the emitter-base collect becomes more likely to occur, resulting in a problem that the breakdown voltage between the source and the drain is lowered.

  The present invention solves the above-mentioned conventional problems, and can output an output signal having an amplitude exceeding the breakdown voltage between the source and drain of the transistor, and can operate the transistor normally without deterioration or destruction. An object of the present invention is to provide a level shift circuit.

The output circuit of the present invention is an output circuit that receives an input signal having the same amplitude as the power supply voltage and outputs an output signal having the same amplitude as the power supply voltage in response to the input signal. is input the input signal to the other driving terminal, control the first intermediate potential and the first one conductivity type transistors that are applied to the control terminal, the control terminal is one driving terminal of the one conductivity type the first transistor connected, whereas a second one conductivity type transistors that drive terminal is connected to the supply end of the ground potential, whereas the drive terminal connected to the other driving terminal of the one conductivity type the second transistor, the control terminal a third one conductivity type transistor in which the first intermediate potential is applied, is input the input signal to the other driving terminal, the first other conductivity type Trang second intermediate potential is applied to the control terminal And a control terminal is connected to one drive terminal of the first other conductivity type transistor, one drive terminal is connected to the power supply voltage supply terminal, and one drive terminal is the first drive terminal. It is connected to the other driving terminal of the second other conductivity type transistor, the control terminal and the second intermediate potential is applied to the other driving terminal is connected in common to the other driving terminal of the third one conductivity type transistors output Each of the first to third one-conductivity type transistors and each of the first to third other-conductivity type transistors has an insulating surface, respectively. a partial depletion type thin film transistor fabricated on a substrate having, whereas the breakdown voltage between the drive terminals / other driving terminal is a low voltage transistor of half the power supply voltage, the first in Potential is set to a threshold voltage higher by a voltage of the one conductivity type transistor than half of the power supply voltage, said second intermediate potential threshold voltage of the other conductivity type transistor than half of the supply voltage Of the first to third one-conductivity type transistors is connected to one drive terminal and a substrate terminal, and the first to third other-conductivity types are connected to each other. One of the drive terminals of each of the transistors and the substrate terminal are connected to achieve the above object.

Further, the output circuit of the present invention receives an input signal having the same amplitude as the power supply voltage, and outputs an output signal having the same amplitude as the power supply voltage in response to the input signal. The first drive transistor of the first one-conductivity type transistor, the first one-conductivity-type transistor in which the input signal is inputted to the other drive terminal and the first intermediate potential is applied to the control terminal. And one drive terminal is connected to the supply terminal of the ground potential, and one drive terminal is connected to the other drive terminal of the second one conductivity type transistor and is connected to the control terminal. The third one conductivity type transistor to which the first intermediate potential is applied, and the first other conductivity type to which the input signal is input to the other drive terminal and the second intermediate potential is applied to the control terminal. A transistor, a control terminal connected to one drive terminal of the first other conductivity type transistor, a one drive terminal connected to the power supply voltage supply terminal, and a one drive terminal connected to the first drive terminal. Connected to the other drive terminal of the second other conductivity type transistor, the second intermediate potential is applied to the control terminal, and the other drive terminal is commonly connected to the other drive terminal of the third one conductivity type transistor and output. Each of the first to third one-conductivity type transistors and each of the first to third other-conductivity type transistors has an insulating surface, respectively. A fully-depleted thin film transistor manufactured over a substrate having a low withstand voltage between one drive terminal and the other drive terminal that is half of the power supply voltage; Is set to a voltage higher than the half of the power supply voltage by the threshold voltage of the one conductivity type transistor, and the second intermediate potential is set to a threshold value of the other conductivity type transistor than the half of the power supply voltage. The voltage is set lower by the absolute value of the value voltage, thereby achieving the above object.

  Further preferably, the input signal in the output circuit of the present invention is a signal whose minimum level is the ground potential and whose maximum level is the power supply voltage.

More preferably, the channel widths of the first one-conductivity type transistor and the first other-conductivity-type transistor are at least as large as the channel widths of the second one-conductivity type transistor and the second other-conductivity-type transistor. Is also set larger .

The level shift circuit of the present invention has a first input signal having a first amplitude and a first amplitude that is the same as the first input signal, and the minimum level of the signal is the maximum of the first input signal. A second input signal having the same level as that of the first input signal and having a second amplitude that is twice as large as the first amplitude in response to the first input signal and the second input signal. A level shift circuit for outputting an output signal, wherein the first input signal is applied to a control terminal, and one drive terminal is connected to a ground potential supply terminal; A second one-conductivity type transistor having a terminal connected to the other drive terminal of the first one-conductivity type transistor and a first intermediate potential applied to the control terminal; and the second input signal at the control terminal. One drive terminal is connected to the supply end of the power supply voltage The first other conductivity type transistor connected, one drive terminal is connected to the other drive terminal of the first other conductivity type transistor, a second intermediate potential is applied to the control terminal, and the other drive terminal is A second other conductivity type transistor connected in common with the other drive terminal of the second one conductivity type transistor and serving as an output terminal, and each of the first and second one conductivity type transistors and the first Each of the first and second other conductivity type transistors is a partially depleted thin film transistor fabricated on a substrate having an insulating surface, and the breakdown voltage between one drive terminal / the other drive terminal is half of the power supply voltage. The first intermediate potential is set to a voltage higher than the half of the power supply voltage by the threshold voltage of the one conductivity type transistor, The second intermediate potential is set to a voltage lower than half of the power supply voltage by the absolute value of the threshold voltage of the other conductivity type transistor, and each of the first and second one conductivity type transistors. One drive terminal and a substrate terminal are connected, and one drive terminal and a substrate terminal of each of the first and second other conductivity type transistors are connected.

The level shift circuit of the present invention has a first input signal having a first amplitude, the same first amplitude as the first input signal, and the minimum level of the signal being the first input signal. And a second input signal having the same level as the second input signal, and a second amplitude that is twice the first amplitude according to the first input signal and the second input signal. A first shift transistor that outputs an output signal having the first input signal applied to a control terminal and one drive terminal connected to a ground potential supply terminal; A second one-conductivity type transistor in which one drive terminal is connected to the other drive terminal of the first one-conductivity type transistor and a first intermediate potential is applied to the control terminal; and the second input to the control terminal A signal is applied, while the drive terminal supplies the supply voltage. A first other conductivity type transistor connected to the end, one drive terminal is connected to the other drive terminal of the first other conductivity type transistor, a second intermediate potential is applied to the control terminal, and the other drive terminal Has a second other conductivity type transistor connected in common to the other drive terminal of the second one conductivity type transistor and serving as an output terminal, and each of the first and second one conductivity type transistors and Each of the first and second other conductivity type transistors is a fully depleted thin film transistor fabricated on a substrate having an insulating surface, and the withstand voltage between one drive terminal / the other drive terminal is the power supply voltage. The first intermediate potential is set to a voltage higher than the half of the power supply voltage by the threshold voltage of the one conductivity type transistor. The second intermediate potential is set to absolute value of only low voltage of the threshold voltage of the other conductivity type transistor than half of the supply voltage.

Preferably, the first input signal, the minimum level is the maximum level at the ground potential is half of the signal of the power supply voltage, the second input signal, a maximum level at half the minimum level the power supply voltage The power supply voltage signal.

  The operation of the present invention will be described below with the above configuration.

  In the output circuit of the present invention, in the first to third one conductivity type (for example, N channel type) transistors and the first to third other conductivity type (P channel type) transistors constituting the output circuit. The first N-channel transistor control terminal (gate terminal) to which the input signal is input and the first N-channel transistor control terminal (gate terminal) to which the output signal is output are applied to the first N-channel transistor control terminal (gate terminal). The intermediate voltage Vref1 is set to a voltage higher than the half of the power supply voltage Vdd by the threshold voltage, and the control terminal (gate terminal) of the first P-channel transistor to which the input signal is input and the output signal are output. The second intermediate voltage Vref2 applied to the control terminal (gate terminal) of the third P-channel transistor is a threshold voltage amount more than half of the power supply voltage Vdd. It is set to a low voltage.

  Thus, the amplitude of the signal output to one drive terminal (for example, the source terminal) of the first N-channel transistor and the first P-channel transistor, and the third N-channel transistor and the third P-channel transistor The amplitude of the signal input to the source terminal of the transistor is half of the power supply voltage. Accordingly, the voltage between the one drive terminal (for example, the source terminal) and the other drive terminal (the drain terminal) of the first to third N-channel transistors and the first to third P-channel transistors is only half the power supply voltage. Since no voltage is applied, even if a transistor having a breakdown voltage between one drive terminal (for example, a source terminal) and the other drive terminal (drain terminal) is about half the power supply voltage, the transistor can be operated normally without being destroyed. Is possible.

  Further, by connecting all the substrate terminals of the transistors constituting the output circuit of the present invention to the source terminal, the voltage difference between the substrate and the source terminal can be made zero. Therefore, variation in the threshold voltage due to the voltage difference between the substrate / source terminals can be suppressed.

  Further, by using a transistor formed over a substrate having an insulating surface as a transistor constituting the output circuit of the present invention, the drain junction capacitance can be reduced, so that the operation speed of the transistor is improved. Thus, the delay time can be shortened. Accordingly, the time during which a voltage higher than the withstand voltage is applied between the source terminal and the drain terminal can be shortened, and deterioration of the transistor can be suppressed.

  Furthermore, by using a fully depleted transistor manufactured on a substrate having an insulating surface as a transistor constituting the output circuit of the present invention, a dynamic substrate floating effect can be prevented from appearing. Therefore, it is not necessary to provide a body contact (substrate terminal) for fixing the body potential. Therefore, an increase in the area occupied by the element can be prevented, and restrictions on layout design can be relaxed.

  Further, the channel widths of the first N-channel transistor and the first P-channel transistor constituting the output circuit of the present invention are the channel widths of the second N-channel transistor and the second P-channel transistor. By setting it to be larger than that, the drive capability of the first N-channel transistor and the first P-channel transistor is increased, and the rise time of the first N-channel transistor and the rise time of the first P-channel transistor are increased. Downtime is shortened. Therefore, when the first N-channel transistor rises and when the first P-channel transistor falls, the time during which a voltage higher than the withstand voltage is applied between the source and drain is shortened, so that deterioration of the transistor is suppressed. Can do.

  In the level shift circuit of the present invention, the first and second N-channel transistors and the first and second P-channel transistors constituting the level shift circuit output second output signals. The second P-channel transistor in which the first intermediate voltage Vref1 applied to the gate terminal of the N-channel transistor is set to a voltage higher than the half of the power supply voltage Vdd by the threshold voltage and the output signal is output. The second intermediate voltage Vref2 applied to the gate terminal is set to a voltage lower than the half of the power supply voltage Vdd by the threshold voltage.

As a result, the amplitudes of the signals input to the source terminals of the second N-channel transistor and the second P-channel transistor are both half of the power supply voltage. Therefore, since only half the power supply voltage is applied between the source / drain of the first and second N-channel transistors and the first and second P-channel transistors, the breakdown voltage between the source / drain is the power supply voltage. Even when about half of the transistors are used, the transistors can be operated normally without being destroyed.
Further, by connecting all the substrate terminals of the transistors constituting the level shift circuit of the present invention to the source terminals, the voltage difference between the substrate and the source terminals can be made zero. Therefore, fluctuations in the threshold voltage due to the voltage difference between the substrate / source terminals can be suppressed.
In addition, by using a transistor manufactured over a substrate having an insulating surface as a transistor constituting the level shift circuit of the present invention, the drain junction capacitance can be reduced, so that the operation speed of the transistor is improved. Thus, the delay time can be shortened. Therefore, the time during which a voltage higher than the withstand voltage is applied between the source and drain can be shortened, and deterioration of the transistor can be suppressed.
Further, by using a fully depleted transistor manufactured on a substrate having an insulating surface as a transistor constituting the level shift circuit of the present invention, a dynamic substrate floating effect is prevented from appearing. Therefore, there is no need to provide a body contact for fixing the body potential. Therefore, an increase in the area occupied by the element can be prevented, and restrictions on layout design can be relaxed.

  As described above, according to the present invention, the first to third one conductivity type (for example, N channel type) transistors and the first to third other conductivity type (P channel type) transistors constituting the output circuit are input. The first intermediate voltage Vref1 applied to the control terminal (gate terminal) of the first N-channel transistor to which a signal is input and the control terminal (gate terminal) of the third N-channel transistor to which an output signal is output. Is set to a voltage higher than the half of the power supply voltage Vdd by the threshold voltage, and the gate terminal of the first P-channel transistor to which the input signal is input and the third P-channel transistor to which the output signal is output. By setting the second intermediate voltage Vref2 applied to the gate terminal to a voltage lower than the half of the power supply voltage Vdd by the threshold voltage. On the other hand also withstand voltage between the drive terminal (for example, a source terminal) / other driving terminal (drain terminal) using about half of the transistors of the power supply voltage, it can be operated normally without the transistor is destroyed.

  Further, by connecting all the substrate terminals of the transistors constituting the output circuit of the present invention to the source terminal, fluctuations in the threshold voltage due to the voltage difference between the substrate and the source terminal can be suppressed.

  Furthermore, as a transistor included in the output circuit of the present invention, a transistor manufactured over a substrate having an insulating surface can be used, so that drain junction capacitance can be reduced and the operation speed of the transistor can be improved. The deterioration of the transistor can be suppressed by shortening the time during which a voltage higher than the withstand voltage is applied between the source terminal and the drain terminal.

  Furthermore, by using a fully depleted transistor manufactured on a substrate having an insulating surface as a transistor constituting the output circuit of the present invention, a body potential can be prevented from appearing because a dynamic substrate floating effect does not appear. Therefore, it is not necessary to provide a body contact for fixing the element, and an increase in the area occupied by the element can be prevented, and restrictions on layout design can be relaxed.

  Further, the channel widths of the first N-channel transistor and the first P-channel transistor constituting the output circuit of the present invention are set as the second and third N-channel transistors and the second and third N-channel transistors. By setting the channel width larger than each channel width of the P-channel transistor, the driving capability of the first N-channel transistor and the first P-channel transistor can be increased. At the time of rising and at the time of falling of the first P-channel transistor, the time during which a voltage higher than the withstand voltage is applied between the source terminal and the drain terminal can be shortened to suppress deterioration of the transistor.

  Next, according to the level shift circuit of the present invention, the second output signal is output for the first and second N-channel transistors and the first and second P-channel transistors constituting the level shift circuit. A second P-channel transistor from which an output signal is output by setting the first intermediate voltage Vref1 applied to the gate terminal of the N-channel transistor to a voltage higher than the half of the power supply voltage Vdd by a threshold voltage By setting the second intermediate voltage Vref2 applied to the gate terminal of the transistor to a voltage lower than the half of the power supply voltage Vdd by a threshold voltage, a transistor having a source / drain breakdown voltage of about half of the power supply voltage is used. However, the transistor can be operated normally without being destroyed.

  Further, by connecting all the substrate terminals of the transistors constituting the level shift circuit of the present invention to the source terminal, fluctuations in the threshold voltage due to the voltage difference between the substrate and the source terminal can be suppressed.

  Furthermore, by using a transistor manufactured over a substrate having an insulating surface as a transistor constituting the level shift circuit of the present invention, the drain junction capacitance can be reduced and the operation speed of the transistor can be improved. Therefore, the deterioration of the transistor can be suppressed by reducing the time during which a voltage higher than the withstand voltage is applied between the source terminal and the drain terminal.

  Further, as a transistor constituting the level shift circuit of the present invention, a fully depleted transistor manufactured on a substrate having an insulating surface is used, so that a dynamic substrate floating effect does not appear, so that the body potential Therefore, it is not necessary to provide a body contact for fixing the element, and an increase in the area occupied by the element can be prevented, and restrictions on layout design can be relaxed.

  The output circuits of Embodiments 1 to 4 of the present invention and the level shift circuits of Embodiments 5 to 7 of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 is a circuit diagram showing a configuration of an output circuit according to Embodiment 1 of the present invention.

  In FIG. 1, this output circuit includes a first N-channel type (one conductivity type) transistor N11 and a first P-channel type (other conductivity type) transistor P11 to which an input signal Vin is input, a power supply voltage Vdd and a ground. A second N-channel transistor N12, a second N-channel transistor N13, a second P-channel transistor P12, and a third P-channel transistor P13 connected in series between the potential GND. Yes.

  The substrate terminals of the first to third N-channel transistors N11 to N13 and the first to third P-channel transistors P11 to P13 are all connected to the source terminal (one drive terminal). The reason why all the substrate terminals of the N-channel transistors N11 to N13 and the P-channel transistors P11 to P13 are connected to the source terminals will be described later.

  The input signal Vin is applied to the drain terminal (the other drive terminal) of the first N-channel transistor N11, the first intermediate voltage Vref1 is applied to the gate terminal (control terminal), and the source terminal is the second N The channel type transistor N12 is connected to the gate terminal.

  The drain terminal of the first P-channel transistor P11 is connected in common with the drain terminal of the first N-channel transistor N11, the input signal Vin is applied, the second intermediate voltage Vref2 is applied to the gate terminal, The source terminal is connected to the gate terminal of the second P-channel transistor P12.

  The drain terminal of the second N-channel transistor N12 is connected to the source terminal of the third N-channel transistor N13, and the source terminal of the second N-channel transistor N12 is connected to the ground potential GND.

  The drain terminal of the second P-channel transistor P12 is connected to the source terminal of the third P-channel transistor P13, and the power supply voltage Vdd is applied to the source terminal of the second P-channel transistor P12. .

  The first intermediate voltage Vref1 is applied to the gate terminal of the third N-channel transistor N13, and the drain terminal of the third N-channel transistor N13 is connected to the output terminal Vout.

  The second intermediate voltage Vref2 is applied to the gate terminal of the third P-channel transistor P13, and the drain terminal of the third P-channel transistor P13 is connected in common with the drain terminal of the third N-channel transistor N13. And connected to the output terminal Vout.

  The first intermediate voltage Vref1 is a voltage obtained by adding the threshold voltage Vtn of the N-channel transistor to half of the potential difference between the power supply voltage Vdd and the ground potential GND, and Vref1 = Vdd / 2 + Vtn.

  The second intermediate voltage Vref2 is a voltage obtained by subtracting the absolute value | Vtp | of the threshold voltage of the P-channel transistor from half of the potential difference between the power supply voltage Vdd and the ground potential GND, and Vref2 = Vdd / 2− | Vtp. | For example, if Vdd = 10V, Vtn = 1V, and Vtp = −1V, then Vref1 = 10/2 + 1 = 6V and Vref2 = 10 / 2− | −1 | = 4V.

  The operation of the output circuit of the first embodiment will be described with the above configuration.

  2A to 2E are waveform diagrams when the output circuit shown in FIG. 1 is operated.

  FIG. 2A shows the waveform of the input signal Vin (solid line) and the waveform of the output signal Vout (dotted line).

  FIG. 2B shows a waveform (solid line) of the voltage Va at the connection point A between the transistors N11 and N12 and a waveform (dotted line) of the voltage Vd at the connection point D between the transistors P11 and P12.

  FIG. 2C shows the waveform (solid line) of the voltage Vb at the connection point B between the transistors N12 and N13 and the waveform (dotted line) of the voltage Vc at the connection point C between the transistors P12 and P13.

  FIG. 2D shows the voltage difference Vin−Va (solid line) between the source and drain of the transistor N11 and the voltage difference Vd−Vin (dotted line) between the source and drain of P13.

  FIG. 2E shows the voltage difference Vout−Vb (solid line) between the source and drain of the transistor N13 and the voltage difference Vc−Vout (dotted line) between the source and drain of P13.

  Hereinafter, for convenience of description, the gate voltage of the transistor N11 is expressed as Vg (N11), the drain voltage is expressed as Vd (N11), and the source voltage is expressed as Vs (N11). The gate voltage, drain voltage, and source voltage of the transistors N12, N13 and P11 to P13 will be described using the same notation.

  First, the operation of the first N-channel transistor N11 will be described.

  As shown in FIG. 2A, when the input signal Vin is at a low level (Vin = 0) at time T1, the transistor N11 has Vg (N11) = Vref1 = Vdd / 2 + Vtn, Vd (N11) = Vin. Since = 0, Vg (N11) −Vd (N11)> Vtn, so that the ON state is entered. Therefore, as shown in FIG. 2B, the voltage Va at the connection point A is pulled down to Va = 0.

  At time T2, when the input signal Vin changes from Low → High level (Vin: 0 → Vdd) as shown in FIG. 2A, Vin = Vd (N11) <Vg (N11) −Vtn = Vdd / 2 During this period, the transistor N11 is in the ON state. Therefore, as shown in FIG. 2B, the connection point A is pulled up so that the voltage Va at the connection point A becomes a value in the range of 0 <Va <Vdd / 2, and the input signal Vin becomes Vin: 0 → Vdd / As it increases to 2, Va increases from 0 to Vdd / 2. When Vin = Vd (N11)> Vg (N11) −Vtn = Vdd / 2, the transistor N11 is turned off, so that the voltage Va at the connection point A is not further pulled up and is held at Va = Vdd / 2. Is done.

  At time T3, when the input signal Vin is at a high level (Vin = Vdd) as shown in FIG. 2A, the transistor N11 has Vg (N11) = Vdd / 2 + Vtn and Vd (N11) = Vin = Vdd. Since Vd (N11)> Vg (N11) −Vtn, it is in the OFF state. Therefore, as shown in FIG. 2B, the voltage Va at the connection point A is held at Va = Vdd / 2.

  At time T4, as shown in FIG. 2A, when the input signal Vin changes from High to Low level (Vin: Vdd → 0), Vin = Vd (N11)> Vg (N11) −Vtn = Vdd / During 2, the transistor N11 remains in the OFF state. Therefore, as shown in FIG. 2B, the voltage Va at the connection point A is held at Va = Vdd / 2. When Vin = Vd (N11) <Vg (N11) −Vtn = Vdd / 2, the transistor N11 is turned on, so that the connection point A is pulled down and the voltage Va at the connection point A is 0 <Va <Vdd / 2. As the input signal Vin decreases from Vin: Vdd / 2 → 0, Va: Vdd / 2 → 0.

  At time T5, as shown in FIG. 2A, when the input signal Vin is at a low level (Vin = 0), the transistor N11 has Vg (N11) = Vref1 = Vdd / 2 + Vtn, Vd (N11) = Vin = 0. Since Vg−Vd> Vtn, the ON state is established. Therefore, as shown in FIG. 2B, the voltage Va at the connection point A is pulled down to Va = 0.

  Next, the operation of the first P-channel transistor P11 will be described. The first P-channel transistor P11 also operates substantially the same as the first N-channel transistor N11.

  As shown in FIG. 2A, at time T1, the input signal Vin is at a low level (when Vin = 0), and the transistor P11 has Vg (P11) = Vdd / 2− || Vtp |, Vd (P11) = Vin. Since Vin = 0Vd (P11) <Vg (P11) + | Vtp | from 0, the state is OFF. Therefore, as shown in FIG. 2B, the voltage Vd at the connection point D is held at Vd = Vdd / 2.

  At time T2, as shown in FIG. 2A, when the input signal Vin changes from Low → High level (Vin: 0 → Vdd), Vin = Vd (P11) <Vg (P11) + | Vtp | = During Vdd / 2, the transistor P11 remains in the OFF state. Therefore, as shown in FIG. 2B, the voltage Vd at the connection point D is held at Vd = Vdd / 2. As shown in FIG. 2A, when Vin = Vd (P11)> Vg (P11) + | Vtp | = Vdd / 2, the transistor P11 is turned on. Therefore, as shown in FIG. 2B, the connection point D is pulled up, and the voltage Vd at the connection point D becomes a value in the range of Vdd / 2 <Vd <Vdd, and the input signal Vin becomes Vin: 0 → Vdd. As it increases, Va increases from Vdd / 2 to Vdd.

  At time T3, when the input signal Vin is at a high level (Vin = Vdd) as shown in FIG. 2A, the transistor P11 has Vg (P11) = Vref2 = Vdd / 2− || Vtp |, Vd (P11). Since = Vin = Vdd, Vd (P11) -Vg (P11)> | Vtp | Therefore, as shown in FIG. 2B, the voltage Vd at the connection point D is pulled up to Vd = Vdd.

  At time T4, when the input signal Vin changes from High to Low level (Vin: Vdd → 0) as shown in FIG. 2A, Vin = Vd (P11)> Vg (P11) + | Vtp | = Vdd. During / 2, the transistor P11 is in the ON state. Therefore, as shown in FIG. 2B, the connection point D is pulled down, and the voltage Vd at the connection point D becomes a value in the range of Vdd / 2 <Vd <Vdd, and the input signal Vin falls to Vin: Vdd → 0. As Va decreases from Vdd to Vdd / 2. As shown in FIG. 2A, when Vin = Vd (P11) <Vg (P11) + | Vtp | = Vdd / 2, the transistor P11 is turned off. Therefore, as shown in FIG. 2B, the voltage Vd at the connection point D is not pulled down any more, and is held at Vd = Vdd / 2.

  At time T5, when the input signal Vin is at a low level (Vin = 0) as shown in FIG. 2A, the transistor P11 has Vg (P11) = Vdd / 2− || Vtp |, Vd (P11) = Vin. Since 0 = Vin = Vd (P11) <Vg (P11) + | Vtp |, the transistor P11 is in the OFF state. Therefore, as shown in FIG. 2B, the voltage Vd at the connection point D is held at Vd = Vdd / 2.

  Next, operations of the second N-channel transistor N12, the third N-channel transistor N13, the second P-channel transistor P12, and the third P-channel transistor P13 will be described.

  At time T1, as shown in FIG. 2B, when the voltage Va at the connection point A is at the low level (Va = 0), the voltage Vd at the connection point D is also at the low level (Vd = Vdd / 2). Therefore, the transistor N12 is in an OFF state since Vg (N12) −Vs (N12) <Vtn from Vg (N12) = 0 and Vs (N12) = 0, and the transistor P12 is in the OFF state. From Vdd / 2, Vs (P12) = Vdd, Vs (P12) −Vg (P12)> | Vtp | Therefore, as shown in FIG. 2C, the connection point C is pulled up to Vc = Vdd.

  At this time, since the transistor P13 is Vg (P13) = Vref2 = Vdd / 2− | Vtp | and Vs (P13) = Vc = Vdd, Vs (P13) −Vg (P13)> | Vtp | It becomes. Therefore, as shown in FIG. 2A, the output signal Vout is also pulled up to Vout = Vdd. Further, since Vg (N13) = Vref1 = Vdd / 2 + Vtn and Vd (N13) = Vout = Vdd, Vg (N13) −Vd (N13) <Vtn, the transistor N13 is turned off. Therefore, as shown in FIG. 2C, the voltage Vb at the connection point B is Vdd / 2 at the time before the time T1, and thus is held at Vb = Vdd / 2.

  At time T2, as shown in FIG. 2B, when the voltage Va at the connection point A changes from Low to High level (Va: 0 to Vdd / 2), the voltage Vd at the connection point D also changes from Low to High level. (Vd: Vdd / 2 → Vdd) also changes. Here, the transistor N12 is in the OFF state while Vg (N12) <Vs (N12) + Vtn = Vtn. The transistor N13 is also in an OFF state because Vd (N13) −Vg (N13) <Vtn from Vg (N13) = Vdd / 2 + Vtn and Vd (N13) = Vout = Vdd. As shown in FIG. 2B, when the voltage Va at the connection point A increases and Vg (N12)> Vs (N12) + Vtn = Vtn, the transistor N12 is turned on. Therefore, as shown in FIG. 2C, the connection point B is pulled down to a value in the range of 0 <Vb <Vdd / 2, and decreases to Vb: Vdd / 2 → 0. Along with this, the transistor N13 also starts to operate, and the output signal Vout starts to drop below Vdd as shown in FIG.

  The transistor P12 is ON while Vg (P12) <Vs (P12) − | Vtp | = Vdd− | Vtp |, but the transistor P13 is also Vg (P13) = Vref2 = Vdd / 2− || Vtp |, Vd During (P13) = Vout> Vdd / 2, Vd (P13) −Vg (P13)> | Vtp | is in the ON state. Therefore, since the transistors N12 and N13 are also in the ON state, the voltage Vc at the connection point C starts to decrease as shown in FIG. 2C, and becomes a value in the range of Vdd / 2 <Vc <Vdd, and Vc: Vdd → It decreases to Vdd / 2.

  When Vg (N12)> Vs (N12) − | Vtp | = Vdd− | Vtp |, the transistor P12 is turned off, so that the power supply voltage Vdd is supplied to the connection point C as shown in FIG. It will not be done. In addition, when Vd (P13) = Vout <Vdd / 2, the transistor P13 becomes Vd (P13) −Vg (P13) <| Vtp | from Vg (P13) = Vref2 = Vdd / 2− || Vtp | Therefore, as shown in FIG. 2C, the voltage Vc at the connection point C is held at Vc = Vdd / 2. When the transistors P12 and P13 are turned off and the transistors N12 and N13 are turned on, as shown in FIGS. 2A and 2C, the output voltage Vout and the voltage Vb at the connection point B are reduced. Pulled down to ground potential.

  At time T3, as shown in FIG. 2B, when the voltage Va at the connection point A is at a high level (Va1 = Vdd / 2), the voltage Vd at the connection point D is also at a high level (Vd = Vdd). Therefore, since the transistor N12 is Vg (N12) = Vdd / 2 + Vtn and Vs (N12) = 0, and Vg (N12) −Vs (N12)> Vtn, the transistor P12 is in the ON state, and the transistor P12 is Vg (P12) = Since Vdd, Vs (P12) = Vdd, Vs (P12) −Vg (P12) <| Vtp |. Therefore, as shown in FIG. 2C, the connection point B is pulled down to Vb = 0.

  At this time, the transistor N13 is in the ON state because Vg (N13) = Vdd / 2 + Vtn and Vs (N13) = Vb1 = 0, so that Vg (N13) −Vs (N13)> Vtn. Therefore, as shown in FIG. 2A, the output signal Vout is also pulled down to Vout = Vs = 0. The transistor P13 is turned off because Vs (P13) −Vg (P13) = | Vtp | from Vg (P13) = Vdd / 2− | Vtp | and Vs (P13) = Vdd / 2.

  At time T4, as shown in FIG. 2B, when the voltage Va at the connection point A changes from High to Low level (Va: Vdd / 2 → 0), the voltage Vd at the connection point D also changes from High to Low level. (Vd: Vdd → Vdd / 2). Here, during Vg (P12)> Vs (P12) − | Vtp | = Vdd− | Vtp |, the transistor P12 is in the OFF state, and the transistor P13 also has Vg (P13) = Vref2 = Vdd / 2− || Vtp | Since Vd (P13) = Vout = 0, Vd (P13) −Vg (P13) <| Vtp | Therefore, as shown in FIG. 2C, the voltage Vc at the connection point C is also held at Vc = Vdd / 2.

  As shown in FIG. 2B, when the voltage Vd at the connection point D decreases and Vg (P12) <Vs (P12) − | Vtp | = Vdd− | Vtp |, the transistor P12 is turned on. Become. Therefore, as shown in FIG. 2C, the connection point C is pulled up to a value in the range of Vdd / 2 <Vc <Vdd, and increases from Vc: Vdd / 2 → Vdd. Along with this, the transistor P13 also starts to operate, and the output signal Vout starts to increase from the ground potential as shown in FIG.

  The transistor N12 is ON while Vg (N12)> Vs (N12) + Vtn = Vtn, but the transistor N13 also has Vg (N13) = Vref2 = Vdd / 2 + Vtn and Vd (N13) = Vout <Vdd / 2. In the meantime, Vg (N13) −Vd (N13)> Vtn, and the state is ON. Therefore, since the transistors P12 and P13 are also in the ON state, as shown in FIG. 2C, the voltage Vb at the connection point B starts to increase and becomes a value in the range of 0 <Vb <Vdd / 2, and Vb: 0 → Increases to Vdd / 2.

  When Vg (N12)> Vs (N12) + Vtn = Vtn, the transistor N12 is turned off, so that the connection point B becomes non-conductive with the ground potential as shown in FIG. In addition, when Vd (N13) = Vout> Vdd / 2, the transistor N13 is in an OFF state with Vg (N13) −Vd (N13) <Vtn from Vg (N13) = Vref1 = Vdd / 2 + Vtn. As shown in FIG. 2C, the voltage Vb at the connection point B is maintained at Vb = Vdd / 2.

  At time T5, as shown in FIG. 2B, when the voltage Va at the connection point A is at the low level (Va = 0), the voltage Vd at the connection point D is also at the low level (Vd = Vdd / 2). Therefore, the transistor N12 is in the OFF state because Vg (N12) −Vs (N12) <Vtn from Vg (N12) = 0 and Vs (N12) = 0, so that the transistor P12 has Vg (P12) = From Vdd / 2, Vs (P12) = Vdd, Vs (P12) −Vg (P12)> | Vtp | is in the ON state. Therefore, as shown in FIG. 2C, the connection point C is pulled up to Vc = Vdd.

  At this time, the transistor P13 is in an ON state because Vs (P13) −Vg (P13)> | Vtp | from Vg (P13) = Vref2 = Vdd / 2− | Vtp | and Vs (P13) = Vc = Vdd. It becomes. Therefore, as shown in FIG. 2A, the output signal Vout is also pulled up to Vout = Vdd. The transistor N13 is in an OFF state because Vg (N13) −Vd (N13) <Vtn from Vg (N13) = Vref1 = Vdd / 2 + Vtn and Vd (N13) = Vout = Vdd. Therefore, as shown in FIG. 2B, the voltage Vb at the connection point B is held at Vb = Vdd / 2.

  As described above, in the output circuit of the first embodiment, the voltages Va to Vd at the connection points A to D are 0 <Va <Vdd / 2, 0 <Vb <Vdd / 2, Vdd / 2 <Vc <Vdd, A signal of Vdd / 2 having a value in the range of Vdd / 2 <Vd <Vdd and having an amplitude half the power supply voltage is output.

  Further, between the sources / drains of the transistors N11 to N13 and P11 to P13, as shown in FIGS. 2 (d) and 2 (e), the transistors N11 to N13 are at the rise and fall of the input signal Vin. When P11 to P13 are switched, a large voltage is instantaneously applied, but only Vdd / 2, which is half the power supply voltage, is applied between the source and drain in the stable state. Therefore, if the source / drain withstand voltages of the transistors N11 to N13 and P11 to P13 are about Vdd / 2, which is half the power supply voltage, the transistor can be operated normally without being damaged by the high voltage. Is possible.

  Next, the reason why all the substrate terminals of the N-channel transistors N11 to N13 and the P-channel transistors P11 to P13 are connected to the source terminals in the first embodiment will be described.

  In an integrated circuit, since a plurality of transistors are operated on the same substrate, a potential difference Vbs is generated between the substrate and the source depending on the transistor, and it is necessary to consider the influence. For example, when the substrate terminal of the N-channel transistor is connected to the ground potential and the substrate terminal of the P-channel transistor is connected to the power supply voltage, if the substrate / source voltage Vbs is a negative value and the absolute value increases, the channel / substrate connection Therefore, it is necessary to apply an extra gate voltage to allow the drain current to flow as much as the fixed charge of the depletion layer is charged. Therefore, if the threshold voltage when the substrate / source voltage Vbs is 0 is Vth0, the threshold voltage Vth is expressed by the following equation.

上記式において、γはしきい値電圧バイアス依存係数（Bulk threshold parameter）、φは表面ポテンシャル（Surface potential）である。また、Ｎｓｕｂは基板不純物濃度、Ｎｉは真性不純物濃度、εｓｉはＳｉの誘電率、εｏｘは酸化膜の誘電率、Ｔｏｘは酸化膜厚である。

In the above equation, γ is a threshold voltage bias dependency coefficient (Bulk threshold parameter), and φ is a surface potential. Nsub is the substrate impurity concentration, Ni is the intrinsic impurity concentration, εsi is the dielectric constant of Si, εox is the dielectric constant of the oxide film, and Tox is the oxide film thickness.

  In the output circuit of the first embodiment, when the substrate terminal of the N-channel transistor N12 is connected to the ground potential and the substrate terminal of the P-channel transistor P12 is connected to the power supply voltage, the N-channel transistor N12 and the P-channel transistor P12 Since all the substrate terminals are connected to the source terminal, there is no voltage difference between the substrate and the source. However, when the substrate terminals of the N-channel transistors N11 and N13 are connected to the ground potential and the P-channel transistors P11 and P13 are connected to the power supply voltage, the absolute value increases when the substrate-source voltage Vbs is negative. Therefore, the threshold voltage Vth increases.

  Therefore, when the substrate terminals of the N-channel transistors N11 to N13 constituting the output circuit of the present invention are connected to the ground potential and the substrate terminals of the P-channel transistors P11 to P13 are connected to the power supply voltage, the first intermediate If the voltage Vref1 and the second intermediate voltage Vref2 are set without considering the influence of the substrate / source voltage Vbs, the amplitude of the signal output to the connection points A to D decreases, and the transistors N11, N13, The voltage applied between the source / drain of P11 and P13 increases by the threshold voltage due to the influence of the substrate / source voltage Vbs. Further, when the first intermediate voltage Vref1 and the second intermediate voltage Vref2 are set in consideration of the influence of the substrate / source voltage Vbs, the gate / drain voltages of the transistors N11, N13, P11 and P13 and The gate / source voltage will increase. Therefore, as in the first embodiment, it is desirable that the substrate terminals of the N-channel transistors N11 to N13 and the P-channel transistors P11 to P13 are all connected to the source terminals so that Vbs = 0.

  As described above, according to the output circuit of the first embodiment, the first intermediate voltage Vref1 applied to the gate terminals of the N-channel transistors N11 and N13 is more than the threshold voltage Vtn than half of the power supply voltage Vdd. Is set to Vref1 = Vdd / 2 + Vtn, which is a higher voltage, and the second intermediate voltage Vref2 applied to the gate terminals of the P-channel transistors P11 and P13 is lower than the half of the power supply voltage Vdd by the threshold voltage Vtp. By setting Vref2 = Vdd / 2− | Vtp |, the voltage applied to the terminals of the transistors constituting the output circuit can be suppressed to about Vdd / 2, which is half the power supply voltage. Therefore, only Vdd / 2, which is half the power supply voltage, is applied between the sources / drains of the transistors N11 to N13 and P11 to P13, so that the low withstand voltage transistor whose breakdown voltage between the source and drain is about half of the power supply voltage. Can be used to configure an output circuit. As a result, it is not necessary to use a high-breakdown-voltage transistor in the output circuit, and the cost increase due to an increase in manufacturing steps can be reduced.

(Embodiment 2)
The output circuit of the second embodiment is substantially the same as the output circuit of the first embodiment shown in FIG. 1, except that the output circuit is manufactured on a substrate having an insulating surface as a transistor constituting the output circuit. The transistor (SOI (Silicon On Insulator) structure) is used.

  As a method of manufacturing a transistor on a substrate having an insulating surface, for example, a method of manufacturing a transistor on an SOI substrate in which a buried oxide film layer is formed by implanting oxygen ions into a Si substrate, an oxide film is formed on the surface. A method of manufacturing a transistor on an SOI substrate formed by bonding a formed Si substrate and another Si substrate to form a thin film, and forming an Si film on an insulating substrate such as glass by a CVD apparatus or the like And a method for manufacturing a transistor by (deposition).

In this manner, a method for producing an SOI substrate that is thinned by bonding another Si substrate having an oxide film formed on the surface thereof to another Si substrate will be further described. In the case of this manufacturing method, two Si substrates are required, and one has an oxide film (SiO ₂ ) formed on the surface (the method for forming the oxide film is thermal oxidation, CVD, etc.). Thus, the Si substrate having the oxide film (SiO ₂ ) formed on the surface and another Si substrate are bonded together from above the oxide film. An SOI substrate is manufactured by thinning the silicon layer on one side (front surface) of the bonded Si substrate (the method of thinning is polishing or the like). A transistor is formed on the thinned silicon layer.

  In a LSI, examples of load capacitance that a transistor should charge and discharge for signal propagation include drain junction capacitance, gate capacitance, and wiring capacitance. Among these, the drain junction capacitance is reduced by about one digit by using the SOI structure as compared with the case of using a normal bulk Si substrate.

  As shown in FIG. 3, the drain junction capacitance CJ of the SOI transistor is composed of a drain / body capacitance CJL and a drain / substrate capacitance CJV. The thickness of the body region is usually 0.1 μm or less in a CMOS SOI substrate, the junction area between the drain and the body is extremely small, and the junction capacitance CJL is also small.

  The junction capacitance CJV is constituted by a series connection of a buried oxide film capacitance CJVB made of a Si oxide film having a dielectric constant as small as 1/3 of Si and a depletion layer capacitance CJVD extending under the buried oxide film. ing. For example, in an N-channel transistor manufactured on an SOI substrate using a P-type substrate, since the drain layer is n + type, even when the drain voltage is 0 V, the Fermi level difference between the drain layer and the substrate Therefore, a depletion layer is formed under the buried layer. During the operation of the circuit, the potential of the drain layer varies from 0 V to the power supply voltage, but a depletion layer is formed under the buried oxide film at any potential.

  In the capacitance-voltage characteristics between the gate and the substrate when the drain layer is measured as the gate electrode and the buried oxide film as the gate oxide film, when a negative gate voltage is applied, a storage layer is formed under the buried oxide film. The buried oxide film capacitance CJVB is observed. When a gate voltage of 0 V or higher is applied, a depletion layer is formed under the buried oxide film, and the buried oxide film capacitance CJVB and the depletion layer capacitance CJVD are connected in series. The capacity will decrease rapidly.

  In the bulk Si substrate, the drain junction capacitance CJ of the transistor is constituted by a drain / body capacitance CJL and a drain / substrate capacitance CJV. In the SOI structure, as can be seen from the capacitance-voltage characteristics, the change in the depletion layer capacitance value due to the voltage change is very small with respect to the positive voltage, and CJ hardly depends on the drain voltage. On the other hand, when a bulk Si substrate is used, the drain voltage VD decreases, so that the depletion layer width of the drain n + -p junction decreases in proportion to (Vbi + VD) 1/2. CJ will increase. Here, Vbi is a built-in voltage.

  Although the drain junction capacitance of the N-channel transistor has been described above, consider the case of a P-channel transistor. In a P-channel transistor manufactured on an SOI substrate using a P-type substrate, since the drain layer is p + type, when the drain voltage is 0 V, the substrate side is almost in a flat band state and is depleted under the buried oxide film. No layer will be formed. However, when a slight positive voltage is applied to the drain layer, the depletion layer starts to grow. The drain layer of the P-channel transistor during circuit operation changes from 0 V to a positive power supply voltage, and on average, a depletion layer is formed under the buried oxide film. Therefore, the effect is slightly smaller than that of the N-channel transistor, but it is considered that the drain-channel capacitance reduction effect is similar in the case of the P-channel transistor.

  Although the N-channel transistor and the P-channel transistor manufactured on the SOI substrate using the P-type substrate have been described above, the N-channel transistor and the P-channel transistor manufactured on the SOI substrate using the N-type substrate have been described. Since the same applies to the type transistor, the description thereof is omitted here.

  As described above, according to the present invention, by using a transistor manufactured on a substrate having an insulating surface, the drain junction capacitance is reduced by about an order of magnitude compared to the case of using a bulk Si substrate. . Therefore, the operation speed of the transistors constituting the output circuit is improved, and the delay time can be shortened. Accordingly, the time during which a voltage higher than the withstand voltage is applied between the source / drain can be shortened, so that deterioration of the transistor can be suppressed.

(Embodiment 3)
FIG. 4 is a circuit diagram showing the configuration of the output circuit of the third embodiment.

  The output circuit of the third embodiment is substantially the same as the output circuit of the first embodiment shown in FIG. 1, but a fully depleted type manufactured on a substrate having an insulating surface as a transistor constituting the output circuit. Therefore, the substrate terminal (body contact) is not provided.

  In the partially depleted transistor, there are three types of dynamic substrate floating effects, which are related to the impact ionization phenomenon, the case related to the redistribution of majority carriers due to on / off of the gate, and the case related to the charge pumping phenomenon. appear. Therefore, it is necessary to provide a body contact in order to fix the body potential. However, in a fully depleted transistor, such a phenomenon is not observed, so that it is not necessary to provide a body contact. The reason will be described in detail below.

  First, the dynamic substrate floating effect related to the impact ionization phenomenon will be described.

  A fully depleted transistor has a thinner body region than a partially depleted transistor. For example, a partially depleted transistor has a body region thickness of about 100 nm, and a fully depleted transistor has a body region thickness of about 50 nm. For this reason, in a partially depleted transistor, there is a neutral region that is not depleted at the bottom of the body region, but in a fully depleted transistor, the entire body region is both in the on state and in the off state. It is depleted. This difference causes a difference in potential distribution in the body region between the partially depleted transistor and the fully depleted transistor.

  In a fully depleted transistor, the entire body region has a potential gradient in the depth direction, and a gate electric field enters the buried oxide film. On the other hand, in the partially depleted transistor, the gate field effect stops in the body region, and a neutral region without a potential gradient exists at the bottom of the body region. Therefore, the potential difference between the surface and the bottom of the body region is larger in the partially depleted transistor than in the fully depleted transistor, and the potential barrier between the source / body for holes near the bottom of the body region is that of the partially depleted transistor. Is higher than a fully depleted transistor.

  Due to such a difference in potential barrier height with respect to holes, a difference occurs in the number of holes that can exist in the body region. These holes are generated by impact ionization. During the operation of the N-channel transistor, when the channel electrons pass through the high electric field region near the drain, the high energy electrons gaining energy from the electric field collide with Si valence electrons, and the impact ions cause the electrons and holes. appear. At this time, in the partially depleted transistor having a higher potential barrier than the fully depleted transistor, more holes are accumulated in the body region. Therefore, in the partially depleted transistor, the body potential when the gate is turned on is increased to a larger positive potential, and an increase in drain current is observed immediately after the gate signal is input. This phenomenon becomes more prominent as the signal period is shorter, and becomes more prominent as the drain voltage is larger.

  Next, the dynamic substrate floating effect related to the redistribution phenomenon of majority carriers due to on / off of the gate will be described. Here, an N-channel transistor will be described as an example.

  In the case of a partially depleted transistor, the channel depletion layer width increases when the gate changes from off to on, and holes (majority carriers) present in the extended region are eliminated and flow out to the source side. Subsequently, when the gate is turned off, the channel depletion layer width is reduced to a neutral region, so that necessary holes (majority carriers) are supplied as a reverse junction current from the source side. At this time, due to the balance between the hole outflow / supply capability at the source junction and the elimination / recursion amount of holes due to expansion and contraction of the channel depletion layer, the number of holes in the body region is excessive and insufficient, and the body potential changes. The hole outflow from the body region at the source junction is the forward current of the source junction, and the supply of holes to the body region is the reverse current of the source junction.

  Therefore, when a good source junction is formed, it takes more time to inject holes into the body region due to a reverse current. For this reason, when the gate is turned on / off at a high speed, holes in the body region are constantly insufficient. As a result, the body potential becomes negative, the threshold voltage increases, and the drain current decreases. Such an effect does not appear in a fully depleted transistor in which the entire body region is depleted.

  Finally, the dynamic substrate floating effect related to the charge pumping phenomenon will be described.

  The charge pumping phenomenon is that when the gate voltage is sharply turned off, most of the carriers in the inversion layer flow out to the drain or source side, but some of the carriers are left behind and injected into the body region. Alternatively, carriers trapped at the interface state existing at the interface between the gate oxide film and the body region are injected into the body region when the gate is turned off. As a result, for example, in the case of an N-channel transistor, the body region becomes a negative potential, the threshold voltage increases, and the drain current decreases.

  Since the transistors constituting the output circuit of the third embodiment are fully depleted transistors, the dynamic substrate floating effect as seen in partially depleted transistors is not observed. Therefore, it is not necessary to provide a body contact for suppressing the dynamic substrate floating effect, and it is possible to prevent an increase in the area occupied by the element, thereby relaxing the constraints on the layout design. become.

  By the way, in a fully depleted transistor, a parasitic bipolar effect in which the source, body and drain are used as the emitter, base and collector is likely to occur, so that the source / drain breakdown voltage VDS is small. However, in the output circuit of the third embodiment, the first intermediate potential Vref1 applied to the gate electrodes of the N-channel transistors N11 and N13 is a voltage higher than the half of the power supply voltage by the threshold voltage Vref1 = Vdd. At / 2 + Vtn, the second intermediate potential Vref2 applied to the gate electrodes of the P-channel transistors P11 and P13 is Vref2 = Vdd / 2− | Vtp |, which is a voltage lower than half the power supply voltage by the threshold voltage. Since it is set, only a signal having an amplitude half the power supply voltage is output from the source terminal of each transistor.

  On the other hand, when the intermediate potential applied to the gate electrodes of the N-channel transistors N11 and N13 and the P-channel transistors P11 and P13 is set to Vdd / 2, which is half the power supply voltage, the N-channel transistors Vdd / 2-Vtn, which is a voltage lower than the power supply voltage, is output to the source terminal of the transistor, and the source terminal of the P-channel transistor is a voltage higher than the power supply voltage by the threshold voltage. Vdd / 2 + | Vtp | is output.

  Therefore, according to the third embodiment, the voltage applied between the source and the drain can be reduced by the threshold voltage of the transistor. Therefore, even for a fully depleted transistor having a low withstand voltage between the source and drain. It is valid.

(Embodiment 4)
Since the output circuit of the fourth embodiment can be applied to any of the configurations of the first to third embodiments, the output circuit will be described with reference to the circuit diagram shown in FIG.

  In the fourth embodiment, regarding the channel width of the transistors constituting the output circuit of the present invention, the channel widths of the first N-channel transistor N11 and the first P-channel transistor P11 are the second N-channel transistors. The channel width of each of the transistor N12, the third N-channel transistor N13, the second P-channel transistor P12, and the third P-channel transistor P13 is set larger. The reason will be described below.

  First, the case where the channel widths of the transistors constituting the output circuit of the present invention are all set to the same size will be described.

  In FIG. 2B, the delay time of the rise time is long at the voltage Va at the connection point A, and the delay time of the fall time is long at the voltage Vd at the connection point D. The transistors N12, N13, P12 and P13 are connected in series between the power supply voltage Vdd and the ground potential GND, and one of the N-channel transistors N12 and N13 or the P-channel transistors P12 and P13 is Even if the transition is from the ON state to the OFF state, the delay time is not so long because the other transitions from the OFF state to the ON state.

  However, the transistors N11 and P11 function as transfer gates, and are charged and discharged independently, so that the delay time becomes long when transitioning from the ON state to the OFF state. Therefore, as shown in FIG. 2D, the time during which a voltage higher than Vdd / 2, which is half of the power supply voltage, is applied between the sources / drains of the transistors N11 and P11 becomes longer.

  FIGS. 5A to 5E show the first N-channel transistor N11 and the first P-channel transistor P11 in order to optimize the channel width of the transistors constituting the output circuit of the fourth embodiment. The channel width of the second N-channel transistor N12, the third N-channel transistor N13, the second P-channel transistor P12, and the third P-channel transistor P13 is ½ times the channel width ( It is an operation waveform diagram of the output circuit when changed to a dotted line), equal magnification (solid line), and double (double line).

  5A shows the waveform of the output signal Vout, and FIG. 5B shows the voltage Va at the connection point A between the transistors N11 and N12 and the voltage Vd at the connection point D between the transistors P11 and P12. (C) shows the voltage Vb at the connection point B between the transistors N12 and N13 and the voltage Vc at the connection point C between the transistors P12 and P13. FIG. 5D shows the voltage difference Vin−Va between the source and drain of the transistor N11 and the voltage difference Vd−Vout between the source and drain of the transistor P11. FIG. 5E shows the source / drain of the transistor N13. A voltage difference Vout−Vb between the source and the drain of the transistor P13 is shown.

  As shown in FIG. 5B, as the channel widths of the transistors N11 and P11 are increased to 1/2 to 2 times the channel widths of the transistors N12, N13, P12, and P13, the transistors Since the drive capability of N11 and P11 increases, the rise time of transistor N11 and the fall time of transistor P11 are shortened. As a result, as shown in FIG. 5D, the time during which a voltage of Vdd / 2 or higher, which is half the power supply voltage, is applied between the sources / drains of the transistors N11 and P11 is also shortened.

  As described above, for the transistors constituting the output circuit of the present invention, the transistors N11 and P11 are made larger by making the channel widths of the transistors N11 and P11 larger than the channel widths of the transistors N12, N13, P12 and P13. The time during which a voltage of Vdd / 2 or more, which is half of the power supply voltage, is applied to the source / drain of the transistor can be shortened, so that deterioration of the transistors N11 and P11 can be suppressed. .

(Embodiment 5)
FIG. 6 is a circuit diagram showing the configuration of the level shift circuit according to the fifth embodiment.

  In FIG. 6, this level shift circuit includes a first N-channel transistor N21 and a second N-channel transistor N22 connected in series between a power supply voltage Vdd and a ground potential GND, and a first P-channel transistor. It has a transistor P21 and a second P-channel transistor P22.

  Further, as described in the first embodiment, in order to prevent the threshold voltage Vth from fluctuating due to the substrate / source Vbs, the substrate terminals of the N-channel transistors N21 and N22 and the P-channel transistors P21 and P22 are Are all connected to the source terminals.

  The first input signal Vin1 is input to the gate terminal of the N-channel transistor N21, the drain terminal is connected to the source terminal of the N-channel transistor N22, and the source terminal is connected to the supply terminal of the ground potential GND.

  The second input signal Vin2 is input to the gate terminal of the P-channel transistor P21, the drain terminal is connected to the source terminal of the P-channel transistor P22, and the supply terminal of the power supply voltage Vdd is applied to the source terminal. .

  The first intermediate voltage Vref1 is applied to the gate terminal of the N-channel transistor N22.

  The second intermediate voltage Vref2 is applied to the gate terminal of the P-channel transistor P22, and the drain terminal is connected in common with the drain terminal of the N-channel transistor 22 and is connected to the output terminal Vout.

  The first input signal Vin1 is a Vdd / 2 signal whose Low level is the ground potential GND and whose High level is half of the power supply voltage. The second input signal Vin2 is a signal having a low level of Vdd / 2, which is half of the power supply voltage, and a high level of the power supply voltage Vdd.

  The first intermediate voltage Vref1 is a voltage obtained by adding the threshold voltage Vtn of the N-channel transistor to half the potential difference between the power supply voltage Vdd and the ground potential GND, and Vref1 = Vdd / 2 + Vtn. The second intermediate voltage Vref2 is a voltage obtained by subtracting the absolute value | Vtp | of the threshold voltage of the P-channel transistor from half the potential difference between the power supply voltage Vdd and the ground potential GND, and Vref2 = Vdd / 2. − | Vtp |. As an example, if Vdd = 10V, Vtn = 1V, and Vtp = −1V, then Vref1 = 10/2 + 1 = 6V and Vref2 = 10 / 2− | −1 | = 4V.

  Next, the operation of the level shift circuit according to the fifth embodiment will be described.

  Waveform diagrams when the level shift circuit shown in FIG. 6 is operated are substantially the same as those shown in FIGS. 2A, 2C, and 2E. Therefore, in the following, FIGS. The operations of the N channel transistors N21 and N22 and the P channel transistors P21 and P22 will be described with reference to c) and (e). In FIG. 2A, the high level of Vin is Vdd and the low level is 0. However, in the fifth embodiment, Vin1 varies between 0 and Vdd / 2, and Vin2 varies between Vdd / 2 and Vdd. .

  As shown in FIG. 2A, when the first input signal Vin1 is at the low level (Vin1 = 0) at time T1, the second input signal Vin2 is also at the low level (Vin2 = Vdd / 2). Here, since Vg (N21) = 0 and Vs (N21) = 0, Vg (N21) −Vs (N21) <Vtn, the transistor N21 is in the OFF state, and the transistor P21 is Vg (P21) = Vdd / 2. Since Vs (P21) -Vg (P21)> | Vtp | from Vs (P21) = Vdd, it is in the ON state. Therefore, as shown in FIG. 2C, the connection point C is pulled up to Vc = Vdd.

  At this time, since the transistor P22 is Vg (P22) = Vref2 = Vdd / 2− | Vtp | and Vs (P22) = Vc = Vdd, Vs (P22) −Vg (P22)> | Vtp | It becomes a state. Therefore, as shown in FIG. 2A, the output signal Vout is also pulled up to Vout = Vdd. Further, since Vg (N22) = Vref1 = Vdd / 2 + Vtn and Vd (N22) = Vout = Vdd, Vg (N22) −Vd (N22) <Vtn, the transistor N22 is turned off. Therefore, as shown in FIG. 2C, the voltage Vb at the connection point B is held at Vb = Vdd / 2.

  At time T2, as shown in FIG. 2A, when the first input signal Vin1 changes from Low → High level UVin1: 0 → Vdd / 2), the second input signal also changes from Low → High level (Vin2). : Vdd / 2 → Vdd). Here, the transistor N21 is in an OFF state while Vg (N21) <Vs (N21) + Vtn = Vtn, and the transistor N22 is also Vg (N22) = Vdd / 2 + Vtn, Vd (N22) = Vout = Vdd from Vd (N Since N22) −Vg (N22) <Vtn, the state is OFF.

  As shown in FIG. 2A, when the first input signal Vin1 increases and Vg (N21)> Vs (N21) + Vtn = Vtn, the transistor N21 is turned on. Therefore, as shown in FIG. 2C, the connection point B is pulled down to a value in the range of 0 <Vb <Vdd / 2, and decreases from Vb: Vdd / 2 → 0. Along with this, the transistor N22 also starts to operate, and the output signal Vout starts to drop below Vdd as shown in FIG. The transistor P21 is ON while Vg (P21) <Vs (P21) − | Vtp | = Vdd− | Vtp |, but the transistor P22 is also Vg (P22) = Vref2 = Vdd / 2− | Vtp | During Vd (P22) = Vout> Vdd / 2, Vd (P22) −Vg (P22)> | Vtp | is in the ON state. Therefore, since the transistors N21 and N22 are also in the ON state, as shown in FIG. 2C, the voltage Vc at the connection point C starts to decrease and becomes a value in the range of Vdd / 2 <Vc <Vdd, and Vc: Vdd → Decreases to Vdd / 2.

  When Vg (N21)> Vs (N21) − | Vtp | = Vdd− | Vtp |, the transistor P21 is in an OFF state. Therefore, as illustrated in FIG. It will not be supplied. Further, when Vd (P22) = Vout <Vdd / 2, the transistor P22 is in an OFF state from Vg (P22) = Vref2 = Vdd / 2− || Vtp | from Vd (P22) −Vg (P22) <| Vtp |. Therefore, as shown in FIG. 2C, the voltage Vc at the connection point C is held at Vc = Vdd / 2. When the transistors P21 and P22 are turned off and the transistors N21 and N22 are turned on, the output voltage Vout and the voltage Vb at the connection point B decrease as shown in FIGS. 2 (a) and 2 (c). Pulled down to ground potential.

  At time T3, as shown in FIG. 2A, when the first input signal Vin1 is at a high level (Vin1 = Vdd / 2), the second input signal Vin2 is also at a high level (Vin2 = Vdd). For this reason, the transistor N21 is in the ON state because Vg (N21) -Vs (N21)> Vtn from Vg (N21) = Vdd / 2 + Vtn and Vs (N21) = 0. The transistor P21 is in an OFF state because Vs (P21) −Vg (P21) <| Vtp | from Vg (P21) = Vdd and Vs (P21) = Vdd. Therefore, as shown in FIG. 2C, the connection point B is pulled down to Vb = 0.

  At this time, the transistor N22 is in an ON state because Vg (N22) = Vdd / 2 + Vtn and Vs (N22) = Vb = 0 from Vg (N22) −Vs (N22)> Vtn. Therefore, as shown in FIG. 2A, the output signal Vout is also pulled down, and Vout = Vs (N22) = 0. Further, since Vg (P22) = Vdd / 2− | Vtp | and Vs (P22) = Vdd / 2, Vs (P22) −Vg (P22) = | Vtp |

  At time T4, as shown in FIG. 2A, when the first input signal Vin1 changes from High → Low level (Vin1: Vdd / 2 → 0), the second input signal Vin2 is also High → Low level. (Vin2: Vdd → Vdd / 2). Here, the transistor P21 is in an OFF state between Vg (P21)> Vs (P21) − | Vtp | = Vdd− | Vtp |, and the transistor P22 also has Vg (P22) = Vref2 = Vdd / 2− || Since Vtp |, Vd (P22) = Vout = 0, Vd (P22) −Vg (P22) <| Vtp | Therefore, as shown in FIG. 2C, the voltage Vc at the connection point C is also held at Vc = Vdd / 2.

  As shown in FIG. 2A, when the second input signal Vin2 decreases and Vg (P21) <Vs (P21) − | Vtp | = Vdd− | Vtp |, the transistor P21 is turned on. Become. Therefore, as shown in FIG. 2C, the connection point C is pulled up to a value in the range of Vdd / 2 <Vc <Vdd, and increases from Vc: Vdd / 2 → Vdd. Along with this, the transistor P22 also starts to operate, and the output signal Vout starts to increase from the ground potential as shown in FIG.

  The transistor N21 is in an ON state while Vg (N21)> Vs (N21) + Vtn = Vtn, but the transistor N22 also has Vg (N22) = Vref2 = Vdd / 2 + Vtn and Vd (N22) = Vout <Vdd / 2. Since Vg (N22) −Vd (N22)> Vtn, the ON state is established. Therefore, since the transistors P21 and P22 are also in the ON state, as shown in FIG. 2C, the voltage Vb at the connection point B starts to increase and becomes a value in the range of 0 <Vb <Vdd / 2, and Vb: 0 → It increases to Vdd / 2. When Vg (N21)> Vs (N21) + Vtn = Vtn, the transistor N21 is turned off, so that the connection point B becomes non-conductive with the ground potential. Further, when Vd (N22) = Vout> Vdd / 2, the transistor N22 is turned off because Vg (N22) −Vd (N22) <Vtn from Vg (N22) = Vref1 = Vdd / 2 + Vtn. Therefore, as shown in FIG. 2C, the voltage Vb at the connection point B is held at Vb = Vdd / 2.

  At time T5, as shown in FIG. 2A, when the first input signal Vin1 is at the low level (Vin1 = 0), the second input signal Vin2 is also at the low level (Vin2 = Vdd / 2). For this reason, the transistor N21 is in an OFF state because Vg (N21) −Vs (N21) <Vtn from Vg (N21) = 0 and Vs (N21) = 0, and the transistor P21 is Vg (P21) = Vdd. / 2, Vs (P21) = Vdd, so Vs (P21) −Vg (P21)> | Vtp | Therefore, as shown in FIG. 2C, the connection point C is pulled up to Vc = Vdd.

  At this time, since the transistor P22 is Vg (P22) = Vref2 = Vdd / 2− | Vtp | and Vs (P22) = Vc = Vdd, Vs (P22) −Vg (P22)> | Vtp | It becomes. Therefore, as shown in FIG. 2A, the output signal Vout is also pulled up to satisfy Vout = Vdd. Further, since Vg (N22) = Vref1 = Vdd / 2 + Vtn and Vd (N22) = Vout = Vdd, Vg (N22) −Vd (N22) <Vtn, the transistor N22 is turned off. Therefore, as shown in FIG. 2C, the voltage Vb at the connection point B is held at Vb = Vdd / 2.

  As described above, in the level shift circuit according to the fifth embodiment, the voltages Vb and Vc at the connection points B and C are in the range of 0 <Vb <Vdd / 2, Vdd / 2 <Vc <Vdd, and the amplitude is A Vdd / 2 signal that is half the power supply voltage is output.

  Further, a large voltage is instantaneously applied between the sources / drains of the transistors N21, N22, P21 and P22 when the transistors N21, N22, P21 and P22 are switched at the rise and fall of the input signal Vin. However, in a stable state, only a voltage of Vdd / 2, which is half of the power supply voltage, is applied between the source and drain. Therefore, if the source / drain breakdown voltage of the transistors N21, N22, P21 and P22 is about Vdd / 2 which is half the power supply voltage, the level shift circuit operates normally without being damaged by the high voltage. It becomes possible.

  As described above, according to the level shift circuit of the fifth embodiment, the first intermediate voltage Vref1 applied to the gate terminal of the N-channel transistor N22 is equal to the threshold voltage Vtn than half the power supply voltage Vdd. The second intermediate voltage Vref2 applied to the gate terminal of the P-channel transistor P22 is lower than the half of the power supply voltage Vdd by the threshold voltage Vtp. By setting Vref2 = Vdd / 2− | Vtp |, the voltage applied to the terminals of the transistors constituting the level shift circuit can be suppressed to about Vdd / 2, which is half the power supply voltage. Therefore, since only Vdd / 2, which is half the power supply voltage, is applied between the sources / drains of the transistors N11, N12, P11 and P12, a low breakdown voltage transistor whose breakdown voltage between the source / drain is about half of the power supply voltage. Can be used to configure a level shift circuit. As a result, it is not necessary to use a high breakdown voltage transistor in the level shift circuit, and it is possible to reduce the cost increase due to an increase in the manufacturing process.

(Embodiment 6)
The level shift circuit according to the sixth embodiment is substantially the same as the level shift circuit according to the fifth embodiment shown in FIG. 6 except that the transistors constituting the level shift circuit are on a substrate having an insulating surface. The transistor (SOI structure) manufactured in (1) is used.

  As described in the second embodiment, in a LSI, a load capacitance that a transistor should charge and discharge for signal propagation includes a drain junction capacitance, a gate capacitance, and a wiring capacitance. Among these, the drain junction capacitance is reduced by about one digit by using the SOI structure as compared with the case of using a normal bulk Si substrate. Therefore, the operation speed of the transistors constituting the level shift circuit is improved, and the delay time can be shortened. Accordingly, the time during which a voltage higher than the withstand voltage is applied between the source / drain can be shortened, so that deterioration of the transistor can be suppressed.

(Embodiment 7)
FIG. 7 is a circuit diagram showing a configuration of the level shift circuit according to the seventh embodiment.

  The level shift circuit according to the seventh embodiment is substantially the same as the output circuit according to the fifth embodiment shown in FIG. 6, but is manufactured on a substrate having an insulating surface as a transistor constituting the level shift circuit according to the present invention. Since the fully depleted transistor is used, the substrate terminal (body contact) is not provided.

  As described in the third embodiment, since the transistors constituting the level shift circuit of the seventh embodiment are fully depleted transistors, the dynamic substrate floating effect as seen in the partially depleted transistors is not observed. I can't. Therefore, it is not necessary to provide a body contact for suppressing the dynamic substrate floating effect, and it is possible to prevent an increase in the area occupied by the element, so that restrictions on layout design are eased.

  By the way, in a fully depleted transistor, a parasitic bipolar effect in which the source, body and drain are used as the emitter, base and collector is likely to occur, so that the source / drain breakdown voltage VDS is small. However, in the level shift circuit according to the seventh embodiment, the first intermediate potential Vref1 applied to the gate electrode of the N-channel transistor N22 is Vref1 = Vdd / V, which is higher than the half of the power supply voltage by the threshold voltage. At 2 + Vtn, the second intermediate potential Vref2 applied to the gate electrode of the P-channel transistor P23 is set to Vref2 = Vdd / 2− | Vtp |, which is a voltage lower than the half of the power supply voltage by the threshold voltage. Therefore, only a signal having an amplitude half the power supply voltage is output from the source terminal of each transistor.

  On the other hand, when the intermediate potential applied to the gate electrodes of the N-channel transistor N23 and the P-channel transistor P23 is set to Vdd / 2, which is half the power supply voltage, the source terminal of the N-channel transistor Vdd / 2−Vtn, which is a voltage lower than the power supply voltage by the threshold voltage, is output, and Vdd / 2 + |, which is a voltage higher than the power supply voltage by the threshold voltage, is output to the source terminal of the P-channel transistor. Vtp | is output.

  Therefore, according to the seventh embodiment, since the voltage applied between the source and drain can be reduced by the threshold voltage of the transistor, it can be applied to a fully depleted transistor having a low source / drain breakdown voltage. It is valid.

  As described above, according to the first to seventh embodiments, the first intermediate voltage Vref1 applied to the gate terminals of the N-channel transistors N11 and N13 is the voltage Vref1 that is higher than the half of the power supply voltage Vdd by the threshold voltage Vtn. = Vdd / 2 + Vtn, and the second intermediate voltage Vref2 applied to the gate terminals of the P-channel transistors P11 and P13 is a voltage Vref2 = Vdd / 2− || Vtp lower than the half of the power supply voltage Vdd by the threshold voltage Vtp. By setting |, the amplitude of the signal output to the connection points A to D can be suppressed to Vdd / 2 or less, which is half of the power supply voltage. Therefore, even when the breakdown voltage between the source and drain of each transistor is about half of the power supply voltage, a signal with a high amplitude can be output without deterioration or destruction of the transistor.

  In the field of an output circuit constituted by transistors and a level shifter circuit, a high-amplitude signal can be output without using a high voltage transistor.

It is a circuit diagram which shows one structural example of the output circuit in Embodiment 1 of this invention. (A)-(e) is a wave form diagram for demonstrating operation | movement of the output circuit of FIG. It is a schematic diagram for demonstrating the drain junction capacity | capacitance of the transistor of the output circuit in Embodiment 2 of this invention. It is a circuit diagram which shows one structural example of the output circuit in Embodiment 3 of this invention. (A)-(e) is a wave form diagram for demonstrating operation | movement of the output circuit in Embodiment 4 of this invention. It is a circuit diagram which shows one structural example of the level shift circuit in Embodiment 5 of this invention. It is a circuit diagram which shows one structural example of the level shift circuit in Embodiment 6 of this invention. It is a circuit diagram which shows one structural example of the conventional output circuit. (A)-(e) is a wave form diagram for demonstrating operation | movement of the conventional output circuit.

Explanation of symbols

N11 to N13, N21, N22 N channel type transistors P11 to P13, P21, P22 P channel type transistors

Claims (7)

In an output circuit that receives an input signal having the same magnitude as the power supply voltage and outputs an output signal having the same magnitude as the power supply voltage in response to the input signal,
Is input the input signal to the other driving terminal, a first one conductivity type transistor in which the first intermediate potential is applied to the control terminal,
A second one-conductivity-type transistor having a control terminal connected to one drive terminal of the first one-conductivity-type transistor and one drive terminal connected to a ground potential supply terminal;
On the other hand drive terminal connected to the other driving terminal of the one conductivity type the second transistor, and a third one conductivity type transistor to which the first intermediate potential to the control terminal is applied,
Is input the input signal to the other driving terminal, the first other conductivity type transistor in which the second intermediate potential is applied to the control terminal,
A second other conductivity type transistor having a control terminal connected to one drive terminal of the first other conductivity type transistor and one drive terminal connected to a power supply voltage supply terminal;
On the other hand drive terminal connected to the other driving terminal of the other conductivity type transistor of the second control terminal and the second intermediate potential is applied to, in the other driving terminal other driving terminal of the third one conductivity type transistor A third other conductivity type transistor connected in common and serving as an output terminal,
Each of the first to third one-conductivity type transistors and each of the first to third other-conductivity type transistors is a partially depleted thin film transistor fabricated on a substrate having an insulating surface. A low breakdown voltage transistor whose breakdown voltage between the drive terminal and the other drive terminal is half of the power supply voltage;
The first intermediate potential is set to a threshold voltage higher by a voltage of the one conductivity type transistor than half of the power supply voltage, said second intermediate potential and the other conductivity type transistor than half of the supply voltage of which is set in absolute value of only low voltage of the threshold voltage,
One drive terminal and substrate terminal of each of the first to third one conductivity type transistors are connected, and one drive terminal and substrate terminal of each of the first to third other conductivity type transistors are connected. It is, output circuit. In an output circuit that receives an input signal having the same magnitude as the power supply voltage and outputs an output signal having the same magnitude as the power supply voltage in response to the input signal,
Is input the input signal to the other driving terminal, a first one conductivity type transistor in which the first intermediate potential is applied to the control terminal,
A second one-conductivity-type transistor having a control terminal connected to one drive terminal of the first one-conductivity-type transistor and one drive terminal connected to a ground potential supply terminal;
On the other hand drive terminal connected to the other driving terminal of the one conductivity type the second transistor, and a third one conductivity type transistor to which the first intermediate potential to the control terminal is applied,
Is input the input signal to the other driving terminal, the first other conductivity type transistor in which the second intermediate potential is applied to the control terminal,
A second other conductivity type transistor having a control terminal connected to one drive terminal of the first other conductivity type transistor and one drive terminal connected to a power supply voltage supply terminal;
On the other hand drive terminal connected to the other driving terminal of the other conductivity type transistor of the second control terminal and the second intermediate potential is applied to, in the other driving terminal other driving terminal of the third one conductivity type transistor A third other conductivity type transistor connected in common and serving as an output terminal,
Each of the first to third one-conductivity type transistors and the first to third other-conductivity type transistors is a fully depleted thin film transistor fabricated on a substrate having an insulating surface, A low breakdown voltage transistor whose breakdown voltage between the drive terminal and the other drive terminal is half of the power supply voltage;
The first intermediate potential is set to a threshold voltage higher by a voltage of the one conductivity type transistor than half of the power supply voltage, said second intermediate potential and the other conductivity type transistor than half of the supply voltage absolute value of which is lower is set to the voltage, the output circuit of the threshold voltage of the. The output circuit according to claim 1 , wherein the input signal is a signal whose minimum level is a ground potential and whose maximum level is a power supply voltage. Each channel width of said first one conductivity type transistor and the first other conductivity type transistor is set larger than the channel width of at least the second one conductivity type transistor and the second of the other conductivity type transistor The output circuit according to claim 1 . A first input signal having a first amplitude and a second input having the same first amplitude as the first input signal, the minimum level of the signal being the same as the maximum level of the first input signal And a level shift circuit that outputs an output signal having a second amplitude that is twice the first amplitude in response to the first input signal and the second input signal. Because
Wherein the control terminal a first input signal is applied, whereas the first one conductivity type transistors that drive terminal is connected to the supply end of the ground potential,
On the other hand drive terminal connected to the other driving terminal of said first one conductivity type transistor, and the first second one conductivity type transistors intermediate potential is applied to the control terminal,
Wherein the control terminal and the second input signal is applied, whereas a first of the other conductivity type transistors that drive terminal is connected to the supply terminal of the power supply voltage,
On the other hand drive terminal connected to the other driving terminal of the first of the other conductivity type transistor, the control terminal and the second intermediate potential is applied to the common and the other driving terminal and the other driving terminal of the second one conductivity type transistor A second other conductivity type transistor connected to the output terminal and serving as an output terminal,
Each of the first and second one-conductivity type transistors and each of the first and second other-conductivity type transistors is a partially depleted thin film transistor fabricated on a substrate having an insulating surface. A low breakdown voltage transistor whose breakdown voltage between the drive terminal and the other drive terminal is half of the power supply voltage;
The first intermediate potential is set to a threshold voltage higher by a voltage of the one conductivity type transistor than half of the power supply voltage, said second intermediate potential the other conductivity type than half of the supply voltage It is set to a voltage that is lower by the absolute value of the threshold voltage of the transistor ,
One drive terminal and substrate terminal of each of the first and second one conductivity type transistors are connected, and one drive terminal and substrate terminal of each of the first and second other conductivity type transistors are connected. A level shift circuit. A first input signal having a first amplitude and a second input having the same first amplitude as the first input signal, the minimum level of the signal being the same as the maximum level of the first input signal And a level shift circuit that outputs an output signal having a second amplitude that is twice the first amplitude in response to the first input signal and the second input signal. Because
Wherein the control terminal a first input signal is applied, whereas the first one conductivity type transistors that drive terminal is connected to the supply end of the ground potential,
On the other hand drive terminal connected to the other driving terminal of said first one conductivity type transistor, and the first second one conductivity type transistors intermediate potential is applied to the control terminal,
Wherein the control terminal and the second input signal is applied, whereas a first of the other conductivity type transistors that drive terminal is connected to the supply terminal of the power supply voltage,
On the other hand drive terminal connected to the other driving terminal of the first of the other conductivity type transistor, the control terminal and the second intermediate potential is applied to the common and the other driving terminal and the other driving terminal of the second one conductivity type transistor A second other conductivity type transistor connected to the output terminal and serving as an output terminal,
Each of the first and second one-conductivity type transistors and each of the first and second other-conductivity type transistors is a fully depleted thin film transistor fabricated on a substrate having an insulating surface. A low breakdown voltage transistor whose breakdown voltage between the drive terminal and the other drive terminal is half of the power supply voltage;
The first intermediate potential is set to a threshold voltage higher by a voltage of the one conductivity type transistor than half of the power supply voltage, said second intermediate potential the other conductivity type than half of the supply voltage A level shift circuit that is set to a voltage that is lower by the absolute value of the threshold voltage of the transistor. The first input signal, the minimum level is half the signal of the maximum level of the power supply voltage to the ground potential, said second input signal, the maximum level of the power supply voltage minimum level at half the supply voltage The level shift circuit according to claim 5 or 6 , wherein

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