JP2010192625A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which enhances the stability of circuit operation and enables reduction in power consumption. <P>SOLUTION: The semiconductor device is provided with a frequency-dividing circuit which has floating body type PD-SOI-MOSFETs 21-26. At the operation of the frequency-dividing circuit, a fixed voltage is applied to each gate (G) of MOSFETs 22, 23, 24, and 26. The MOSFETs 22 and 24 turn on, and the MOSFETs 23 and 26 turn off. Moreover, an amplitude voltage is applied to each gate (G) of MOSFETs 21 and 25. The MOSFETs 21 and 25 turn ON and OFF repeatedly. In the frequency-dividing circuit which operates in this manner, the absolute values of the threshold voltages of the MOSFETs 23 and 26 are set to be larger than the absolute values of the threshold voltages of the MOSFETs 21 and 25, for example, by channel doping. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device.

  Conventionally, a MOSFET having an SOI structure (Silicon on Insulator) is known (see, for example, Patent Document 1). Here, the SOI structure is a structure in which a silicon thin film (SOI layer) is stacked on an insulating film, and a MOSFET having an SOI structure (hereinafter also referred to as SOI-MOSFET) is formed in this SOI layer. It is a MOSFET. The SOI-MOSFET has a feature that enables a reduction in junction capacitance and a reduction in operating voltage due to a low threshold voltage, and has attracted attention as a technique for realizing various circuits that require operation with low power consumption. . In such an SOI-MOSFET, a body region made of a silicon layer is formed in a region corresponding to the channel region of the bulk MOSFET. Depending on whether or not there is a neutral region where majority carriers exist in this body region, the characteristics of the SOI-MOSFET differ. Here, the case where the neutral region exists in the body region is called a partially depleted type (PD), and the case where the neutral region does not exist is called a fully depleted type (FD).

  A fully-depleted SOI-MOSFET (hereinafter also referred to as FD-SOI-MOSFET) has a smaller S value than a bulk type, and therefore, a threshold voltage is set low without increasing an off-leakage current. Suitable for low power consumption. On the other hand, since the thinning required for the SOI layer is severe and it is difficult to make the film thickness uniform, there is a demerit that the threshold voltage tends to vary. On the other hand, a partially depleted SOI-MOSFET (hereinafter also referred to as PD-SOI-MOSFET) has a manufacturing margin in the film thickness of the SOI layer, and can use the same process as the bulk type. There is a big advantage. Further, like the fully depleted type, the junction capacitance is low, so that high speed operation and low power consumption are possible.

Further, in the PD-SOI-MOSFET, the body region is electrically connected to the source region and the potential is fixed (so-called body tie type), and the body region is not electrically connected to other regions. There is a floating type (so-called floating body type). The body tie type has a carrier escape area, so that the depletion layer easily spreads, and its characteristics are close to those of the bulk type. On the other hand, since the floating body type has no escape space for carriers, the depletion layer is difficult to expand, and its characteristics are close to those of the complete depletion type. Further, since the number of element terminals is small and the occupation area is small, the PD-SOI-MOSFET can be reduced in size and cost.
In addition, it is known that a floating body type PD-SOI-MOSFET is applied to a digital circuit including a frequency divider (see, for example, Patent Documents 1 and 2). By adopting the floating body type, it is possible to realize the smallest MOSFET in terms of design rules, and ideally reduce the junction capacitance.

JP 2002-111005 A JP 2002-111006 A

  By the way, the floating body type PD-SOI-MOSFET has instability in its electrical characteristics due to the substrate floating effect of the SOI layer. That is, in the PD-SOI-MOSFET, the body tie type Id-Vg characteristic does not show hysteresis, but the floating body type Id-Vg shows hysteresis. Here, Id is a current (ie, drain current) flowing between the source region and the drain region, and Vg is a voltage applied to the gate electrode (ie, gate voltage). The Id-Vg characteristic is also called a current-voltage characteristic or a transfer characteristic. The hysteresis (that is, the history effect) is a property that the state of the MOSFET changes depending on not only the currently applied voltage but also the voltage applied in the past.

  FIGS. 13A and 13B are diagrams showing measurement results and measurement conditions when the transfer characteristics of the floating body type PD-SOI-MOSFET are measured. In FIG. 13A, the horizontal axis indicates the gate voltage (Vg), and the vertical axis indicates the drain current (Id). Here, as shown in FIG. 13B, the drain voltage Vd = 0.5 [V] is applied between the source region and the drain region, and the gate voltage Vg is applied to the gate electrode in this state. The value of the gate voltage Vg was gradually increased from −2 [V] to 2 [V], and then gradually decreased from 2 [V] to −2 [V]. The present invention is directed to a low voltage drive (<0.8 V) region where impact ionization does not occur.

  As shown in FIG. 13A, the transfer characteristic measured when the gate voltage Vg rises does not match the transfer characteristic measured when the gate voltage Vg falls. For example, in the vicinity of Vg = 0 to 0.5 [V], even when the gate voltage Vg is the same value, the drain current Id is larger when rising than when falling. As described above, the transfer characteristics of the floating body type change depending on the voltage application method (voltage increase / decrease and change speed thereof) and exhibit hysteresis.

  However, in the conventional semiconductor device, although the floating body type PD-SOI-MOSFET is applied to a frequency divider circuit or the like, the circuit design is made in consideration of the difference in the floating state of the substrate in each PD-SOI-MOSFET. It wasn't. In other words, floating body type PD-SOI-MOSFETs formed with the same pattern and under the same conditions are unstable in their electrical characteristics regardless of their position in the circuit (that is, voltage application state). The circuit design was based on the premise that they are the same.

  For example, in a quasi-static type T flip-flop that constitutes a frequency divider, a gate electrode is connected to a set (S) terminal or a reset (XR) terminal, and a floating body type that is turned off by applying a fixed potential during circuit operation A gate electrode is connected to a PD-SOI-MOSFET and an input terminal to which an alternating voltage or a pulse voltage (hereinafter also referred to as an amplitude voltage) is input, and repeats ON (On) / OFF (Off) during circuit operation. The floating body type PD-SOI-MOSFET was formed in the same pattern and under the same conditions.

Such a frequency dividing circuit is formed on an SOI substrate together with an oscillation circuit, a control circuit, etc. as a part of an integrated circuit, for example. During circuit operation, a voltage application state to each PD-SOI-MOSFET Are different. For this reason, the substrate floating state of each PD-SOI-MOSFET (that is, the state of the potential of the body region) becomes different after the circuit operation is started. That is, the electrical characteristics of the individual PD-SOI-MOSFETs show different changes after the circuit operation is started.
In the conventional semiconductor device, this point is not taken into consideration in the circuit design, so that the circuit operation margin of oscillation / frequency division changes during circuit operation, and problems such as frequency division missing of the frequency divider circuit occur. There was a possibility.

  On the other hand, as one method for reducing such instability of circuit operation, circuit design is performed assuming that the electrical characteristics of the PD-SOI-MOSFET have the most unfavorable values (that is, the worst case). A method is conceivable. For example, when the threshold voltage of the PD-SOI-MOSFET is found to increase by about 0.1 [V] at the maximum depending on the voltage application state, the threshold voltages of all the MOSFETs included in the frequency divider circuit are The circuit design is performed on the assumption that the value is about 0.1 [V] higher. That is, this is a method of providing a margin for the threshold voltages of all the PD-SOI-MOSFETs included in the frequency divider circuit.

However, when this method is used, in an extremely low voltage drive type circuit with an operating voltage of about 0.5 V, the on-state current value is increased only by a slight increase in the threshold absolute value (for example, about 0.1 [V]). In other words, the drain current value when the MOSFET is turned on is lowered by an order of magnitude or more, and the circuit may not operate normally.
Therefore, the present invention has been made in view of such problems, and the stability of circuit operation is improved by setting the threshold voltage of each transistor in consideration of the difference in the floating state of the substrate during circuit operation. An object of the present invention is to provide a semiconductor device that can increase power consumption and reduce power consumption.

In order to achieve the above object, a semiconductor device according to one embodiment of the present invention includes a circuit including a first transistor and a second transistor formed in a semiconductor layer on an insulating layer, respectively. A first gate electrode formed on the semiconductor layer via a gate insulating film, and a first source region or a first drain region formed in the semiconductor layer laterally below the first gate electrode. A first body region sandwiched between the first source region and the first drain region of the semiconductor layer is placed in an electrically floating state, and a threshold is applied to the first gate electrode. The first body region is partially depleted when a voltage is applied, and the second transistor includes a second gate electrode formed on the semiconductor layer via a gate insulating film, and the second gate electrode Side of A second source region or a second drain region formed in the lower semiconductor layer, and a second body region sandwiched between the second source region and the second drain region of the semiconductor layer is The second body region is partially depleted when it is placed in an electrically floating state and a threshold voltage is applied to the second gate electrode, and the absolute value of the threshold voltage of the first transistor Is set to be larger than the absolute value of the threshold voltage of the second transistor, and during operation of the circuit, a fixed voltage is applied to the first gate electrode to turn off the first transistor, and the second gate electrode An amplitude voltage is applied to the second transistor, and the second transistor is repeatedly turned on and off.

  Here, “the first (or second) body region is placed in an electrically floating state” means that the first (or second) transistor is a floating body type. To do. Further, “the first (or second) body region is partially depleted when a threshold voltage is applied to the first (or second) gate electrode” means that the first (or second). 2) This means that the transistor is partially depleted. That is, each of the first transistor and the second transistor is a PD-SOI-MOSFET.

  With such a configuration, in the second transistor that repeatedly turns on and off during circuit operation (hereinafter also referred to as circuit operation), the potential of the second body region oscillates stably within a certain range. The on-current value and the off-leakage current value are constant values while gradually decreasing. On the other hand, in the first transistor that is turned off during circuit operation (that is, normally turned off), since the potential of the first gate electrode is fixed, the potential of the first body region matches the potential of the first source region. Become.

At this time, the absolute value of the threshold voltage of the first transistor (hereinafter also referred to as | Vth1 |) and the absolute value of the threshold voltage of the second transistor (hereinafter also referred to as | Vth2 |) are set to the same magnitude. Therefore, | Vth1 | is apparently smaller (that is, relatively) than | Vth2 | due to a difference in potential of the body region, and the off-leakage current of the first transistor is larger than the off-leakage current of the second transistor. .
However, in the above configuration, | Vth1 | is set larger than | Vth2 |, so that the off-leak current of the first transistor can be suppressed. Thereby, the off-leakage current value of the first transistor can be suppressed. Considering the difference in potential between the first body region and the second body region during circuit operation, the threshold voltages of the first transistor and the second transistor can be optimized, thereby improving the stability of the circuit operation. However, the power consumption can be reduced.

  Note that the threshold voltage of the floating body type PD-SOI-MOSFET varies depending on the measurement method. For this reason, when comparing the magnitudes of threshold voltages, it is necessary to define the measurement method. That is, it is necessary to determine the measurement method for each n-channel type and p-channel type. For example, the threshold voltage of an n-channel MOSFET is a current-voltage (DC-I-V) characteristic by gradually reducing the applied voltage after applying a voltage higher than the use (drive) voltage between the gate and source. Can be determined by evaluating. For example, after holding the gate voltage Vg = 0.4 [V] for several to several tens of seconds, the gate voltage is decreased from 0.4 [V] to 0 [V], and the transfer characteristic measured at the time of the decrease. Based on the above, the threshold voltage of the n-channel MOSFET can be determined. At this time, the voltage between the source and the drain is set to a low voltage that does not cause impact ionization. In addition, the threshold voltage of the p-channel type MOSFET is set such that, after applying a voltage higher than the absolute value of the use (drive) voltage between the gate and the source, the absolute value of the applied voltage is gradually reduced to reduce the current-voltage (DC -IV) can be determined by evaluating the characteristics. For example, after holding the gate voltage Vg = −0.4 [V] for several to several tens of seconds, the gate voltage is increased from −0.4 [V] to 0 [V], and measured at the time of this increase. Based on the transfer characteristics, the threshold voltage of the p-channel MOSFET can be determined.

  In the above structure, the circuit further includes a third transistor formed in the semiconductor layer on the insulating layer, and the third transistor is formed on the semiconductor layer through a gate insulating film. A third source region of the semiconductor layer, and a third source region or a third drain region formed in the semiconductor layer laterally below the third gate electrode. And the third body region sandwiched between the third drain region and the third drain region are placed in an electrically floating state, and when the threshold voltage is applied to the third gate electrode, the third body region is The absolute value of the threshold voltage of the first transistor is set larger than the absolute value of the threshold voltage of the third transistor, and the fixed voltage is applied to the third gate electrode during operation of the circuit. Applied Wherein the third transistor is turned Te may be characterized.

Here, “the third body region is placed in an electrically floating state” means that the third transistor is a floating body type. Further, “the third body region is partially depleted when a threshold voltage is applied to the third gate electrode” means that the third transistor is a partially depleted type. That is, the third transistor is a PD-SOI-MOSFET.
With such a configuration, since the absolute value of the threshold voltage of the third transistor (hereinafter also referred to as | Vth3 |) is smaller than | Vth1 |, the on-current of the third transistor is smaller than that of the first transistor. The value can be increased.

In the above structure, the first body region, the second body region, and the third body region each contain impurities of the same conductivity type, and the concentration of the impurities in the first body region is the second body region. The concentration may be higher than the concentration of the impurity in the body region and higher than the concentration of the impurity in the third body region.
Here, “conductivity type” means n-type or p-type. For example, when each of the first transistor, the second transistor, and the third transistor is an n-channel type, the concentration of the p-type impurity (for example, boron) in the first body region is the concentration of the p-type impurity in the second body region. Higher than the concentration of the p-type impurity in the third body region. In the case where each of the first transistor, the second transistor, and the third transistor is a p-channel type, the concentration of the n-type impurity (for example, phosphorus or arsenic) in the first body region is the n-type impurity in the second body region. And a concentration higher than the concentration of the n-type impurity in the third body region.

With such a configuration, the absolute value of the threshold voltage of the first transistor can be set larger than the absolute value of the threshold voltage of the second transistor, and more than the absolute value of the threshold voltage of the third transistor. Can be set large.
In the above structure, the concentration of the impurity in the second body region may be the same as the concentration of the impurity in the third body region. With such a configuration, the absolute value of the threshold voltage of the second transistor can be set to the same magnitude as the absolute value of the threshold voltage of the third transistor.
In the above structure, the circuit is a circuit having at least one flip-flop, and a typical circuit includes a frequency divider. The first gate electrode of the first transistor is connected to a set or reset terminal of the flip-flop, and the second gate electrode of the second transistor is connected to an input terminal of the flip-flop. good.

With such a structure, off-leakage current flowing inside the flip-flop can be reduced, so that power consumption of the divider circuit can be reduced. For example, since the off-leakage current from the flip-flop set or reset terminal to the inside thereof can be reduced, power consumption during standby of the frequency divider can be reduced.
In the above structure, the transistors included in the flip-flop may be only the first transistor, the second transistor, and the third transistor. With such a structure, a frequency divider circuit with a small number of transistors and a small area occupied by the transistor can be realized, which contributes to cost reduction of the frequency divider circuit. In addition, the ON / OFF ratio of the driving current is large and the diffusion capacitance is small, which can contribute to speeding up and lowering of the frequency dividing circuit.
Such a semiconductor device is extremely suitable for application to portable electronic devices such as a watch (watch), a mobile phone, and a mobile personal computer that require a long-time operation with a small and light battery.

The figure which shows the structural example of the flip-flop 10 which concerns on embodiment, and its operation example. The figure which shows the structural example of the frequency divider circuit 100 which concerns on embodiment. The figure which showed the flip-flop 10 using the code | symbol of a logic circuit. The figure which shows the structural example of the clocked inverter 1, and its operation example. The figure which shows the structural example of the inverter. The figure which shows an example of the cross-sectional structure of the inverter. The figure which shows the state change of the body area | region 66 (the 1). The figure which shows the state change of the body area | region 66 (the 2). The figure which shows the transfer characteristic at the time of starting of MOSFET21. The figure which shows the transmission characteristic at the time of stability of MOSFET21. The figure which shows the measurement result when driving MOSFET21 on / off. The figure which shows the other structural example of the inverter. The figure which shows a subject.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and redundant description thereof is omitted.
<Configuration example of frequency divider>
FIGS. 1A and 1B are a circuit diagram showing a configuration example of a quasi-static T flip-flop 10 according to an embodiment of the present invention, and a timing chart showing an operation example thereof.

  As shown in FIGS. 1A and 1B, this quasi-static T flip-flop (hereinafter also simply referred to as flip-flop) 10 includes clocked inverters 1, 3, 4, 5 and inverters 2, 6. And have. The clocked inverters 1, 3, 4, and 5 are each provided with one or both of a C input terminal and an XC input terminal. Here, a signal input to the C input terminal (hereinafter also referred to as a C input signal) is a clock input signal, and is high (High: hereinafter, also simply referred to as h) and low (Low :) at regular intervals. Hereinafter, the signal is also simply referred to as L). A signal input to the XC input terminal (hereinafter, XC input signal) is a signal obtained by inverting H and L of the C input signal. The inverters 2 and 6 are each provided with a set terminal and a reset terminal (not shown).

  The connection relationship between the clocked inverters 1, 3, 4, 5 and the inverters 2, 6 will be described. As shown in FIG. 1A, the output terminal of the clocked inverter 1 It is connected to the output terminal of the clocked inverter 3. The output terminal of the inverter 2 and the input terminal of the clocked inverter 3 are connected to the input terminal of the clocked inverter 4. Further, the output terminal of the clocked inverter 4 is connected to the output terminal of the clocked inverter 5, the input terminal of the inverter 6, the input terminal of the clocked inverter 1, and the Q output terminal. The input terminal of the clocked inverter 5 and the output terminal of the inverter 6 are connected to the XQ output terminal.

Thus, in synchronization with the C input signal, the Q output signal is output from the Q output terminal, and the XQ output signal is output from the XQ output terminal. As shown in FIG. 1B, the Q output signal is a signal having a cycle twice that of the C input signal (that is, the frequency is ½), and the XQ output signal is the H and L of the Q output signal. Is a signal obtained by inverting.
FIG. 2 is a diagram illustrating a configuration example of the frequency dividing circuit 100 according to the embodiment of the present invention. As shown in FIG. 2, the frequency divider circuit 100 includes, for example, n flip-flops 10 shown in FIG. Here, n is 1 or an integer of 2 or more. In particular, when n is 2 or more, the frequency dividing circuit 100 has a configuration in which n flip-flops 10 are connected in series (that is, a configuration in which n flip-flops 10 are connected). The output terminal Q _{n−1 of the first} flip-flop 10 is connected to the input terminal C _n of the nth flip-flop 10, and the output terminal XQ _n−1 of the n−1th flip-flop 10 is nth Are connected to the output terminal XQ _n of the flip-flop 10.

Thus, in synchronism with the clock input signal, with Q _n output signals from the output terminals Q _n of the frequency divider circuit 100 is output, XQ _n output signal from the output terminal XQ _n is outputted. Here, the Q _n output signal is a signal having a period 2 ⁿ times (that is, the frequency is ½) compared to the C ₁ input signal (that is, the clock input signal), and the XQ _n output signal is the Qn output signal. This is a signal obtained by inverting H and L. Such a frequency dividing circuit 100 is formed on the same SOI substrate as other circuits (such as an oscillation circuit and a control circuit) as part of an integrated circuit, and is provided in a semiconductor device.
FIG. 3 is a diagram showing the flip-flop 10 shown in FIG. As shown in FIG. 3, each of the inverters 2 and 6 is composed of, for example, a combination of one AND circuit and one NOR circuit, and a reset (XR) terminal is connected to an input terminal of the AND circuit, and a NOR circuit A set (S) terminal is connected to the input terminal. Next, a configuration example of the clocked inverters 1, 3, 4, and 5 included in the flip-flop 10 will be described.

<Configuration example of clocked inverter>
4A and 4B are a circuit diagram showing a configuration example of the clocked inverter 1 and a timing chart showing an operation example thereof. As illustrated in FIG. 4A, the clocked inverter 1 includes n-channel MOSFETs 11 and 12 and p-channel MOSFETs 13 and 14. Among these, the MOSFETs 11 and 13 constitute an inverter body, the source (S) of the MOSFET 11 is connected to, for example, the ground potential (or the regulator potential Vreg), and the drain (D) of the MOSFET 13 is set to, for example, the power supply potential Vdd. It is connected. The gates (G) of the MOSFETs 11 and 13 are connected to the input terminal A of the clocked inverter 1. Further, the MOSFET 12 is connected between the MOSFET 11 and the output terminal B, and the MOSFET 14 is connected between the MOSFET 13 and the output terminal B. The gate of the MOSFET 12 is connected to the C input terminal, and the gate of the MOSFET 14 is connected to the XC input terminal.

  As shown in FIGS. 4A and 4B, in this clocked inverter 1, when the C input signal is H (that is, the XC input signal is L), both the MOSFETs 12 and 14 are turned on. As the name suggests, the inverter 1 functions as an inverter (ie, an element that outputs L when the input signal is H and outputs H when the input signal is L). On the other hand, when the C input signal is L (that is, the XC input signal is H), both the MOSFETs 12 and 14 are turned off, so that the drain of the MOSFET 11 and the output terminal B are electrically separated, and the MOSFET 13 The source and the output terminal B are electrically separated. Therefore, the potential of the output terminal B is maintained as it is. The other clocked inverters 3, 4, and 5 shown in FIG. 1 also have the same configuration as the clocked inverter 1 shown in FIGS. 4 (a) and 4 (b), for example. Next, a configuration example of the inverters 2 and 6 included in the flip-flop 10 will be described.

<Inverter configuration example>
FIG. 5 is a circuit diagram illustrating a configuration example of the inverter 2. As shown in FIG. 5, the inverter 2 includes n-channel MOSFETs 21 to 23 and p-channel MOSFETs 24 to 26. Among these, the MOSFETs 21 and 25 constitute an inverter body, the source (S) of the MOSFET 21 is connected to, for example, the ground potential (or Vreg), and the drain (D) of the MOSFET 25 is connected to, for example, the power supply potential Vdd. ing. The gates (G) of these MOSFETs 21 and 25 are connected to the input terminal A of the inverter 2. Further, the MOSFET 22 is connected between the MOSFET 21 and the output terminal B, and the MOSFET 24 is connected between the MOSFET 25 and the output terminal B. The gate of the MOSFET 22 is connected to the reset (XR) terminal, and the gate of the MOSFET 24 is connected to the set (S) terminal. Further, the MOSFET 23 is connected between the ground potential (or Vreg) and the output terminal B, and the MOSFET 26 is connected between the power supply potential Vdd and the MOSFET 24 (that is, connected in parallel with the MOSFET 25). . The gate of the MOSFET 23 is connected to the S input terminal, and the gate of the MOSFET 26 is connected to the XR input terminal.

  As shown in FIG. 5, in the inverter 2, when the signal input to the S input terminal is L and the signal input to the XR input terminal is H, the MOSFETs 22 and 24 are turned on and the MOSFETs 23 and 26 are turned on. Therefore, the inverter 2 functions as an inverter as the name suggests. On the other hand, when the signal input to the S input terminal is H and the signal input to the XR input terminal is L, the MOSFETs 22 and 24 are turned off and the MOSFETs 23 and 26 are turned on. Becomes the ground potential (or Vreg) without depending on H and L of the signal input to the input terminal A. Therefore, the initial setting of the B potential is possible.

  FIG. 6 is a diagram illustrating an example of a cross-sectional configuration of the n-type MOSFET group of the inverter 2. As shown in FIG. 2, the n-channel MOSFET 21 includes a support substrate 51, an insulating layer 52 formed on the support substrate 51, and a silicon thin film (SOI layer) 53 formed on the insulating layer 52. A gate electrode 63 formed on the SOI layer 53 via a gate insulating film 62, and an n-type formed on the SOI layer 53 below the side of the gate electrode 63. Source region 64 or drain region 65. In the n-channel MOSFET 21, the lower portion of the SOI layer 53 is covered with an insulating layer 52 in a cross-sectional view, and the side thereof is surrounded by an element isolation insulating film 54, and the elements are isolated from the surroundings. In addition, the body region 66 sandwiched between the source region 64 and the drain region 65 in the SOI layer 53 is not connected to other terminals or the like and is placed in an electrically floating state (that is, Floating body type). Further, the body region 66 is partially depleted when a threshold voltage is applied to the gate electrode 63 (ie, partially depleted). That is, the body region 66 is divided into a depletion layer 66a and a neutral region 66b. Thus, the n-channel type MOSFET 21 included in the inverter 2 is a floating body type PD-SOI-MOSFET.

  As shown in FIG. 6, the n-channel MOSFET 22 is also formed on the SOI substrate 50, and includes a gate electrode 73 formed on the SOI layer 53 via a gate insulating film 72, and a gate electrode 73. And an n-type source region 74 or drain region 75 formed in the SOI layer 53 on the lower side of the semiconductor layer. The n-channel type MOSFET 22 has a lower portion of the SOI layer 53 covered with an insulating layer 52 in a cross-sectional view, and a side thereof is surrounded by an element isolation insulating film 54, and the elements are isolated from the surroundings. The body region 76 is not connected to other terminals or the like and is placed in an electrically floating state (that is, a floating body type). Further, the body region 76 is partially depleted when a threshold voltage is applied to the gate electrode 73 (ie, partially depleted). That is, the body region 76 is divided into a depletion layer 76a and a neutral region 76b. Thus, the n-channel type MOSFET 22 included in the inverter 2 is also a floating body type PD-SOI-MOSFET.

  Further, as shown in FIG. 6, the n-channel MOSFET 23 is also formed on the SOI substrate 50, and includes a gate electrode 83 formed on the SOI layer 53 via a gate insulating film 82, and a gate electrode 83. And an n-type source region 84 or drain region 85 formed in the SOI layer 53 on the lower side of each. In the n-channel MOSFET 23, the lower part of the SOI layer 53 is covered with an insulating layer 52 in a cross-sectional view, and the side thereof is surrounded by an element isolation insulating film 54, and the elements are isolated from the surroundings. The body region 86 is not connected to other terminals or the like and is placed in an electrically floating state (that is, a floating body type). Further, the body region 86 is partially depleted when a threshold voltage is applied to the gate electrode 83 (ie, partially depleted). That is, the body region 86 is divided into a depletion layer 86a and a neutral region 86b. Thus, the n-channel type MOSFET 23 included in the inverter 2 is also a floating body type PD-SOI-MOSFET.

Here, in the embodiment of the present invention, the n-channel MOSFETs 21 to 23 are formed in the same pattern and under the same conditions except for channel doping. That is, the n-channel MOSFETs 21 to 23 are formed in the same structure, but the concentrations of p-type impurities (for example, boron) for adjusting the threshold voltage are different. . The concentration of the p-type impurity contained in the region where the channel of the MOSFET 21 is formed (that is, the region near the surface of the body region 66 and immediately below the gate electrode 63) is N _A1 , and the region where the channel of the MOSFET 22 is formed (that is, The concentration of the p-type impurity contained in the vicinity of the surface of the body region 76 and immediately below the gate electrode 73 is N _A2 , and the region where the channel of the MOSFET 23 is formed (that is, in the vicinity of the surface of the body region 86 and the gate electrode). when the concentration of the p-type impurity contained in the 83 region immediately below) was _{N A3,} respectively N A1 _{to N A3,} satisfy the relationship of _{N A1 <N A3, N A2} <N A3. N _A1 and N _A2 may be the same value (that is _, N _A1 = N _A2 ), or may be different values (that is, N _A1 ≠ N _A2 ).

Although not shown, the p-channel type MOSFETs 24 to 26 included in the inverter 2 are also floating body type PD-SOI-MOSFETs, each of which has the same pattern, and processes other than channel doping are performed under the same conditions. Is formed. That is, the p-channel MOSFETs 24 to 26 are also formed in the same structure. Further, the concentration of n-type impurities (for example, phosphorus or arsenic) for adjusting the threshold voltage is different. The concentration of n-type impurity contained in the region where the channel of MOSFET 24 is formed is N _D1 , the concentration of n-type impurity contained in the region where the channel of MOSFET 25 is formed is N _D2 , and the region where the channel of MOSFET 26 is formed. N _{D1 to} N _D3 satisfy the relationship of N _D1 <N _D3 and N _D2 <N _D3 , respectively, where the concentration of the n-type impurity to be obtained is N _D3 . Note that N _D1 and N _D2 may be the same value (that is _, N _D1 = N _D2 ), or may be different values (that is, N _D1 ≠ N _D2 ).
The other inverters 6 shown in FIG. 1 have the same configuration as that of the inverter 2 shown in FIG. 5 and FIG. 6, for example. In the frequency dividing circuit 100 shown in FIG. 2, for example, all MOSFETs are floating body type PD-SOI-MOSFETs.

<About PD-SOI-MOSFET>
By the way, in the floating body type PD-SOI-MOSFET, when the amplitude voltage is applied, the absolute value of the threshold voltage tends to be low for a few seconds at the initial stage of the start-up, and the absolute value of the threshold voltage tends to increase with the passage of time. There is. Such threshold voltage fluctuation is caused by a forward bias acting between the neutral region of the body region and the source region for a few seconds at the beginning of the start-up, and majority carriers in the source region move to the neutral region. This is because the majority of the carriers in the neutral region of the body are eliminated, so that the potential of the entire body region becomes unstable. This point will be described using, for example, an n-channel MOSFET 21 as an example.

  FIG. 7A to FIG. 8B are diagrams showing changes in the state of the body region 66. Among these, FIG. 7A is a conceptual diagram showing the spread of the depletion layer 66a and the neutral region 66b. Each figure (b) is the figure which showed along the depth direction the potential energy distribution in a cut surface when the body region 66 is cut | disconnected from the source end surface in the depth direction. In FIG. 7B and FIG. 8B, the horizontal axis indicates the potential energy, and the vertical axis indicates the depth from the surface of the body region 66. φ0 is the initial surface potential of the MOSFET 21 to which no voltage is applied. φf is a function of the Fermi level Ef of the body region, and q · Φf = Ef−Ei. Here, Ei is an intrinsic silicon Fermi level, and q is a charge amount of electrons. 2φf corresponds to a threshold voltage.

First, in FIG. 7A, a gate voltage Vg is applied to the gate electrode 63 and a drain voltage Vd is applied between the source region 64 and the drain region 65. Both the gate voltage Vg and the drain voltage Vd are DC voltages (that is, voltages whose directions do not change periodically). As an example, the drain voltage Vd = 0.4 [V] is applied between the source region 64 and the drain region 65, and the gate voltage Vg is changed from, for example, 0 [V] to 0.4 [V] in this state. Note that the drain voltage Vd corresponds to a difference between the power supply potential Vdd shown in FIG. 5 and the ground potential (or Vreg). A case where the threshold voltage is smaller than the gate applied voltage 0.4V will be described.
Then, as shown in FIG. 7A, the depletion layer 66a gradually expands downward in the body region 66, and the neutral region 66b becomes smaller by that amount (from the broken line region to the solid line region). This is shown in FIG. When Vg is increased from 0 V to 0.4 V, the depletion layer does not spread immediately, so that the potential energy (ie, potential) of the body region 66 also increases as a whole (process I).

  In this process I, the potential of the body region 66 b is higher than the potential of the source region 64. For this reason, in FIGS. 7A and 7B, a forward bias acts between the p-type body region 66b and the n-type source region 64, and the source region 64 changes to the neutral region 66b. Electron e flows in. As a result, the holes h and electrons e, which are majority carriers, are recombined in the neutral region 66b to reduce the hole h, and the neutral region 66b becomes smaller (that is, the depletion layer 66a expands). The potential at 66b gradually decreases (process II). The flow of electrons e into the neutral region 66b continues until the potential of the neutral region 66b becomes substantially the same as the potential of the source region 64. When the potential of the neutral region 66b and the potential of the source region 64 become approximately the same level, the forward bias does not work, so the flow of electrons e stops and the reduction of the neutral region 66b also stops. That is, the source region 64 and the body region (depletion layer 66a and neutral region 66b) are in an equilibrium state, and the potential (number of majority carriers) of the body region 66 is stabilized. While the n-channel MOSFET 21 is on (On) for a few seconds at the beginning of startup, the process I and the process II proceed in parallel.

  When the number of majority carriers in the neutral region 66b is stabilized, as shown in FIGS. 8A and 8B, the potential of the body region 66 shifts as a whole as the MOSFET 21 is turned on / off. (Process III, IV). In these processes III and IV, the potential of the neutral region 66b is lower than the potential of the source region 64, and a reverse bias acts between the body region 66 and the source region 64. The charge e is less likely to move between the conductive regions 66b. Therefore, the size of the neutral region 66b (that is, the number of majority carriers) hardly changes. While the depletion layer 66a and the neutral region 66b are maintained in an equilibrium state, the potential of the body region 66 repeatedly decreases and increases as the MOSFET 21 is turned on / off.

  FIG. 9 is a diagram showing the results of actual measurement of the transfer characteristics when the MOSFET 21 is activated. Here, the “transfer characteristic” can also be called a current-voltage characteristic, for example, an Id-Vg characteristic. Id is a current flowing between the source region 64 and the drain region 65 (ie, drain current), and Vg is a voltage applied to the gate electrode 63 (ie, gate voltage). In FIG. 9, the horizontal axis represents the gate voltage Vg, and the vertical axis represents the drain current Id. Here, the gate voltage Vg is gradually increased from 0 [V] to 0.4 [V] while maintaining the drain voltage Vd = 0.4 [V], and then from 0.4 [V] to 0 [V]. V] was gradually reduced.

As shown in FIG. 9, the transfer characteristic measured in the process of increasing the gate voltage Vg and the transfer characteristic measured in the process of decreasing the gate voltage Vg do not match. When the value of the drain current Id is compared between when Vg rises and when it falls, the rise time is greater than the fall time, and this difference ΔId is a hysteresis.
FIG. 10 is a diagram showing the results of actual measurement of the stable transfer characteristics of the MOSFET 21. In FIG. 10, the horizontal axis indicates the gate voltage Vg, and the vertical axis indicates the drain current Id. Here, after the gate voltage Vg = 0.4 V is applied for several seconds and the number of majority carriers in the neutral region is stabilized, the gate voltage is set to 0.4 [V while maintaining the drain voltage Vd = 0.4 [V]. ] To 0 [V] gradually. Thereafter, the gate voltage Vg is gradually increased from 0 [V] to 0.4 [V] while maintaining the drain voltage Vd = 0.4 [V] while the majority carrier number in the neutral region is stable. ing.

As shown in FIG. 10, the transfer characteristic measured in the process of increasing the gate voltage Vg and the transfer characteristic measured in the process of decreasing the gate voltage Vg are almost the same. That is, when the value of the drain current Id is compared between when Vg rises and when it falls, the rise time is almost equal to the fall time, and ΔId is hardly seen. That is, hysteresis is suppressed.
As can be seen by comparing FIG. 9 and FIG. 10, the value of the drain current Id is higher at the time of startup than at the time of stabilization. For example, when the drain current Id when the gate voltage Vg = 0.4 [V] is compared, the drain current Id at the time of startup is 1.0E-6 [A] or more, whereas The drain current Id has a value of 1.0E-6 [A] or less. From this, it can be seen that a larger drain current Id can be caused to flow at the same gate voltage Vg and a larger amount of power can be supplied at the time of startup than at the time of stabilization.

  FIGS. 11A and 11B are diagrams showing the results of actual measurement of on-current and off-leakage current when MOSFET 21 is continuously turned on / off. In FIG. 11A, the horizontal axis indicates time, and the vertical axis indicates on-current. In FIG. 11B, the horizontal axis represents time, and the vertical axis represents off-leakage current. Here, the gate electrode 63 and the drain region 65 are electrically connected (that is, short-circuited), and a voltage Vgs = 0.4 V is applied between the gate and the source at an interval of 500 msec.

  As shown in FIG. 11A, when the application of the voltage Vgs pulse is started, the on-current gradually decreases with the pulse, and after about 10 seconds, the value becomes stable. It was. Also, the hysteresis seen in the on-current almost disappeared after about 10 seconds. Similarly, as shown in FIG. 11B, when the application of the pulse of the voltage Vgs is started, the off-leakage current gradually decreases with the pulse, and the value becomes stable after about 10 seconds. It became a thing. That is, when about 10 seconds have elapsed after the on / off drive of the MOSFET 21 is started, the hysteresis disappears and the on / off ratio is close to the ideal characteristics of the FD-SOI-MOSFET.

  As described above, the n-channel PD-SOI-MOSFET 21 can flow a larger drain current (that is, an on-current and an off-current) Id at the same gate voltage Vg at the time of starting than when it is stable. Larger power can be supplied. At the same time, the leakage current increases. This is because the potential of the neutral region 66b is higher than the potential of the source region 64 at the time of startup, and the absolute value of the apparent threshold voltage is small. In the stable state, the potential of the neutral region 66b is smaller than the potential of the source region 64, and the apparent absolute value of the threshold voltage is increased. In addition, a reverse bias is applied between the source and the body, making it difficult for electrons e to flow from the source region 64 to the neutral region 66b, and the sizes of the neutral region 66b and the depletion layer region 66a hardly change. For this reason, the gate potential acts almost 100% on the potential barrier between the source and the channel without expanding the depletion layer, and exhibits a steep subthreshold current characteristic.

  Such characteristics can be seen not only in the n-channel type but also in the p-channel type PD-SOI-MOSFET. That is, the p-channel PD-SOI-MOSFET can flow a larger drain current (that is, an on-current, an off-current) Id at the same gate voltage Vg at the time of start-up than when it is stable, and is larger. Electric power can be supplied. At the same time, the leakage current increases. Although not shown, when the p-channel PD-SOI-MOSFET is started, the potential of the neutral region is lower than the potential of the source region, and the hole h flows from the source region to the neutral region by the forward bias. The neutral area becomes smaller. Further, at the stable time, the potential of the neutral region becomes larger than the potential of the source region, and holes h do not easily flow from the source region to the neutral region due to the reverse bias. Thereby, in the p-channel PD-SOI-MOSFET, the absolute value of the threshold voltage at the time of activation is lower than the absolute value of the threshold voltage at the time of stabilization.

  Note that in the PD-SOI-MOSFET, the absolute value of the gate voltage Vg, the absolute value of the drain voltage Vd, or the absolute value of the gate-source voltage Vgs is 0.8 [V] or less, more preferably 0. It is preferably set to 6 [V] or less. That is, in the MOSFETs 11 to 14 and 21 to 26, the absolute value of the drive voltage is preferably 0.8 [V] or less, more preferably 0.6 [V] or less. Thereby, in the body region, pair creation (ie, generation of electron-hole pairs) due to impact ionization can be suppressed, and the potential of each body region can be prevented from fluctuating in an unintended direction. Therefore, it is possible to contribute to stabilization of the characteristics of the frequency divider circuit. When the absolute value of the drive voltage exceeds 0.8 [V], pair creation tends to occur in the body region.

<Operation example of inverter>
Next, an operation example of the inverter 2 shown in FIG. 5 will be described.
For example, after an oscillation circuit (not shown) starts its oscillation operation, in the frequency dividing circuit 100 connected to the oscillation circuit, the potential of the set (S) terminal connected to the inverter 2 is fixed to L, and the reset (XR) terminal Is fixed at H. As a result, the n-channel PD-SOI-MOSFET 23 and the p-channel PD-SOI-MOSFET 26 shown in FIG. 5 are turned off, and the n-channel PD-SOI-MOSFET 22 and the p-channel PD- The SOI-MOSFET 24 is turned on. The n-channel PD-SOI-MOSFET 21 and the p-channel PD-SOI-MOSFET 25 constitute an inverter body, and these MOSFETs 21 and 25 are repeatedly turned on / off. At this time, the potentials (hereinafter also referred to as body potentials) of the body regions (neutral regions) of the MOSFETs 22, 23, 24, and 26 are stabilized at the potentials of the respective source regions (hereinafter also referred to as source potentials). (For example, see steps I and II in FIG. 7B). That is, the body potentials of the n-channel type MOSFETs 22 and 23 are fixed to L, and the body potentials of the p-channel type MOSFETs 24 and 26 are fixed to H and stabilized.

  On the other hand, the body potentials of the n-channel MOSFET 21 and the p-channel MOSFET 25 constituting the inverter oscillate with the amplitude of the input voltage (amplitude voltage) applied to the input terminal A, but the n-channel MOSFET 21. The body potential of the MOSFET 21 stably oscillates between the source potential (L) and a potential lower than the source potential by the threshold voltage, and the body potential of the p-channel MOSFET 25 is changed from the source potential (H) and the source potential to the threshold voltage. Oscillates stably with a potential higher by that amount (for example, see steps III and IV in FIG. 8B). That is, the body potential of the n-channel MOSFET 21 stably oscillates between fixed potential differences in a region lower than its source potential, and the body potential of the p-channel MOSFET 25 is fixed potential difference in a region higher than its source potential. It vibrates stably between.

  As described above, even in the same channel type MOSFET, the body potential of the MOSFET 21 oscillates and the body potentials of the MOSFETs 22 and 23 are fixed. Therefore, the MOSFET 21 and the MOSFETs 22 and 23 exhibit different electrical characteristics. Similarly, even in the p-channel type, the body potential of the MOSFET 25 oscillates and the body potentials of the MOSFETs 24 and 26 are fixed. Therefore, the MOSFET 25 and the MOSFETs 24 and 26 exhibit different electrical characteristics.

  For example, as shown in FIGS. 11A and 11B, in the n-channel MOSFET 21, when the gate electrode potential (hereinafter also referred to as the gate potential) swings and the on / off drive is started, the on-current is turned on. Although the value / off-leakage current value gradually decreases, after a few seconds, the on-current value / off-leakage current value become stable values, and stable transfer characteristics are exhibited. On the other hand, in the n-channel MOSFET 22, since the gate potential is fixed, the body potential is stabilized in a state where it matches the source potential. At this time, due to the difference in body potential, the threshold voltage of the MOSFET 22 is apparently smaller than the threshold voltage of the MOSFET 21, and the on-current value of the MOSFET 22 increases compared to the on-current value of the MOSFET 21. Similarly, in the p-channel type, the absolute value of the threshold voltage of the MOSFET 24 is apparently smaller than the absolute value of the threshold voltage of the MOSFET 25 due to the difference in body potential, and the on-current value of the MOSFET 24 is the same as the on-current value of the MOSFET 25. Compared to increase.

  Note that the threshold voltage of the floating body type PD-SOI-MOSFET varies depending on the measurement method. For this reason, when comparing the magnitudes of the threshold voltages, it is necessary to determine the measurement method for each channel. In the present embodiment, for example, the threshold voltage can be obtained by the following measurement method. That is, the threshold voltage of the n-channel MOSFETs 21 to 23 is, for example, a gate voltage of 0.4 [V] to 0 [V] after holding the gate voltage Vg = 0.4 [V] for several to tens of seconds. And can be determined based on the transmission characteristics measured during the descent. The threshold voltage of the p-channel MOSFETs 24 to 26 is, for example, the gate voltage Vg = −0.4 [V] is held for several to tens of seconds and the gate voltage is changed from −0.4 [V] to 0 [0]. V] and can be determined based on the transfer characteristics measured during this rise.

  Further, in the inverter 2 shown in FIG. 5, the threshold voltage of the n-channel MOSFET 21 functioning as an inverter and the p-channel type are within the allowable range of the standby current (ie, off-leakage current) of the inverter. The drive voltage can be lowered by setting the absolute value of the threshold voltage of the MOSFET 25 to be low. That is, both standby current and charge / discharge operation current can be reduced. Here, if the n-channel type MOSFETs 21 to 23 are formed with the same pattern and the same conditions, the body potential of the MOSFET 23 is fixed at a potential higher than the body potential of the MOSFET 21. This off-leakage current increases more than the off-leakage current of the MOSFET 21. For this reason, the standby current of the inverter increases. Further, if the p-channel MOSFETs 24 to 26 are formed with the same pattern and the same conditions, the body potential of the MOSFET 26 is fixed at a potential lower than the body potential of the MOSFET 25, and therefore the off-leak current of the MOSFET 26 Increases more than the off-leakage current of the MOSFET 25. For this reason, the standby current cannot be reduced.

  However, in the embodiment of the present invention, the impurity concentration in the body region of each of the n-channel type MOSFET 23 and the p-channel type MOSFET 26 is increased, and the absolute value of the threshold voltage is increased by, for example, about 0.05 to 0.1V. Yes. For this reason, the off-leakage current value of the MOSFETs 23 and 26 can be set to the same level as or lower than the off-leakage current value of the MOSFETs 21 and 25. As a result, a lower standby current can be realized as compared with a case where MOSFETs of the same channel type are formed in the same pattern and under the same conditions.

  In the embodiment of the present invention, the n-channel MOSFET 22 that is always turned on from the start of the operation of the inverter is created in the same pattern and under the same conditions as the n-channel MOSFET 21 (that is, under the same conditions). The body potential of the MOSFET 22 is fixed at a potential higher than the body potential of the MOSFET 21. Thereby, the on-current value of the MOSFET 22 is greatly increased as compared with the on-current value of the MOSFET 21. This means that the resistance of the MOSFET 22 which is a resistor from the viewpoint of the inverter function is reduced, so that the on / off delay time of the MOSFET 21 can be shortened.

  Similarly, the p-channel type MOSFET 24 that is always turned on from the start of the operation of the inverter is formed in the same pattern and under the same conditions as the p-channel type MOSFET 25, and the body potential of the MOSFET 24 is higher than the body potential of the MOSFET 25. Is also fixed at a low potential. As a result, the on-current value of the MOSFET 24 is greatly increased as compared with the on-current value of the MOSFET 25, so that the on / off delay time of the MOSFET 21 can be shortened. As a result, even if the drive voltages of the MOSFETs 21 and 25 are lowered, problems such as missing frequency division can be avoided, and normal operation of the frequency divider circuit with an ultra-low voltage of about 0.3 V becomes possible.

Note that the inverter 6 shown in FIG. 1 also operates in the same manner as the inverter 2 shown in FIG. 5, for example. For this reason, in the flip-flop 10 and the frequency dividing circuit 100 including the flip-flop 10, power consumption during standby and during operation can be reduced.
Thus, according to the embodiment of the present invention, in the PD-SOI-MOSFETs 21 and 25 that repeatedly turn on and off during circuit operation, the body potential stably oscillates within a certain range, and the on-current value and off-leakage current Each value gradually decreases and becomes a constant value. On the other hand, in the PD-SOI-MOSFETs 23 and 26 that maintain the off state, the gate potential is fixed, so that the body potential matches the potential of the source region.

  Here, according to the embodiment of the present invention, the absolute value of the threshold voltage of the MOSFETs 23 and 26 is set larger than the absolute value of the threshold voltage of the MOSFETs 21 and 25 by changing the channel doping condition, for example. For this reason, the off-leakage current values of the MOSFETs 23 and 26 can be suppressed, and the power consumption during standby and operation of the frequency divider can be reduced. Considering the difference in body potential during circuit operation, the threshold voltage of each MOSFET can be optimized, so that the circuit operation can be performed at a low voltage while improving the stability of the circuit operation. The power consumption can be reduced.

  That is, the present invention is based on the discovery that the body potentials of the floating body type PD-SOI-MOSFETs are stable and have different body potentials when the frequency divider circuit operates. In the present invention, it is clarified that the substrate floating state (body potential) of each MOSFET constituting the integrated circuit has a stable state, and the threshold voltage of each MOSFET is considered in consideration of the difference in each substrate floating stable state. Optimize circuit design. Thereby, instability of circuit operation can be avoided, and a low standby current and an ultra-low voltage drive of 0.5 V or less can be realized.

  In this embodiment, the SOI layer 53 corresponds to the “semiconductor layer” of the present invention, and the frequency dividing circuit 100 corresponds to the “circuit” of the present invention. Further, the floating body type PD-SOI-MOSFETs 23 and 26 correspond to the “first transistor” of the present invention, and the floating body type PD-SOI-MOSFETs 21 and 25 correspond to the “second transistor” of the present invention. The floating body type PD-SOI-MOSFETs 22 and 24 correspond to the “third transistor” of the present invention. Further, the gate electrode 83 corresponds to the “first gate electrode” of the present invention, the source region 84 or the drain region 85 corresponds to the “first source region or the first drain region” of the present invention, and the body region 86 corresponds to the main region 86. This corresponds to the “first body region” of the invention. The gate electrode 63 corresponds to the “second gate electrode” of the present invention, the source region 64 or the drain region 65 corresponds to the “second source region or the second drain region” of the present invention, and the body region 66 corresponds to the main region 66. This corresponds to the “second body region” of the invention. Further, the gate electrode 73 corresponds to the “third gate electrode” of the present invention, the source region 74 or the drain region 75 corresponds to the “third source region or the third drain region” of the present invention, and the body region 76 corresponds to the main region 76. This corresponds to the “third body region” of the invention.

  In the above embodiment, the case where the inverters 2 and 6 have both the set (S) terminal and the reset (XR) terminal has been described, but the present invention is not limited to this. For example, as shown in FIG. 12, the inverter 2 may have only floating body type PD-SOI-MOSFETs 21, 22, 25, 26, a reset (XR) terminal, and input terminals A and B. good. That is, the set (S) terminal may not be provided. The same applies to the inverter 6. Even with such a configuration, by setting the absolute value of the threshold voltage of the MOSFET 26 to be higher than the absolute value of the threshold voltage of the MOSFET 25, it is possible to obtain the same effect as in the above embodiment.

1, 3, 4, 5 clocked inverter, 2, 6 inverter, 10 quasi-static type T flip-flop, 11-14, 21-26 floating body type PD-SOI-MOSFET, 50 SOI substrate, 51 support substrate, 52 Insulating layer, 53 SOI layer, 54 Element isolation insulating film, 62, 72, 82 Gate insulating film, 63, 73, 83 Gate electrode, 64, 74, 84 Source region, 65, 75, 85 Drain region, 66, 76, 86 Body region, 66a, 76a, 86a Depletion layer, 66b, 76b, 86b Neutral region, 100 frequency divider

Claims (6)

A circuit having a first transistor and a second transistor respectively formed in a semiconductor layer on an insulating layer,
The first transistor includes:
A first gate electrode formed on the semiconductor layer via a gate insulating film;
A first source region or a first drain region formed in the semiconductor layer under the side of the first gate electrode,
A first body region sandwiched between the first source region and the first drain region of the semiconductor layer is placed in an electrically floating state, and a threshold voltage is applied to the first gate electrode. When applied, the first body region is partially depleted,
The second transistor is
A second gate electrode formed on the semiconductor layer via a gate insulating film;
A second source region or a second drain region formed in the semiconductor layer under the side of the second gate electrode,
A second body region sandwiched between the second source region and the second drain region of the semiconductor layer is placed in an electrically floating state, and a threshold voltage is applied to the second gate electrode. When applied, the second body region is partially depleted,
The absolute value of the threshold voltage of the first transistor is set larger than the absolute value of the threshold voltage of the second transistor;
During operation of the circuit,
A semiconductor device, wherein a fixed voltage is applied to the first gate electrode to turn off the first transistor, and an amplitude voltage is applied to the second gate electrode to repeatedly turn on and off the second transistor. . The circuit is
A third transistor formed in the semiconductor layer on the insulating layer;
The third transistor is
A third gate electrode formed on the semiconductor layer via a gate insulating film;
A third source region or a third drain region formed in the semiconductor layer under the side of the third gate electrode,
A third body region sandwiched between the third source region and the third drain region of the semiconductor layer is placed in an electrically floating state, and a threshold voltage is applied to the third gate electrode. The third body region is partially depleted when applied,
The absolute value of the threshold voltage of the first transistor is set larger than the absolute value of the threshold voltage of the third transistor;
During operation of the circuit,
2. The semiconductor device according to claim 1, wherein the third transistor is turned on by applying the fixed voltage to the third gate electrode. The first body region, the second body region, and the third body region each include impurities of the same conductivity type,
The concentration of the impurity in the first body region is higher than the concentration of the impurity in the second body region and higher than the concentration of the impurity in the third body region. The semiconductor device described.   4. The semiconductor device according to claim 3, wherein the concentration of the impurity in the second body region is the same as the concentration of the impurity in the third body region. The circuit is a frequency divider having at least one flip-flop,
The first gate electrode of the first transistor is connected to a set or reset terminal of the flip-flop;
5. The semiconductor device according to claim 1, wherein the second gate electrode of the second transistor is connected to an input terminal of the flip-flop. 6.   6. The semiconductor device according to claim 5, wherein transistors included in the flip-flop are only the first transistor, the second transistor, and the third transistor.

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