JP3886716B2 - Semiconductor integrated circuit, timepiece and electronic device equipped with the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit including a field effect transistor having an SOI (Silicon On Insulator) structure, a timepiece including the same, and an electronic device.
[0002]
[Background Art and Problems to be Solved by the Invention]
Due to recent advances in integration technology and communication technology, various electronic devices such as mobile phones and information terminals have been ported, and further reduction in power consumption is required for semiconductor integrated circuits incorporated therein.
[0003]
For example, in the case of watches (watches), those that do not use a primary battery are increasing due to environmental considerations, and self-generated power due to self-winding, solar cells, thermoelectric effects, etc. is stored in a secondary battery for motors and built-in controls. Some of them are used as power sources for ICs. In recent years, there has been put into practical use what guarantees an accurate time at a quartz clock level by moving a needle mechanically with a mainspring and simultaneously generating power for a quartz oscillator and a built-in control IC. In this case, the upper limits of the operating voltage and the operating current allowed for the built-in control IC are, for example, 0.5 volts ([V]) and 50 nanoamperes ([nA]), respectively.
[0004]
In general, the above-described control IC is composed of a metal oxide semiconductor (Metal-Oxide-Semiconductor) transistor. In order to reduce the power consumption of the control IC, it goes without saying that the parasitic capacitance of the built-in MOS transistor is reduced. However, since the power consumption is proportional to the square of the operating voltage (power supply voltage), the operating voltage is lowered. Is most effective.
[0005]
A device having an SOI (Silicon On Insulator) structure has a feature that enables a reduction in junction capacitance and a reduction in operating voltage due to a low threshold voltage, and operation with ultra-low power consumption as described above is required. It is attracting attention as a technology for realizing various circuits.
[0006]
In such a MOS field effect transistor (hereinafter referred to as FET) having an SOI structure, a body region made of a silicon layer is formed in a region corresponding to a channel region of a bulk MOSFET. The behavior and characteristics differ depending on whether or not the body region includes a neutral region in which carriers moving between the source region and the drain region exist.
[0007]
Those having a neutral region in the body region can be classified as partially depleted (PD), and those having no neutral region can be classified as fully depleted (FD). Whether or not this neutral region exists is determined by the thickness of the silicon layer forming the body region.
[0008]
A fully depleted SOI-structure MOSFET has the advantage of having excellent saturation characteristics and being suitable for low power consumption. On the other hand, the required technique for manufacturing a thin silicon layer is difficult, and the threshold value cannot be accurately controlled.
[0009]
On the other hand, the partially depleted SOI structure MOSFET has a manufacturing margin of the thickness of the silicon layer in the body region, and has the advantage that the same process as that of the bulk type can be used. On the other hand, when the body region is in a floating state, it causes instability of operation due to the substrate floating effect caused by carriers existing in the neutral region, and there is a disadvantage that kinks may occur due to parasitic bipolar operation. Have.
[0010]
Therefore, for example, a semiconductor integrated circuit such as a watch IC, which is intended for “super” low power consumption operation, is simply constituted by a MOSFET having a fully depleted SOI structure, which is caused by the thin film thickness of the silicon layer. The threshold control is difficult and the manufacturing cost is high, so that mass production is difficult. On the other hand, if this semiconductor integrated circuit is simply constituted by a partially depleted SOI structure MOSFET, an ultra-low power consumption operation becomes impossible due to the unstable operation caused by the above-mentioned substrate floating effect or the like.
[0011]
Therefore, the present invention has been made in view of the technical problems as described above, and the object of the present invention is to apply, for example, an IC for a watch appropriately according to the characteristics of devices having various SOI structures. It is an object of the present invention to provide a semiconductor integrated circuit capable of ultra-low power consumption operation as described above, a timepiece including the same, and an electronic device.
[0012]
[Means for Solving the Problems]
  In order to solve the above problems, the present invention provides a first power supply line for supplying a first potential, a second power supply line for supplying a second potential lower than the first potential, and the first power supply line. And a constant voltage generation circuit electrically connected to the second power supply line, and a third power supply line for supplying a constant voltage generated by the constant voltage generation circuit with reference to the first potential And an operation circuit electrically connected to the first and third power supply lines, and constitutes the constant voltage generation circuitTransistorA first field effect transistor having a partially depleted SOI structure in which a body region and a source region are electrically connected, and constitutes the operation circuit.TransistorThe body region is composed of a second field effect transistor having a partially depleted SOI structure in which the body region is in an electrically floating state,The proportion of the number of elements of the first field effect transistor in the entire circuit is so small that the influence of the increase in off-leakage current of the first field effect transistor can be ignored, and the gate-source voltage V _GS (However, V _GS > 0), the threshold values of the first and second field effect transistors are adjusted so that the drain currents are equal to each other, and this relates to a semiconductor integrated circuit in which the circuit operation stop voltage of the entire circuit is lowered.
[0013]
  Here, the constant voltage generation circuit generates a constant voltage using the potential difference between the first and second potentials supplied to the first and second power supply lines as an operating voltage. Configuring such a constant voltage generation circuitTransistorAnd a field effect transistor having a partially depleted SOI structure in which a body region and a source region are electrically connected, and the entire circuit has a field effect of such a source tie partially depleted SOI structure. It is desirable that the transistor is configured.
[0014]
  The operation circuit is a constant voltage generated by the constant voltage generation circuit with the first potential as a reference, and preferably operates at an extremely low voltage.Body areaIs composed of a partially depleted SOI field effect transistor which is electrically floating, and the entire circuit is composed of such a floating body partially depleted SOI field effect transistor. It is desirable.
[0015]
That is, according to the present invention, the constant voltage generation circuit connected to the first and second power supply lines to which a high voltage may be applied is electrically connected to the partially depleted body region and the source region. The field effect transistor is configured by a connected SOI structure, and a constant voltage generated by the constant voltage generation circuit is supplied to the operation circuit by the first and third power supply lines. If the constant voltage generation circuit can generate an ultra-low constant voltage, a semiconductor integrated circuit capable of ultra-low power consumption operation can be obtained by configuring the operation circuit with a field effect transistor having an SOI structure whose body region is in a floating state. Can be provided.
[0016]
Note that a digital circuit that performs a logical operation is suitable as the operation circuit. In general, when most part of a semiconductor integrated circuit is a digital circuit part that performs a logic operation, it is possible to achieve an effect by adopting a floating body type SOI structure field effect transistor capable of an ultra-low constant voltage operation as described above. In particular, ultra-low power consumption can be achieved.
[0017]
Furthermore, the operation circuit electrically connected to the first and third power supply lines with the constant voltage reference as the first potential is the second potential supplied by the second power supply line. There may be.
[0018]
By the way, the threshold value of the field effect transistor of the SOI structure (source tie type (body tie type in a broad sense)) in which the body region is electrically connected to the source region, and the body region are in an electrically floating state. When the threshold value of the field effect transistor of the SOI structure (floating body type) is the same, that is, approximately the same, the off-leak current of the field effect transistor of the source tie type SOI structure increases.
[0019]
Although the circuit portion constituted by the field effect transistor having the floating body type SOI structure can be operated up to a lower operating voltage, the circuit operation stop voltage of the entire semiconductor integrated circuit is the source tie type SOI. It relied on the circuit portion formed by the field effect transistor of the structure. However, by making the threshold value of the field effect transistor of the source tie type SOI structure and the threshold value of the field effect transistor of the floating body type SOI structure equal, the drain current of the field effect transistor of the source tie type SOI structure is reduced. Since it can be increased, the circuit operation stop voltage of the entire semiconductor integrated circuit can be further lowered.
[0020]
In particular, the smaller the ratio of the number of field-effect transistors having a source-tie SOI structure in the entire semiconductor integrated circuit, the more the off-leakage current can be ignored, while the circuit operation stop voltage is further reduced. Therefore, low power consumption can be effectively achieved.
[0021]
The present invention also includes first and second external terminals electrically connected to the first and second power supply lines, respectively, and the first and second external terminals are connected to the first and second external terminals, respectively. A potential of 2 is supplied.
[0022]
According to the present invention, the circuit operation becomes unstable due to the substrate floating effect, so that a high voltage cannot be applied, and the circuit operates with respect to an operation circuit including a field effect transistor having a floating body type SOI structure that operates at an extremely low constant voltage. When supplying the voltage, the uncontrollable external power supply voltage applied from the external terminal is once supplied to the constant voltage generating circuit according to the present invention. Since the constant voltage generating circuit according to the present invention is composed of a field effect transistor having a body tie type SOI structure, it can obtain the same DC characteristics and AC characteristics as those of the bulk type, and from the outside which varies for some reason. This is a case where a high operating voltage is supplied and instability of operation due to the substrate floating effect is not caused.
[0023]
With such a constant voltage generation circuit, an ultra-low constant voltage is generated and supplied to the above-described operation circuit, so that an operation circuit portion that occupies most of the circuit generally performs an ultra-low constant voltage operation. Reduce power consumption.
[0024]
In addition, since the operation circuit is configured by a field effect transistor having an SOI structure having a body region that is partially depleted, the existing bulk type manufacturing process can be used and the threshold control is caused by the thinness of the silicon layer. Therefore, the manufacturing cost can be reduced and the threshold value can be controlled with high accuracy, so that a more reliable semiconductor integrated circuit can be provided.
[0025]
  In the present invention, the value of the constant voltage isThe constant voltage generation circuitIt is a value corresponding to the sum of the threshold values of the N-channel and P-channel field effect transistors constituting the.
[0026]
  According to the present invention,Constant voltage generatorSince the value corresponding to the sum of the thresholds of the N-channel type and P-channel field effect transistors constituting N is supplied to the operation circuit as a constant voltage, the temperature gradient between the constant voltage and the circuit operation stop voltage of the operation circuit By constantly supplying a constant voltage value that is slightly higher than the circuit operation stop voltage without setting a uselessly high constant voltage value in the temperature range in which operation is guaranteed, it is possible to effectively reduce power consumption. be able to.
[0027]
  The present invention also includes an oscillation circuit that is electrically connected to the first and third power supply lines and whose oscillation output is supplied to the operation circuit, and constitutes the oscillation circuit.TransistorThe semiconductor device is characterized by comprising a field effect transistor having a partially depleted SOI structure in which a body region and a source region are electrically connected.
[0028]
According to the present invention, an oscillation circuit having an undesirable frequency dependency and voltage dependency is configured by a field effect transistor having an SOI structure in which a partially depleted body region is electrically connected to a source region. The stability of the oscillation output can be realized.
[0029]
In addition, since the oscillation circuit constantly consumes current repeatedly, it is desirable that the power supply voltage has as low an amplitude as possible. However, in the present invention, since it is configured by a field effect transistor having an SOI structure, low power consumption operation can be achieved. Make it possible.
[0030]
According to the present invention, the constant voltage generating circuit has one end electrically connected to the second power supply line and one end electrically connected to the first power supply line. A second constant current source and a body region are electrically connected to a source region electrically connected to the first power supply line, and a gate electrode and a drain region are connected to the other end of the first constant current source. An electrically connected first P-channel field effect transistor having an SOI structure, one of which is electrically connected to the gate electrode of the first P-channel field effect transistor, and the other is the second constant current. A differential pair comparator circuit electrically connected to the other end of the source; a body region electrically connected to the source region; and a gate electrode electrically connected to the other end of the second constant current source A first N-channel field effect transistor having an SOI structure; The gate electrode is electrically connected to the differential output of the differential pair comparator circuit connected to the gate electrode of the first P-channel field effect transistor, and the body region and the source region are A second N-channel field effect transistor electrically connected to a second power supply line and having a drain region electrically connected to a source region of the first N-channel field effect transistor, By adjusting the drain current of the second N-channel field effect transistor, the first P-channel type and the N-channel type are used as constant voltage values supplied to the third power supply line with the first potential as a reference. A sum of thresholds of field effect transistors is generated.
[0031]
According to the present invention, the field effect transistor having a body tie type SOI structure in which the body region is electrically connected to the source region in order to fix the potential of the body region, the P channel type and the N channel can be formed with a very simple configuration. The sum of the threshold values of the channel field effect transistor is generated as a constant voltage. Since this is supplied as a constant voltage to the N-channel and P-channel field effect transistors constituting the operation circuit, the temperature gradient between the constant voltage and the circuit operation stop voltage of the operation circuit becomes equal, and the operation Low power consumption can be effectively achieved by always supplying a constant voltage value slightly higher than the circuit operation stop voltage without setting a uselessly high constant voltage value in the temperature range to be guaranteed.
[0032]
According to the present invention, a body region is electrically connected to each source region between a source region and a drain region of the first N-channel field effect transistor, and a gate electrode is the other end of the second constant current source. Including at least one second N-channel field effect transistor having an SOI structure or a plurality of SOI structures electrically connected to the semiconductor device, and changing a mask for photography at the time of manufacturing a semiconductor integrated circuit. The constant voltage value with the first potential as a reference is adjusted by cutting in this manner.
[0033]
According to the present invention, a body region is electrically connected to each source region between a source region and a drain region of the first N-channel field effect transistor, and a gate electrode is the other end of the second constant current source. And a second N-channel field effect transistor having one or more SOI structures electrically connected to each other, and at least one of the fuse wirings connecting them is cut off, and the first potential is used as a reference. The constant voltage value is adjusted.
[0034]
According to the present invention, fine adjustment of the generated low constant voltage value can be performed with high accuracy by using a nonvolatile memory such as wiring switching by changing a mask for photography at the time of manufacturing a semiconductor integrated circuit or fusing of a fuse. In addition, since the operation voltage can be set just below the circuit operation stop voltage based on the temperature gradient, it is possible to further reduce the power consumption.
[0035]
In the present invention, the second N-channel field effect transistor having the SOI structure has different gate width / gate length (W / L).
[0036]
According to the present invention, since a plurality of field effect transistors having different current amplification factors are provided, a process for changing a photolithography mask at the time of manufacturing a semiconductor integrated circuit for obtaining a target constant voltage value In addition to reducing the fusing process, the same fine adjustment can be achieved.
[0037]
Further, the present invention is a timepiece including any of the semiconductor integrated circuits described above.
[0038]
According to the present invention, it is possible to provide a timepiece capable of ultra-low power consumption and stable oscillation without depending on the power supply voltage of other circuits of the timepiece.
[0039]
  The present invention also includes a detection circuit that is electrically connected to the first and third power lines and detects a given signal from the watch body;the aboveAny one of the semiconductor integrated circuits,The detection circuit includes:The watch is composed of a partially depleted SOI field effect transistor in which a body region and a source region are electrically connected, and the operation circuit is a watch that performs a given operation in accordance with a detection result of the detection circuit. It is characterized by.
[0040]
According to the present invention, it is possible to provide a timepiece that performs accurate timekeeping with stable oscillation and can be carried for a long time by ultra-low power consumption operation.
[0041]
According to the present invention, the electronic device includes any one of the semiconductor integrated circuits described above.
[0042]
According to the present invention, it is possible to provide an electronic device that can extend the life of a battery by an ultra-low power consumption operation without depending on the power supply voltage of another circuit.
[0043]
  According to the invention, there is provided a detection circuit that is electrically connected to the first and third power supply lines and detects a given input signal, and any one of the semiconductor integrated circuits described above,The detection circuitA field effect transistor having a partially depleted SOI structure in which a body region and a source region are electrically connected, and the operation circuit performs a given operation in accordance with a detection result of the detection circuit. And
[0044]
ADVANTAGE OF THE INVENTION According to this invention, while performing appropriate control according to the operation state of another circuit part, the electronic device which can be carried for a long time by ultra-low power consumption operation | movement can be provided.
[0045]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0046]
1. MOSFET with SOI structure
First, an SOI structure MOSFET will be described.
[0047]
1.1 Fully depleted and partially depleted
1A to 1C schematically show cross-sectional structures of a conventional bulk MOSFET and an SOI structure MOSFET.
[0048]
As shown in FIG. 1A, in a conventional bulk MOSFET 10, a source region (S) 16 and a drain region (D) 18 into which impurities are implanted are formed in a well 14 formed on a silicon substrate 12. The The source region 16 and the drain region 18 are formed on both sides of the channel region 20 having a distance corresponding to the channel length. A gate electrode (G) 22 is disposed above the channel region 20 via a gate oxide film.
[0049]
In contrast, as shown in FIGS. 1B and 1C, a fully depleted type (hereinafter abbreviated as FD) and a partially depleted type (hereinafter abbreviated as PD). The SOI-structure MOSFETs 30 and 50 each have a similar structure in which a buried oxide film (hereinafter abbreviated as BOX) is formed on a silicon substrate.
[0050]
That is, in the MOSFETs 30 and 50 having the SOI structure, the BOXes 34 and 54 are formed on the silicon substrates 32 and 52 used for the conventional bulk type, and the silicon layer is formed on the BOXes 34 and 54. Source regions (S) 36 and 56 and impurity regions (D) 38 and 58 into which impurities are implanted are formed on both sides of the silicon layer formed on the top of each BOX 34 and 54. The silicon layers between the source regions (S) 36 and 56 and the drain regions (D) 38 and 58 are called body regions (or body portions) 40 and 60, and a gate oxide film is formed above each of the body regions 40 and 60. Gate electrodes (G) 42 and 62 are formed through the.
[0051]
The difference between the FD and the PD is caused by the film thickness of the silicon layer constituting the body regions 40 and 60, as schematically shown in FIGS.
[0052]
In the case of PD, the body region 40 includes a depletion layer in which no carriers are present and a neutral region in which many carriers are present.
[0053]
On the other hand, in the case of the FD, the neutral region does not exist in the body region 40 and only the depletion layer is formed.
[0054]
Here, the operation of the MOSFET having the SOI structure will be briefly described by taking an N-channel type in which the potential of the body region is not fixed (floating state) as an example.
[0055]
In PD, since there is no potential gradient in the neutral region, the majority carrier potential barrier between the source region and the body region (φ_h) Is higher for PD than for FD. Therefore, when a given bias is applied between the source region and the drain region, when electrons and holes are generated by the impact ionization phenomenon, the holes that are majority carriers flow toward the source region.
[0056]
Potential barrier against holes (φ_h), Some holes accumulate in the body region. In PD, this potential barrier (φ_h) Is high, the amount of majority carriers accumulated in the body region is larger in PD.
[0057]
In the case of PD, when the holes, which are majority carriers, continue to be accumulated in the body region, the threshold value of the N-channel MOSFET is lowered due to the bias effect. Therefore, the drain current increases rapidly.
[0058]
In order to reduce the influence of the substrate floating effect in which the drain current kinks and the transient threshold change due to the fluctuation of the potential of the PD body region, the body region potential is fixed at the sacrifice of integration density ( It is said that it is necessary to adopt a body tie type) or an FD that is more difficult to manufacture.
[0059]
However, since the present embodiment is applied to a field specialized in “super” low power consumption operation such as a watch IC, for example, by operating in a low electric field where the impact ionization phenomenon can be ignored, the above-described substrate floating It is characterized by reducing the effect.
[0060]
That is, when the bias between the body region and the source region is a high electric field, a large number of majority carriers are generated by the impact ionization phenomenon and accumulated in the body region. This means that the body potential increases as the gate voltage increases, and as a result, the drain current increases due to the lowering of the threshold and the parasitic bipolar effect.
[0061]
When the gate voltage is lowered from this state, the body potential does not decrease immediately. This is because the time constant of the majority carrier annihilation process is large. As a result, the drain current remains larger than the initial value for a while. Accordingly, the sub-threshold current including the off-current also increases, which is inconvenient for low power consumption.
[0062]
In contrast, at low electric fields where the impact ionization phenomenon can be ignored, the change in the number of majority carriers is governed by the generation and recombination mechanisms, so that when the gate voltage under “normal operation” changes, The career hardly changes.
[0063]
Therefore, while the gate voltage of the MOSFET is increasing, the diffusion of the depletion layer is delayed, so that the potential of the body region increases and the threshold value decreases. As a result, the drain current increases in a region where the gate voltage is high.
[0064]
On the other hand, while the gate voltage is decreasing, the contraction of the depletion layer is delayed, thereby causing a decrease in the potential of the body region and an increase in the threshold value. As a result, the drain current decreases in the region where the gate voltage is low.
[0065]
By both of these phenomena, the change in the subthreshold is made steep, the on-current is increased, and the off-current is decreased. Therefore, the low voltage operation and the low power consumption operation performance can be remarkably improved.
[0066]
FIG. 2 shows an example of sub-threshold characteristics of a MOSFET having a typical PD type SOI structure.
[0067]
Here, the horizontal axis represents the gate voltage (unit [V]) and the vertical axis represents the drain current (unit [A / μm]), and the change in the subthreshold current in the subthreshold region of the P channel type and N channel type MOS is shown. ing.
[0068]
As described above, when the voltage Vd between the drain region and the source region is 1.1 V, kinks are generated in the N-channel type, but it is steep under a low electric field such as Vd of 0.1 V or 0.6 V. The subthreshold change is maintained.
[0069]
Therefore, in a field specialized in ultra-low power consumption such as a watch IC, by actively utilizing the substrate floating effect which has been regarded as one of the disadvantages in the PD type SOI structure MOSFET, Voltage operation and low power consumption operation performance can be improved. In addition, since an existing bulk type process can be used, the manufacturing cost is excellent.
[0070]
1.2 Floating body type and body tie type
As a device for reducing the influence of the substrate floating effect of the MOSFET having the SOI structure in which the body region is in a floating state, there is a MOSFET having a body tie type SOI structure.
[0071]
In the body tie type, the potential of the body region described in FIGS. 1B and 1C is fixed. As the body tie type, by connecting the body region to, for example, the source region (source tie type), the majority carriers accumulated in the body region can be quickly extracted. Thereby, the kink phenomenon and the bipolar effect caused by the increase in the potential of the body region can be removed.
[0072]
FIGS. 3 and 4 show an example of the on / off current ratio of the MOSFET of the PD type SOI structure when the body region is in a floating state (floating body type) and in a fixed state (body tie type).
[0073]
Here, the horizontal axis represents the on-current (V_GS= V_DS= 0.5V) (unit [A / μm]), with the vertical axis representing the off-state current (unit [A / μm]), the N-channel type in FIG. 3 and the P-channel type on / off current ratio in FIG. It shows a change.
[0074]
Thus, when trying to obtain the same on-current, the body tie type has more off-state current than the floating body type, and the floating body type is superior in low power consumption operation. It is shown that. The same applies to the N channel type and the P channel type.
[0075]
On the other hand, when trying to obtain the same off-current, the floating body type has a higher on-current than the body tie type, which means that a steep sub-threshold characteristic can be obtained. This indicates that high-speed operation is possible. The same applies to the N channel type and the P channel type.
[0076]
FIGS. 5A and 5B show an example of a layout of floating body type and body tie type PD type SOI structure MOSFETs.
[0077]
Since it is necessary to provide an electrode for fixing the potential of the body region in the body tie type, compared with the floating body type MOSFET shown in FIG. 5A, the body tie type MOSFET shown in FIG. The layout area becomes larger.
[0078]
As described above, regarding the PD type SOI structure MOSFET, when the floating body type and the body tie type are compared, the floating body type is clearly more advantageous in terms of the on / off current ratio and the layout area.
[0079]
However, in the present embodiment, the body tie type of the MOSFET having the PD type SOI structure is a source tie type in which the body region and the source region are electrically connected, so that the DC characteristic and the AC characteristic similar to the conventional bulk are obtained. Focus on the point.
[0080]
FIG. 6 shows an outline of the basic configuration of the semiconductor integrated circuit according to the present embodiment as described above.
[0081]
The semiconductor integrated circuit of this embodiment includes first and second external terminals 80 and 82, and a first power supply line V to which first and second potentials are supplied from the outside, respectively._DDSecond power line V_SSAnd are electrically connected.
[0082]
First power line V_DDAre electrically connected to a constant voltage generation circuit 90 and an operation circuit 92.
[0083]
Second power line V_SSAre connected to a constant voltage generation circuit 90.
[0084]
Since the constant voltage generation circuit 90 may be applied with a high voltage that cannot reduce the influence of the substrate floating effect as described above, a body tie type (particularly, body region ( (Synonymous with the body part) and source tie type) in which the source region is electrically connected, and has characteristics similar to those of the conventional bulk and depends on fluctuations in the first and second potentials applied from the outside. Without generating a stable constant voltage.
[0085]
As the operation circuit 92, a floating body type is applied to at least a part of a transistor as a component as a part where ultra-low power consumption is effective such as a logic circuit that occupies most of the other circuits.
[0086]
That is, the first power supply line V is connected to the floating body type circuit portion that causes circuit instability due to the substrate floating effect._DDThe operation circuit unit 92 to which the floating body type is applied by supplying a constant voltage generated by a constant voltage generation circuit 90 configured as a body tie type via the third power supply line 94 with reference to the potential as a reference. Enables ultra-low power consumption.
[0087]
The constant voltage generation circuit 90 is desirably configured as a body tie type as a whole. Further, it is desirable that the operation circuit 92 is configured as a floating body type as a whole.
[0088]
In addition, by applying a partially depleted SOI structure transistor, existing manufacturing equipment can be used to obtain good threshold controllability and excellent cost performance.
[0089]
Hereinafter, the semiconductor integrated circuit of the present embodiment will be specifically described.
[0090]
2. IC for watch with ultra-low power consumption
2.1 Circuit configuration
FIG. 7 shows an example of the configuration of a watch IC that operates with ultra-low power consumption to which the semiconductor integrated circuit of this embodiment is applied.
[0091]
This watch IC includes an analog circuit unit 100 that requires a linear operation and a digital circuit unit 110 that performs a logical operation.
[0092]
The analog circuit unit 100 includes a constant voltage generation circuit (Voltage Regulator) 102, an oscillation circuit (Oscillator) 104, and a detection circuit (Detector) 106.
[0093]
The digital circuit unit 110 includes a frequency divider (Divider) 112 and a control circuit (Controller) 114.
[0094]
The analog circuit unit 100 includes the first power line V_DDAnd the second power line V_SSIs connected.
[0095]
The constant voltage generation circuit 102 of the analog circuit unit 100 includes a first power supply line V_DDAnd the second power line V_SSIs connected. The constant voltage generation circuit 102 includes a first power supply line V_DDAnd the second power line V_SSThe first power line V as the operating (power) voltage with the potential difference between_DDA given low constant voltage can be generated with reference to the potential. This low constant voltage is applied to the first power line V_DDAnd the power supply line 120 are supplied to each part of the circuit.
[0096]
The oscillation circuit 104 and the detection circuit 106 are connected to the first power line V_DDAnd the power line 120 are connected, and the potential difference between the two power lines operates as an operating (power) voltage.
[0097]
The frequency divider 112 and the control circuit 114 of the digital circuit 110 are connected to the first power line V_DDAnd the power line 120 are connected, and the potential difference between the two power lines operates as an operating (power) voltage.
[0098]
FIG. 8 shows an example of a main configuration part of the watch IC in the present embodiment shown in FIG.
[0099]
However, the same parts as those of the watch IC shown in FIG.
[0100]
Such a watch IC has a first power supply line V_DDIs at the ground level, the constant voltage generation circuit 102 receives the second power supply line V from the outside of the IC._SSAn external voltage is supplied via the.
[0101]
The constant voltage generation circuit 102 supplies a given low constant voltage generated between the power supply line 120 and the ground level to each part of the circuit.
[0102]
The oscillation circuit 104 takes out a 32 kilohertz (KHz) oscillation output from the externally attached 32 KHz crystal resonator 130 and supplies it to the digital circuit unit 110.
[0103]
As shown in FIG. 8, the digital circuit unit 110 is composed of a logic circuit, and the oscillation output from the oscillation circuit 104 is sequentially divided by a frequency dividing circuit 112 which is a part of the logic circuit, for example, 0.1 Hz. A circumferential signal is generated.
[0104]
On the other hand, the detection circuit 106 detects various notification signals indicating the operation state of a watch body (not shown) input from the operation state notification signal terminal 134 and outputs the detection result signal 136 to the control circuit 114 of the digital circuit 110.
[0105]
The control circuit 114 of the digital circuit unit 110 controls the output timing of the frequency-divided signal 132 output from the frequency-dividing circuit 112 according to the result indicated by the detection result signal 136 from the detection circuit 106. For example, the detection circuit 106 monitors the movement of the hands of a clock body (not shown) by various notification signals from the operation state notification signal terminal 134, and generates and supplies a clock signal 138 with an accurate timing by the control circuit 114, and The hand movement control is performed on the body.
[0106]
2.2 Digital circuit
The digital circuit unit 110 is a logic circuit in which a logical operation is performed, and usually has the largest number of elements in the watch IC and occupies most of the circuit.
[0107]
In the present embodiment, as shown in FIG. 7, the digital circuit section 110 such as the frequency divider 112 and the control circuit 114 is configured by a floating body type PD type SOI structure MOSFET.
[0108]
By adopting the floating body type, as shown in FIGS. 5A and 5B, it is possible to realize a MOSFET having the minimum size in terms of design rules, and ideally reduce the junction capacitance. .
[0109]
In addition, by adopting a floating body type PD-type SOI structure MOSFET, the threshold value during actual operation (AC operation) is made higher than the threshold during DC operation by actively utilizing the substrate floating effect in the body region. Can be further reduced, and the low voltage drive of the digital circuit unit 110 occupying most of the watch IC can be realized. Thereby, ultra-low power consumption can be achieved effectively. Therefore, the digital circuit unit 110 is supplied with an ultra-low constant voltage necessary for positively utilizing the above-described substrate floating effect in the floating body type PD-type SOI structure MOSFET by the constant voltage generation circuit 102. I have to.
[0110]
2.3 Analog circuit
The analog circuit unit 100 according to the present embodiment includes the second power line V_SSThe constant voltage generation circuit 102 to which an external power supply voltage is supplied via the external power supply and a part of the MOSFET of the detection circuit 106 that receives an external signal to which an ultra-low constant voltage is not supplied by the constant voltage generation circuit 102 are respectively provided in the body. A tie-type PD type SOI structure MOSFET is employed. Thereby, the substrate floating effect in the body region can be suppressed, and analog characteristics at the same level as the bulk type can be obtained.
[0111]
Further, in this embodiment, the oscillation inverter of the oscillation circuit 104 is also configured by a body tie type PD type SOI structure MOSFET. This is because, in the case of an oscillation circuit in particular, an analog characteristic having no frequency dependency or voltage dependency is required. That is, the oscillation circuit 104 adopts a body tie type PD type SOI structure MOSFET and operates at an ultra-low constant voltage, whereby a low power consumption operation and a stable oscillation output can be obtained.
[0112]
Further, in the detection circuit 106, except for the interface portion of the signal from the outside to which the ultra-low constant voltage is not supplied by the constant voltage generation circuit 102, it is configured as a floating body type, so that further low power consumption operation can be achieved. it can.
[0113]
In such an analog circuit 100, by further supplying a constant current and driving at a constant current, the operating current is suppressed and the operating current of the MOSFET is operated in a subthreshold region of about 1 nA. This ensures low current consumption operation and constant voltage operation.
[0114]
In particular, the oscillation inverter of the oscillation circuit 104 is selectively doped with impurities in the P-channel type and N-channel type SOI structure MOSFETs, and controlled to be lower than the threshold value of other MOSFETs in the analog circuit unit 100. Thus, the low constant voltage operation of the oscillation circuit 104 can be ensured.
[0115]
2.4 Constant voltage generator
2.4.1 Circuit configuration
FIG. 9 shows an example of a main part of the constant voltage generation circuit 102 in the present embodiment shown in FIGS.
[0116]
The P channel type and N channel type PD type SOI structure MOSFETs included in the constant voltage generation circuit 102 of this embodiment are all body tie type as shown in FIG. 9, and the body region is connected to the source region. .
[0117]
First, the constant voltage generation circuit 102 includes a differential pair comparator circuit 200.
[0118]
The comparator circuit 200 of the differential pair includes a constant current source 202, P-channel MOSFETs 204 and 206, and N-channel MOSFETs 208 and 210 on the load side.
[0119]
One end of the comparator circuit 200 of the differential pair is grounded (the first power line V_DDThe source terminals of the P-channel MOSFETs 204 and 206 are connected to the other end of the constant current source 202 connected to the other.
[0120]
The drain terminals of the P-channel MOSFETs 204 and 206 are connected to the drain terminals of the load-side N-channel MOSFETs 208 and 210, respectively.
[0121]
The gate terminals of the N-channel MOSFETs 208 and 210 on the load side are connected to each other, and the gate terminal and the drain terminal of the N-channel MOSFET 210 are connected. Thereby, a mirror circuit is configured on the load side.
[0122]
The source terminal of the P-channel MOSFET 212 is grounded (first power line V_DDThe gate terminal and the drain terminal are connected. The gate terminal and the drain terminal are connected to the node P. The node P has a gate terminal of the P-channel MOSFET 204 and one end at the second power supply line V._SSIs connected to the other end of the constant current source 214 connected to.
[0123]
Furthermore, one end is grounded (the first power line V_DDThe other end of the constant current source 216 connected to the node P ′ is connected to the node P ′. The node P ′ is connected to the gate terminal of the P-channel MOSFET 206 and the drain terminal of the N-channel MOSFET 218.
[0124]
The gate terminal and drain terminal of the N-channel MOSFET 218 are connected to each other, and the source terminal is connected to the node Q. This node Q is connected to an output terminal 220 that outputs an extremely low constant voltage value with reference to the ground level (the potential level of the first power supply line) and the drain terminal of the N-channel MOSFET 222.
[0125]
The gate terminal of the N-channel MOSFET 222 is connected to the drain terminal of the P-channel MOSFET 204 and the drain terminal of the N-channel MOSFET 208. The source terminal of the N-channel MOSFET 222 is connected to the second power line V_SSIt is connected to the. The N-channel MOSFET 222 is an output control transistor.
[0126]
Further, N-channel MOSFETs 230, 232 and 234 are connected between the node P ′ and the node Q in parallel with the N-channel MOSFET 218. The drain terminals and gate terminals of the N-channel MOSFETs 230, 232, and 234 are connected to each other.
[0127]
Here, three MOSFETs 230, 232, and 234 are connected in parallel with the N-channel MOSFET 218, but one, two, four, or more MOSFETs may be connected.
[0128]
2.4.2 Outline of operation
In the constant voltage generating circuit 102 having such a configuration, the potential of the node P, which is the potential of the drain terminal of the P-channel MOSFET 212, is set so that the constant current value supplied by the constant current source 214 flows. The potential of the node P is input to the gate terminal of the P-channel MOSFET 204 which is one input terminal of the differential pair comparator circuit 200 described above.
[0129]
A potential controlled by the output control N-channel MOSFET 222 and the N-channel MOSFET 218 is generated at the node P ′, and the potential of the node P ′ is the P-channel which is the other input terminal of the differential pair comparator. Negative feedback is provided to the gate terminal of the type MOSFET 206. With this configuration, the node P and the node P ′ are controlled to the same potential by the operations of the differential pair P-channel MOSFETs 204 and 206 and the output control N-channel MOSFET 222. Since the current flowing through the node P ′ is constant by the constant current source 216, the potential difference between the node Q and the node P ′ is constant voltage (V) controlled by the N-channel MOSFET 218._N)
[0130]
By doing so, the constant voltage V supplied from the output terminal 220 is obtained._QIs a potential difference V generated in the P-channel MOSFET 212 with the ground level (the potential level of the first power supply line) as a reference potential._PAnd the potential difference V generated in the N-channel MOSFET 218_NWill be output.
[0131]
2.4.3 Adjustment of constant voltage value
In this embodiment, the constant voltage V supplied from the output terminal 220 with the ground level (the potential level of the first power supply line) as the reference potential._QHowever, there is a case where it fluctuates due to variations in the threshold value of the MOSFET at the time of manufacturing a semiconductor integrated circuit. Therefore, an N-channel MOSFET having a W / L different from the W / L of the N-channel MOSFET 218 is arranged and the wiring is switched. Thus, a desired constant voltage can be supplied.
[0132]
In this case, the N-channel MOSFETs 230, 232, and 234 are set to different W / L, and the current amplification factor is changed, whereby wiring (for example, Al wiring) for connecting the MOSFETs is used for photolithography when manufacturing a semiconductor integrated circuit. N-channel MOSFETs having any W / L are selected by connecting or blocking any MOSFET by using a non-volatile memory such as mask change (master slice) or fuse wiring fusing The low voltage value can be adjusted with high accuracy.
[0133]
2.4.4 Circuit operation stop voltage V_STORelationship with
By the way, the circuit operation is stopped in the oscillation circuit 104, the digital circuit 110, and the detection circuit 106 that operate using the constant voltage generated by the constant voltage generation circuit 102 using the ground level (the potential level of the first power supply line) as a reference potential. Voltage V_STOIs decided. Therefore, in order to reduce the power consumption as much as possible, the constant voltage value to be generated by the constant voltage generation circuit 102 is the circuit operation stop voltage V in the guaranteed operating temperature range._STOIt needs to be higher and as low as possible.
[0134]
Circuit operation stop voltage V_STODepends on the threshold value of the MOSFET constituting the circuit to which the low voltage is supplied. Therefore, in the constant voltage generation circuit 102 in this embodiment, the constant current value is adjusted to adjust the saturation of the P-channel MOSFET 212 connected in saturation. The sum of the value of Vds (drain-source voltage) and the value of Vds of the saturation-connected N-channel MOSFET 218 is output as a constant voltage.
[0135]
Therefore, the constant voltage V supplied from the output terminal 220_QIs the threshold V of each of the P-channel MOSFET 212 and the N-channel MOSFET 218._thN, | V_thPThe value depends on the sum of |.
[0136]
As a result, the low constant voltage generated by the constant voltage generation circuit 102 and the circuit operation stop voltage V of the circuit to which the low constant voltage is supplied._STOThe circuit operation stop voltage V is always set without setting an unnecessarily high constant voltage value in a temperature range in which operation is guaranteed._STOBy supplying a slightly higher constant voltage value, it is possible to effectively reduce power consumption.
[0137]
2.5 Threshold adjustment
As described above, in the watch IC in this embodiment, the floating body type and the body tie type are mixed for the MOSFET of the PD type SOI structure, but the process conditions are the same when both are manufactured in the same silicon chip. As a result, the off-state leakage current is at the same level.
[0138]
FIG. 10A shows an example of characteristics when a floating body type and a body tie type are manufactured under the same process conditions.
[0139]
Here, the horizontal axis shows the voltage V between the gate and source of the MOSFET having the SOI structure._GSThe drain-source current I on the vertical axis_DSThis shows the floating type and body tie type.
[0140]
In other words, when aiming at ultra-low power consumption, the leakage current during standby is the same level between the floating body type and body tie type by manufacturing under the same process conditions in order to minimize the leakage current during standby. It is said.
[0141]
In this case, the same V_GSFor floating body type, I_DSTherefore, the rise of the circuit becomes steep, and the threshold during operation can be lowered by the substrate floating effect. Therefore, the power consumption can be reduced more effectively by adopting it in the logic circuit part that shows most of the circuit. be able to. For circuit parts that must depend on an external power supply, a body tie type that is less affected by the substrate floating effect is adopted.
[0142]
However, the body tie type is I_DSCircuit operation stop voltage V_STOWill depend on the circuit part composed of the body tie type. That is, the circuit portion constituted by the floating body type operates to a lower operating voltage, but the body tie type does not operate._STOWill depend on this body tie part.
[0143]
Therefore, in the watch IC according to the present embodiment, when the proportion of the analog circuit portion adopting the body tie type in the IC is very small, the leakage current of the body tie type during standby can be ignored for the entire IC. Pay attention to the optimal V_GSI_DSIs characterized in that the process conditions are adjusted so as to be substantially the same.
[0144]
FIG. 10B shows an example of characteristics when the floating body type and the body tie type are manufactured by adjusting the process conditions.
[0145]
Here, the horizontal axis shows the voltage V between the gate and source of the MOSFET having the SOI structure._GSThe drain-source current I on the vertical axis_DSThis shows the floating type and body tie type.
[0146]
That is, a certain V_GSAt I_DSAre adjusted so that the thresholds are substantially equal (so that the thresholds are approximately equal or equal). As a result, the leakage current during standby of the body tie type increases.
[0147]
However, the number of elements in the analog circuit part where the body tie type is adopted in the watch IC is much smaller than the number of elements in the digital circuit part. However, the increase in leakage current during standby in the entire IC is small.
[0148]
Since the leakage current during standby depends on the W (gate width) / L (gate length) of the MOSFET, the circuit tie-down voltage V_STOCan be lowered further.
[0149]
This becomes more effective as the proportion of the body tie type in the floating body type in the IC is smaller.
[0150]
As described above, according to this embodiment, a logic circuit is constituted by a floating body type PD type SOI structure MOSFET, and a constant voltage (low constant voltage) with the first power supply line as a reference potential is applied thereto. Since it is provided, it is possible to eliminate the influence of the floating substrate type peculiar to the floating body type, and it is possible to provide a semiconductor integrated circuit capable of operating with extremely low power consumption.
[0151]
In addition, the constant voltage generation circuit in this embodiment is configured as a body tie type, and supplies a power supply voltage from the outside, and supplies a low constant voltage generated by the constant voltage generation circuit to an internal floating body type circuit. As a result, effective power consumption can be reduced.
[0152]
In particular, when the ratio of the body tie type is small with respect to the floating type occupying most of the circuit in the IC, the same V_GSAgainst I_DSBy adjusting the process conditions so that the values are substantially the same, the operating voltage at which the body tie type operates can be lowered, so that the power consumption can be reduced and the circuit operation stop voltage V of the entire IC can be reduced._STOIt is possible to achieve coexistence with lowering.
[0153]
In addition, since the oscillation circuit in this embodiment is configured as a body tie type and supplies a low constant voltage generated by a constant voltage generation circuit, the influence of frequency dependency and voltage dependency is eliminated, and stable oscillation is achieved. Output and ultra-low power consumption operation can be performed.
[0154]
3. Semiconductor device
The semiconductor integrated circuit according to the present embodiment as described above can be operated with an ultra-low power consumption that has not been conventionally achieved by mounting the semiconductor integrated circuit on a silicon chip or the like to constitute a semiconductor device. However, in a broad sense, the semiconductor integrated circuit of this embodiment is included in a semiconductor device.
[0155]
FIG. 11 shows an example of the configuration of a semiconductor device in which the semiconductor integrated circuit of this embodiment is built.
[0156]
The semiconductor device 300 includes a power supply / clock generation circuit 310 including the constant voltage generation circuit and oscillation circuit of the present embodiment, a CPU 312, a RAM 314, a DMA 316, a timer circuit 318, a serial interface circuit 320, and the like mounted on a silicon chip. And a plurality of external terminals. The CPU 312, RAM 314, DMA 316, timer circuit 318, and serial interface circuit 320 are connected to each other via a bus 322.
[0157]
Each circuit in the silicon chip is input from the outside of the semiconductor device via these various external terminals, and an operation signal of the circuit is output to the outside of the semiconductor device via these various external terminals.
[0158]
In the silicon chip mounted on the semiconductor device 300 of the present embodiment, a part of the power / clock generation circuit 310 is configured with a PD type SOI structure MOSFET body tie type, and other CPU 312, RAM 314, DMA 316, timer At least a part of the circuit 318 and the serial interface circuit 320 includes a circuit configured by a floating body type MOSFET having a PD type SOI structure.
[0159]
The power / clock generation circuit 310 includes a constant voltage generation circuit 330 and a clock signal generation circuit 332, and the constant voltage generation circuit 330 is connected to the first and second power supply lines via the power supply terminals 334 and 336. The second power supply lines 338 and 340 and the clock signal generation circuit 332 are connected to the first power supply line 338 and the low constant voltage supply line 342 to which the low constant voltage generated by the constant voltage generation circuit 330 is supplied, respectively. Is done.
[0160]
Further, the clock signal generation circuit 332 can be externally connected to the crystal resonator 348 via the crystal resonator connection terminals 344 and 346, and can divide the oscillation signal of a given frequency and output the clock signal 350. It is like that.
[0161]
Then, in the circuit formed of the floating body type of the PD type SOI structure MOSFET, the first power supply line 338 and the low constant voltage supply wiring 342 are connected, and the clock signal 350 generated by the oscillation circuit 332 is supplied. The
[0162]
Thus, as described above, the floating body type of the PD type SOI structure MOSFET is adopted for the logic circuit portion occupying most of the circuit, and a low constant voltage for reducing the influence of the substrate floating effect is supplied thereto. I did it. Further, as described above, the constant voltage generation circuit 330 for generating the low constant voltage and the oscillation circuit portion for obtaining the oscillation output are constituted by the body tie type of the PD type SOI structure MOSFET. As a result, a semiconductor device capable of operating with ultra-low power consumption without manufacturing costs can be provided.
[0163]
Note that since the frequency dividing circuit portion of the oscillation output of the clock signal generation circuit 332 performs a logic operation, the power consumption can be further reduced by adopting a floating body type of a PD type SOI structure MOSFET.
[0164]
4). Electronics
By applying the semiconductor integrated circuit (semiconductor device) as described above to an electronic device, power consumption of the electronic device can be reduced. That is, when the electronic device is battery-driven, the life of the battery can be extended, and an electronic device that is convenient for the user can be provided. This is applicable not only to the watch of this embodiment but also to various portable information terminal devices.
[0165]
FIGS. 12A and 12B show an example of a block diagram of the electronic apparatus of this embodiment.
[0166]
As shown in FIG. 12A, the electronic apparatus 400 includes a power supply / clock generation circuit 410 that generates an ultra-low constant voltage and a clock signal corresponding to the ultra-low constant voltage, and a clock signal using the ultra-low constant voltage as an operating voltage. Therefore, an operation circuit 420 for performing a given operation is included.
[0167]
The power / clock generation circuit 410 includes a constant voltage generation circuit 412 and a clock signal generation circuit 414.
[0168]
The constant voltage generation circuit includes a first power line V_DDAnd the second power line V_SSAn ultra-low constant voltage is generated from the potential difference between and a body type of a PD type SOI structure MOSFET.
[0169]
The clock signal generation circuit 414 includes the first power supply line V_DDAnd the ultra-low constant voltage generated by the constant voltage generation circuit 412 is operated as an operating voltage, the oscillation output of the externally attached crystal resonator 416 is taken out, and this is divided to obtain a clock signal 418. Generate. The portion from which the oscillation output of the clock signal generation circuit 414 is taken out is preferably constituted by a body tie type of a PD type SOI structure MOSFET, and the frequency division portion is preferably constituted by a floating body type of a MOSFET of a PD type SOI structure.
[0170]
The operation circuit 420 performs a given logic operation in accordance with the clock signal 418 and is configured by a floating body type MOSFET having a PD type SOI structure.
[0171]
As shown in FIG. 12B, the operation circuit 420 includes a CPU (or a semiconductor integrated circuit (semiconductor device) of this embodiment) 422, an input unit 424, a memory 426, an image generation unit 428, a sound output unit 430, a communication. Part 432.
[0172]
It is desirable that each unit that performs these logic operations is constituted by a floating body type MOSFET having a PD type SOI structure.
[0173]
Here, the input unit 424 is for inputting various data. The CPU (or the semiconductor integrated circuit (semiconductor device) of this embodiment) 422 performs various processes based on the data input by the input unit 424. The memory 426 serves as a work area for the CPU (or the semiconductor integrated circuit (semiconductor device) of this embodiment) 422 and the like. The image output unit 428 is for outputting various images (characters, icons, graphics, etc.) displayed by the electronic device, and the function can be realized by hardware such as an LCD or CRT. The sound output unit 430 is for outputting various sounds (sound, game sound, etc.) output by the electronic device, and the function can be realized by hardware such as a speaker.
[0174]
FIG. 13A illustrates an example of an external view of a mobile phone 950 which is one of electronic devices. The cellular phone 950 includes a dial button 952 that functions as an input unit, an LCD 954 that functions as an image output unit and displays a telephone number, a name, an icon, and the like, and a speaker 956 that functions as a sound output unit and outputs sound.
[0175]
FIG. 13B illustrates an example of an external view of a portable game device 960 that is one of electronic devices. The portable game device 960 includes an operation button 962 that functions as an input unit, a cross key 964, an LCD 966 that functions as an image output unit and displays a game image, and a speaker 968 that functions as a sound output unit and outputs game sound. Prepare.
[0176]
FIG. 13C illustrates an example of an external view of a personal computer 970 that is one of electronic devices. The personal computer 970 includes a keyboard 972 that functions as an input unit, an LCD 974 that functions as an image output unit and displays characters, numbers, graphics, and the like, and a sound output unit 976.
[0177]
By incorporating the semiconductor integrated circuit (semiconductor device) of this embodiment into the electronic devices of FIGS. 13A to 13C, it is possible to achieve ultra-low power consumption of the electronic devices.
[0178]
In addition to the devices shown in FIGS. 13A, 13 </ b> B, and 13 </ b> C, electronic devices that can use this embodiment include portable information terminals, pagers, electronic desk calculators, devices equipped with touch panels, Various electronic devices such as a projector, a word processor, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, and a printer can be considered.
[0179]
In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.
[Brief description of the drawings]
FIGS. 1A to 1C are schematic views showing a cross-sectional structure of a conventional bulk MOSFET and an SOI structure MOSFET. FIG.
FIG. 2 is an explanatory diagram illustrating an example of subthreshold characteristics of a MOSFET having a typical PD type SOI structure;
FIG. 3 is an explanatory diagram showing an example of an on / off current ratio of a MOSFET (N-channel type) having a floating body type and a body tie type PD type SOI structure.
FIG. 4 is an explanatory diagram showing an example of an on / off current ratio of a MOSFET (P channel type) having a floating body type and a body tie type PD type SOI structure.
FIGS. 5A and 5B are explanatory diagrams illustrating an example of a layout of a floating body type and a body tie type PD type SOI structure MOSFET. FIGS.
FIG. 6 is a configuration diagram showing an outline of a basic configuration of a semiconductor integrated circuit according to the present embodiment;
FIG. 7 is a configuration diagram showing an example of a configuration of a watch IC for ultra-low power consumption operation in the present embodiment.
8 is a block diagram showing an example of a main part of the configuration of the watch IC in the present embodiment shown in FIG. 6;
FIG. 9 is a configuration diagram showing an example of a configuration main part of a constant voltage generation circuit in the present embodiment.
FIGS. 10A and 10B are explanatory diagrams showing an example of characteristics when the floating body type and the body tie type are adjusted when the process conditions are the same.
FIG. 11 is a block diagram showing an example of a configuration of a semiconductor device in which the semiconductor integrated circuit according to the present embodiment is built.
FIGS. 12A and 12B are block diagrams of an example of an electronic apparatus according to the present embodiment.
13A, 13B, and 13C are examples of external views of various electronic devices.
[Explanation of symbols]
10 Bulk MOSFET
12, 32, 52 Silicon substrate
14 wells
16, 36, 56 Source region (S)
18, 38, 58 Drain region (D)
20 channel region
22, 42, 62 Gate electrode
30 FD type SOI structure MOSFET
34, 54 BOX
40, 60 body area
50 FD-type SOI structure MOSFET
80 First external terminal
82 Second external terminal
90, 102 Constant voltage generation circuit
92 Operation circuit
94 Third power line
100 Analog circuit
104 Oscillator circuit
106 Detection circuit
110 Digital circuit section
112 divider circuit
114 Control circuit
120 power line
130 Crystal resonator
132 Divide signal
134 Operation state notification signal terminal
136 Detection result signal
138 clock signal
200 Comparator circuit of differential pair
202, 214, 216 constant current source
204, 206, 212 P-channel MOSFET
208, 210, 218, 222, 230, 232, 234 N-channel MOSFET
220 Output terminal

Claims (12)

A first power supply line for supplying a first potential;
A second power supply line for supplying a second potential lower than the first potential;
A constant voltage generating circuit electrically connected to the first and second power supply lines;
A third power supply line for supplying a constant voltage generated by the constant voltage generation circuit with reference to the first potential;
An operation circuit electrically connected to the first and third power supply lines,
The transistor that constitutes the constant voltage generation circuit includes a first field effect transistor having a partially depleted SOI structure in which a body region and a source region are electrically connected,
The transistor constituting the operation circuit is composed of a second field effect transistor having a partially depleted SOI structure whose body region is in an electrically floating state,
The proportion of the number of elements of the first field effect transistor in the entire circuit is so small that the influence of an increase in off-leakage current of the first field effect transistor is negligible, and the gate-source voltage V _GS (however, V _GS > 0), the threshold values of the first and second field effect transistors are adjusted so that their drain currents are equal to each other, so that the circuit operation stop voltage of the entire circuit is lowered. . In claim 1,
Including first and second external terminals electrically connected to the first and second power supply lines, respectively;
The semiconductor integrated circuit, wherein the first and second potentials are supplied to the first and second external terminals, respectively. In claim 1 or 2,
The value of the constant voltage is a value corresponding to the sum of the threshold values of the N-channel and P-channel field effect transistors constituting the constant voltage generating circuit. In any one of Claims 1 thru | or 3,
An oscillation circuit electrically connected to the first and third power supply lines, the oscillation output of which is supplied to the operation circuit;
2. The semiconductor integrated circuit according to claim 1, wherein the transistor included in the oscillation circuit includes a field effect transistor having a partially depleted SOI structure in which a body region and a source region are electrically connected. In any one of Claims 1 thru | or 4,
The constant voltage generation circuit includes:
A first constant current source having one end electrically connected to the second power supply line;
A second constant current source having one end electrically connected to the first power line;
An SOI structure in which a body region is electrically connected to a source region electrically connected to the first power supply line, and a gate electrode and a drain region are electrically connected to the other end of the first constant current source. A first P-channel field effect transistor of
A differential pair comparator circuit in which one is electrically connected to the gate electrode of the first P-channel field effect transistor and the other is electrically connected to the other end of the second constant current source;
A first N-channel field effect transistor having an SOI structure in which a body region is electrically connected to a source region and a gate electrode is electrically connected to the other end of the second constant current source;
The gate electrode is electrically connected to the differential output of the differential pair comparator circuit connected to the gate electrode of the first P-channel field effect transistor, and the body region and the source region are A second N-channel field effect transistor electrically connected to a second power supply line and having a drain region electrically connected to a source region of the first N-channel field effect transistor;
By adjusting the drain current of the second N-channel field effect transistor, the first P-channel type and the N-channel as constant voltage values supplied to the third power supply line with the first potential as a reference. A semiconductor integrated circuit characterized by generating a sum of thresholds of a field effect transistor. In claim 5,
Between the source region and the drain region of the first N-channel field effect transistor, a body region is electrically connected to each source region, and a gate electrode is electrically connected to the other end of the second constant current source. A second N-channel field effect transistor having one or more SOI structures,
The value of the constant voltage based on the first potential is adjusted by cutting at least one of the wirings connecting them by changing a photolithography mask at the time of manufacturing a semiconductor integrated circuit. A semiconductor integrated circuit characterized by the above. In claim 5,
Between the source region and the drain region of the first N-channel field effect transistor, a body region is electrically connected to each source region, and a gate electrode is electrically connected to the other end of the second constant current source. A second N-channel field effect transistor having one or more SOI structures,
A semiconductor integrated circuit, wherein the constant voltage value with respect to the first potential is adjusted by cutting at least one of the fuse wirings connecting them. Either of claims 6 or 7,
The second N-channel field effect transistor having an SOI structure has a different gate width / gate length (W / L).   A timepiece comprising the semiconductor integrated circuit according to claim 1. A detection circuit which is electrically connected to the first and third power supply lines and detects a given signal from the watch body;
A semiconductor integrated circuit according to claim 1,
The detection circuit includes a field effect transistor having a partially depleted SOI structure in which a body region and a source region are electrically connected.
The operation circuit performs a given operation according to a detection result of the detection circuit.   An electronic apparatus comprising the semiconductor integrated circuit according to claim 1. A detection circuit that is electrically connected to the first and third power lines and detects a given input signal;
A semiconductor integrated circuit according to claim 1,
The detection circuit includes a field effect transistor having a partially depleted SOI structure in which a body region and a source region are electrically connected.
The electronic device is characterized in that the operation circuit performs a given operation in accordance with a detection result of the detection circuit.

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