JP2011041467A - Method for correcting voltage balance of power storage system, and power storage system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently equalize voltages of a plurality of power storage cells connected in series without great power loss. <P>SOLUTION: In the power storage system, one end of an inductor L1 is connected to an intermediate connection point of two cells, B1 and B2 alternately arranged in the order of series connection, and the other end is connected to one end and the other end of series connection of the cells B1 and B2 through switching elements respectively. By turning both switching elements S1 and S2 on or off alternately, charging the inductor with an inductor current iL from one of the cells and discharging the inductor current iL through a route for charging the other cell is switched alternately. A pause td is provided to turn off both switching elements S1 and S2 when a voltage difference Vx between at least two cells decreases. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a voltage balance correction circuit for series cells, and more particularly to a technique that is effective when a plurality of storage cells such as secondary batteries and capacitors are connected in series.

  In many cases, a large number of storage cells such as secondary batteries and capacitors are connected in series. For example, in motive power sources for electric vehicles or power storage systems for load leveling, tens to hundreds of cells are often connected in series.

  In such a case, when voltage variation occurs between cells, there is a problem that the life of the cell is shortened due to the concentration of voltage in a specific cell. This problem becomes more prominent as the number of series connections increases. Therefore, equalization of the voltage of each cell is an important issue when using the storage cells connected in series.

  As an effective means for equalizing the voltages of the storage cells connected in series, as shown in FIG. 12A, an inductor L1, first and second switching elements S1, S2, and a two-phase pulse generator 11 is known (see, for example, Patent Documents 1 and 2).

  In the figure, one end of the inductor L1 is connected to an intermediate connection point N1 between the first cell B1 and the second cell B2 that are back and forth in the order of series connection. The first switching element S1 is interposed between the other end of the inductor L1 and one series connection end of the two cells B1 and B2 to form a switching circuit.

  Similarly, the second switching element S2 is interposed between the other end of the inductor L1 and the other series connection end of the two cells B1 and B2 to form a switching circuit. The two-phase pulse generator 11 generates complementary square wave pulse signals + Φ1 and −Φ1 (the positive and negative signs indicate logic or phase polarity) to complementarily turn on the first and second switching elements S1 and S2.・ Turn it off.

  FIG. 2B shows an operation waveform chart in the main part of the voltage balance correction circuit. In the figure, when the voltage of the first cell B1 is higher than that of the second cell B2 (B1> B2), when S1 is on, the first cell B1 transfers to the inductor L1, and B1-S1-L1 The inductor current Li is charged (stored) in the direction of the solid arrow in the current path of −N1.

  Thereafter, when S1 is turned off and S2 is turned on, the inductor current Li charged in the inductor L1 is discharged through the current path N1-B2-S2-L1. This discharge is performed while charging the second cell B2.

  Contrary to the above, when the voltage of the second cell B2 is higher than that of the first cell B1 (B1 <B2), when S2 is on, the second cell B2 to the inductor L1 The inductor current Li is charged in the direction of the broken line arrow through the current path of -N1-L1-S2.

  Thereafter, when S2 is turned off and S1 is turned on, the inductor current Li charged in the inductor L1 is discharged through the current path of S1-B1-N1-L1. This discharge is performed while charging the first cell B1.

  As described above, electrical energy is transferred between the two cells B1 and B2 via the inductor L1. Thereby, the voltages of the cells B1 and B2 are equalized.

  In this equalization operation, the inductor current iL decreases with time due to discharge, but when this discharge current becomes zero, a charging current in a direction opposite to the discharge current flows. Therefore, when the voltages of the two cells B1 and B2 are in a substantially equal balance state (B1≈B2), the inductor current iL is discharged and charged approximately equally by the ON period of S1 and S2. . That is, the transfer of electrical energy performed through the inductor L1 is performed approximately equally between the two cells B1 and B2. Thereby, a voltage balance state is maintained.

JP 2001-185229 A JP 2006-67742 A

It has been made clear by the present inventors that the voltage balance correction circuit described above has the following problems.
That is, in the voltage balance correction circuit described above, for example, as shown in FIG. 12B, charging and discharging of the inductor current iL are performed even in a balanced state where the voltages of the two cells B1 and B2 are substantially equal. It ’s done just as it was before it was in balance. That is, the voltage balance correction circuit is always in a full operation state regardless of whether or not the balance correction is necessary.

  However, charging and discharging of the inductor current iL involve some power loss due to impedance components such as resistors parasitic on the inductor L1 and the switching elements S1 and S2, for example. For this reason, the voltage balance correction circuit described above has a problem that there is a lot of wasted power loss.

  The present invention has been made in view of the technical background as described above, and an object of the present invention is to efficiently equalize the voltages of a plurality of storage cells connected in series without causing a large power loss. It is to provide a power storage system.

  Other objects and configurations of the present invention will become apparent from the description of the present specification and the accompanying drawings.

In the power storage system according to the present invention, a series circuit of two storage cells and a series circuit of two switches are connected in parallel, and an inductor is provided between the intermediate point of the two storage cells and the intermediate point of the two switches. In the connected power storage system, when the voltage difference between the two power storage cells is larger than a predetermined value, the following first operation and second operation are repeated, and the voltage difference between the two power storage cells becomes smaller than the predetermined value. The following first operation, second operation, and third operation are repeated in this order, and when the voltage difference between the two storage cells disappears, the following third operation is maintained.
(1) The first operation is to turn on the switch on the high-voltage storage cell side, turn off the other switch, and charge the inductor by passing a current through the closed circuit of the storage cell, the switch, and the inductor. (2) In the second operation, the switch on the side of the high-voltage storage cell is turned off, the other switch is turned on, and the discharge current from the inductor is passed through the closed circuit of the other storage cell, the other switch, and the inductor. (3) In the third operation, the two switches are both turned off and no current flows through the inductor.

  The voltages of a plurality of storage cells connected in series can be equalized efficiently without causing a large power loss.

1 is a circuit diagram showing a first embodiment of a voltage balance correction circuit according to the present invention. FIG. 2 is an operation waveform chart in a main part of the balance correction circuit shown in FIG. 1. It is the circuit diagram which shows 2nd Embodiment of the voltage balance correction circuit by this invention, and the operation | movement waveform chart of the component. 4 is an operation waveform chart of the waveform generation circuit shown in FIG. 3. 4 is an operation waveform chart of the balance correction circuit shown in FIG. 3. It is an operation | movement waveform chart which shows 3rd Embodiment of the voltage balance correction circuit by this invention. It is a circuit diagram which shows 4th Embodiment of the voltage balance correction circuit by this invention. FIG. 8 is a circuit diagram and an operation waveform chart showing a fifth embodiment of the voltage balance correction circuit according to the present invention. It is a circuit diagram which shows 6th Embodiment of the voltage balance correction circuit by this invention. It is a circuit diagram which shows 7th Embodiment of the voltage balance correction circuit by this invention. It is a circuit diagram which shows the case where the voltage balance correction circuit of this invention is applied to three or more multi-series cells. It is the circuit diagram which shows the structure of the conventional voltage balance correction circuit, and an operation | movement waveform chart.

  FIG. 1 shows a first embodiment of a voltage balance correction circuit to which the technique of the present invention is applied. The voltage balance correction circuit shown in FIG. 1 equalizes each voltage of a plurality of storage cells connected in series, and includes an inductor L1, first and second switching elements S1, S2, and a correction control circuit 20. Is provided.

One end of the inductor L1 is connected to an intermediate connection point N1 between the first cell B1 and the second cell B2 that are moved back and forth in the series connection order. The other end is connected to a common connection point of the first and second switching elements S1, S2.

  The first switching element S1 is interposed between the series connection end of one B1 of the two cells B1 and B2 and the other end of the inductor L1 to form a switching circuit. The second switching element S2 is interposed between the other series connection end of the two cells B1 and B2 and the other end of the inductor L1 to form a switching circuit.

  The correction control circuit 20 includes resistors R1 and R2, an analog differential amplifier circuit 21, and a variable pulse generation circuit 12. The resistors R1 and R2 form a voltage dividing circuit that equally divides the series voltage of the two cells B1 and B2. For this reason, the resistors R1 and R2 are set to be equal.

  The differential amplifier circuit 21 linearly amplifies and transmits the voltage difference Vx (= Vm−Vn) between the voltage Vm appearing at the intermediate connection point N1 of the cells B1 and B2 and the divided voltage Vn of the resistors R1 and R2 with a predetermined gain.

  The variable pulse generation circuit 12 generates pulse signals Φ1 and Φ2 having a constant period for alternately turning on and off the first and second switching elements S1 and S2, and also, as shown in FIG. 2, the control pulse signal Φ1 , Φ2 duty width tw (ON period of S1 and S2) is variably controlled according to the voltage difference Vx.

  FIG. 2 shows an operation waveform chart in the main part of the balance correction circuit. In the figure, (a) and (e) show the operation (B1> B2 or B1 <B2) when a relatively large voltage difference appears between the first cell B1 and the second cell B2.

  In this case, the first and second switching elements S1 and S2 are alternately turned on and off at a constant period (tw + td). Thereby, the charging period in which the inductor current iL is charged in the inductor L1 from one cell B1 (or B2) and the discharging period in which the other cell B2 (or B1) is charged with the inductor current iL are alternately switched. .

  Furthermore, the charging / discharging period (tw) in which one of S1 and S2 is turned on is set to be sufficiently longer than the suspension period td in which both S1 and S2 are turned off. As a result, the amount of charge (electric energy) from the cell B1 (or B2) to the cell B2 (or B1) performed via the inductor L1 increases, and the voltage between the cells B1 and B2 is rapidly equalized. Become so.

  (B) and (d) show operations when the voltage difference between the two cells B1 and B2 is reduced (B1≈B2), respectively. In this case, the switching elements S1 and S2 are turned on / off at a constant cycle, but the charge / discharge period (tw) in which either S1 or S2 is turned on is shortened, and instead, both S1 and S2 are turned off. The pause period td is set longer.

  (C) shows the operation (B1≈B2) when the voltages of the cells B1 and B2 are perfectly balanced. In this case, both of the switching elements S1 and S2 continue to be in the off state, and only the idle period td in which the charging and discharging of the inductor L1 is not performed at all.

  As described above, when the voltage difference Vx between the two cells B1 and B2 is reduced, the power loss is increased by setting the idle period td in which both the first and second switching elements S1 and S2 are turned off. Excessive operation can be avoided. Thereby, the voltage of the some electrical storage cell connected in series can be equalized efficiently, without accompanying a big power loss.

  In the above configuration, the discharging period and the charging period of the inductor current iL are switched and set at a constant cycle, and the idle period td in which both S1 and S2 are turned off by the expansion and contraction of the duty width tw of the charging period and the discharging period is variable. As a result, the voltage balance of the cells B1 and B2 is always monitored at a fixed period, and when the voltage balance needs to be corrected, the correction operation is immediately performed properly without excess or deficiency. To be done.

  Furthermore, in the circuit shown in FIG. 1, rectifier diodes D1 and D2 that perform switching operations in accordance with the current direction are connected in parallel to the switching elements S1 and S2, respectively. The diodes D1 and D2 are in the reverse direction with respect to the voltages of the cells B1 and B2, but are in the forward direction with respect to the inductor current iL.

  If the inductor current iL remains during the period when both the switches S1 and S2 are off, the residual inductor current iL can continue to flow through the diode D1 or D2. Thereby, the inductor current iL once generated in the inductor L can be used for the voltage equalizing operation without waste, and the generation of the surge voltage generated when the inductor current iL is cut off can be surely suppressed.

  Use of power MOS-FETs is suitable as the switching elements S1 and S2. In power MOS-FETs, a diode parallel to the source and drain is normally formed. This diode is called a parasitic diode or an internal diode. By using this diode as the diodes D1 and D2, the circuit configuration can be simplified and the number of elements can be reduced.

  FIG. 3 shows a second embodiment of the voltage balance correction circuit according to the present invention. In the figure, (a) is a circuit diagram showing the main part of the balance correction circuit, and (b) shows a partial operation waveform chart.

  The basic configuration of this embodiment is the same as that of the above-described embodiment. The voltage balance correction circuit shown in FIG. 1 will be described with attention to the difference. As shown in FIG. 4A, the multi-output waveform generation circuit 31, voltage comparison circuits 41 to 44, and logic gate (OR logic) 45 , 46 and the like, the variable pulse generation circuit 13 is provided.

  The waveform generation circuit 31 is configured using a triangular wave generation circuit 32, an analog gate (or analog switch) 33, a phase inversion and level shift circuit 34, and the like, in synchronization with a reference clock signal CK provided from the clock generation circuit 35, As shown in (b), the following first to fourth fluctuation reference voltages f1 to f4 are generated.

First fluctuation reference voltage f1: A sawtooth non-sinusoidal voltage that periodically repeats a linear decrease from a predetermined high level reference voltage VH toward a first intermediate level voltage VHM.
Second fluctuation reference voltage f2: Appears with a half-cycle phase difference with respect to the first fluctuation reference voltage f1, and the voltage increases linearly from the first intermediate level voltage VMH toward the high level reference voltage VH. A sawtooth non-sinusoidal voltage that repeats periodically.
Third fluctuation reference voltage f3: Appears in phase with respect to the second fluctuation reference voltage f2, and a period in which the voltage linearly increases from the predetermined low level reference voltage VL toward the second intermediate level voltage VML. Repetitively sawtooth non-sinusoidal voltage.
Fourth fluctuation reference voltage f4: Appears with a half-cycle phase difference with respect to the third fluctuation reference voltage f3, and the voltage decreases linearly from the second intermediate level voltage VML toward the low level reference voltage VL. A sawtooth non-sinusoidal voltage that repeats periodically.

  The voltage comparison circuits 41 to 44 compare the voltage difference Vx between the two cells B1 and B2 moving back and forth in series connection order with the fluctuation reference voltages f1 to f4, respectively. The comparison result is output as binary logic signals p1 to p4. Based on the comparison results p1 to p4, the logic gates (OR logic) 45 and 46 logically generate pulse signals Φ1 and Φ2 for controlling on and off of the first and second switching elements S1 and S2.

  In this case, S1 is turned on when f1 <Vx, and S2 is turned on when f2 <Vx. When f3> Vx, S2 is turned on, and when f4> Vx, S1 is turned on.

  The voltage difference Vx is detected using the resistors R1 and R2 and the analog differential amplifier circuit 21 as in the above-described embodiment.

  FIG. 4 shows an operation waveform chart of the waveform generation circuit 31 shown in FIG. 3 and 4, the clock generation circuit 35 supplies a two-phase reference clock signal CK (CK 1, CK 2) to the waveform generation circuit 31. The clock signal CK (CK1, CK2) has a constant period ta and duty widths w1, w2.

  In the waveform generation circuit 31, first, the triangular wave generation circuit 32 generates two-phase triangular wave voltages g10 and g20 in synchronization with the clock signal CK (CK1, CK2). The triangular wave voltage g10 of one phase is separated into the first and second sawtooth voltages g11 and g12 by switching distribution every half cycle by the analog gate 33.

  The sawtooth voltages g11 and g12 are converted by the phase inversion and level shift circuit 34 into the first and second fluctuation reference voltages f1 and f2. The triangular phase voltage g20 of the other phase is converted into the third and fourth fluctuation reference voltages f1 and f2 by switching distribution every half cycle.

  FIG. 5 shows an operation waveform chart of the balance correction circuit shown in FIG. FIG. 4A shows an operation waveform when the voltage of the first cell B1 is higher than that of the second cell B2 (B1> B2). In this case, the period in which Vx> f1 and the period in which Vx> f2 appear alternately, S1 is turned on during the period of Vx> f1, and S2 is turned on during the period of Vx> f2.

  FIG. 5B shows an operation waveform when the voltage of the first cell B1 is lower than that of the second cell B2 (B1 <B2). In this case, the period where Vx <f4 and the period where Vx <f3 appear alternately, S1 is turned on during the period Vx <f4, and S2 is turned on during the period Vx <f3.

  FIG. 5C shows an operation waveform when the first cell B1 and the second cell B2 have substantially the same voltage (B1≈B2). In this case, Vx is in the vicinity of the intermediate voltage Vn between the two cells B1 and B2, is always low for both voltages f1 and f2, and is always high for both voltages f4 and f3. . Accordingly, neither S1 nor S2 is turned on, and both remain off.

  As described above, the discharging period and the charging period of the inductor current iL are switched and set at a constant cycle, and the idle period td in which both S1 and S2 are turned off is variably set by the expansion and contraction of the duty width of the charging period and the discharging period.

  In this embodiment, the first intermediate level voltage VMH that is the low level side peak voltage of f1 and f2 is higher than the second intermediate level voltage VML that is the high level side peak voltage of f3 and f4. A predetermined voltage difference width Vh is set between the intermediate level voltages VMH and VML.

  As a result, when the voltages of the cells B1 and B2 are almost in a balanced state and the equalizing operation is not necessary, a completely non-operating state in which neither S1 nor S2 is turned on is reliably maintained. In this non-operating state, charging and discharging of the inductor current iL in the inductor L is not performed at all, and so-called reactive current can be completely eliminated.

  The condition for generating the non-operation state can be arbitrarily set by the voltage difference width Vh. Thereby, the voltage balance correction of the cells B1 and B2 can be efficiently performed with arbitrary accuracy.

  FIG. 6 shows a third embodiment of the voltage balance correction circuit according to the present invention by an operation waveform chart in the main part thereof. The basic configuration of this embodiment is the same as that of the above-described embodiment (see FIG. 3). To explain the difference, in the embodiment shown in the figure, the waveform slopes of the second and fourth fluctuation reference voltages f2 and f4 are larger than those of the first and third fluctuation reference voltages f1 and f2. It is configured to be steep.

  In this embodiment, as shown in FIG. 6A or 6B, when the voltage equalizing operation is performed, the discharge period tb is shortened compared to the charging period ta of the inductor current iL. The discharge period tb of the inductor current iL is a charge period for the low voltage cell (B1 or B2), but the charge current to the cell (B1 or B2) is concentrated immediately after the start of the discharge of the inductor current iL. .

  That is, when the voltage of the first cell B1 is higher than that of the second cell B2 (B1> B2), the inductor current iL is charged from B1 to the inductor L by turning on S1, as shown in (a). After that, the inductor current iL is charged to B2 by turning on S2. The charging current has a maximum peak immediately after S2 is turned on, and thereafter decreases with time.

  When the voltage of the first cell B1 is lower than that of the second cell B2 (B1 <B2), the inductor current iL from B2 to the inductor L is turned on by turning on S2, as shown in FIG. 6B. Is charged, the inductor current iL is charged to B1 by turning on S1. This charging current also has a maximum peak immediately after S1 is turned on, and thereafter decreases with time.

  Therefore, as shown in FIG. 6A or 6B, the discharge period tb of the inductor current iL that supplies the charging current to the cell (B1 or B2) may be shorter than the charging period ta of the inductor current iL. The charging effect (charge amount) on the cell (B1 or B2) does not decrease so much.

  Thereby, even if the discharge period tb of the inductor current iL, that is, the charge period to the cell (B1 or B2) is shortened, the balance state as shown in FIG. This is effective in shortening the equalization operation cycle by charging / discharging the inductor current iL and speeding up the cell voltage balance correction operation.

  FIG. 7 shows a fourth embodiment of the voltage balance correction circuit according to the present invention. Focusing on the difference from the above-described embodiment, in this embodiment, a direct current gain is selectively applied to the signal transmission path until the voltage difference Vx between the two cells B1 and B2 is input to the comparison circuits 41 to 44. An amplifying circuit 22 for increasing is provided.

  For example, as shown in the figure, the amplifier circuit 22 can be easily formed by providing the analog differential amplifier circuit 21 for amplifying and transmitting the voltage difference Vx with an integration time constant of resistors R11 and R12 and a capacitor Ct.

  As a result, the DC gain of the feedback control loop that converges the voltage difference Vx to zero increases, and the state when the voltage difference Vx converges near zero can be stably maintained.

  FIG. 8 shows a fifth embodiment of the voltage balance correction circuit according to the present invention. Focusing on the difference from the above-described embodiment, in this embodiment, when the voltage difference Vx between the two cells B1 and B2 is input to the comparison circuits 41 to 44, as shown in FIG. A voltage limiting circuit 23 is provided that suppresses the input voltage Vx within a range between a high level limiting voltage VHL lower than the high level reference voltage VH and a low level limiting voltage VLL higher than the low level reference voltage VL. And

  When the voltages of the cells B1 and B2 are greatly different, the voltage difference Vx input to the comparison circuits 41 to 44 exceeds the voltage range of the fluctuation reference voltages f1 to f4, and S1 and S2 are simultaneously turned on and penetrated. There is a risk of current flowing.

  However, in this embodiment, as shown in FIG. 8B, the voltage range of the voltage difference Vx input to the comparison circuits 41 to 44 is limited to be surely within the voltage range of the fluctuation reference voltages f1 to f4. Therefore, the simultaneous ON of S1 and S2 is surely prevented. Even if the voltages of the cells B1 and B2 are different from each other, it is possible to reliably perform an equalizing operation for correcting the voltages.

  FIG. 9 shows a sixth embodiment of the voltage balance correction circuit according to the present invention. In this embodiment, an inductor current iL is used as a control parameter for variably setting the idle period td (see FIG. 2).

  In order to detect the inductor current iL, a current detection circuit 25 is interposed in series in the switching elements S1 and S2. The current detection circuit 25 is formed in a part of the MOS-FET that forms the switching elements S1 and S2.

  The switching elements S1 and S2 are formed using power MOS-FETs, and the power MOS-FETs are formed by a group of MOS-FET cells integrated on a semiconductor substrate. By forming the current detection circuit 25 using a part of the MOS-FET cell group, the cost can be reduced by simplifying the circuit and reducing the number of elements.

  The circuit shown in the figure is provided with a variable pulse generation circuit 14 that variably sets the ON period of the switching elements S1 and S2 based on the detection of the current detection circuit 25. The variable pulse generation circuit 14 switches the switching element S1 or S2 from ON to OFF when the inductor current iL becomes zero in the discharge mode of the inductor current iL, that is, the charging mode of the cell B1 or B2.

  The inductor current iL is charged by the high voltage cell (B1 or B2), and the charged inductor current iL is discharged while flowing as a charging current in the low voltage cell (B2 or B1). When the voltage difference between them is not so large, the charging of the cell (B2 or B1) by the inductor current iL (in the direction of the solid arrow) ends early, and thereafter the inductor current from the low voltage cell (B2 or B1) in the reverse direction. iL (broken arrow direction) is charged.

  This reverse inductor current iL is a reactive current that does not contribute to voltage equalization of the cells B1 and B2. This reactive current can be avoided by ending the ON period of the switching elements S1 and S2 when the inductor current iL becomes zero.

  Thus, in this embodiment, by variably setting the pause period td using the inductor current iL as a control parameter, it is possible to effectively suppress power loss due to the reactive current flowing through the inductor Li.

  FIG. 10 shows a seventh embodiment of the voltage balance correction circuit according to the present invention. In this embodiment, an inductor voltage Vi appearing at both ends of the inductor L is used as a control parameter for variably setting the idle period td (see FIG. 2).

  For this reason, in the balance correction circuit of the figure, the analog differential amplifier circuit 27 that detects the inductor voltage Vi from both ends of the inductor L, and the variable that sets the ON period of the switching elements S1 and S2 variably based on the inductor voltage Vi. A pulse generation circuit 15 is provided.

  Since the inductor current iL is proportional to the value obtained by integrating the terminal voltage of L, the variable pulse generation circuit 15 performs the period from the time when the calculated value becomes zero until the start of charging of the next inductor current iL. The switching elements S1 and S2 operate so as to be in a rest period in which both are turned off.

  Thereby, similarly to the case of the sixth embodiment, it is possible to effectively suppress the power loss due to the reactive current flowing through the inductor Li.

  FIG. 11 shows a connection example when the voltage balance correction circuit described above is applied to three or more multi-series cells B1 to B6,. As shown in the figure, in the voltage balance correction in three or more multi-series cells B1 to B6,..., An inductor L is installed at each connection point between the cells, and first and second for each inductor L. Switching elements S1 and S2 are provided, and the correction control circuit 20 described above is provided for each of the switching elements S1 and S2 so that voltage balance correction is performed among all the cells B1 to B6,. be able to.

  As described above, the present invention has been described based on the representative embodiments, but the present invention can have various modes other than those described above. For example, the first to fourth fluctuation reference voltages f1 to f4 can be easily generated by performing DA conversion on voltage waveform information stored as digital data for each predetermined sampling period and outputting it.

12 to 15 variable pulse generation circuit, 20 correction control circuit,
21 differential amplifier circuit, 22 amplifier circuit,
23 voltage limiting circuit, 25 current detection circuit,
27 differential amplifier circuit, 31 waveform generator circuit,
32 triangular wave generation circuit, 33 analog gate,
34 phase inversion and level shift circuit, 35 clock generation circuit,
41-44 voltage comparison circuit, 45, 46 logic gate (OR logic),
B1-B6 cells, CK reference clock signal,
Ct capacitor (time constant), D1, D2 diode,
f1 to f4, first to fourth fluctuation reference voltages, iL inductor current,
L1 inductor, N1 intermediate connection point,
p1 to p4 binary logic signal (comparison output), R1, R2 resistors (voltage divider circuit),
R11, R12 resistance (time constant), S1, S2 switching elements,
ta charging period of the inductor current iL, tb discharging period of the inductor current iL,
Vx cell voltage difference, VH high level reference voltage,
VL low high level reference voltage, VMH first intermediate level voltage,
VML second intermediate level voltage, Vh voltage difference width (offset),
VHL high level limit voltage, VLL low level limit voltage,
Vi Inductor voltage, Φ1, Φ2 pulse signal

Claims (1)

A storage system in which a series circuit of two storage cells and a series circuit of two switches are connected in parallel, and an inductor is connected between an intermediate point of the two storage cells and an intermediate point of the two switches. When the voltage difference between the two storage cells is larger than a predetermined value, the following first operation and second operation are repeated. When the voltage difference between the two storage cells becomes smaller than the predetermined value, the following first operation and second operation are performed. The second operation and the third operation are repeated in this order, and the following third operation is maintained when the voltage difference between the two storage cells disappears.
(1) The first operation is to turn on the switch on the high-voltage storage cell side, turn off the other switch, and charge the inductor by passing a current through the closed circuit of the storage cell, the switch, and the inductor. (2) In the second operation, the switch on the side of the high-voltage storage cell is turned off, the other switch is turned on, and the discharge current from the inductor is passed through the closed circuit of the other storage cell, the other switch, and the inductor. (3) In the third operation, the two switches are both turned off and no current flows through the inductor.

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