JP2011087377A - Circuit for correcting charge balance in multiserial accumulating cell - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid congestion of wiring, to reduce a cost, and also to reduce noise caused by a transformer or wiring, through the reduction of wiring in number between the transformer and a cell module, in a circuit for correcting the charge balance of a multiserial accumulating cell by a transformer system. <P>SOLUTION: Insulated transformers T1-Tn, in each of which primary winding and secondary winding are magnetically coupled to each other in an insulated state, are installed individually for each cell module M1-Mn, and the cell modules are charged individually with secondary currents induced to the secondary winding of the transformers. On the other hand, the primary winding of each transformer is connected in common to a resonance current generating circuit 20 via common wiring, and the resonance current generating circuit 20 generates a resonance current and distributes it to the primary winding of each transformer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a charge balance correction circuit for multi-series storage cells, and more particularly to a charge balance correction circuit for equalizing voltages of a large number of series-connected storage cells in units of modules using a transformer.

  As this type of charge balance correction circuit, for example, a transformer type charge balance correction circuit as described in Patent Documents 1 and 2 is known.

  FIG. 3 exemplifies a transformer type charge balance correction circuit which the present inventors have examined prior to the present invention. The charge balance correction circuit shown in the figure is also called a flyback type, and in order to equalize the voltages of a large number of series-connected power storage cells 11 in units of cell modules M1 to Mn, Charging is performed independently for each of the modules M1 to Mn using a flyback type multi-winding transformer (flyback transformer) Tx.

  The multi-winding flyback transformer Tx has a plurality of secondary windings L21 to L2n with respect to one primary winding L11. The plurality of secondary windings L21 to L2n are respectively magnetically coupled to the primary winding L11 while being insulated from each other.

  The primary winding L11 is pulse-energized with the balance correction power source E1 via the switching element S1. Accordingly, a secondary current is induced in each of the secondary windings L21 to L2n. The secondary windings L21 to L2n are individually connected to the cell modules M1 to Mn via the individual wiring 31 in a one-to-one correspondence.

  The secondary currents induced in the secondary windings L21 to L2n are individually supplied to the cell modules M1 to Mn via the individual wiring 31. In each of the modules M1 to Mn, the secondary current is rectified by the rectifier circuit D1 and charged to the cell modules M1 to Mn. Thereby, the voltage of the multi series electrical storage cell 10 can be equalized per module M1-Mn.

Japanese Patent No. 3267221 Japanese Patent No. 3630303

  The flyback type charge balance correction circuit described above has the following problems.

  A flyback multi-winding transformer uses a magnetic core having a magnetic gap to obtain an inductor with a predetermined winding. However, the leakage magnetic flux from the magnetic gap is large, and this leakage magnetic flux causes noise. Cheap.

  The wires 31 between the secondary windings L21 to L2n and the cell modules M1 to Mn are individual wires having a large number of wires, and each wire has a large wire diameter due to a relatively large secondary current flowing therethrough. There was a need to do. For this reason, there is a problem that the wiring is congested and the cost is increased.

  The individual wiring 31 between the transformer Tx and each of the cell modules M1 to Mn has to be routed to some extent in order to match the arrangement of the modules M1 to Mn, but harmonic noise is radiated from the routed wiring 31. Is done.

  In the illustrated circuit example, the number of secondary windings L21 to L2n is only three for simplification of explanation, but a multi-series storage cell used for, for example, an electric vehicle, a plug-in hybrid vehicle, a system linkage storage system, etc. In some cases, the number of cell modules may be several to several hundreds. In such a case, since the number of secondary windings of the multi-winding transformer increases accordingly, the above-described problem becomes more prominent.

  The present invention has been made in view of the above problems, and its purpose is to reduce the number of wires between the transformer and the cell module and to reduce the wire diameter, thereby avoiding the congestion of wires. An object of the present invention is to provide a charge balance correction circuit for a multi-series storage cell that can reduce costs and reduce noise generated from a transformer and wiring.

The first means of the present invention is specified by the following (1) to (4).
(1) A charge balance correction circuit for a multi-series storage cell that equalizes the voltages of a large number of storage cells connected in series in a cell module unit composed of one or a plurality of storage cells connected in series.
(2) Each cell module is individually provided with an insulating transformer in which the primary winding and the secondary winding are magnetically coupled to each other, and the secondary current induced in the secondary winding of the transformer. A rectifier circuit is provided to rectify and supply the battery module with charging.
(3) The primary winding of each transformer is connected to a resonance current generating circuit.
(4) The resonance current generation circuit includes a resonance circuit composed of an inductor and a capacitor, and a switching element that drives the resonance circuit by applying a pulse to the balance correction power source for resonance, and is generated every time the pulse is energized. Is distributed to the primary winding of each transformer.

  According to a second means of the present invention, in the first means, the resonance current generated by the resonance current generation circuit is distributed to the primary winding of each transformer by a common wiring. This is a balance correction circuit.

  According to a third means of the present invention, in the first or second means, the resonance current generation circuit is configured using a series resonance circuit including an inductor and a capacitor. This is a balance correction circuit.

  According to a fourth means of the present invention, in any one of the first to third means, the same reference voltage as an intermediate voltage expected to appear at a connection point between modules when the voltages of the modules are equal to each other, A voltage dividing circuit obtained by resistively dividing the output voltage of the multi-series storage cell, and a difference detecting circuit for detecting an absolute value of a difference between the divided voltage of the divided circuit and an intermediate voltage corresponding to the divided voltage. A charge balance correction circuit for a multi-series storage cell, wherein a detection output of the difference detection circuit is fed back to a pulse control circuit.

  According to a fifth means of the present invention, in the fourth means, the difference detecting circuit is proportional to the absolute value difference between the divided voltage of the voltage dividing circuit and the intermediate voltage corresponding to the divided voltage with a predetermined amplification gain. It is a charge balance correction circuit for a multi-series storage cell, characterized by detecting.

  According to a sixth means of the present invention, in any one of the first to fifth means, the output of the multi-series storage cell is used as a power source for balance correction of the multi-series storage cell. This is a charge balance correction circuit.

  In the charge balance correction circuit for multi-series storage cells using the transformer method, the number of wires between the transformer and the cell module can be reduced and the wire diameter can be reduced, which makes it possible to avoid wiring congestion and reduce costs. In addition, noise generated from the transformer and wiring can be reduced.

It is a circuit diagram which shows the charge balance correction circuit of the multi series electrical storage cell which makes one Embodiment of this invention. It is a circuit diagram which shows the principal part of further more preferable embodiment of this invention. It is a circuit diagram which shows the conventional charge balance correction circuit examined prior to the present invention.

FIG. 1 shows a charge balance correction circuit for a multi-series storage cell according to an embodiment of the present invention.
The balance correction circuit shown in the figure equalizes the voltages (module voltages) of the cell modules M1 to Mn constituting the multi-series storage cell 10 using transformers T1 to Tn.

  In the case of this embodiment, the cell modules M1 to Mn are composed of a plurality of power storage cells 11 connected in series. By connecting an arbitrary number of these cell modules M1 to Mn in series, a multi-series storage cell 10 having a predetermined terminal voltage is configured.

  The balance correction circuit of this embodiment is a transformer system, but unlike a conventional flyback type, a multi-winding flyback transformer is not used. Instead, one primary winding and one secondary winding are used. Insulating transformers T1 to Tn are provided for each of the cell modules M1 to Mn. Voltage equalization is performed in units of cell modules M1 to Mn.

  Insulation transformers T1 to Tn in which the primary winding and the secondary winding are magnetically coupled with each other in an insulated state are individually installed in each of the cell modules M1 to Mn, and the secondary of the transformers T1 to Tn. Rectifying circuits D1 to D4 are provided that rectify secondary currents induced in the windings and charge the cell modules M1 to Mn.

  The primary windings of the transformers T <b> 1 to Tn are commonly connected to the resonance current generating circuit 20 through the common wiring 30. The resonance current generation circuit 20 includes a resonance circuit composed of an inductor L1 and capacitors C1 and C2, and switching elements S1 and S2 that are driven to resonate with the resonance circuit by applying a current to the balance correction power source E1. Is distributed to the primary windings of the transformers T1 to Tn via the common wiring 30.

  Here, each transformer T1-Tn is comprised by the same turns ratio, and the primary voltage of T1-Tn of each transformer is each restrict | limited by the voltage of the modules M1-Mn connected to the secondary side. Therefore, when there is a voltage difference between the modules M1 to Mn, the resonance current distributed to the transformers T1 to Tn as the primary current is concentrated on the transformer connected to the module having the lowest voltage.

  The resonant circuit is a series resonant circuit (series resonant current resonant circuit), which is formed by switching elements S1 and S2, capacitors C1 and C2, inductor L1, and transformers T1 to Tn. Resonant drive is performed by a pulse energization operation, and a resonance current flows. This resonance current is distributed as a primary current to each of the transformers T1 to Tn via the common wiring 30.

  The switching elements S1 and S2 are, for example, MOSFETs to which back diodes are equivalently connected, and the switching operation is controlled by a PFM (pulse frequency modulation) control circuit 35. The PFM control circuit (pulse control circuit) 35 detects the interval of pulse energization by the switching elements S1 and S2 (and the pulse width if necessary) by the balance detection circuit 15 that detects the voltage difference between the cell modules M1 to Mn. Based on the variable control. That is, the PFM control circuit 35 forms a negative feedback control loop that performs feedback control so that the voltage difference between the cell modules M1 to Mn detected by the balance detection circuit 15 is minimized.

  The balance detection circuit 15 uses the same reference voltage as the intermediate voltage expected to appear at the connection point between the modules M1 to Mn when the voltages of the modules M1 to Mn are equal to each other. A voltage dividing circuit 16 obtained by dividing the resistance; and a difference detecting circuit 17 for detecting an absolute value of a difference between the divided voltage of the voltage dividing circuit 16 and an intermediate voltage corresponding to the divided voltage. The negative feedback control loop is formed by feeding back the detection output of the detection circuit 17 to the PFM control circuit 35.

  The voltage dividing circuit 16 is configured using resistance elements R11, R12, R31, and R32, and has a number of voltage dividing outputs corresponding to the number of connection points between the modules M1 to Mn. In the illustrated example, since the number of connection points between the modules M1 to Mn is two, the voltage dividing circuit 16 that obtains two divided voltages corresponding to the intermediate voltages respectively appearing at the respective locations is formed.

  The difference detection circuit 17 is configured using operational amplifiers H1 and H2. In the illustrated example, two sets of operational amplifiers H1 and H2 are provided because there are two sets of intermediate voltages and divided voltages to be compared. The differential amplification outputs of the operational amplifiers H1 and H2 are converted into absolute values by the absolute value detection circuit 18 and output. The outputs of the absolute value detection circuits 18 are logically added and fed back to the PFM control circuit 35. This logical addition is a logical addition of analog values, and the largest absolute value among a plurality of absolute values (analog values) is output.

  Thereby, the PFM control circuit 35 feedback-controls the energization intervals (frequency) of the switching elements S1 and S2 so that the absolute value outputs of the absolute value detection circuits 18 are both minimized.

  The above-described charge balance correction circuit does not use a multi-winding flyback transformer having a large leakage magnetic flux, but uses insulating transformers T1 to Tn each having one primary winding and one secondary winding. Since the transformers T1 to Tn can eliminate the magnetic gap for adjusting the winding inductance, noise emission due to the leakage magnetic flux can be reduced.

  A current for balance correction is distributed to the transformers T1 to Tn. This current distribution can be performed by the common wiring 30 with a small number of wirings. Moreover, since the current distributed in the common wiring 30 is a primary winding current having a relatively small current value, the wire diameter of the wiring 30 can be reduced. This makes it possible to avoid wiring congestion and reduce costs.

  Further, it should be noted that the balance correction current distributed by the common wiring 30 is a resonance current, and this resonance current has few harmonic components. Therefore, even if the common wiring 30 is routed long in order to match the arrangement of the modules M1 to Mn, the radiation of harmonic noise from the routed wiring 31 can be reduced.

  As described above, the above-described charge balance correction circuit can reduce the number of wires between the transformers T1 to Tn and the cell modules M1 to Mn and reduce the wire diameter, thereby avoiding the congestion of wires and reducing the cost. And noise generated from the transformers T1 to Tn and the wiring 30 can be reduced.

  Furthermore, by distributing the resonance current generated by the resonance current generation circuit to the primary windings of each transformer using common wiring, the number of wirings can be greatly reduced, thereby avoiding wiring congestion and reducing costs. Can be made more thorough.

  The above effect is particularly effective in a multi-series storage cell in which the number of cell modules is several to several hundreds, such as a multi-series storage cell used in an electric vehicle, a plug-in hybrid vehicle, a power storage system for system linkage, and the like. It is valid.

  In the embodiment shown here, each of the cell modules M1 to Mn is configured by a plurality of power storage cells 11 connected in series, but the cell module may be configured by one power storage cell. In this case, since the electromotive force (charge / discharge voltage) of the cell module is lowered, the rectifier circuits D1 to D4 are preferably configured using switching diodes using MOSFETs with low on-resistance instead of diodes having forward voltages.

  In addition to the configuration described above, in the circuit of the embodiment shown in FIG. 1, negative feedback resistance elements Ra and Rb for gain adjustment (gain suppression) are respectively added to the operational amplifiers H1 and H2 constituting the difference detection circuit 17. Is connected. As a result, the difference detection circuit 17 performs a proportional operation, and proportionally detects an absolute value difference from the intermediate voltage corresponding to the divided voltage with a predetermined amplification gain.

  When the difference detection circuit 17 performs a proportional operation (linear operation), for example, when the voltage balance state greatly deviates, the correction operation is performed with a control amount corresponding to the voltage balance state, while the voltage balance is almost balanced. Then, the correction operation or the correction operation with the control amount reduced to a small value is stopped. As a result, the charge balance correction operation can be performed with a control amount corresponding to the voltage balance state of the modules M1 to Mn without excess or deficiency, and the excessive correction operation is suppressed and the equalization operation is stabilized. Can do.

  As for the power source E1 for balance correction, a power source dedicated for balance correction may be separately prepared. However, in the present invention, the output of the multi-series storage cell 10 may be used. By using the output of the multi-series storage cell 10 as the balance correction power source E1 of the multi-series storage cell 10, voltage equalization can be performed not only during charging but also during discharging and storage. .

FIG. 2 shows the essential parts of a further preferred embodiment of the circuit shown in FIG.
In the above-described embodiment, the balance detection circuit 15 uses the same reference voltage as the intermediate voltage expected to appear at the connection point between the modules M1 to Mn when the voltages of the modules M1 to Mn are equal to each other. A voltage dividing circuit 16 obtained by resistance-dividing the output voltage of the cell 10, and a difference detecting circuit 17 for detecting an absolute value of a difference between the divided voltage of the voltage dividing circuit 16 and an intermediate voltage corresponding to the divided voltage. Have

  Here, in the circuit shown in FIG. 2, the voltage dividing circuit 16 for obtaining the reference voltage is constituted by a series of series resistance elements R11, R12, and R13. Each resistance element R11, R12, R13 has the same value, and the same reference voltage as the intermediate voltage expected to appear at the connection point between the modules M1 to Mn is divided from the connection point (tap).

  This voltage dividing circuit 16 using a single series of series resistance elements R11, R12, and R13 is particularly effective when the number of cell modules of the multi-series storage cell 10 is large.

DESCRIPTION OF SYMBOLS 10 Multi series electrical storage cell 11 Electrical storage cell 15 Balance detection circuit 16 Voltage dividing circuit 17 Difference detection circuit 18 Absolute value detection circuit 20 Resonance current generation circuit 30 Common wiring 35 PFM (pulse frequency modulation) control circuit M1-Mn as a pulse control circuit Cell module T1-Tn Insulation transformer D1-D4 Rectifier circuit L1 Inductor C1, C2 Capacitor E1 Balance correction power source S1, S2 Switching element H1, H2 Operational amplifier Ra, Rb Negative feedback resistance element for gain adjustment

Claims (6)

A multi-series storage cell charge balance correction circuit for equalizing the voltage of a plurality of storage cells connected in series in a cell module unit consisting of one or a plurality of storage cells connected in series,
Each cell module is individually provided with an isolation transformer in which the primary winding and the secondary winding are magnetically coupled to each other, and rectifies the secondary current induced in the secondary winding of the transformer. A rectifier circuit for charging and supplying the cell module,
The primary winding of each transformer is connected to a resonance current generating circuit.
The resonance current generation circuit includes a resonance circuit composed of an inductor and a capacitor, and a switching element that performs resonance driving by applying a pulse to a power supply for balance correction in the resonance circuit, and generates a resonance current generated every time the pulse is supplied to each transformer. Distributed to the primary windings of
A charge balance correction circuit for a multi-series storage cell.   2. The charge balance correction circuit for a multi-series storage cell according to claim 1, wherein the resonance current generated by the resonance current generation circuit is distributed to the primary winding of each transformer by a common wiring.   3. The charge balance correction circuit according to claim 1, wherein the resonance current generation circuit is configured using a series resonance circuit including an inductor and a capacitor.   4. The method according to claim 1, wherein when the voltages of the modules are equal to each other, the same reference voltage as the intermediate voltage expected to appear at the connection point between the modules is divided by the resistance voltage of the output voltage of the multi-series storage cell. And a difference detection circuit for detecting an absolute value of a difference between the divided voltage of the voltage dividing circuit and an intermediate voltage corresponding to the divided voltage, and the detection output of the difference detection circuit is A charge balance correction circuit for a multi-series storage cell, which is fed back to a pulse control circuit.   5. The multi-series power storage according to claim 4, wherein the difference detection circuit proportionally detects an absolute value difference between the divided voltage of the voltage dividing circuit and an intermediate voltage corresponding to the divided voltage with a predetermined amplification gain. Cell charge balance correction circuit.   6. The multi-series storage cell charge balance correction circuit according to claim 1, wherein the output of the multi-series storage cell is used as a power source for balance correction of the multi-series storage cell.

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