JP2011040888A - Semiconductor electronic circuit, transmission circuit, and flip-flop circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor electronic circuit which achieves a high-fast driving, and has FETs capable of being easily manufactured in one and the same process by being composed of the same depletion type transistors and obtaining superior output characteristics, even when generated at low temperature. <P>SOLUTION: A digital circuit 100 includes: a level shift circuit unit 110 consisting of two depletion type FETs to shift the voltage level of an input voltage in the negative direction; and an inverter circuit unit 120 consisting of two depletion type FETs to invert a logical output by using the input voltage subjected to level shifting. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor electronic circuit using a depletion type field effect FET and an oscillation circuit or flip-flop circuit using the same.

  2. Description of the Related Art In recent years, with the advancement of technologies related to semiconductor elements, various semiconductor electronic circuits are used in various electronic devices such as home appliances, communication systems, and computers regardless of analog or digital.

  Recently, each of the above electronic devices has been required to be downsized, sophisticated, and speeded up various processes, and the price has been required to be reduced. There is also a demand for the semiconductor electronic circuits that constitute them.

  In particular, such a semiconductor electronic circuit is desired to be easily manufactured and to have excellent output characteristics. For example, many semiconductor electronic circuits are constituted by a polysilicon TFT (Thin Film Transistor) or an oxide film TFT. It has become to.

  However, in these TFTs, the threshold voltage of the gate to which an external voltage is applied may be negative due to the influence of hysteresis or bias stress.

Usually, a TFT used in a semiconductor electronic circuit is driven by applying a voltage between 0 V and the maximum voltage of the power supply voltage V _DD to its gate. Even when a voltage of 0 V is applied, the TFT is driven, that is, the TFT is always turned on, and normal output characteristics cannot be obtained.

  For this reason, in recent semiconductor electronic circuits, the input voltage applied to the gate is shifted to the minus side to drive the TFT accurately and output normal circuit characteristics.

  Conventionally, there is known a current mirror circuit which is one of semiconductor electronic circuits for accurately driving a field effect transistor (hereinafter referred to as “FET (Field Effect Transistor)”) by shifting the level of such an input voltage to the minus side. (For example, Patent Document 1).

  This current mirror circuit is provided in the preceding stage of the depletion type FET when the gate voltage threshold of the FET becomes negative, that is, when the depletion type FET (hereinafter referred to as “depletion type FET”) is provided. The input voltage input from the outside is level-shifted to the minus side using an FET and a diode.

Japanese Patent Publication No. 6-3851

  However, in the above-described current mirror circuit, although the TFT can be operated by shifting the input voltage applied to the gate to the minus side, the enhanced type is used for the FET that performs the level shift. In manufacturing technology, it cannot be generated in the same process, and the semiconductor electronic circuit cannot be easily created.

  That is, in such a semiconductor electronic circuit, an enhancement type FET and a depletion type FET are configured by different processes. Therefore, it is difficult to produce the semiconductor electronic circuit easily and at low cost.

  In addition, when the gate insulating film in the FET such as a thermal oxide film TFT is generated at a low temperature by sputtering or the like, the film quality of the gate insulating film is deteriorated. Depending on the method of application, output characteristics at a positive voltage may deteriorate.

  In particular, when the oxide film TFT is generated at a lower temperature by printing or the like, it is more difficult for such an enhanced FET to obtain good output characteristics at a positive voltage.

  The present invention has been made in order to solve the above-mentioned problems, and the object thereof is to be able to be easily manufactured in the same process by being composed of the same depletion type transistor and to be produced at a low temperature. Another object of the present invention is to provide a semiconductor electronic circuit having an FET capable of obtaining excellent output characteristics and capable of being driven at high speed, and an oscillation circuit and a flip-flop circuit using the same.

  In order to solve the above problems, the invention described in claim 1 is composed of one or more transistors, and is composed of one or more level shift circuit units for shifting the voltage level of the input voltage, and one or more transistors. An electronic circuit unit that performs a predetermined logical operation using the shifted input voltage, and the level shift circuit unit and all of the transistors provided in the electronic circuit unit are depletion type, and the level The shifted input voltage is input to the gate of at least one transistor of the electronic circuit unit.

  With this configuration, according to the first aspect of the present invention, all the transistors can be configured as a depletion type, and a level-shifted input voltage can be applied to the gates of the transistors in the electronic circuit unit.

  Therefore, the invention according to claim 1 can shift the voltage level of the input voltage to a range in which the transistor in the electronic circuit unit is appropriately driven. Therefore, the depletion type transistor in which the threshold voltage at the gate is negative is provided. Even when used in an electronic circuit unit, an accurate logic output can be obtained based on a change in input voltage.

  As a result, the invention described in claim 1 can be easily manufactured in the same process, and can be driven at high speed even when it is generated at a low temperature, and good output characteristics can be obtained.

  According to a second aspect of the present invention, in the semiconductor electronic circuit according to the first aspect, the level shift circuit unit includes a first transistor and a second transistor, and the first transistor has the input voltage of A gate to be applied; a drain to which a first voltage having a predetermined value is applied; and a source connected to the gate and drain of the second transistor and connected to the input of the electronic circuit unit. The second transistor has a source to which a second voltage having a predetermined value is applied.

  With this configuration, the invention according to claim 2 can shift the voltage level of the input voltage according to the balance between the first voltage and the second voltage, so that, for example, the input voltage varies with the change in the second voltage. The voltage level shift amount can be changed.

  Therefore, the invention according to claim 2 can apply the input voltage appropriately level-shifted to the gate of the transistor in the electronic circuit unit.

  According to a third aspect of the present invention, in the semiconductor electronic circuit according to the second aspect, the amount of shift of the voltage level of the input voltage accompanying a change in the second voltage applied to the source of the second transistor. Has a configuration that changes.

  With this configuration, the invention according to claim 3 is configured such that even if there is a manufacturing variation in the gate voltage of the transistor in the level shift circuit unit, the voltage level of the input voltage varies with the change in the voltage level of the second voltage. Since the shift amount can be easily changed, an input voltage appropriately level-shifted can be applied to the gate of the transistor in the electronic circuit unit.

  According to a fourth aspect of the present invention, in the semiconductor electronic circuit according to the third aspect, a plurality of resistors for changing the value of the second voltage are connected to the source of the second transistor. have.

  With this configuration, the invention according to claim 4 can easily change the value of the second voltage by disconnecting the resistor with a laser or the like, for example. It can be easily changed.

  According to a fifth aspect of the present invention, in the semiconductor electronic circuit according to any one of the first to fourth aspects, the electronic circuit unit is composed of an n-type transistor, and the logic output is inverted. An inverter circuit is configured.

  With this configuration, the invention according to claim 5 can provide an inverter logic circuit that can be driven at high speed and can obtain good output characteristics even when generated at a low temperature. The process can be further simplified by using n-type transistors.

  According to a sixth aspect of the present invention, in the semiconductor electronic circuit according to the fifth aspect, the electronic circuit unit has a gate connected to an output of the level shift circuit unit, and the level shift circuit unit A third transistor that switches the potential of the external output terminal connected to the drain based on the output voltage that is output, a gate, a short circuit connection to the gate, and an external output terminal and the drain of the third transistor It has a configuration including a source, a drain to which a predetermined voltage is applied as a reference voltage, and a fourth transistor for adjusting a load of the reference voltage.

  With this configuration, the invention according to claim 6 can increase the on-resistance of the transistor by short-circuiting the gate and the source of the transistor that adjusts the load of the reference voltage in the inverter circuit. The potential of the external output terminal can be determined based on the on-resistance of the resistor.

  Therefore, when the on-resistance of the third transistor is extremely lower than that of the fourth transistor that adjusts the load of the reference voltage, the invention according to the sixth aspect of the present invention can be used when the third transistor is switched to the driving state. Since the output is steep from the high level to the low level, it is possible to obtain excellent output characteristics of the logic circuit.

That is, according to the sixth aspect of the present invention, the gate voltage of the transistor for adjusting the load of the reference voltage in the inverter circuit is linked to the source potential.

  According to a seventh aspect of the present invention, in the semiconductor electronic circuit according to any one of the first to fourth aspects, N level shift circuit units (N is a natural number not including “0”) are provided. The electronic circuit unit is composed of an n-type transistor and constitutes a NAND circuit that performs N-input NAND operation, and the output of each level shift circuit unit is the N input of the electronic circuit unit. Are connected to each other.

  With this configuration, the invention described in claim 7 can provide a NAND logic circuit that can be driven at high speed and can obtain good output characteristics even when generated at a low temperature. The process can be further simplified by using n-type transistors.

  According to an eighth aspect of the present invention, in the semiconductor electronic circuit according to the seventh aspect, the electronic circuit unit has a gate connected to an output of each level shift circuit unit, and the level shift circuit N third transistors for switching the potential of the external output terminal connected to the drain based on the output voltage output from the unit, the gate, a short circuit connection to the gate, the external output terminal, and any one of the above-mentioned A fourth transistor for adjusting a load of the reference voltage, the source including a source connected to a drain of the third transistor and a drain to which a predetermined voltage is applied as a reference voltage; The third transistor is arranged in series between the source of the fourth transistor and a ground reference potential.

  With this configuration, the invention according to claim 8 can increase the on-resistance of the transistor by short-circuiting the gate and the source of the transistor that adjusts the load of the reference voltage in the electronic circuit unit. The potential of the external output terminal can be determined based on the high on-resistance.

  Therefore, according to the eighth aspect of the present invention, when the on-resistance of the third transistor is extremely lower than that of the fourth transistor for adjusting the load of the reference voltage, the output of the inverter circuit is switched to the driving state of the third transistor. At this time, the output level of the logic circuit of the electronic circuit unit can be obtained because the output level is steep from the High level to the Low level.

  As a result, the invention according to claim 8 can provide a NAND logic circuit capable of obtaining good output characteristics.

  According to a ninth aspect of the present invention, in the semiconductor electronic circuit according to any one of the first to fourth aspects, N (N is a natural number not including “0”) N level shift circuit units are provided. The electronic circuit unit is configured by an n-type transistor and constitutes a NOR circuit that performs a negative OR output of N inputs, and an output of each level shift circuit unit is an N input of the electronic circuit unit. Are connected to each other.

  With this configuration, the invention described in claim 9 can provide a NOR logic circuit that can be driven at high speed and can obtain good output characteristics even when generated at a low temperature. The process can be further simplified by using n-type transistors.

  The invention according to claim 10 is the semiconductor electronic circuit according to claim 9, wherein the electronic circuit unit has a gate connected to an output of each level shift circuit unit, and the level shift circuit N third transistors for switching the potential of the external output terminal connected to the drain based on the output voltage output from the unit, a gate, a short circuit connection to the gate, and the external output terminal and the N number of the first transistors. A third transistor having a source connected to each drain of the three transistors and a drain to which a predetermined voltage is applied as a reference voltage, and for adjusting a load of the reference voltage; The third transistor is arranged in parallel between the drain of the fourth transistor and the ground reference potential.

  With this configuration, the invention according to claim 10 can increase the on-resistance of the transistor by short-circuiting the gate and the source of the transistor that adjusts the load of the reference voltage in the electronic circuit unit. The potential of the external output terminal can be determined based on the high on-resistance.

  Therefore, in the invention according to claim 10, when the on-resistance of the third transistor is extremely lower than that of the fourth transistor for adjusting the load of the reference voltage, the output of the inverter circuit is switched to the driving state of the third transistor. At this time, the output level of the logic circuit of the electronic circuit unit can be obtained because the output level is steep from the High level to the Low level.

  As a result, the invention according to claim 10 can provide a NOR logic circuit capable of obtaining good output characteristics.

  In order to solve the above problem, the invention described in claim 11 is such that M semiconductor logic circuits (M is an odd natural number not including “0”) are connected in series and are connected in series to the final stage. An output circuit in which an output of a connected semiconductor logic circuit is fed back to an input of a leading semiconductor logic circuit, and the semiconductor logic circuit is composed of one or more transistors and shifts the voltage level of the input voltage And a level shift circuit unit that includes one or more transistors, and an inverter circuit unit that inverts the logic output using the level-shifted input voltage, and is provided in the level shift circuit unit and the inverter circuit unit. All of the transistors are depletion type and N type, and the level-shifted input voltage is Serial has a configuration which is input to the gate of at least one said transistor of the inverter circuit unit.

  With this configuration, the invention according to claim 11 can configure all the transistors in a depletion type, and can apply a level-shifted input voltage to the gates of the transistors in the inverter circuit unit.

  Therefore, the invention according to claim 11 can shift the voltage level of the input voltage input to each inverter circuit unit. Therefore, a depletion type transistor having a negative threshold voltage at the gate is provided in the inverter circuit unit. Even if it is used, an accurate output can be obtained based on the change in the input voltage.

  As a result, the invention according to claim 11 can provide a ring oscillator that can be driven at high speed and can obtain good output characteristics even when generated at a low temperature.

  In order to solve the above problem, the invention described in claim 12 is a flip-flop circuit including a plurality of inverter circuits and a plurality of NOR circuits, and each of the inverter circuits includes one or more inverter circuits. A first level shift circuit unit configured to shift the voltage level of the input voltage, and an inverter circuit unit configured to invert the logic output using the level-shifted input voltage. The level-shifted input voltage is input to the gate of at least one of the transistors of the inverter circuit unit, and each NOR circuit is provided for each input and is configured of one or more transistors. A plurality of second level shift circuit units that shift voltage levels, and N inputs (N is “0”) NOR circuit unit that performs a negative OR output of a natural number that does not include the output of each of the second level shift circuit units connected to an N input of the electronic circuit unit, All of the transistors provided in the plurality of NOR circuits are of a depletion type and an N type.

  With this configuration, the invention according to claim 12 can configure all the transistors in a depletion type, and can apply an input voltage level-shifted to the gates of the transistors in the inverter circuit unit and the NOR circuit unit.

  Therefore, the invention according to claim 12 can shift the voltage level of the input voltage inputted to the range in which the transistors in the inverter circuit unit and the NOR circuit unit are appropriately driven. Even if a negative depletion type transistor is used in the inverter circuit unit and the NOR circuit unit, an accurate logic output can be obtained based on the change in the input voltage.

  As a result, the invention described in claim 12 can provide a flip-flop circuit that can be driven at high speed and can obtain good output characteristics even when generated at a low temperature.

  In order to solve the above-mentioned problem, the invention according to claim 13 is composed of one or more transistors, a level shift circuit unit for shifting the voltage level of the input voltage, and one or more transistors, and the level shift. An amplification circuit unit that performs inverting amplification of the input voltage, and the level shift circuit unit and all of the transistors provided in the amplification circuit unit are depletion type, and the level shifted input voltage is The amplifier circuit unit is configured to be input to the gate of at least one of the transistors.

  With this configuration, the invention according to claim 13 can configure all the transistors in a depletion type, and can apply a level-shifted input voltage to the gates of the transistors in the amplifier circuit unit.

  Therefore, the invention according to claim 13 can shift the voltage level of the input voltage that is input to the range in which the transistor in the amplifier circuit unit is appropriately driven. Even if the type transistor is used in the amplifier circuit unit, an accurate output can be obtained based on the change in the input voltage.

  As a result, the invention described in claim 13 can provide an amplifier circuit that can be driven at high speed and can obtain good output characteristics even when generated at a low temperature.

  Since the present invention can shift the voltage level of the input voltage to a range in which the transistor in the electronic circuit unit is appropriately driven, a depletion type transistor having a negative threshold voltage at the gate is used in the electronic circuit unit. In addition, an accurate logic output can be obtained based on the change of the input voltage.

  Therefore, it can be easily manufactured in the same process, and even when it is generated at a low temperature, high-speed driving is possible and good output characteristics can be obtained.

1 is a block diagram showing a configuration of a first embodiment of a digital circuit (inverter circuit) according to the present invention. It is a block diagram which shows the structure of a general inverter circuit. It is a figure for demonstrating a general inverter circuit, (a) is a graph which shows the characteristic of the input voltage _VIN -drain current _ID of a general inverter circuit, and (b) is general It is a graph which shows the output characteristic of the voltage in an inverter circuit. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram (I) for explaining the problem of the present invention, in which (a) shows an input voltage V _IN −drain current _ID of a general inverter circuit when a threshold value of a gate voltage is shifted to a negative value; The graph which shows a characteristic, and (b) are the graphs which show the output characteristic of the voltage in the general inverter circuit at that time. FIG. 2 is a diagram (II) for explaining the problem of the present invention, in which (a) is a graph showing voltage input / output characteristics in a general inverter circuit, and (b) is a graph showing the gate voltage in FIG. It is a graph which shows the input-output characteristic of the voltage in a general inverter circuit when a threshold value shifts to minus. It is a figure for demonstrating the flow of the voltage pulse of the digital circuit of 1st Embodiment. It is a graph which shows the voltage characteristic of the output voltage _VOUT output from the digital circuit of 1st Embodiment, and the input voltage Vm input into an inverter circuit unit. It is a figure which shows the output characteristic at the time of adjusting the size of the transistor in the level shift circuit unit of the digital circuit of 1st Embodiment. It is the other example (I) of the block diagram of the digital circuit in 1st Embodiment. It is a graph which shows the characteristic of the input-output voltage in the digital circuit shown in FIG. In the digital circuit according to the first embodiment, the voltage input / output characteristics of the level shift circuit unit when the power supply voltage _VSS is changed are shown. It is the other example (II) of the block diagram of the digital circuit in 1st Embodiment. It is a block diagram which shows the structure of 2nd Embodiment of the digital circuit (NAND circuit) based on this invention. It is a block diagram which shows the structure of 3rd Embodiment of the digital circuit (NOR circuit) which concerns on this invention. It is a block diagram which shows the structure of embodiment (4th Embodiment) of the ring oscillator circuit based on this invention. It is a graph which shows the output characteristic of the ring oscillator comprised by connecting several digital circuit (inverter circuit) of 5 stages, 7 stages, and 9 stages in 4th Embodiment. It is a block diagram which shows the structure of embodiment (5th Embodiment) of the D type flip-flop circuit based on this invention. It is a graph which shows the input-output characteristic of the D-type flip-flop circuit in 5th Embodiment. It is a block diagram which shows embodiment (6th Embodiment) structure of the analog circuit (amplifier circuit) which concerns on this invention.

  Hereinafter, embodiments of the present application will be described with reference to the drawings.

  The embodiment described below constitutes an electronic circuit as a digital circuit composed of a level shift circuit unit and an inverter circuit unit, a ring oscillator and a D-type flip-flop circuit composed of the digital circuit, and an amplifier circuit. In this embodiment, the semiconductor electronic circuit, the transmission circuit, and the flip-flop circuit of the present invention are applied to an electronic circuit as an analog circuit.

[First Embodiment]
First, a first embodiment of an electronic circuit (digital circuit) according to the present invention will be described with reference to FIGS.

  First, a schematic configuration and a characteristic point of a digital circuit (inverter circuit) including a level shift circuit unit and an inverter circuit unit according to the present embodiment will be described with reference to FIGS.

  FIG. 1 is a block diagram illustrating a configuration of a digital circuit (inverter circuit) including a level shift circuit unit and an inverter circuit unit in the present embodiment, and FIG. 2 is a block diagram illustrating a configuration of a general inverter circuit. It is.

FIG. 3 is a diagram for explaining a general inverter circuit. FIG. 3A is a graph showing characteristics of the input voltage V _IN −drain current _ID of the general inverter circuit, and (b) ) Is a graph showing voltage output characteristics in a general inverter circuit.

FIG. 4 is a diagram (I) for explaining the problem of the present invention. FIG. 4A is a diagram showing an input voltage V _IN −drain current of a general inverter circuit when the threshold voltage of the gate voltage is shifted. The graph showing the characteristic of _ID and (b) are the graphs showing the output characteristic of the voltage in the general inverter circuit at that time.

  Further, FIG. 5 is a diagram (II) for explaining the problem of the present invention, (a) is a graph showing input / output characteristics of voltage in a general inverter circuit, and (b) is FIG. 4 is a graph showing voltage input / output characteristics in a general inverter circuit when the gate voltage threshold value is shifted to minus.

  As shown in FIG. 1, the digital circuit 100 according to the present embodiment includes two depletion type FETs, and includes a level shift circuit unit 110 that shifts the voltage level of the input voltage in the negative direction and two depletion type FETs. And an inverter circuit unit 120 that inverts the logic output using the level-shifted input voltage.

  For example, the level shift circuit unit 110 of the present embodiment constitutes the level shift circuit unit 110 of the present invention, and the inverter circuit unit 120 constitutes the logic circuit unit of the present invention.

  In general, an enhanced FET deteriorates the quality of a gate insulating film when manufactured at a low temperature, and cannot provide good output characteristics at an applied voltage.

  Therefore, even in such a case, it is desired to use a depletion type FET that can be driven at high speed and has good output characteristics for a digital circuit such as an inverter circuit.

  However, since the depletion type FET has a negative gate voltage threshold value, even if an input voltage is accurately applied to the gate, depending on how the voltage is applied, good output characteristics can be obtained in the FET. I can't.

  For example, in the inverter circuit shown in FIG. 2, as shown in FIG. 3A, a pulsed positive input voltage (for example, a pulse voltage having a minimum voltage of 0 V and a maximum voltage of +10 V. As shown in FIG. When the threshold voltage of the gate of the FET exists on the positive side, the inverter circuit has an output characteristic as shown in FIG. 3B. become.

  However, when the threshold voltage of the gate of the transistor to which the input voltage is applied is shifted to the negative side in this inverter circuit as shown in FIG. Even if a pulsed positive input voltage (0V− + 10V) is input, the switching operation at the gate of the FET does not move properly, so this inverter circuit has an output characteristic as shown in FIG. Therefore, it cannot be said that it is driving properly.

  For example, as shown in FIG. 5 (b), when the gate threshold voltage becomes negative as shown in FIG. 5 (b), compared to when the gate threshold voltage shown in FIG. When a voltage (0 V− + 10 V) is applied, it is not possible to obtain better inverter dynamic characteristics than in a normal case.

  Therefore, in this embodiment, in order to drive the inverter circuit unit 120 accurately, the level shift circuit unit 110 that shifts the input voltage to the inverter circuit unit 120 to the minus side in accordance with the threshold voltage of the gate is provided. In addition, the inverter circuit unit 120 is configured by a depletion type FET, and can be driven at high speed, and the digital circuit 100 having good output characteristics is provided.

  Next, specific configurations and operations of the level shift circuit unit 110 and the inverter circuit unit 120 of this embodiment will be described with reference to FIGS. 6 and 7 together with FIG.

6 is a diagram for explaining the flow of voltage pulses of the digital circuit 100 of the present embodiment, and FIG. 7 shows the output voltage _VOUT output from the digital circuit 100 of the present embodiment and the inverter circuit unit. 12 is a graph showing voltage characteristics of an input voltage Vm input to 120.

  As shown in FIG. 1, the level shift circuit unit 110 of the present embodiment shifts the voltage level of the input voltage input via the input terminal 10 in the negative direction and outputs it to the inverter circuit unit 120. ing.

  The level shift circuit unit 110 includes two n-type FETs, a first n-type FET 111 and a second n-type FET 112, which can be manufactured by the same process.

  The first n-type FET 111 is a depletion type FET, and is constituted by a polysilicon TFT, an oxide TFT, or an organic transistor, and includes a channel having a width of 100 μm and a length of 10 μm, for example.

The first n-type FET 111 is connected to the input terminal 10, connected to the gate to which the input voltage is applied, the drain connected to the power supply voltage V _DD , the gate and the drain of the second n-type FET 112, and And a source connected to an output terminal in the level shift circuit unit 110 (that is, an input terminal of the inverter circuit unit 120).

In the present embodiment, the power supply voltage V _DD has a predetermined voltage value determined in advance. For example, a voltage of +10 V is applied to the drain of the first n-type FET 111.

  Similar to the first n-type FET 111, the second n-type FET 112 is a depletion type FET, and is constituted by a polysilicon TFT, an oxide TFT, or an organic transistor. For example, the channel has a width of 100 μm and a length of 10 μm. It has.

The second n-type FET 112 is connected to the source of the first n-type FET, connected to the output terminal 20 in the level shift circuit unit 110, and drain connected to the gate and the source of the first n-type FET 111 in a short circuit. And a source connected to the power supply voltage V _SS (−6 V).

  The inverter circuit unit 120 of the present embodiment inverts the logic output based on the input voltage input from the input terminal 10 based on the voltage output from the level shift circuit unit 110 and outputs the result to the output terminal 20. Yes.

  The inverter circuit unit 120 includes two n-type FETs, a third n-type FET 121 and a fourth n-type FET 122, which can be manufactured by the same process as the first n-type FET 111 and the second n-type FET 112 in the level circuit unit.

  The third n-type FET 121 is a depletion type FET, similar to the first n-type FET 111 and the second n-type FET 112, and is composed of a polysilicon TFT, an oxide TFT, or an organic transistor, and has a width of 100 μm and a thickness of 10 μm, for example. A channel having a length is provided.

  The third n-type FET 121 includes a gate to which the voltage output from the level shift circuit unit 110 is applied, a drain connected to the output terminal 20, and a source grounded to the ground.

  Similar to the first n-type FET 111, the second n-type FET 112, and the third n-type FET 121, the fourth n-type FET 122 is a depletion type FET, and is configured by a polysilicon TFT, an oxide TFT, or an organic transistor, and has a thickness of 100 μm, for example. A channel having a width and a length of 10 μm is provided.

The fourth n-type FET 122 includes a gate connected to the output terminal 20, a drain connected to the power supply voltage V _DD , a short-circuit connected to the gate, and a source connected to the output terminal 20 together with the gate. Composed.

In the present embodiment, the power supply voltage V _DD has a predetermined voltage value as in the level shift circuit unit 110. For example, the drain of the fourth n-type FET 122 has a voltage of + 10V. Is to be applied to.

Further, the power supply voltage V _DD may be applied from the same power source or may be applied from different power sources.

  Thus, as shown in FIG. 6, the digital circuit 100 of the present embodiment shifts the voltage level of the input voltage to the minus side to lower the voltage level of the input voltage to the inverter circuit unit 120 and has good characteristics. Is output.

The graph shown in FIG. 7, the power supply voltage _{V DD} + 10V, and the power supply voltage _{V SS} is -6V, 0V- + 10V input voltage Vm of inverter circuit unit 120 when the pulsed input voltage is input The output voltage V _OUT of the digital circuit 100 obtained at the output terminal 20 is shown.

This graph shows that the level of the input voltage Vm input to the inverter circuit unit 120 is shifted to the negative side, and that the output voltage _VOUT has an appropriate inverter output. Has been shown to drive properly.

  As described above, the digital circuit 100 according to the present embodiment can shift the voltage level of the input voltage to a range where the FET (specifically, the third n-type FET 121) in the inverter circuit unit 120 is appropriately driven. Even if a depletion type FET having a negative threshold voltage at the gate is used for the inverter circuit unit 120, an accurate output can be obtained based on a change in the input voltage.

  Therefore, the digital circuit 100 according to the present embodiment can configure all the FETs in a depletion type, so that it can be easily manufactured in the same process, can be driven at a high speed, and has good output characteristics. be able to.

  In particular, the digital circuit 100 according to the present embodiment can be driven at high speed even when it is generated at a low temperature such as printing, and can obtain good output characteristics. The process can be further simplified by using an n-type FET.

  Further, the digital circuit 100 according to the present embodiment can increase the on-resistance of the transistor by short-circuiting the gate and the source of the FET (specifically, the fourth n-type FET 122) in the inverter circuit unit 120. Therefore, the potential of the output terminal 20 can be determined based on this high on-resistance.

  That is, in the digital circuit 100 according to the present embodiment, the on-resistance of the third n-type FET is extremely lower than that of the fourth nFET that adjusts the load of the reference voltage, and the output of the digital circuit 100 is obtained when the third transistor is switched to the driving state. In addition, since it is steep from the High level to the Low level, it is possible to obtain good output characteristics.

  Note that the output characteristics of the digital circuit 100 can be adjusted by changing the transistor size of the second FET 112 in the level shift circuit unit of the present embodiment.

  For example, as shown in FIG. 8, in this embodiment, the channel of the second FET 112 is (A) 50 μm wide and 10 μm long, (B) 100 μm wide, 10 μm (C) 150 μm wide, and 10 μm long. When set to this value, the characteristics shown in the respective graphs can be obtained.

  Next, a modified example of the digital circuit 100 according to the present embodiment will be described with reference to FIGS.

  FIG. 9 is another example (I) of the block diagram of the digital circuit 100 in the first embodiment, and FIG. 10 is a graph showing the input / output voltage characteristics in the digital circuit 100 shown in FIG.

FIG. 11 is a diagram showing the input / output characteristics of the voltage in the level shift circuit unit 110 when the power supply voltage _VSS changes in the digital circuit 100 in the first embodiment, and FIG. 12 shows the first embodiment. It is the other example (II) of the block diagram of the digital circuit 100 in FIG.

  In the digital circuit 100 of the present embodiment, the FET of the inverter circuit unit 120, specifically, the gate of the fourth n-type FET 123 is connected to the source thereof, but as shown in FIG. It may be connected to the drain.

  Even in this case, the digital circuit 100 has good output characteristics as shown in FIG. However, in this case, the third n-type FET 121 has a channel having a width of 150 μm and a length of 10 μm, and the fourth n-type FET 123 has a channel having a width of 10 μm and a length of 10 μm. I have.

Further, in this embodiment, the power supply voltage _{V SS} is set to -6 V, for example, 0V, -5V, may be set to the voltage of -10V and -15V.

That is, the digital circuit 100 of the present embodiment, as shown in FIG. 11, based on the voltage value of the power supply voltage _{V SS} is applied to the source of the 2n-type FET 112, changes the output characteristic in the level shift circuit unit 110 since, the input voltage may be adjusted supply voltage _{V SS} based on the power supply voltage _{V DD} and the voltage characteristic of the 1n type FET111 and second 2n-type FET 112.

Further, in the present embodiment, although the power supply voltage V _SS is adapted to be directly applied to the source of the 2n-type FET 112, as shown in FIG. 12, between the power supply voltage V _SS and the source After the plurality of resistors R1 and R2 are connected and the level shift circuit unit 110 is generated, the connection of the resistors R1 and R2 is changed based on the characteristics of the generated level shift circuit unit 110 to change the power supply voltage. adjust the V _SS, i.e., may be adjusted to supply voltage _{V SS} by thinning out the resistors R1, R2.

[Second Embodiment]
Next, a second embodiment of the electronic circuit (digital circuit) according to the present invention will be described with reference to FIG.

  The digital circuit of the present embodiment is a NAND circuit that performs a NAND operation of N inputs (N is a natural number not including “0”) 1 output, and the level shift circuit unit in the first embodiment is provided for each input. There is a feature that a NAND circuit unit is provided instead of the inverter circuit unit.

  In addition, the NAND circuit unit of the present embodiment has another configuration in which a plurality of the third n-type FETs of the first embodiment are arranged in series between the source of the fourth n-type FET and the ground reference potential. Has the same configuration as the inverter circuit unit of the first embodiment.

  In the present embodiment, the same members as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  Next, the configuration of the digital circuit (NAND circuit) 200 of this embodiment will be described with reference to FIG. FIG. 13 is a block diagram showing the configuration of the digital circuit (NAND circuit) 200 in this embodiment.

  As shown in FIG. 13, the digital circuit 200 of the present embodiment is a NAND circuit that performs, for example, a NAND operation of three inputs and one output, and includes a first level shift circuit unit 110-1 provided at each input, The second level shift circuit unit 110-2 and the third level shift circuit unit 110-3, and a NAND circuit unit 130 that performs a NAND operation based on each input voltage whose level is shifted. .

  As in the first embodiment, each of the first, second, and third level shift circuit units 110 uses the first input terminal 10-1, the second input terminal 10-2, and the third input terminal 10-3, respectively. The input level of each input voltage input via the input is shifted to the minus side and output to the NAND circuit unit 130.

  Each of the first, second, and third level shift circuit units 110 includes two n-type FETs, a first n-type FET 111 and a second n-type FET 112, which can be manufactured by the same process, as in the first embodiment. Consists of

  The NAND circuit unit 130 outputs, to the output terminal 20, a NAND operation result based on a three-input input voltage based on each voltage output from the first, second, and third level shift circuit units 110. It has become.

The NAND circuit unit 130 includes three third n-type FETs 121 corresponding to the respective inputs, and a single fourth n-type FET 122 for adjusting the load of the power supply voltage V _DD .

  Each third n-type FET 121 is arranged in series between the source of the fourth n-type FET 122 and the ground reference potential.

  Each of the third n-type FETs 121 has a gate connected to the output of each level shift circuit unit 110, and the corresponding drain-source is connected based on the output voltage output from each level shift circuit unit 110. Energized.

The fourth n-type FET 122 has a gate, a source that is short-circuited to the gate and connected to the output terminal 20 and the drain of one third n-type FET 121, a drain to which the power supply voltage V _DD is applied as a reference voltage, And is used to adjust the load of the power supply voltage V _DD .

  As described above, the digital circuit 200 according to this embodiment can shift the voltage level of the input voltage to a range in which each FET (specifically, each third n-type FET 121) in the inverter circuit unit 120 is appropriately driven. Therefore, even if a depletion type transistor having a negative threshold voltage at the gate is used for the NAND circuit unit 130, an accurate logic output can be obtained based on a change in the input voltage.

  Therefore, since the digital circuit 200 of this embodiment can configure all the FETs in a depletion type, it can be easily manufactured in the same process, can be driven at a high speed, and has good output characteristics. be able to.

  In particular, the digital circuit 200 of the present embodiment can be driven at high speed even when it is generated at a low temperature such as printing, and can obtain good output characteristics. The process can be further simplified by using an n-type FET.

  Further, the digital circuit 200 of the present embodiment can increase the on-resistance of the transistor by short-circuiting the gate and the source of the FET (specifically, the fourth n-type FET 122) in the inverter circuit unit 120. Therefore, the potential of the output terminal 20 can be determined based on this high on-resistance.

  That is, in the digital circuit 200 of the present embodiment, the on-resistance of each third n-type FET is extremely lower than that of the fourth nFET that adjusts the load of the reference voltage, and the output of the digital circuit 200 is that all the third transistors are in the drive state. When switching, the output level is steep from High level to Low level, so that excellent output characteristics can be obtained.

  Note that the digital circuit 200 of the present embodiment is configured to connect the FET of the NAND circuit unit 130, specifically, the gate of the fourth n-type FET 122 to the source thereof, but as in the first embodiment, The gate may be connected to the drain.

[Third Embodiment]
Next, a third embodiment of the electronic circuit (digital circuit) according to the present invention will be described with reference to FIG.

  The digital circuit of the present embodiment is a NOR circuit that performs a negative OR output of N inputs (N is a natural number not including “0”) 1 output, and the level shift circuit unit in the first embodiment is provided for each input. It is characterized in that a NOR circuit unit is provided instead of the inverter circuit unit.

  The NOR circuit unit according to the present embodiment has another configuration in which a plurality of third n-type FETs 121 according to the first embodiment are provided in parallel between the source of the fourth n-type FET 122 and the ground reference potential. Has the same configuration as the inverter circuit unit 120 of the first embodiment.

  In the present embodiment, the same members as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  Next, the configuration of the digital circuit (NOR circuit) 300 of this embodiment will be described with reference to FIG. FIG. 14 is a block diagram showing the configuration of the digital circuit (NOR circuit) 300 in this embodiment.

  As shown in FIG. 14, the digital circuit 300 according to the present embodiment is a NOR circuit that performs, for example, a three-input one-output NAND operation, and includes a first level shift circuit unit 110-1 provided at each input, The circuit includes a second level shift circuit unit 110-2 and a third level shift circuit unit 110-3, and a NOR circuit unit 140 that performs a NAND operation based on the level-shifted input voltage.

  Each of the first, second, and third level shift circuit units 110 is input through the first input terminal 10, the second input terminal 10, and the third input terminal 10, respectively, as in the first embodiment. The input level of the input voltage is shifted to the negative side and output to the NOR circuit unit 140.

  Each of the first, second, and third level shift circuit units 110 includes two n-type FETs, a first n-type FET 111 and a second n-type FET 112, which can be manufactured by the same process, as in the first embodiment. Consists of

  The NOR circuit unit 140 outputs, to the output terminal 20, an operation result of a negative OR based on the input voltage of three inputs based on each voltage output from the first, second, and third level shift circuit units 110. It has become.

The NOR circuit unit 140 includes three third n-type FETs 121 corresponding to the respective inputs and a single fourth n-type FET 122 for adjusting the load of the power supply voltage V _DD .

  Each third n-type FET 121 is disposed in parallel between the source of the fourth n-type FET 122 and the ground reference potential.

  Each of the third n-type FETs 121 has a gate connected to the output of each level shift circuit unit 110. Based on the output voltage output from each level shift circuit unit 110, the third n-type FET 121 is connected between the output terminal 20 and the grind ground. Are to be short-circuited.

The fourth n-type FET 122 includes a gate, a source that is short-circuited to the gate and connected to the output terminal 20 and the drain of each third n-type FET 121, and a drain to which the power supply voltage V _DD is applied as a reference voltage. , And is used to adjust the load of the power supply voltage V _DD .

  As described above, the digital circuit 300 according to the present embodiment can shift the voltage level of the input voltage to a range in which each FET (specifically, each third n-type FET 121) in the NOR circuit unit 140 is appropriately driven. Therefore, even if a depletion type transistor having a negative threshold voltage at the gate is used for the NOR circuit unit 140, an accurate logic output can be obtained based on a change in the input voltage.

  Therefore, the digital circuit 300 of the present embodiment can be configured with a depletion type of all the FETs, so that it can be easily manufactured in the same process, can be driven at high speed, and has good output characteristics. be able to.

  In particular, the digital circuit 300 according to the present embodiment can be driven at high speed even when it is generated at a low temperature such as printing, and can obtain good output characteristics. The process can be further simplified by using an n-type FET.

Further, the digital circuit 300 of the present embodiment can increase the on-resistance of the transistor by short-circuiting the gate and the source of the FET (specifically, the fourth n-type FET 122) in the inverter circuit unit 120. Therefore, the potential of the output terminal 20 can be determined based on this high on-resistance.
That is, in the digital circuit 300 of this embodiment, the on-resistance of each third n-type FET is extremely lower than that of the fourth nFET that adjusts the load of the reference voltage, and the output of the digital circuit 300 is switched to the driving state of each third transistor. In this case, the output level is steep from the high level to the low level, so that excellent output characteristics can be obtained.

  Note that the digital circuit 300 of the present embodiment is configured to connect the FET of the NOR circuit unit 140, specifically, the gate of the fourth n-type FET 122 to its source, but as in the first embodiment, The gate may be connected to the drain.

[Fourth Embodiment]
Next, an embodiment (fourth embodiment) of the ring oscillator according to the present invention will be described with reference to FIGS. 15 and 16.

  The ring oscillator of the present embodiment is characterized in that it is configured by connecting a plurality of digital circuits in the first embodiment in series, and each digital circuit has the same configuration as that of the first embodiment. Yes.

  In the present embodiment, the same members as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  Next, the configuration of the ring oscillator of this embodiment will be described with reference to FIGS. 15 and 16.

  FIG. 15 is a block diagram showing the configuration of the ring oscillator (9 stages) in this embodiment, and FIGS. 16 (a), (b) and (c) are a plurality of stages of 5, 7, and 9 stages. It is a graph which shows the output characteristic of the ring oscillator comprised by connecting this digital circuit (inverter circuit).

  As shown in FIG. 15, the ring oscillator 400 circuit of the present embodiment includes a transmission circuit unit 410 configured by an odd number of digital circuits 100 connected in series, and a buffer circuit unit 420.

  The transmission circuit unit 410 is configured by, for example, nine odd-numbered digital circuits 100 connected in series, and the output of the digital circuit 100-9 connected in series at the final stage is the first digital. Feedback is made to the input of the circuit 100-1.

  In particular, each digital circuit 100 of the present embodiment receives a voltage input to the ring oscillator 400 or output from the preceding digital circuit 100, and the digital circuit 100-9 connected in series to the final stage includes: The output is output to the leading digital circuit 100-1 and the buffer circuit section 420.

  Note that the ring oscillator 400 of the present embodiment only needs to connect an odd number of digital circuits 100 such as five stages or seven stages in series.

  The buffer circuit unit 420 basically includes the digital circuit 100 similar to that of the first embodiment. However, each FET of the buffer circuit section 420 of the present embodiment has a channel width that is about 10 times larger than each FET of the digital circuit 100 of the first embodiment.

  Note that the FET of the buffer circuit of the present embodiment is required to have a value about 10 times the channel width of each FET of the digital circuit 100 of the first embodiment. If each value of is more than twice the channel width of each FET of the digital circuit 100 of the first embodiment, the ring oscillator 400 of this embodiment can be implemented.

  As described above, in the present embodiment, the ring oscillator 400 is configured by connecting in series a plurality of inverter circuits each composed of an appropriately driven depletion type n-type FET.

  16A is a graph showing the output characteristics of the ring oscillator 400 configured by connecting the five-stage inverter circuit 100, and FIG. 16B is a diagram illustrating connecting the seven-stage inverter circuit 100. FIG. 16C is a graph showing the output characteristics of the ring oscillator 400 configured by connecting the nine-stage inverter circuit 100. FIG.

  Each of FIGS. 16A, 16B, and 16C shows the output characteristic (A) of the ring oscillator 400 and the output characteristic (B) of the signal fed back to the leading inverter circuit. .

  In any ring oscillator 400, since the pulse waveforms that raise and lower the High and Low levels are accurately output, it is indicated that the ring oscillator of this embodiment is driven appropriately.

  As described above, the ring oscillator 400 of the present embodiment shifts the voltage level of the input voltage input to each inverter circuit unit 120 to a range in which the FET of the inverter circuit unit 120 in each digital circuit 100 is appropriately driven. Therefore, even if a depletion type FET having a negative threshold voltage at the gate is used for the inverter circuit unit 120, an accurate logic output can be obtained based on a change in the input voltage.

  Therefore, the ring oscillator 400 according to the present embodiment can be driven at high speed and can have good output characteristics even when generated at a low temperature by printing or the like.

[Fifth Embodiment]
Next, an embodiment (fifth embodiment) of a flip-flop circuit according to the present invention will be described with reference to FIGS.

  The flip-flop circuit of this embodiment is a D-type flip-flop circuit, and is characterized by being configured by a plurality of inverter circuits of the first embodiment and a plurality of NOR circuits of the fourth embodiment. The configuration is the same as that of the first embodiment or the fourth embodiment.

  In the present embodiment, the same members as those in the first embodiment or the fourth embodiment are denoted by the same reference numerals and the description thereof is omitted.

  Next, the configuration of the D-type flip-flop circuit of this embodiment will be described with reference to FIGS. 17 and 18.

  FIG. 17 is a block diagram showing the configuration of the D-type flip-flop circuit in this embodiment, and FIG. 18 is a graph showing the input / output characteristics of the D-type flip-flop circuit in this embodiment.

  As shown in FIG. 17, the D-type flip-flop circuit 500 of the present embodiment includes six three-input NOR circuits 300 and four inverter circuits 100 provided at each input and output.

  A voltage as data in the flip-flop circuit is input to the first inverter circuit 100-1 via the first external input terminal TI-1, and the first inverter circuit 100-1 The output is output to the third NOR circuit 300-3.

  A voltage is input to the second inverter circuit 100-2 as a synchronization signal in the flip-flop circuit via the second external input terminal TI-2, and the second inverter circuit 100-2 The output is output to the second NOR circuit 300-2.

  The voltage as a reset signal in the flip-flop circuit is input to the third inverter circuit 100-3 via the third external input terminal T-3. The third inverter circuit 100-3 The output is output to the first NOR circuit 300-1.

  The output of the first input inverter circuit 100-1, the third input inverter circuit 100-3, and the second NOR circuit 300-2 is input to the first NOR circuit 300-1. .

  The first NOR circuit 300-1 outputs the result of the logical operation to the second NOR circuit 300-2.

  The output of the second input inverter circuit 100-2, the first NOR circuit 300-1, and the third NOR circuit 300-3 is input to the second NOR circuit 300-2.

  The second NOR circuit 300-2 outputs the result of the logical operation to the sixth NOR circuit 300-6 and the first NOR circuit 300-1.

  The output of the third input inverter circuit 100-3, the second input inverter circuit 100-2, and the fourth NOR circuit 300-4 is input to the third NOR circuit 300-3. .

  The third NOR circuit 300-3 outputs the result of the logical operation to the second NOR circuit 300-2 and the fourth NOR circuit 300-4.

  The fourth NOR circuit 300-4 has an input terminal grounded to the ground, and the fourth NOR circuit 300-5 receives the outputs of the first NOR circuit 300-1 and the third NOR circuit 300-3. It has become.

  Further, the fourth NOR circuit 300-4 outputs the result of the logical operation to the third NOR circuit 300-3.

  The fifth NOR circuit 300-5 has an input terminal grounded to the ground, and the fifth NOR circuit 300-5 receives the outputs of the third NOR circuit 300-3 and the sixth NOR circuit 300-6. It has become.

  The fifth NOR circuit 300-5 outputs the result of the logical operation to the sixth NOR circuit 300-6.

  The sixth NOR circuit 300-6 receives the outputs of the third inverter circuit 100-3, the second NOR circuit 300-2, and the fifth NOR circuit 300-5.

  The sixth NOR circuit 300-6 outputs the result of the logical operation to the fifth NOR circuit 300-5 and the output inverter circuit 100-4.

  The output from the sixth NOR circuit 300-6 is input to the output inverter circuit 100-4. The output inverter circuit 100-4 outputs the output to the outside via the external output terminal TO. It is supposed to be.

  As described above, in this embodiment, in order to configure each inverter circuit 100 and each NOR circuit 300 with each depression type n-type FET, the voltage level of the input voltage of each inverter circuit 100 and each NOR circuit 300 is shifted. Thus, the voltage level of the input voltage to the inverter circuit unit 120 in each inverter circuit 100 or the NOR circuit unit 140 in each NOR circuit 300 can be lowered.

  18A is a graph showing a pulse of a synchronization signal, FIG. 18B is a graph showing a pulse of data, FIG. 18C is a graph showing a pulse of a reset signal, and FIG. (D) is a graph showing an output pulse and a pulse input to the inverter circuit, and shows that the D-type flip-flop circuit 500 of the present embodiment is appropriately driven.

  As described above, the D-type flip-flop circuit 500 of the present embodiment has an input voltage that is input within a range in which the FETs of the inverter circuit unit 120 and the NOR circuit unit 140 in each inverter circuit 100 and each NOR circuit 300 are appropriately driven. Therefore, even if a depletion type FET having a negative threshold voltage at the gate is used for the inverter circuit unit 120 and the NOR circuit unit 140, an accurate logic based on the change of the input voltage can be obtained. Output can be obtained.

  Therefore, the D-type flip-flop circuit 500 of the present embodiment can be driven at high speed and can obtain good output characteristics even when generated at a low temperature by printing or the like.

  The D-type flip-flop circuit 500 of the present embodiment is configured by the inverter circuit 100 and the NOR circuit 300, but of course, the D-type flip-flop circuit 500 may be configured by using the NAN 100 circuit of the second embodiment.

[Sixth Embodiment]
Next, a sixth embodiment of an electronic circuit (analog circuit) constituting the amplifier circuit according to the present invention will be described with reference to FIG.

  In the amplifier circuit of this embodiment, an analog signal (voltage) is input instead of the point that the fourth n-type FET 122 in the inverter circuit 100 is changed to a resistor in the first embodiment and the point that a digital pulse is input. The other features are the same as those in the first embodiment.

  For example, the amplifier circuit according to the present embodiment is a source-grounded amplifier circuit connected to a subsequent stage of a differential amplifier circuit in an operational amplifier, for example, and amplifies the signal level of the differentially amplified signal.

  In the present embodiment, the same members as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  Next, the configuration of the amplifier circuit (source grounded amplifier circuit) of this embodiment will be described with reference to FIG. FIG. 19 is a block diagram showing the configuration of the amplifier circuit (source grounded amplifier circuit) in this embodiment.

  As shown in FIG. 19, the analog circuit 600 of the present embodiment is, for example, a grounded source amplifier circuit used in an amplification part of an operational amplifier, and a level shift circuit to which a voltage output from an operational amplifier circuit of the operational amplifier is input The unit 110 includes an amplification circuit unit 610 that performs inverting amplification based on an input voltage whose level is shifted.

  As in the first embodiment, the level shift circuit unit 110 shifts the input level of each input voltage input via the input terminal 10 to the minus side and outputs it to the amplifier circuit unit 610.

  The amplifier circuit unit 610 of this embodiment includes a third n-type FET 611 and an amplifier circuit resistor 612 that can be manufactured in the same process as the first n-type FET 111 and the second n-type FET 112 in the level shift circuit unit 110.

  Similar to the first n-type FET 111 and the second n-type FET 112, the third n-type FET 611 is a depletion type FET, and is configured by a polysilicon TFT, an oxide TFT, or an organic transistor.

  The third n-type FET 611 includes a gate to which the voltage output from the level shift circuit unit 110 is applied, a drain connected to the output terminal 20, and a source grounded to the ground.

The amplifier circuit resistor 612 is composed of an n-type diffused resistor and is connected between the power supply voltage V _DD and the output terminal 20.

  As described above, the analog circuit 600 of the present embodiment can shift the voltage level of the input voltage to a range in which the FET (specifically, the third n-type FET 611) in the amplifier circuit unit 610 is appropriately driven. Even if a depletion type transistor having a negative threshold voltage at the gate is used for the amplifier circuit unit 610, accurate amplification can be performed based on a change in the input voltage.

  Therefore, the analog circuit 600 of the present embodiment can be configured with a depletion type of all FETs, so that it can be easily manufactured in the same process, can be driven at high speed, and has good output characteristics. be able to.

  In particular, the analog circuit 600 of the present embodiment can be driven at high speed and can have good output characteristics even when generated by a low temperature such as printing, and is depletion type for all FETs and n The process can be further simplified by using a type FET.

  In the level shift circuit unit 110 of this embodiment, the gate of the second n-type FET 112 is short-circuited to the drain thereof, but the gate of the second n-type FET 112 is connected to the second input terminal 10 connected to the outside. You may make it connect.

  For example, when the analog circuit of the present embodiment is an amplifier circuit used for an operational amplifier, it may be connected to an arbitrary external power supply voltage.

In this case, the transistor itself, which is connected to any supply voltage, i.e., if the present embodiment, since the 1n-type FET acts as a variable resistor, the amplifier circuit unit without varying the supply voltage V _SS The voltage input to the gate of the third-type FET 611 of 610 can be adjusted.

R1, R2 ... Resistor TI ... External input terminal TO ... External output terminal 10 ... Input terminal 20 ... Output terminal 100 ... Digital circuit (inverter circuit)
110 ... Level shift circuit unit 111 ... 1st n-type FET
112 ... 2nd n-type FET
120: Inverter circuit 121: Third n-type FET
122, 123 ... 4th n-type FET
130 ... NAND circuit unit 140 ... NOR circuit unit 200 ... Digital circuit (NAND circuit)
300 ... Digital circuit (NOR circuit)
400 ... Ring oscillator 410 ... Transmission circuit section 420 ... Buffer circuit section 500 ... D-type flip-flop circuit 600 ... Analog circuit (amplifier circuit)

Claims (13)

One or more level shift circuit units configured by one or more transistors to shift the voltage level of the input voltage;
An electronic circuit unit composed of one or more transistors and performing a predetermined logic operation using a level-shifted input voltage;
With
All of the transistors provided in the level shift circuit unit and the electronic circuit unit are depletion type, and the level-shifted input voltage is input to the gate of at least one of the transistors in the electronic circuit unit. A semiconductor electronic circuit. The semiconductor electronic circuit according to claim 1,
The level shift circuit unit includes a first transistor and a second transistor;
The first transistor is
A gate to which the input voltage is applied;
A drain to which a first voltage having a predetermined value is applied;
A source connected to the gate and drain of the second transistor and connected to the input of the electronic circuit unit;
Consisting of
The semiconductor electronic circuit, wherein the second transistor has a source to which a second voltage having a predetermined value is applied. The semiconductor electronic circuit according to claim 2,
A semiconductor electronic circuit, wherein a shift amount of a voltage level of the input voltage changes with a change of the second voltage applied to a source of the second transistor. The semiconductor electronic circuit according to claim 3.
A semiconductor electronic circuit, wherein a plurality of resistors for changing a value of the second voltage are connected to a source of the second transistor. The semiconductor electronic circuit according to any one of claims 1 to 4,
A semiconductor electronic circuit, wherein the electronic circuit unit includes an n-type transistor and forms an inverter circuit that inverts a logic output. The semiconductor electronic circuit according to claim 5, wherein
The electronic circuit unit is
A third transistor having a gate connected to the output of the level shift circuit unit and switching the potential of the external output terminal connected to the drain based on the output voltage output from the level shift circuit unit;
A reference voltage load having a gate, a source short-circuited to the gate and connected to the external output terminal and the drain of the third transistor, and a drain to which a predetermined voltage is applied as a reference voltage A fourth transistor for adjusting
A semiconductor electronic circuit comprising: The semiconductor electronic circuit according to any one of claims 1 to 4,
N level shift circuit units (N is a natural number not including “0”) are provided,
The electronic circuit unit is composed of n-type transistors, and constitutes a NAND circuit that performs N-input NAND operation,
A semiconductor electronic circuit, wherein an output of each level shift circuit unit is connected to an N input of the electronic circuit unit. The semiconductor electronic circuit according to claim 7,
The electronic circuit unit is
N third transistors each having a gate connected to the output of each level shift circuit unit and switching the potential of the external output terminal connected to the drain based on the output voltage output from the level shift circuit unit When,
A gate, a source short-circuited to the gate and connected to the external output terminal and the drain of any one of the third transistors, and a drain to which a predetermined voltage is applied as a reference voltage, A fourth transistor for adjusting the load of the reference voltage;
With
A semiconductor electronic circuit, wherein the N third transistors are arranged in series between a source of the fourth transistor and a ground reference potential. The semiconductor electronic circuit according to any one of claims 1 to 4,
N level shift circuit units (N is a natural number not including “0”) are provided,
The electronic circuit unit is composed of an n-type transistor, and constitutes a NOR circuit that performs a negative OR output of N inputs,
A semiconductor electronic circuit, wherein an output of each level shift circuit unit is connected to an N input of the electronic circuit unit. The semiconductor electronic circuit according to claim 9.
The electronic circuit unit is
N third transistors each having a gate connected to the output of each level shift circuit unit and switching the potential of the external output terminal connected to the drain based on the output voltage output from the level shift circuit unit When,
A gate, a source short-circuited to the gate and connected to an external output terminal and each drain of the N third transistors, and a drain to which a predetermined voltage is applied as a reference voltage, A fourth transistor for adjusting the load of the reference voltage;
With
A semiconductor electronic circuit, wherein the N third transistors are arranged in parallel between a drain of the fourth transistor and a ground reference potential. M semiconductor logic circuits (M is an odd natural number not including “0”) are connected in series, and the output of the semiconductor logic circuit connected in series in the final stage is the input of the semiconductor logic circuit at the head A transmission circuit that has been fed back to
The semiconductor logic circuit is
A level shift circuit unit configured by one or more transistors and shifting a voltage level of an input voltage;
An inverter circuit unit comprising one or more transistors and inverting a logic output using a level-shifted input voltage;
With
All of the transistors provided in the level shift circuit unit and the inverter circuit unit are depletion type and N type, and the level shifted input voltage is applied to the gate of at least one of the transistors in the inverter circuit unit. A transmission circuit characterized by being input. A flip-flop circuit composed of a plurality of inverter circuits and a plurality of NOR circuits,
Each inverter circuit is
A first level shift circuit unit configured by one or more transistors to shift the voltage level of the input voltage;
An inverter circuit unit comprising one or more transistors and inverting a logic output using a level-shifted input voltage;
With
The level-shifted input voltage is input to the gate of at least one transistor of the inverter circuit unit;
Each NOR circuit is
A plurality of second level shift circuit units that are provided for each input and are configured of one or more transistors and shift the voltage level of the input voltage;
A NOR circuit unit for performing a NOR operation of N inputs (N is a natural number not including “0”);
With
The output of each second level shift circuit unit is connected to the N input of the electronic circuit unit,
A flip-flop circuit characterized in that all of the transistors provided in the plurality of inverter circuits and the plurality of NOR circuits are depletion type and N type. A level shift circuit unit configured by one or more transistors and shifting the voltage level of the input voltage;
An amplification circuit unit configured by one or more transistors and performing level-shifted input voltage inversion amplification;
With
All of the transistors provided in the level shift circuit unit and the amplifier circuit unit are depletion type, and the level-shifted input voltage is input to the gate of at least one of the transistors in the amplifier circuit unit. A semiconductor electronic circuit.

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